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Searched refs:txFifoIntEnableMask (Results 1 – 6 of 6) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/source/
Dcy_scb_spi.c89 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->txFifoIntEnableMask, CY_SCB_SPI_TX_INTR_MASK)); in Cy_SCB_SPI_Init()
177 SCB_INTR_TX_MASK(base) = (config->txFifoIntEnableMask & CY_SCB_SPI_TX_INTR_MASK); in Cy_SCB_SPI_Init()
Dcy_scb_uart.c287 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->txFifoIntEnableMask, CY_SCB_UART_TX_INTR_MASK)); in Cy_SCB_UART_Init()
365 SCB_INTR_TX_MASK(base) = (config->txFifoIntEnableMask & CY_SCB_UART_TX_INTR_MASK); in Cy_SCB_UART_Init()
/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/include/
Dcy_scb_spi.h591 uint32_t txFifoIntEnableMask; member
Dcy_scb_uart.h535 uint32_t txFifoIntEnableMask; member
/hal_infineon-3.7.0/mtb-hal-cat1/source/
Dcyhal_spi.c125 .txFifoIntEnableMask = 0,
972 (cfg_local.txFifoIntEnableMask != 0) || in cyhal_spi_init_cfg()
Dcyhal_uart.c143 .txFifoIntEnableMask = 0x0UL