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Searched refs:sampleClockDiv (Results 1 – 4 of 4) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/source/
Dcy_crypto_core_trng.c103 …CRYPTO_TR_CTL0(base) = (uint32_t)(_VAL2FLD(CRYPTO_TR_CTL0_SAMPLE_CLOCK_DIV, config->sampleClockDiv) in Cy_Crypto_Core_Trng_Init()
Dcy_cryptolite_trng.c95 …RNG_CTL0(base) = (uint32_t)(_VAL2FLD(CRYPTOLITE_TRNG_CTL0_SAMPLE_CLOCK_DIV, config->sampleClockDiv) in Cy_Cryptolite_Trng_Init()
/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/include/
Dcy_crypto_common.h1088 uint8_t sampleClockDiv; member
Dcy_cryptolite_trng.h85 uint8_t sampleClockDiv; member