Searched refs:regValue (Results 1 – 7 of 7) sorted by relevance
| /hal_infineon-3.7.0/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM0P/ |
| D | system_cm0plus.c | 399 uint32_t regValue = 0u; in Cy_SysGetCM7Status() local
406 regValue = _FLD2VAL(CPUSS_CM7_0_PWR_CTL_PWR_MODE, CPUSS->CM7_0_PWR_CTL); in Cy_SysGetCM7Status()
411 regValue = _FLD2VAL(CPUSS_CM7_1_PWR_CTL_PWR_MODE, CPUSS->CM7_1_PWR_CTL); in Cy_SysGetCM7Status()
418 return (regValue); in Cy_SysGetCM7Status()
426 uint32_t regValue; in Cy_SysEnableCM7() local
450 …regValue = CPUSS->CM7_0_PWR_CTL & ~(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_0_PWR_CTL_PWR_… in Cy_SysEnableCM7()
451 regValue |= _VAL2FLD(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN); in Cy_SysEnableCM7()
452 regValue |= CY_SYS_CM7_STATUS_ENABLED; in Cy_SysEnableCM7()
453 CPUSS->CM7_0_PWR_CTL = regValue; in Cy_SysEnableCM7()
468 …regValue = CPUSS->CM7_1_PWR_CTL & ~(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_1_PWR_CTL_PWR_… in Cy_SysEnableCM7()
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| /hal_infineon-3.7.0/mtb-template-cat1/files/templates/cat1a/COMPONENT_MTB/COMPONENT_CM0P/ |
| D | system_psoc6_cm0plus.c | 278 uint32_t regValue; in Cy_SysGetCM4Status() local
281 regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk; in Cy_SysGetCM4Status()
283 return (regValue); in Cy_SysGetCM4Status()
301 uint32_t regValue; in Cy_SysEnableCM4() local
317 …regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_M… in Cy_SysEnableCM4()
318 regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); in Cy_SysEnableCM4()
319 regValue |= CY_SYS_CM4_STATUS_ENABLED; in Cy_SysEnableCM4()
320 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysEnableCM4()
349 uint32_t regValue; in Cy_SysDisableCM4() local
353 …regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_M… in Cy_SysDisableCM4()
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| /hal_infineon-3.7.0/mtb-pdl-cat1/drivers/include/ |
| D | cy_canfd.h | 1383 uint32_t regValue; in Cy_CANFD_SetFastBitrate() local
1392 regValue = CANFD_DBTP(base, chan); /* Get Data Bit Timing and Prescaler Register */ in Cy_CANFD_SetFastBitrate()
1394 regValue &= ~ (CANFD_CH_M_TTCAN_DBTP_DTSEG2_Msk | in Cy_CANFD_SetFastBitrate()
1399 regValue |= _VAL2FLD(CANFD_CH_M_TTCAN_DBTP_DTSEG2, fastBitrate->timeSegment2) | in Cy_CANFD_SetFastBitrate()
1404 CANFD_DBTP(base, chan) = regValue; /* Set Data Bit Timing and Prescaler Register */ in Cy_CANFD_SetFastBitrate()
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| D | cy_usbfs_dev_drv_reg.h | 1495 uint32_t regValue = CY_USBFS_DEV_READ_ODD(USBFS_DEV_EP_TYPE(base)); in Cy_USBFS_Dev_Drv_SetEpType() local
1500 regValue &= ~mask; in Cy_USBFS_Dev_Drv_SetEpType()
1505 regValue |= mask; in Cy_USBFS_Dev_Drv_SetEpType()
1508 USBFS_DEV_EP_TYPE(base) = CY_USBFS_DEV_DRV_WRITE_ODD(regValue); in Cy_USBFS_Dev_Drv_SetEpType()
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| D | cy_dma.h | 2012 uint32_t regValue; in Cy_DMA_Descr_SetTxfrWidth() local
2013 regValue = descriptor->ctl & ((uint32_t)(~(DW_DESCR_STRUCT_DESCR_CTL_DATA_SIZE_Msk | in Cy_DMA_Descr_SetTxfrWidth()
2017 descriptor->ctl = regValue | in Cy_DMA_Descr_SetTxfrWidth()
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| /hal_infineon-3.7.0/mtb-pdl-cat1/drivers/source/ |
| D | cy_syspm_v3.c | 903 uint32_t regValue; in Cy_SysPm_IoFreeze() local
930 regValue = SRSS_PWR_HIBERNATE; in Cy_SysPm_IoFreeze()
931 SRSS_PWR_HIBERNATE = regValue; in Cy_SysPm_IoFreeze()
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| D | cy_smif_sfdp.c | 2116 uint8_t regValue; in SfdpPopulateRegionInfo() local
2135 regValue = 0U; in SfdpPopulateRegionInfo()
2174 …result = ReadAnyReg(base, slaveSelect, ®Value, currCmd, dummyCycles, &currRegisterAddr[0], addr… in SfdpPopulateRegionInfo()
2179 … regionInfoIdx = ((uint8_t)(regionInfoIdx << 1U)) | (((regValue & regMask) == 0U)?(0U):(1U)); in SfdpPopulateRegionInfo()
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