1 /**
2 * @file xmc_ebu.h
3 * @date 2017-06-24
4 *
5 * @cond
6 *********************************************************************************************************************
7 * XMClib v2.1.24 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015-2019, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
22 * products derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
33 * Infineon Technologies AG dave@infineon.com).
34 *********************************************************************************************************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-06-20:
40 * - Initial
41 *
42 * 2016-03-30:
43 * - Added ebu_data_hold_cycles_for_read_accesses to XMC_EBU_BUS_READ_CONFIG_t
44 * - Added ebu_device_addressing_mode and ebu_data_hold_cycles_for_write_accesses to XMC_EBU_BUS_WRITE_CONFIG_t
45 *
46 * 2017-06-24:
47 * - Changed XMC_EBU_AddressSelectEnable() to make sure arbitartion mode is active
48 *
49 * @endcond
50 *
51 */
52
53 #ifndef XMC_EBU_H
54 #define XMC_EBU_H
55
56 /**********************************************************************************************************************
57 * HEADER FILES
58 *********************************************************************************************************************/
59
60 #include <xmc_common.h>
61 #if defined (EBU)
62 #include <xmc_scu.h>
63
64 /**
65 * @addtogroup XMClib XMC Peripheral Library
66 * @{
67 */
68
69 /**
70 * @addtogroup EBU
71 * @brief External Bus Unit (EBU) driver for the XMC45/XMC47/XMC48 microcontroller
72 *
73 * The External Bus Unit (EBU) controls the transactions between external memories or
74 * peripheral units, and the internal memories and peripheral units. Several external
75 * device configurations are supported; e.g. Asynchronous static memories, SDRAM
76 * and various flash memory types. It supports multiple programmable address regions.
77 *
78 * The EBU low level driver provides functions to configure and initialize the EBU
79 * hardware peripheral.
80 * @{
81 */
82
83 /**********************************************************************************************************************
84 * MACROS
85 **********************************************************************************************************************/
86
87 /**
88 * A convenient symbol for the EBU peripheral base address
89 */
90 #if defined (EBU)
91 # define XMC_EBU ((XMC_EBU_t *)EBU_BASE)
92 #else
93 # error 'EBU' base peripheral pointer not defined
94 #endif
95
96
97 /*
98 * This macro is used in the LLD for assertion checks (XMC_ASSERT).
99 */
100 #define XMC_EBU_CHECK_MODULE_PTR(p) ((p) == XMC_EBU)
101
102 /**********************************************************************************************************************
103 * ENUMS
104 **********************************************************************************************************************/
105
106 /**
107 * Status return values for EBU low level driver
108 */
109 typedef enum XMC_EBU_STATUS
110 {
111 XMC_EBU_STATUS_OK = 0U, /**< Operation successful */
112 XMC_EBU_STATUS_BUSY = 1U, /**< Busy with a previous request */
113 XMC_EBU_STATUS_ERROR = 3U /**< Operation unsuccessful */
114 } XMC_EBU_STATUS_t;
115
116 /**
117 * EBU clock divide ratio
118 */
119 typedef enum XMC_EBU_CLOCK_DIVIDE_RATIO
120 {
121 XMC_EBU_CLOCK_DIVIDED_BY_1 = 0U, /**< Clock divided by 1 */
122 XMC_EBU_CLOCK_DIVIDED_BY_2 = 1U, /**< Clock divided by 2 */
123 XMC_EBU_CLOCK_DIVIDED_BY_3 = 2U, /**< Clock divided by 3 */
124 XMC_EBU_CLOCK_DIVIDED_BY_4 = 3U /**< Clock divided by 4 */
125 } XMC_EBU_CLOCK_DIVIDE_RATIO_t;
126
127 /**
128 * EBU DIV2 clocking mode
129 */
130 typedef enum XMC_EBU_DIV2_CLK_MODE
131 {
132 XMC_EBU_DIV2_CLK_MODE_OFF = 0U, /**< Divider 2 clock mode OFF */
133 XMC_EBU_DIV2_CLK_MODE_ON = 1U /**< Divider 2 clock mode ON */
134 } XMC_EBU_DIV2_CLK_MODE_t;
135
136 /**
137 * EBU clocking mode
138 */
139 typedef enum XMC_EBU_CLK_MODE
140 {
141 XMC_EBU_CLK_MODE_ASYNCHRONOUS_TO_AHB = 0U, /**< EBU is using standard clocking mode */
142 XMC_EBU_CLK_MODE_SYNCHRONOUS_TO_CPU = 1U /**< EBU is running at AHB bus clock divided by 2 */
143 } XMC_EBU_CLK_MODE_t;
144
145 /**
146 * EBU arbitration mode
147 */
148 typedef enum XMC_EBU_ARB_MODE
149 {
150 XMC_EBU_ARB_MODE_NOT_SELECTED = 0U, /**< No Bus arbitration mode selected */
151 XMC_EBU_ARB_MODE_ARBITER_MODE = 1U, /**< Arbiter Mode arbitration mode selected */
152 XMC_EBU_ARB_MODE_PARTICIPANT_MODE = 2U, /**< Participant arbitration mode selected */
153 XMC_EBU_ARB_MODE_SOLE_MASTER_MODE = 3U /**< Sole Master arbitration mode selected */
154 } XMC_EBU_ARB_MODE_t;
155
156 /**
157 * EBU ALE mode
158 */
159 typedef enum XMC_EBU_ALE_MODE
160 {
161 XMC_EBU_ALE_OUTPUT_IS_INV_ADV = 0U, /**< Output is ADV */
162 XMC_EBU_ALE_OUTPUT_IS_ALE = 1U /**< Output is ALE */
163 } XMC_EBU_ALE_MODE_t;
164
165 /**
166 * EBU clock status
167 */
168 typedef enum XMC_EBU_CLK_STATUS
169 {
170 XMC_EBU_CLK_STATUS_DISABLE_BIT = EBU_CLC_DISS_Msk, /**< EBU Disable Status Bit */
171 XMC_EBU_CLK_STATUS_MODE = EBU_CLC_SYNCACK_Msk, /**< EBU Clocking Mode Status */
172 XMC_EBU_CLK_STATUS_DIV2_MODE = EBU_CLC_DIV2ACK_Msk, /**< DIV2 Clocking Mode Status */
173 XMC_EBU_CLK_STATUS_DIV_RATIO = EBU_CLC_EBUDIVACK_Msk /**< EBU Clock Divide Ratio Status */
174 } XMC_EBU_CLK_STATUS_t;
175
176 /**
177 * EBU address selection
178 */
179 typedef enum XMC_EBU_ADDRESS_SELECT
180 {
181 XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_ENABLE = EBU_ADDRSEL0_REGENAB_Msk, /**< Memory Region Enable */
182 XMC_EBU_ADDRESS_SELECT_ALTERNATE_REGION_ENABLE = EBU_ADDRSEL0_ALTENAB_Msk, /**< Alternate Region Enable */
183 XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_WRITE_PROTECT = EBU_ADDRSEL0_WPROT_Msk /**< Memory Region Write Protect */
184 } XMC_EBU_ADDRESS_SELECT_t;
185
186 /**
187 * EBU bus write configuration status
188 */
189 typedef enum XMC_EBU_BUSWCON_SELECT
190 {
191 XMC_EBU_BUSWCON_SELECT_NAN_WORKAROUND = EBU_BUSWCON0_NAA_Msk, /**< Enable flash non-array access workaround */
192 XMC_EBU_BUSWCON_SELECT_DEVICE_ADDRESSING_MODE = EBU_BUSWCON0_PORTW_Msk, /**< Device Addressing Mode */
193 } XMC_EBU_BUSWCON_SELECT_t;
194
195 /**
196 * EBU burst length for synchronous burst
197 */
198 typedef enum XMC_EBU_BURST_LENGTH_SYNC
199 {
200 XMC_EBU_BURST_LENGTH_SYNC_1_DATA_ACCESS = 0U, /**< 1 data access (default after reset) */
201 XMC_EBU_BURST_LENGTH_SYNC_2_DATA_ACCESSES = 1U, /**< 2 data access */
202 XMC_EBU_BURST_LENGTH_SYNC_4_DATA_ACCESSES = 2U, /**< 3 data access */
203 XMC_EBU_BURST_LENGTH_SYNC_8_DATA_ACCESSES = 3U, /**< 4 data access */
204 } XMC_EBU_BURST_LENGTH_SYNC_t;
205
206 /**
207 * EBU burst buffer mode
208 */
209 typedef enum XMC_EBU_BURST_BUFFER_SYNC_MODE
210 {
211 XMC_EBU_BURST_BUFFER_SYNC_LENGTH_SYNC_ENABLE = 0U, /**< Burst buffer length defined by value in FETBLEN */
212 XMC_EBU_BURST_BUFFER_SYNC_SINGLE_MODE = 1U /**< All data required for transaction (single burst transfer) */
213 } XMC_EBU_BURST_BUFFER_SYNC_MODE_t;
214
215 /**
216 * Read single stage synchronization
217 */
218 typedef enum XMC_EBU_READ_STAGES_SYNC
219 {
220 XMC_EBU_READ_STAGES_SYNC_TWO = 0U, /**< Two stages of synchronization used (maximum margin) */
221 XMC_EBU_READ_STAGES_SYNC_ONE = 1U /**< One stage of synchronization used (minimum latency) */
222 } XMC_EBU_READ_STAGES_SYNC_t;
223
224 /**
225 * EBU burst flash clock feedback enable/disable
226 */
227 typedef enum XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK
228 {
229 XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_DISABLE = 0U, /**< BFCLK feedback not used */
230 XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_ENABLE = 1U /**< BFCLK feedback used */
231 } XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_t;
232
233 /**
234 * EBU burst flash clock mode select
235 */
236 typedef enum XMC_EBU_BURST_FLASH_CLOCK_MODE
237 {
238 XMC_EBU_BURST_FLASH_CLOCK_MODE_RUN_CONTINUOSLY = 0U, /**< Burst flash clock runs continuously */
239 XMC_EBU_BURST_FLASH_CLOCK_MODE_DISABLED_BETWEEN_ACCESSES = 1U /**< Burst flash clock disabled */
240 } XMC_EBU_BURST_FLASH_CLOCK_MODE_t;
241
242 /**
243 * EBU flash non-array access
244 */
245 typedef enum XMC_EBU_FLASH_NON_ARRAY_ACCESS
246 {
247 XMC_EBU_FLASH_NON_ARRAY_ACCESS_DISNABLE = 0U, /**< Disable non-array access */
248 XMC_EBU_FLASH_NON_ARRAY_ACCESS_ENABLE = 1U /**< Enable non-array access */
249 } XMC_EBU_FLASH_NON_ARRAY_ACCESS_t;
250
251 /**
252 * EBU early chip select for synchronous burst
253 */
254 typedef enum XMC_EBU_EARLY_CHIP_SELECT_SYNC_BURST
255 {
256 XMC_EBU_EARLY_CHIP_SELECT_DELAYED = 0U, /**< Chip select delayed */
257 XMC_EBU_EARLY_CHIP_SELECT_NOT_DELAYED = 1U /**< Chip select not delayed */
258 } XMC_EBU_EARLY_CHIP_SELECT_SYNC_BURST_t;
259
260 /**
261 * EBU early burst signal enable for synchronous burst
262 */
263 typedef enum XMC_EBU_BURST_SIGNAL_SYNC_BURST
264 {
265 XMC_EBU_BURST_SIGNAL_SYNC_BURST_ADV_DELAYED = 0U, /**< Chip select delayed */
266 XMC_EBU_BURST_SIGNAL_SYNC_BURST_ADV_NOT_DELAYED = 1U /**< Chip select not delayed */
267 } XMC_EBU_BURST_SIGNAL_SYNC_BURST_t;
268
269 /**
270 * EBU burst address wrapping
271 */
272 typedef enum XMC_EBU_BURST_ADDRESS_WRAPPING
273 {
274 XMC_EBU_BURST_ADDRESS_WRAPPING_DISABLED = 0U, /**< Automatically re-aligns any non-aligned synchronous burst access */
275 XMC_EBU_BURST_ADDRESS_WRAPPING_ENABLED = 1U /**< Starts any burst access at address specified by the AHB request */
276 } XMC_EBU_BURST_ADDRESS_WRAPPING_t;
277
278 /**
279 * EBU reversed polarity at WAIT
280 */
281 typedef enum XMC_EBU_WAIT_SIGNAL_POLARITY
282 {
283 XMC_EBU_WAIT_SIGNAL_POLARITY_PIN_ACTIVE_LOW = 0U, /**< OFF, input at WAIT pin is active low */
284 XMC_EBU_WAIT_SIGNAL_POLARITY_PIN_ACTIVE_HIGH = 1U /**< Polarity reversed, input at WAIT pin is active high */
285 } XMC_EBU_WAIT_SIGNAL_POLARITY_t;
286
287 /**
288 * EBU byte control signal control
289 */
290 typedef enum XMC_EBU_BYTE_CONTROL
291 {
292 XMC_EBU_BYTE_CONTROL_FOLLOWS_CHIP_SELECT_TIMMING = 0U, /**< Control signals follow chip select timing */
293 XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING = 1U, /**< Control signals follow control signal timing */
294 XMC_EBU_BYTE_CONTROL_FOLLOWS_WRITE_ENABLE_SIGNAL_TIMMING = 2U /**< Control signals follow write enable timing */
295 } XMC_EBU_BYTE_CONTROL_t;
296
297 /**
298 * EBU device addressing mode
299 */
300 typedef enum XMC_EBU_DEVICE_ADDRESSING_MODE
301 {
302 XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS = 1U, /**< Address will only be driven onto AD[15:0] */
303 XMC_EBU_DEVICE_ADDRESSING_MODE_TWIN_16_BITS_MULTIPLEXED = 2U, /**< Lower 16b will be driven onto A[15:0] & AD[15:0] */
304 XMC_EBU_DEVICE_ADDRESSING_MODE_32_BITS_MULTIPLEXED = 3U /**< Full address driven onto A[15:0] & AD[15:0] */
305 } XMC_EBU_DEVICE_ADDRESSING_MODE_t;
306
307 /**
308 * EBU external wait control
309 */
310 typedef enum XMC_EBU_WAIT_CONTROL
311 {
312 XMC_EBU_WAIT_CONTROL_OFF = 0U, /**< Default after reset; Wait control off */
313 XMC_EBU_WAIT_CONTROL_SYNC_EARLY_WAIT_ASYNC_ASYNC_INPUT_AT_WAIT = 1U, /**< SYNC: Wait for page load (Early WAIT);
314 ASYNC: Asynchronous input at WAIT */
315 XMC_EBU_WAIT_CONTROL_SYNC_WAIT_WITH_DATA_ASYNC_SYNC_INPUT_AT_WAIT = 2U, /**< SYNC: Wait for page load (WAIT with data);
316 ASYNC: Synchronous input at WAIT; */
317 XMC_EBU_WAIT_CONTROL_SYNC_ABORT_AND_RETRY_ACCESS = 3U /**< SYNC: Abort and retry access; */
318 } XMC_EBU_WAIT_CONTROL_t;
319
320 /**
321 * EBU asynchronous address phase
322 */
323 typedef enum XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE
324 {
325 XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_CLOCK_ENABLED_AT_BEGINNING_OF_ACCESS = 0U, /**< Enabled at beginning of access */
326 XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_CLOCK_ENABLED_AFTER_ADDRESS_PHASE = 1U /**< Enabled after address phase */
327 } XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_t;
328
329 /**
330 * EBU device type for region
331 */
332 typedef enum XMC_EBU_DEVICE_TYPE
333 {
334 XMC_EBU_DEVICE_TYPE_MUXED_ASYNCHRONOUS_TYPE = 0U, /**< Device type muxed asynchronous */
335 XMC_EBU_DEVICE_TYPE_MUXED_BURST_TYPE = 1U, /**< Device type muxed burst */
336 XMC_EBU_DEVICE_TYPE_NAND_FLASH = 2U, /**< Device type NAND flash */
337 XMC_EBU_DEVICE_TYPE_MUXED_CELLULAR_RAM = 3U, /**< Device type muxed cellular RAM */
338 XMC_EBU_DEVICE_TYPE_DEMUXED_ASYNCHRONOUS_TYPE = 4U, /**< Device type de-muxed asynchronous */
339 XMC_EBU_DEVICE_TYPE_DEMUXED_BURST_TYPE = 5U, /**< Device type de-muxed burst */
340 XMC_EBU_DEVICE_TYPE_DEMUXED_PAGE_MODE = 6U, /**< Device type de-muxed page mode */
341 XMC_EBU_DEVICE_TYPE_DEMUXED_CELLULAR_RAM = 7U, /**< Device type de-muxed cellular RAM */
342 XMC_EBU_DEVICE_TYPE_SDRAM = 8U /**< Device type SDRAM */
343 } XMC_EBU_DEVICE_TYPE_t;
344
345 /**
346 * EBU lock chip select
347 */
348 typedef enum XMC_EBU_LOCK_CHIP_SELECT
349 {
350 XMC_EBU_LOCK_CHIP_SELECT_DISABLED = 0U, /**< Chip select cannot be locked */
351 XMC_EBU_LOCK_CHIP_SELECT_ENABLED = 1U /**< Chip select automatically locked after a write operation */
352 } XMC_EBU_LOCK_CHIP_SELECT_t;
353
354 /**
355 * EBU Frequency of external clock at pin BFCLKO
356 */
357 typedef enum XMC_EBU_FREQUENCY_EXT_CLK_PIN
358 {
359 XMC_EBU_FREQ_EXT_CLK_PIN_EQUAL_TO_INT_CLK = 0U, /**< Equal to INT_CLK frequency */
360 XMC_EBU_FREQ_EXT_CLK_PIN_HALF_OF_INT_CLK = 1U, /**< 1/2 of INT_CLK frequency */
361 XMC_EBU_FREQ_EXT_CLK_PIN_THIRD_OF_INT_CLK = 2U, /**< 1/3 of INT_CLK frequency */
362 XMC_EBU_FREQ_EXT_CLK_PIN_QUARTER_OF_INT_CLK = 3U /**< 1/4 of INT_CLK frequency */
363 } XMC_EBU_FREQ_EXT_CLK_PIN_t;
364
365 /**
366 * EBU extended data
367 */
368 typedef enum XMC_EBU_EXT_DATA
369 {
370 XMC_EBU_EXT_DATA_OUTPUT_EVERY_1_BFCLK_CYCLES = 0U, /**< External memory outputs data every BFCLK cycle */
371 XMC_EBU_EXT_DATA_OUTPUT_EVERY_2_BFCLK_CYCLES = 1U, /**< External memory outputs data every two BFCLK cycles */
372 XMC_EBU_EXT_DATA_OUTPUT_EVERY_4_BFCLK_CYCLES = 2U, /**< External memory outputs data every four BFCLK cycles */
373 XMC_EBU_EXT_DATA_OUTPUT_EVERY_8_BFCLK_CYCLES = 3U /**< External memory outputs data every eight BFCLK cycles */
374 } XMC_EBU_EXT_DATA_t;
375
376 /**
377 * EBU SDRAM clock mode select
378 */
379 typedef enum XMC_EBU_SDRAM_CLK_MODE
380 {
381 XMC_EBU_SDRAM_CLK_MODE_CONTINUOUSLY_RUNS = 0U, /**< Clock continuously running */
382 XMC_EBU_SDRAM_CLK_MODE_DISABLED_BETWEEN_ACCESSES = 1U /**< Clock disabled between accesses */
383 } XMC_EBU_SDRAM_CLK_MODE_t;
384
385 /**
386 * EBU power save mode used for gated clock mode
387 */
388 typedef enum XMC_EBU_SDRAM_PWR_MODE
389 {
390 XMC_EBU_SDRAM_PWR_MODE_PRECHARGE_BEFORE_CLK_STOP = 0U, /**< Precharge before clock stop */
391 XMC_EBU_SDRAM_PWR_MODE_AUTO_PRECHARGE_BEFORE_CLK_STOP = 1U, /**< Auto-precharge before clock stop */
392 XMC_EBU_SDRAM_PWR_MODE_ACTIVE_PWR_DOWN = 2U, /**< Active power down (stop clock without precharge) */
393 XMC_EBU_SDRAM_PWR_MODE_CLK_STOP_PWR_DOWN = 3U /**< Clock stop power down */
394 } XMC_EBU_SDRAM_PWR_MODE_t;
395
396 /**
397 * EBU disable SDRAM clock output
398 */
399 typedef enum XMC_EBU_SDRAM_CLK_OUTPUT
400 {
401 XMC_EBU_SDRAM_CLK_OUTPUT_ENABLED = 0U, /**< Clock output enabled */
402 XMC_EBU_SDRAM_CLK_OUTPUT_DISABLED = 1U /**< Clock output disabled */
403 } XMC_EBU_SDRAM_CLK_OUTPUT_t;
404
405 /**
406 * EBU mask for bank tag
407 */
408 typedef enum XMC_EBU_SDRAM_MASK_FOR_BANKM_TAG
409 {
410 XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_21_to_20 = 1U, /**< Mask for bank tag addresses 21 to 20 */
411 XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_22_to_21 = 2U, /**< Mask for bank tag addresses 22 to 21 */
412 XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_23_to_22 = 3U, /**< Mask for bank tag addresses 23 to 22 */
413 XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_24_to_23 = 4U, /**< Mask for bank tag addresses 24 to 23 */
414 XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_25_to_24 = 5U, /**< Mask for bank tag addresses 25 to 24 */
415 XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_26_to_25 = 6U, /**< Mask for bank tag addresses 26 to 25 */
416 XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_26 = 7U /**< Mask for bank tag addresses 26 */
417 } XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_t;
418
419 /**
420 * EBU Mask for row tag
421 */
422 typedef enum XMC_EBU_SDRAM_MASK_FOR_ROW_TAG
423 {
424 XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_9 = 1U, /**< Mask for row tag addresses 26 to 9 */
425 XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_10 = 2U, /**< Mask for row tag addresses 26 to 10 */
426 XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_11 = 3U, /**< Mask for row tag addresses 26 to 11 */
427 XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_12 = 4U, /**< Mask for row tag addresses 26 to 12 */
428 XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_13 = 5U /**< Mask for row tag addresses 26 to 13 */
429 } XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_t;
430
431 /**
432 * Number of address bits from bit 0 to be used for column address
433 */
434 typedef enum XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS
435 {
436 XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_8_to_0 = 1U, /**< Address [8:0] */
437 XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_9_to_0 = 2U, /**< Address [9:0] */
438 XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_10_to_0 = 3U /**< Address [10:0] */
439 } XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_t;
440
441 /**
442 * Number of clocks between a READ command and the availability of data
443 */
444 typedef enum XMC_EBU_SDRAM_CAS_LATENCY
445 {
446 XMC_EBU_SDRAM_CAS_LATENCY_2_CLKS = 2U, /**< 2 clocks between a READ command and the availability of data */
447 XMC_EBU_SDRAM_CAS_LATENCY_3_CLKS = 3U /**< 3 clocks between a READ command and the availability of data */
448 } XMC_EBU_SDRAM_CAS_LATENCY_t;
449
450 /**
451 * Number of locations can be accessed with a single command
452 */
453 typedef enum XMC_EBU_SDRAM_BURST_LENGTH
454 {
455 XMC_EBU_SDRAM_BURST_LENGTH_1_LOCATION = 0U, /**< One location accessed with a single command */
456 XMC_EBU_SDRAM_BURST_LENGTH_2_LOCATION = 1U, /**< Two location accessed with a single command */
457 XMC_EBU_SDRAM_BURST_LENGTH_4_LOCATION = 2U, /**< Four location accessed with a single command */
458 XMC_EBU_SDRAM_BURST_LENGTH_8_LOCATION = 3U, /**< Eight location accessed with a single command */
459 XMC_EBU_SDRAM_BURST_LENGTH_16_LOCATION = 4U /**< Sixteen location accessed with a single command */
460 } XMC_EBU_SDRAM_BURST_LENGTH_t;
461
462 /**
463 * EBU SDRAM status
464 */
465 typedef enum XMC_EBU_SDRAM_STATUS
466 {
467 XMC_EBU_SDRAM_STATUS_RX_ERROR = EBU_SDRSTAT_SDERR_Msk, /**< Detected an error when returning read data */
468 XMC_EBU_SDRAM_STATUS_BUSY = EBU_SDRSTAT_SDRMBUSY_Msk, /**< The status of power-up initialization sequence */
469 XMC_EBU_SDRAM_STATUS_REFRESH_ERROR = EBU_SDRSTAT_REFERR_Msk /**< Failed previous refresh req collides with new req */
470 } XMC_EBU_SDRAM_STATUS_t;
471
472 /**
473 * SDRAM refresh status
474 */
475 typedef enum XMC_EBU_SDRAM_RFRSH_STATUS
476 {
477 XMC_EBU_SDRAM_RFRSH_STATUS_SELF_REFRESH_ENTRY_STATUS = EBU_SDRMREF_SELFRENST_Msk, /**< Self refresh entry command issue successful */
478 XMC_EBU_SDRAM_RFRSH_STATUS_SELF_REFRESH_EXIT_STATUS = EBU_SDRMREF_SELFREXST_Msk /**< Self refresh exit command issue successful */
479 } XMC_EBU_SDRAM_RFRSH_STATUS_t;
480
481
482 /**********************************************************************************************************************
483 * DATA STRUCTURES
484 *********************************************************************************************************************/
485
486 /* Anonymous structure/union guard start */
487 #if defined(__CC_ARM)
488 #pragma push
489 #pragma anon_unions
490 #elif defined (__TASKING__)
491 #pragma warning 586
492 #endif
493
494 /**
495 * Clock configuration values of EBU <br>
496 *
497 * The structure presents a convenient way to set/obtain the clock configuration
498 * values for clock mode, div2 clock mode and clock divide ratio of EBU.
499 * The XMC_EBU_Init() can be used to populate the structure with the clock
500 * configuration values of the EBU module.
501 */
502 typedef struct XMC_EBU_CLK_CONFIG
503 {
504 union
505 {
506 uint32_t raw0;
507 struct
508 {
509 uint32_t : 16;
510 uint32_t ebu_clk_mode : 1; /**< Clocking mode (::XMC_EBU_CLK_MODE_t) */
511 uint32_t ebu_div2_clk_mode : 1; /**< DIV2 clocking mode (::XMC_EBU_DIV2_CLK_MODE_t) */
512 uint32_t ebu_clock_divide_ratio : 2; /**< Clock divide ratio (::XMC_EBU_CLOCK_DIVIDE_RATIO_t) */
513 uint32_t : 12;
514 };
515 };
516 } XMC_EBU_CLK_CONFIG_t;
517
518 /**
519 * Mode configuration values for EBU <br>
520 *
521 * The structure presents a convenient way to set/obtain the mode configuration,
522 * SDRAM tristate, external clock, arbitration, timeout control and ALE mode for
523 * EBU. The XMC_EBU_Init() can be used to populate the structure with the
524 * clock configuration values of the EBU module.
525 */
526 typedef struct XMC_EBU_MODE_CONFIG
527 {
528 union
529 {
530 uint32_t raw0;
531 struct
532 {
533 uint32_t : 2;
534 uint32_t ebu_sdram_tristate : 1; /**< 0 - SDRAM cannot be shared; 1 - SDRAM can be shared */
535 uint32_t : 1;
536 uint32_t ebu_extlock : 1; /**< 0 - ext bus is not locked after the EBU gains ownership; 1 - ext bus is not locked */
537 uint32_t ebu_arbsync : 1; /**< 0 - arbitration inputs are sync; 1 - arbitration inputs are async */
538 uint32_t ebu_arbitration_mode : 2; /**< Arbitration mode selection (::XMC_EBU_ARB_MODE_t) */
539 uint32_t bus_timeout_control : 8; /**< Determines num of inactive cycles leading to a bus timeout after the EBU gains ownership <br>
540 00H: Timeout is disabled <br>
541 01H: Timeout is generated after 1 x 8 clock cycles <br>
542 FFH: Timeout is generated after 255 x 8 clock cycles <br> */
543 uint32_t : 15;
544 uint32_t ebu_ale_mode : 1; /**< ALE mode. Switch the ADV output to be an active high ALE signal instead of active low ADV. (::XMC_EBU_ALE_MODE_t) */
545 };
546 };
547 } XMC_EBU_MODE_CONFIG_t;
548
549 /**
550 * GPIO mode configuration for the allocated EBU ports <br>
551 * Configuring this structure frees the allocated EBU ports for GPIO
552 * functionality. The XMC_EBU_Init() is used to populate the structure
553 * with the GPIO mode for the allocated EBU ports.
554 */
555 typedef struct XMC_EBU_FREE_PINS_TO_GPIO
556 {
557 union
558 {
559 uint32_t raw0;
560 struct
561 {
562 uint32_t : 16;
563 uint32_t address_pins_gpio : 9; /**< 0 - Address bit required for addressing memory; 1 - Address bit available as GPIO */
564 uint32_t adv_pin_gpio : 1; /**< Adv pin to GPIO mode */
565 uint32_t : 6;
566 };
567 };
568 } XMC_EBU_FREE_PINS_TO_GPIO_t;
569
570 /**
571 * Read configuration for a region of EBU <br>
572 *
573 * The structure presents a convenient way to set/obtain the read and read timing
574 * configuration for a region for EBU. The XMC_EBU_ConfigureRegion() can be
575 * used to populate the structure with the read configuration values for EBU.
576 */
577 typedef struct XMC_EBU_BUS_READ_CONFIG
578 {
579 /* EBU read configuration parameters */
580 union
581 {
582 uint32_t raw0;
583 struct
584 {
585 uint32_t ebu_burst_length_sync : 3; /**< Burst length for synchronous burst (::XMC_EBU_BURST_LENGTH_SYNC_t) */
586 uint32_t ebu_burst_buffer_sync_mode : 1; /**< Burst buffer mode (::XMC_EBU_BURST_BUFFER_SYNC_MODE_t) */
587 uint32_t ebu_read_stages_synch : 1; /**< Read single stage synchronization */
588 uint32_t ebu_burst_flash_clock_feedback : 1; /**< Burst flash clock feedback enable/disable (::XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_t) */
589 uint32_t ebu_burst_flash_clock_mode : 1; /**< Burst flash clock mode select (::XMC_EBU_BURST_FLASH_CLOCK_MODE_t) */
590 uint32_t ebu_flash_non_array_access : 1; /**< flash non-array access (::XMC_EBU_FLASH_NON_ARRAY_ACCESS_t) */
591 uint32_t : 8;
592 uint32_t ebu_early_chip_select_sync_burst : 1; /**< Early chip select for sync burst (::XMC_EBU_EARLY_CHIP_SELECT_SYNC_BURST_t) */
593 uint32_t ebu_burst_signal_sync : 1; /**< Early burst signal enable for synchronous burst (::XMC_EBU_BURST_SIGNAL_SYNC_BURST_t) */
594 uint32_t ebu_burst_address_wrapping : 1; /**< Burst address wrapping (::XMC_EBU_BURST_ADDRESS_WRAPPING_t) */
595 uint32_t ebu_wait_signal_polarity : 1; /**< Reversed polarity at WAIT (::XMC_EBU_WAIT_SIGNAL_POLARITY_t) */
596 uint32_t ebu_byte_control : 2; /**< Byte control signal control (::XMC_EBU_BYTE_CONTROL_t) */
597 uint32_t ebu_device_addressing_mode : 2; /**< Device addressing mode (::XMC_EBU_DEVICE_ADDRESSING_MODE_t) */
598 uint32_t ebu_wait_control : 2; /**< External wait control (::XMC_EBU_WAIT_CONTROL_t) */
599 uint32_t ebu_asynchronous_address_phase : 1; /**< Asynchronous address phase (::XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_t) */
600 uint32_t : 1;
601 uint32_t ebu_device_type : 4; /**< Device type for region (::XMC_EBU_DEVICE_TYPE_t) */
602 };
603 };
604 /* EBU read access parameters */
605 union
606 {
607 uint32_t raw1;
608 struct
609 {
610 /**
611 * Recovery Cycles between Different Regions: <br>
612 * This bit field determines the number of clock cycles of the Recovery Phase between consecutive accesses directed to different regions or different types of access.<br>
613 * 0000B: No recovery phase clock cycles available <br>
614 * 0001B: 1 clock cycle selected <br>
615 * ... <br>
616 * 1110B: 14 clock cycles selected <br>
617 * 1111B: 15 clock cycles selected <br>
618 */
619 uint32_t ebu_recovery_cycles_between_different_regions : 4;
620 /**
621 * Recovery cycles after read accesses: <br>
622 * This bit field determines the basic number of clock cycles of the Recovery Phase at the end of read accesses.<br>
623 * 000B: No recovery phase clock cycles available <br>
624 * 001B: 1 clock cycle selected <br>
625 * ... <br>
626 * 110B: 6 clock cycles selected <br>
627 * 111B: 7 clock cycles selected <br>
628 */
629 uint32_t ebu_recovery_cycles_after_read_accesses : 3;
630 /**
631 * Programmed wait states for read accesses: <br>
632 * Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock.<br>
633 * 00000B: 1 wait state <br>
634 * 00001B: 1 wait state <br>
635 * 00010B: 2 wait state <br>
636 * ... <br>
637 * 11110B: 30 wait states <br>
638 * 11111B: 31 wait states <br>
639 */
640 uint32_t ebu_programmed_wait_states_for_read_accesses : 5;
641 /**
642 * Data Hold Cycles for Read Accesses <br>
643 * This bit field determines the basic number of Data Hold phase clock cycles during read accesses. It has no effect in the current implementation<br>
644 */
645 uint32_t ebu_data_hold_cycles_for_read_accesses: 4;
646 /**
647 * Frequency of external clock at pin BFCLKO (::XMC_EBU_FREQ_EXT_CLK_PIN_t)
648 */
649 uint32_t ebu_freq_ext_clk_pin : 2;
650 /**
651 * EBU Extended data (::XMC_EBU_EXT_DATA_t)
652 */
653 uint32_t ebu_ext_data : 2;
654 /**
655 * Command delay cycles: <br>
656 * This bit field determines the basic number of Command Delay phase clock cycles.<br>
657 * 0000B: 0 clock cycle selected <br>
658 * 0001B: 1 clock cycle selected <br>
659 * ... <br>
660 * 1110B: 14 clock cycles selected <br>
661 * 1111B: 15 clock cycles selected <br>
662 */
663 uint32_t command_delay_lines : 4;
664 /**
665 * Address hold cycles: <br>
666 * This bit field determines the number of clock cycles of the address hold phase.<br>
667 * 0000B: 0 clock cycle selected <br>
668 * 0001B: 1 clock cycle selected <br>
669 * ... <br>
670 * 1110B: 14 clock cycles selected <br>
671 * 1111B: 15 clock cycles selected <br>
672 */
673 uint32_t address_hold_cycles : 4;
674 /**
675 * Address Cycles:
676 * This bit field determines the number of clock cycles of the address phase.<br>
677 * 0000B: 1 clock cycle selected <br>
678 * 0001B: 1 clock cycle selected <br>
679 * ... <br>
680 * 1110B: 14 clock cycles selected <br>
681 * 1111B: 15 clock cycles selected <br>
682 */
683 uint32_t address_cycles : 4;
684 };
685 };
686 } XMC_EBU_BUS_READ_CONFIG_t;
687
688 /**
689 * Write configuration for a region of EBU <br>
690 *
691 * The structure presents a convenient way to set/obtain the write and write timing
692 * configurations for a region of EBU. The XMC_EBU_ConfigureRegion() can be used
693 * to populate the structure with the write configuration values of EBU.
694 */
695 typedef struct XMC_EBU_BUS_WRITE_CONFIG
696 {
697 /* EBU write configuration parameters */
698 union
699 {
700 uint32_t raw0;
701 struct
702 {
703 uint32_t ebu_burst_length_sync : 3; /**< Burst length for synchronous burst (::XMC_EBU_BURST_LENGTH_SYNC_t) */
704 uint32_t ebu_burst_buffer_sync_mode : 1; /**< Burst buffer mode (::XMC_EBU_BURST_BUFFER_SYNC_MODE_t) */
705 uint32_t : 12;
706 uint32_t ebu_early_chip_select_sync_burst : 1; /**< Early chip select for sync burst (::XMC_EBU_EARLY_CHIP_SELECT_SYNC_BURST_t) */
707 uint32_t ebu_burst_signal_sync : 1; /**< Early burst signal enable for synchronous burst (::XMC_EBU_BURST_SIGNAL_SYNC_BURST_t) */
708 uint32_t : 1;
709 uint32_t ebu_wait_signal_polarity : 1; /**< Reversed polarity at WAIT (::XMC_EBU_WAIT_SIGNAL_POLARITY_t) */
710 uint32_t ebu_byte_control : 2; /**< Byte control signal control (::XMC_EBU_BYTE_CONTROL_t) */
711 uint32_t ebu_device_addressing_mode : 2; /**< Device addressing mode (::XMC_EBU_DEVICE_ADDRESSING_MODE_t) */
712 uint32_t ebu_wait_control : 2; /**< External wait control (::XMC_EBU_WAIT_CONTROL_t) */
713 uint32_t ebu_asynchronous_address_phase : 1; /**< Asynchronous address phase (::XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_t) */
714 uint32_t ebu_lock_chip_select : 1; /**< Lock chip select (::XMC_EBU_LOCK_CHIP_SELECT_t) */
715 uint32_t ebu_device_type : 4; /**< Device type for region (::XMC_EBU_DEVICE_TYPE_t) */
716 };
717 };
718 /* EBU write access parameters */
719 union
720 {
721 uint32_t raw1;
722 struct
723 {
724 /**
725 * Recovery cycles between different regions: <br>
726 * This bit field determines the number of clock cycles of the Recovery Phase between consecutive accesses directed to different regions or different types of access.<br>
727 * 0000B: No recovery phase clock cycles available <br>
728 * 0001B: 1 clock cycle selected <br>
729 * ... <br>
730 * 1110B: 14 clock cycles selected <br>
731 * 1111B: 15 clock cycles selected <br>
732 */
733 uint32_t ebu_recovery_cycles_between_different_regions : 4;
734
735 /**
736 * Recovery cycles after write accesses: <br>
737 * This bit field determines the basic number of clock cycles of the Recovery Phase at the end of write accesses.<br>
738 * 000B: No recovery phase clock cycles available <br>
739 * 001B: 1 clock cycle selected <br>
740 * ... <br>
741 * 110B: 6 clock cycles selected <br>
742 * 111B: 7 clock cycles selected <br>
743 */
744 uint32_t ebu_recovery_cycles_after_write_accesses : 3;
745
746 /**
747 * Programmed wait states for write accesses: <br>
748 * Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock.<br>
749 * 00000B: 1 wait state <br>
750 * 00001B: 1 wait state <br>
751 * 00010B: 2 wait state <br>
752 * ... <br>
753 * 11110B: 30 wait states <br>
754 * 11111B: 31 wait states <br>
755 */
756 uint32_t ebu_programmed_wait_states_for_write_accesses : 5;
757
758 /**
759 * Data Hold Cycles for Write Accesses
760 * This bit field determines the basic number of Data Hold phase clock cycles during write accesses.<br>
761 * 0000B: No recovery phase clock cycles available <br>
762 * 0001B: 1 clock cycle selected <br>
763 * ... <br>
764 * 1110B: 14 clock cycles selected <br>
765 * 1111B: 15 clock cycles selected <br>
766 */
767 uint32_t ebu_data_hold_cycles_for_write_accesses : 4;
768 /**<
769 * Frequency of external clock at pin BFCLKO (::XMC_EBU_FREQ_EXT_CLK_PIN_t)
770 */
771 uint32_t ebu_freq_ext_clk_pin : 2;
772 /**
773 * EBU extended data (::XMC_EBU_EXT_DATA_t)
774 */
775 uint32_t ebu_ext_data : 2;
776 /**
777 * Command delay cycles: <br>
778 * This bit field determines the basic number of Command Delay phase clock cycles.<br>
779 * 0000B: 0 clock cycle selected <br>
780 * 0001B: 1 clock cycle selected <br>
781 * ... <br>
782 * 1110B: 14 clock cycles selected <br>
783 * 1111B: 15 clock cycles selected <br>
784 */
785 uint32_t command_delay_lines : 4;
786 /** Address hold cycles: <br>
787 * This bit field determines the number of clock cycles of the address hold phase.<br>
788 * 0000B: 0 clock cycle selected <br>
789 * 0001B: 1 clock cycle selected <br>
790 * ... <br>
791 * 1110B: 14 clock cycles selected <br>
792 * 1111B: 15 clock cycles selected <br>
793 */
794 uint32_t address_hold_cycles : 4;
795 /**
796 * Address cycles: <br>
797 * This bit field determines the number of clock cycles of the address phase.<br>
798 * 0000B: 1 clock cycle selected <br>
799 * 0001B: 1 clock cycle selected <br>
800 * ... <br>
801 * 1110B: 14 clock cycles selected <br>
802 * 1111B: 15 clock cycles selected <br>
803 */
804 uint32_t address_cycles : 4;
805 };
806 };
807 }XMC_EBU_BUS_WRITE_CONFIG_t;
808
809 /**
810 * SDRAM configuration structure <br>
811 *
812 * The structure is a placeholder for setting (and obtaining) the SDRAM configuration,
813 * operation mode configuration and the right refresh parameters. The XMC_EBU_ConfigureSdram()
814 * can be used to populate the structure with the SDRAM operation mode and
815 * refresh parameters configuration.
816 */
817 typedef struct XMC_EBU_SDRAM_CONFIG
818 {
819 /* EBU SDRAM control parameters */
820 union
821 {
822 uint32_t raw0;
823 struct
824 {
825 /**
826 * Number of clock cycles between row activate command and a precharge
827 * command
828 */
829 uint32_t ebu_row_precharge_delay_counter : 4;
830 /**
831 * (CRFSH) Number of refresh commands issued during powerup init sequence:
832 * Perform CRFSH + 1 refresh cycles
833 */
834 uint32_t ebu_init_refresh_commands_counter : 4;
835 /**
836 * (CRSC) Number of NOP cycles after a mode register set command:
837 * Insert CRSC + 1 NOP cycles
838 */
839 uint32_t ebu_mode_register_set_up_time : 2;
840 /**
841 * (CRP) Number of NOP cycles inserted after a precharge command:
842 * Insert CRP + 1 NOP cycles
843 */
844 uint32_t ebu_row_precharge_time_counter : 2;
845 /**
846 * Number of address bits from bit 0 to be used for column address
847 */
848 uint32_t ebu_sdram_width_of_column_address : 2;
849 /**
850 * (CRCD) Number of NOP cycles between a row address and a column
851 * address: Insert CRCD + 1 NOP cycles
852 */
853 uint32_t ebu_sdram_row_to_column_delay_counter : 2;
854 /**
855 * Row cycle time counter: Insert (CRCE * 8) + CRC + 1 NOP cycles
856 */
857 uint32_t ebu_sdram_row_cycle_time_counter : 3;
858 /**
859 * Mask for row tag
860 */
861 uint32_t ebu_sdram_mask_for_row_tag : 3;
862 /**
863 * Mask for bank tag
864 */
865 uint32_t ebu_sdram_mask_for_bank_tag : 3;
866 /**
867 * Extension to the Row cycle time counter (CRCE)
868 */
869 uint32_t ebu_sdram_row_cycle_time_counter_extension : 3;
870 /**
871 * Disable SDRAM clock output
872 */
873 uint32_t ebu_sdram_clk_output : 1;
874 /**
875 * Power Save Mode used for gated clock mode
876 */
877 uint32_t ebu_sdram_pwr_mode : 2;
878 /**
879 * SDRAM clock mode select
880 */
881 uint32_t ebu_sdram_clk_mode : 1;
882 };
883 };
884 /* EBU SDRAM mode parameters */
885 union
886 {
887 uint32_t raw1;
888 struct
889 {
890 /**
891 * Number of locations can be accessed with a single command
892 */
893 uint32_t ebu_sdram_burst_length : 3;
894 uint32_t : 1;
895 /**
896 * Number of clocks between a READ command and the availability
897 * of data
898 */
899 uint32_t ebu_sdram_casclk_mode : 3;
900 uint32_t : 8;
901 /**
902 * Cold start
903 */
904 uint32_t ebu_sdram_cold_start: 1;
905 /**
906 * Value to be written to the extended mode register of a mobile
907 * SDRAM device
908 */
909 uint32_t ebu_sdram_extended_operation_mode : 12;
910 /**
911 * Value to be written to the bank select pins of a mobile SDRAM
912 * device during an extended mode register write operation
913 */
914 uint32_t ebu_sdram_extended_operation_bank_select : 4;
915 };
916 };
917 /* EBU SDRAM refresh parameters */
918 union
919 {
920 uint32_t raw2;
921 struct
922 {
923 /**
924 * Number of refresh counter period:
925 * Refresh period is 'num_refresh_counter_period' x 64 clock cycles
926 */
927 uint32_t ebu_sdram_num_refresh_counter_period : 6;
928 /**
929 * Number of refresh commands
930 */
931 uint32_t ebu_sdram_num_refresh_cmnds : 3;
932 uint32_t : 1;
933 /**
934 * If 1, the self refresh exit command is issued to all SDRAM devices
935 * regardless of their attachment to type 0 or type 1
936 */
937 uint32_t ebu_sdram_self_refresh_exit : 1;
938 uint32_t : 1;
939 /**
940 * If "1", the self refresh entry command is issued to all SDRAM devices,
941 * regardless regardless of their attachment to type 0 or type 1
942 */
943 uint32_t ebu_sdram_self_refresh_entry : 1;
944 /**
945 * If 1, memory controller will automatically issue the "self refresh
946 * entry" command to all SDRAM devices when it gives up control of the
947 * external bus. It will also automatically issue "self refresh exit"
948 * when it regains control of the bus
949 */
950 uint32_t ebu_sdram_auto_self_refresh : 1;
951 /**
952 * Extended number of refresh counter period
953 */
954 uint32_t ebu_sdram_extended_refresh_counter_period : 2;
955 /**
956 * Number of NOP cycles inserted after a self refresh exit before a
957 * command is permitted to the SDRAM/DDRAM
958 */
959 uint32_t ebu_sdram_self_refresh_exit_delay : 8;
960 /**
961 * If 1, an auto refresh cycle will be performed; If 0, no refresh will
962 * be performed
963 */
964 uint32_t ebu_sdram_auto_refresh : 1;
965 /**
966 * Number of NOPs after the SDRAM controller exits power down before an
967 * active command is permitted
968 */
969 uint32_t ebu_sdram_delay_on_power_down_exit : 3;
970 uint32_t : 4;
971 };
972 };
973 } XMC_EBU_SDRAM_CONFIG_t;
974
975 /* Anonymous structure/union guard end */
976 #if defined (__CC_ARM)
977 #pragma pop
978 #elif defined (__TASKING__)
979 #pragma warning restore
980 #endif
981
982 /**
983 * EBU region initialization with read configurations <br>
984 *
985 * The structure presents a convenient way to set/obtain the read and read timing
986 * configurations for a region of EBU. The XMC_EBU_ConfigureRegion() can be
987 * used to populate the structure with the read configuration values of EBU
988 */
989 typedef struct XMC_EBU_REGION_READ_CONFIG
990 {
991 const uint32_t ebu_region_no; /**< Number of region*/
992 XMC_EBU_BUS_READ_CONFIG_t ebu_bus_read_config; /**< Read configuration and access parameters structure */
993 } XMC_EBU_REGION_READ_CONFIG_t;
994
995 /**
996 * EBU region initialization with write configurations <br>
997 *
998 * The structure presents a convenient way to set/obtain the write and write
999 * timing configurations for a region of EBU. The XMC_EBU_ConfigureRegion()
1000 * can be used to populate the structure with the write configuration
1001 * values of EBU.
1002 */
1003 typedef struct XMC_EBU_REGION_WRITE_CONFIG
1004 {
1005 const uint32_t ebu_region_no; /**< Number of refresh counter period */
1006 XMC_EBU_BUS_WRITE_CONFIG_t ebu_bus_write_config; /**< Write configuration and access parameters structure */
1007 } XMC_EBU_REGION_WRITE_CONFIG_t;
1008
1009 /**
1010 * EBU region initialization with read and write configurations <br>
1011 *
1012 * The structure presents a convenient way to set/obtain the read, read timing,
1013 * write and write timing configurations for a region of EBU. The
1014 * XMC_EBU_ConfigureRegion() can be used to populate the structure with the
1015 * region read and write configuration values of EBU.
1016 */
1017 typedef struct XMC_EBU_REGION
1018 {
1019 XMC_EBU_REGION_READ_CONFIG_t read_config;
1020 XMC_EBU_REGION_WRITE_CONFIG_t write_config;
1021 } XMC_EBU_REGION_t;
1022
1023 /**
1024 * EBU global configurations <br>
1025 *
1026 * The structure presents a convenient way to set/obtain the global configurations
1027 * of the EBU like clock, mode and GPIO mode. The XMC_EBU_Init() can be
1028 * used to populate the structure with the region read and write configuration
1029 * values of EBU.
1030 */
1031 typedef struct XMC_EBU_CONFIG
1032 {
1033 XMC_EBU_CLK_CONFIG_t ebu_clk_config; /**< Clock configuration structure */
1034 XMC_EBU_MODE_CONFIG_t ebu_mode_config; /**< Mode configuration structure */
1035 XMC_EBU_FREE_PINS_TO_GPIO_t ebu_free_pins_to_gpio; /**< Free allocated EBU ports for GPIO */
1036 } XMC_EBU_CONFIG_t;
1037
1038 /**
1039 * External Bus Unit (EBU) device structure <br>
1040 *
1041 * The structure represents a collection of all hardware registers
1042 * used to configure the EBU peripheral on the XMC4500 microcontroller.
1043 * The registers can be accessed with ::XMC_EBU.
1044 */
1045 typedef struct
1046 {
1047 __IO uint32_t CLC;
1048 __IO uint32_t MODCON;
1049 __I uint32_t ID;
1050 __IO uint32_t USERCON;
1051 __I uint32_t RESERVED0[2];
1052 __IO uint32_t ADDRSEL[4];
1053 struct
1054 {
1055 __IO uint32_t RDCON;
1056 __IO uint32_t RDAPR;
1057 __IO uint32_t WRCON;
1058 __IO uint32_t WRAPR;
1059 } BUS[4];
1060 __IO uint32_t SDRMCON;
1061 __IO uint32_t SDRMOD;
1062 __IO uint32_t SDRMREF;
1063 __I uint32_t SDRSTAT;
1064 } XMC_EBU_t;
1065
1066 /**********************************************************************************************************************
1067 * API PROTOTYPES
1068 **********************************************************************************************************************/
1069
1070 #ifdef __cplusplus
1071 extern "C" {
1072 #endif
1073
1074 /**
1075 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1076 * @param config Constant pointer to a constant ::XMC_EBU_CONFIG_t structure containing the
1077 * clock mode and clock configuration.
1078 * @return XMC_EBU_STATUS_t Always returns XMC_EBU_STATUS_OK (Only register assignment statements)
1079 *
1080 * \par<b>Description: </b><br>
1081 * Initialize the EBU peripheral <br>
1082 *
1083 * \par
1084 * The function enables the EBU peripheral, configures time values for clock mode, div2
1085 * clock mode, mode configuration, SDRAM tristate, external clock, arbitration, timeout
1086 * control, ALE mode and configuration to free up the allocated EBU ports for GPIO
1087 * functionality (if required).
1088 */
1089 XMC_EBU_STATUS_t XMC_EBU_Init(XMC_EBU_t *const ebu, const XMC_EBU_CONFIG_t *const config);
1090
1091 /**
1092 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1093 * @param config Constant pointer to a constant ::XMC_EBU_SDRAM_CONFIG_t structure containing
1094 * the SDRAM configuration, operation mode configuration and right refresh
1095 * parameters
1096 * @return None
1097 *
1098 * \par<b>Description: </b><br>
1099 * Configures the SDRAM <br>
1100 *
1101 * \par
1102 * The function enables the SDRAM, sets SDRAM configuration parameters such as operation
1103 * mode and refresh parameters. Please see ::XMC_EBU_SDRAM_CONFIG_t for more information.
1104 */
1105 void XMC_EBU_ConfigureSdram(XMC_EBU_t *const ebu, const XMC_EBU_SDRAM_CONFIG_t *const config);
1106
1107 /**
1108 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1109 * @param region Constant pointer to a constant ::XMC_EBU_REGION_t structure containing the
1110 * read, read timing, write and write timing configurations for a region of
1111 * EBU
1112 * @return None
1113 *
1114 * \par<b>Description: </b><br>
1115 * Configures the SDRAM <br>
1116 *
1117 * \par
1118 * The function configures the EBU region read, read timing, write and write timing parameter
1119 * configuration. It also configures the region registers for read and write accesses. Please
1120 * see ::XMC_EBU_REGION_t for more information.
1121 *
1122 */
1123 void XMC_EBU_ConfigureRegion(XMC_EBU_t *const ebu, const XMC_EBU_REGION_t *const region);
1124
1125 /**
1126 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1127 * @return None
1128 *
1129 * \par<b>Description: </b><br>
1130 * Enable EBU peripheral <br>
1131 *
1132 * \par
1133 * The function de-asserts the peripheral reset. The peripheral needs to be initialized.
1134 * It also enables the control of the EBU.
1135 *
1136 * \par<b>Related APIs:</b><br>
1137 * XMC_EBU_Disable(), XMC_SCU_RESET_AssertPeripheralReset()
1138 */
XMC_EBU_Enable(XMC_EBU_t * const ebu)1139 __STATIC_INLINE void XMC_EBU_Enable(XMC_EBU_t *const ebu)
1140 {
1141 XMC_ASSERT("XMC_EBU_Enable: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1142 XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_EBU);
1143 ebu->CLC &= ~EBU_CLC_DISR_Msk;
1144 }
1145
1146 /**
1147 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1148 * @return None
1149 *
1150 * \par<b>Description: </b><br>
1151 * Disable EBU peripheral <br>
1152 *
1153 * \par
1154 * The function asserts the peripheral reset. It also disables the control of the EBU.
1155 *
1156 * \par<b>Related APIs:</b><br>
1157 * XMC_EBU_Enable(), XMC_SCU_RESET_DeassertPeripheralReset()
1158 */
XMC_EBU_Disable(XMC_EBU_t * const ebu)1159 __STATIC_INLINE void XMC_EBU_Disable(XMC_EBU_t *const ebu)
1160 {
1161 XMC_ASSERT("XMC_EBU_Disable: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1162 ebu->CLC |= EBU_CLC_DISR_Msk;
1163 XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_EBU);
1164 }
1165
1166 /**
1167 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1168 * @param clk_status Constant structure ::XMC_EBU_CLK_STATUS_t, containing the
1169 * disable status, clock mode status, DIV2 clock mode status
1170 * and clock divide ratio
1171 * @return Status Returns clock status, disable status, clock mode status, DIV2 clock
1172 * mode status and clock divide ratio
1173 *
1174 * \par<b>Description: </b><br>
1175 * Gets the clock status of EBU peripheral <br>
1176 *
1177 * \par
1178 * The function returns the clock staus of the EBU peripheral. The return value will
1179 * indicate the following parameters: <br>
1180 * 1) Is EBU disabled? <br>
1181 * 2) Clocking mode <br>
1182 * 3) DIV2 clocking mode <br>
1183 * 4) Clock divide ratio <br>
1184 *
1185 * \par<b>Related APIs:</b><br>
1186 * XMC_EBU_Enable(), XMC_EBU_Disable() and XMC_EBU_CLKDivideRatio()
1187 */
XMC_EBU_GetCLKStatus(XMC_EBU_t * const ebu,const XMC_EBU_CLK_STATUS_t clk_status)1188 __STATIC_INLINE uint32_t XMC_EBU_GetCLKStatus(XMC_EBU_t *const ebu, const XMC_EBU_CLK_STATUS_t clk_status)
1189 {
1190 XMC_ASSERT("XMC_EBU_GetCLKStatus: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1191 return (uint32_t)(ebu->CLC & clk_status);
1192 }
1193
1194 /**
1195 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1196 * @param clock_divide_ratio Structure ::XMC_EBU_CLOCK_DIVIDE_RATIO_t, containing the
1197 * clock division factors of 1, 2, 3 and 4 respectively
1198 * @return None
1199 *
1200 * \par<b>Description: </b><br>
1201 * Sets the clock divide ratio for EBU peripheral <br>
1202 *
1203 * \par
1204 * The function sets the CLC.EBUDIV bit-field to configure the clock divide ratio
1205 * value (input clock divide by factor).
1206 *
1207 * \par<b>Related APIs:</b><br>
1208 * XMC_EBU_Enable(), XMC_EBU_Disable() and XMC_EBU_GetCLKStatus()
1209 */
XMC_EBU_CLKDivideRatio(XMC_EBU_t * ebu,XMC_EBU_CLOCK_DIVIDE_RATIO_t clock_divide_ratio)1210 __STATIC_INLINE void XMC_EBU_CLKDivideRatio(XMC_EBU_t *ebu, XMC_EBU_CLOCK_DIVIDE_RATIO_t clock_divide_ratio)
1211 {
1212 XMC_ASSERT("XMC_EBU_CLKDivideRatio: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1213 ebu->CLC |= ((clock_divide_ratio << EBU_CLC_EBUDIV_Pos) & EBU_CLC_EBUDIV_Msk);
1214 }
1215
1216 /**
1217 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1218 * @return None
1219 *
1220 * \par<b>Description: </b><br>
1221 * Sets the SDRAM self refresh exit (Power up) <br>
1222 *
1223 * \par
1224 * The function sets the SDRMREF.SELFREX bit to issue the self refresh command to
1225 * all the SDRAM units. This ensures that the SDRAM units come out of the power down
1226 * mode. The function also resets the bit SDRMREF.SELFRENST(Self refresh entry status).
1227 */
XMC_EBU_SdramSetSelfRefreshExit(XMC_EBU_t * const ebu)1228 __STATIC_INLINE void XMC_EBU_SdramSetSelfRefreshExit(XMC_EBU_t *const ebu)
1229 {
1230 XMC_ASSERT("XMC_EBU_SdramSetSelfRefreshExit: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1231 ebu->SDRMREF |= EBU_SDRMREF_SELFREX_Msk;
1232 }
1233
1234 /**
1235 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1236 * @return None
1237 *
1238 * \par<b>Description: </b><br>
1239 * Sets the SDRAM self refresh entry <br>
1240 *
1241 * \par
1242 * The function sets the SDRMREF.SELFREN bit-field to issue the self refresh command
1243 * to all the SDRAM units. This ensures that the SDRAM units enter the power down mode
1244 * after pre-charge. The function also resets the bit SDRMREF.SELFREXST(Self refresh
1245 * exit status).
1246 */
XMC_EBU_SdramSetSelfRefreshEntry(XMC_EBU_t * const ebu)1247 __STATIC_INLINE void XMC_EBU_SdramSetSelfRefreshEntry(XMC_EBU_t *const ebu)
1248 {
1249 XMC_ASSERT("XMC_EBU_SdramSetSelfRefreshEntry: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1250 ebu->SDRMREF |= EBU_SDRMREF_SELFREN_Msk;
1251 }
1252
1253 /**
1254 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1255 * @return None
1256 *
1257 * \par<b>Description: </b><br>
1258 * Resets the SDRAM self refresh exit (Power up) <br>
1259 *
1260 * \par
1261 * The function resets the SDRMREF.SELFREX bit-field to stop issuing the self
1262 * refresh command to all the SDRAM units connected to the bus. This ensures that
1263 * the SDRAM units don't come out of the power down mode.
1264 *
1265 */
XMC_EBU_SdramResetSelfRefreshExit(XMC_EBU_t * const ebu)1266 __STATIC_INLINE void XMC_EBU_SdramResetSelfRefreshExit(XMC_EBU_t *const ebu)
1267 {
1268 XMC_ASSERT("XMC_EBU_SdramResetSelfRefreshExit: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1269 ebu->SDRMREF &= ~EBU_SDRMREF_SELFREX_Msk;
1270 }
1271
1272 /**
1273 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1274 * @return None
1275 *
1276 * \par<b>Description: </b><br>
1277 * Resets the SDRAM self refresh entry <br>
1278 *
1279 * \par
1280 * The function resets the SDRMREF.SELFREN bit-field to stop issuing the self
1281 * refresh command to all the SDRAM units. This ensures that the SDRAM units
1282 * don't go into the power down mode after the pre-charge is all done.
1283 *
1284 */
XMC_EBU_SdramResetSelfRefreshEntry(XMC_EBU_t * const ebu)1285 __STATIC_INLINE void XMC_EBU_SdramResetSelfRefreshEntry(XMC_EBU_t *const ebu)
1286 {
1287 XMC_ASSERT("XMC_EBU_SdramResetSelfRefreshEntry: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1288 ebu->SDRMREF &= ~EBU_SDRMREF_SELFREN_Msk;
1289 }
1290
1291 /**
1292 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1293 * @return None
1294 *
1295 * \par<b>Description: </b><br>
1296 * Sets the SDRAM auto refresh on self refresh exit <br>
1297 *
1298 * \par
1299 * The function sets the SDRMREF.ARFSH bit-field to enable an auto refresh cycle
1300 * on existing self refresh before the self refresh exit delay.
1301 *
1302 * \par<b>Related APIs: </b><br>
1303 * XMC_EBU_SdramDisableAutoRefreshSelfRefreshExit()
1304 */
XMC_EBU_SdramEnableAutoRefreshSelfRefreshExit(XMC_EBU_t * const ebu)1305 __STATIC_INLINE void XMC_EBU_SdramEnableAutoRefreshSelfRefreshExit(XMC_EBU_t *const ebu)
1306 {
1307 XMC_ASSERT("XMC_EBU_SdramEnableAutoRefreshSelfRefreshExit: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1308 ebu->SDRMREF |= EBU_SDRMREF_ARFSH_Msk;
1309 }
1310
1311 /**
1312 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1313 * @return None
1314 *
1315 * \par<b>Description: </b><br>
1316 * Resets the SDRAM auto refresh on self refresh exit <br>
1317 *
1318 * \par
1319 * The function resets the SDRMREF.ARFSH bit to disable an auto refresh cycle
1320 * on existing self refresh before the self refresh exit delay. No refresh will be
1321 * performed.
1322 *
1323 * \par<b>Related APIs: </b><br>
1324 * XMC_EBU_SdramEnableAutoRefreshSelfRefreshExit()
1325 */
XMC_EBU_SdramDisableAutoRefreshSelfRefreshExit(XMC_EBU_t * const ebu)1326 __STATIC_INLINE void XMC_EBU_SdramDisableAutoRefreshSelfRefreshExit(XMC_EBU_t *const ebu)
1327 {
1328 XMC_ASSERT("XMC_EBU_SdramDisableAutoRefreshSelfRefreshExit: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1329 ebu->SDRMREF &= ~EBU_SDRMREF_ARFSH_Msk;
1330 }
1331
1332 /**
1333 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1334 * @return None
1335 *
1336 * \par<b>Description: </b><br>
1337 * Sets the SDRAM automatic self refresh <br>
1338 *
1339 * \par
1340 * The function sets the SDRMREF.AUTOSELFR bit-field. When set, the memory controller
1341 * automatically issues the self refresh entry command to all SDRAM units
1342 * devices when it gives up control of the external bus. It will also automatically
1343 * issue the self refresh exit command when it regains control of the bus.
1344 *
1345 * \par<b>Related APIs: </b><br>
1346 * XMC_EBU_SdramDisableAutomaticSelfRefresh()
1347 */
XMC_EBU_SdramEnableAutomaticSelfRefresh(XMC_EBU_t * const ebu)1348 __STATIC_INLINE void XMC_EBU_SdramEnableAutomaticSelfRefresh(XMC_EBU_t *const ebu)
1349 {
1350 XMC_ASSERT("XMC_EBU_SdramEnableAutomaticSelfRefresh: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1351 ebu->SDRMREF |= EBU_SDRMREF_AUTOSELFR_Msk;
1352 }
1353
1354 /**
1355 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1356 * @return None
1357 *
1358 * \par<b>Description: </b><br>
1359 * Resets the SDRAM automatic self refresh <br>
1360 *
1361 * \par
1362 * The function resets the SDRMREF.AUTOSELFR bit-field. When reset, the memory controller
1363 * doesn't issue the self refresh entry command when it gives up control of the external
1364 * bus. It will also not issue the self refresh exit command when it regains control of
1365 * the bus.
1366 *
1367 * \par<b>Related APIs: </b><br>
1368 * XMC_EBU_SdramEnableAutomaticSelfRefresh()
1369 */
XMC_EBU_SdramDisableAutomaticSelfRefresh(XMC_EBU_t * const ebu)1370 __STATIC_INLINE void XMC_EBU_SdramDisableAutomaticSelfRefresh(XMC_EBU_t *const ebu)
1371 {
1372 XMC_ASSERT("XMC_EBU_SdramDisableAutomaticSelfRefresh: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1373 ebu->SDRMREF &= ~EBU_SDRMREF_AUTOSELFR_Msk;
1374 }
1375
1376 /**
1377 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1378 * @return bool Returns if the arbitration mode is selected or not
1379 *
1380 * \par<b>Description: </b><br>
1381 * Check if arbitration mode of EBU peripheral is selected
1382 *
1383 * \par
1384 * The bit field ARBMODE of MODCON indicates the selected arbitration mode of the
1385 * EBU. The follwing are the supported arbitration modes: <br>
1386 * 1) Arbiter Mode arbitration mode <br>
1387 * 2) Participant arbitration mode <br>
1388 * 3) Sole Master arbitration mode <br>
1389 *
1390 * If any of the above modes are selected, the function returns "true". It returns
1391 * false otherwise.
1392 *
1393 * \par<b>Related APIs: </b><br>
1394 * XMC_EBU_Init() \n\n\n
1395 */
XMC_EBU_IsBusAribitrationSelected(XMC_EBU_t * const ebu)1396 __STATIC_INLINE bool XMC_EBU_IsBusAribitrationSelected(XMC_EBU_t *const ebu)
1397 {
1398 XMC_ASSERT("XMC_EBU_IsBusAribitrationSelected: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1399 return (bool)((ebu->MODCON & EBU_MODCON_ARBMODE_Msk) != 0);
1400 }
1401
1402 /**
1403 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1404 * @param ebu_addr_select_en Choose between a memory region enable or an alternate region enable
1405 * @param ebu_region_n A valid region number for which enable and protection settings
1406 * need to be configured
1407 * @return None
1408 *
1409 * \par<b>Description: </b><br>
1410 * Controls the enable and protection settings of a region <br>
1411 *
1412 * \par
1413 * The function controls the enable and protection settings of a memory or alternate
1414 * region. It configures the memory region enable, alternate region enable and the memory
1415 * region's write protection. The bit-fields ADDRSEL.REGENAB, ADDRSEL.ALTENAB and
1416 * ADDRSEL.WPROT are configured.
1417 *
1418 * \par<b>Related APIs: </b><br>
1419 * XMC_EBU_AddressSelectDisable()
1420 */
XMC_EBU_AddressSelectEnable(XMC_EBU_t * const ebu,uint32_t ebu_addr_select_en,const uint32_t ebu_region_n)1421 __STATIC_INLINE void XMC_EBU_AddressSelectEnable(XMC_EBU_t *const ebu,
1422 uint32_t ebu_addr_select_en,
1423 const uint32_t ebu_region_n)
1424 {
1425 XMC_ASSERT("XMC_EBU_AddressSelectEnable: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1426 ebu->ADDRSEL[ebu_region_n] |= ebu_addr_select_en;
1427 while (!XMC_EBU_IsBusAribitrationSelected(ebu));
1428 }
1429
1430 /**
1431 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1432 * @param ebu_addr_select_dis Choose between a memory region disable or an alternate
1433 * region disable
1434 * @param ebu_region_n A valid region number for which disable and protection
1435 * settings configured
1436 * @return None
1437 *
1438 * \par<b>Description: </b><br>
1439 * Controls the disable and protection settings of a region <br>
1440 *
1441 * \par
1442 * The function controls the disable and protection settings of a memory or alternate
1443 * region. It configures the memory region disable, alternate region disable and the
1444 * memory region write protect disable for write accesses. The bits ADDRSEL.REGENAB,
1445 * ADDRSEL.ALTENAB and ADDRSEL.WPROT are configured.
1446 *
1447 * \par<b>Related APIs: </b><br>
1448 * XMC_EBU_AddressSelectEnable()
1449 */
XMC_EBU_AddressSelectDisable(XMC_EBU_t * const ebu,uint32_t ebu_addr_select_dis,const uint32_t ebu_region_n)1450 __STATIC_INLINE void XMC_EBU_AddressSelectDisable(XMC_EBU_t *const ebu,
1451 uint32_t ebu_addr_select_dis,
1452 const uint32_t ebu_region_n)
1453 {
1454 XMC_ASSERT("XMC_EBU_AddressSelectDisable: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1455 ebu->ADDRSEL[ebu_region_n] &= ~ebu_addr_select_dis;
1456 }
1457
1458 /**
1459 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1460 * @param ebu_buswcon_status Enumeration of type ::XMC_EBU_BUSWCON_SELECT_t, representing
1461 * values for non-array access and device addressing modes.
1462 * @param ebu_region_n A valid region number for which status pertaining to WRITE is required
1463 * @return Status Status of non-array access and device addressing mode
1464 *
1465 * \par<b>Description: </b><br>
1466 * Gets WRITE specific status for a region <br>
1467 *
1468 * \par
1469 * The function gets status of the various WRITE specific settings for a region. Status for
1470 * non-array access enable and device addressing mode are obtained. The status bits of the
1471 * BUSWCON register are returned.
1472 *
1473 * \par<b>Related APIs: </b><br>
1474 * XMC_EBU_ConfigureRegion()
1475 */
XMC_EBU_GetBusWriteConfStatus(XMC_EBU_t * const ebu,const XMC_EBU_BUSWCON_SELECT_t ebu_buswcon_status,const uint32_t ebu_region_n)1476 __STATIC_INLINE uint32_t XMC_EBU_GetBusWriteConfStatus(XMC_EBU_t *const ebu,
1477 const XMC_EBU_BUSWCON_SELECT_t ebu_buswcon_status,
1478 const uint32_t ebu_region_n)
1479 {
1480 XMC_ASSERT("XMC_EBU_GetBusWriteConfStatus: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1481 return (ebu->BUS[ebu_region_n].WRCON & ebu_buswcon_status);
1482 }
1483
1484 /**
1485 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1486 * @return Status SDRAM error or busy states
1487 *
1488 * \par<b>Description: </b><br>
1489 * Gets SDRAM error or busy states <br>
1490 *
1491 * \par
1492 * The function gets SDRAM read error, refresh error and busy states. The bit-fields of SDRSTAT
1493 * indicate the various states. REFERR reflects a failed previous refresh request collision
1494 * with a new request. SDRMBUSY indicates the status of power-up initialization sequence. It
1495 * indicates if it is running or not running. SDERR indicates if the SDRAM controller has
1496 * detected an error when returning the read data.
1497 *
1498 * \par<b>Related APIs: </b><br>
1499 * XMC_EBU_ConfigureSdram()
1500 */
XMC_EBU_SdramGetStatus(XMC_EBU_t * const ebu)1501 __STATIC_INLINE uint32_t XMC_EBU_SdramGetStatus(XMC_EBU_t *const ebu)
1502 {
1503 XMC_ASSERT("XMC_EBU_SdramGetStatus: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1504 return (uint32_t)(ebu->SDRSTAT);
1505 }
1506
1507 /**
1508 * @param ebu Constant pointer to ::XMC_EBU_t, pointing to the EBU base address
1509 * @param sdram_rfrsh_status Constant enum of type ::XMC_EBU_SDRAM_RFRSH_STATUS_t
1510 * @return Status Status of self refresh entry and exit command issue
1511 *
1512 * \par<b>Description: </b><br>
1513 * Gets SDRAM refresh status <br>
1514 *
1515 * \par
1516 * The function gets SDRAM refresh status for self refresh entry/exit command successful issue.
1517 * The bit-fields of SDRMREF indicate various states: <br>
1518 * SELFRENST reflects successful issue of self refresh entry command <br>
1519 * SELFREXST reflects successful issue of self refresh exit command <br>
1520 *
1521 * \par<b>Related APIs: </b><br>
1522 * XMC_EBU_SdramResetSelfRefreshEntry(), XMC_EBU_SdramResetSelfRefreshExit()
1523 */
XMC_EBU_SdramGetRefreshStatus(XMC_EBU_t * const ebu,const XMC_EBU_SDRAM_RFRSH_STATUS_t sdram_rfrsh_status)1524 __STATIC_INLINE uint32_t XMC_EBU_SdramGetRefreshStatus(XMC_EBU_t *const ebu,
1525 const XMC_EBU_SDRAM_RFRSH_STATUS_t sdram_rfrsh_status)
1526 {
1527 XMC_ASSERT("XMC_EBU_SdramGetRefreshStatus: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
1528 return (uint32_t)(ebu->SDRMREF & sdram_rfrsh_status);
1529 }
1530
1531
1532 #ifdef __cplusplus
1533 }
1534 #endif
1535
1536 /**
1537 * @}
1538 */
1539
1540 /**
1541 * @}
1542 */
1543
1544 #endif /* defined (EBU) */
1545
1546 #endif /* XMC_EBU_H */
1547
