1 /* ========================================================================== 2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $ 3 * $Revision: #91 $ 4 * $Date: 2010/11/29 $ 5 * $Change: 1636033 $ 6 * 7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, 8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless 9 * otherwise expressly agreed to in writing between Synopsys and you. 10 * 11 * The Software IS NOT an item of Licensed Software or Licensed Product under 12 * any End User Software License Agreement or Agreement for Licensed Product 13 * with Synopsys or any supplement thereto. You are permitted to use and 14 * redistribute this Software in source and binary forms, with or without 15 * modification, provided that redistributions of source code must retain this 16 * notice. You may not view, use, disclose, copy or distribute this file or 17 * any information contained herein except pursuant to this license grant from 18 * Synopsys. If you do not agree with this notice, including the disclaimer 19 * below, then you are not authorized to use the Software. 20 * 21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 31 * DAMAGE. 32 * ========================================================================== */ 33 34 /* 35 * @file xmc_usbd_regs.h 36 * @date 2015-02-20 37 * 38 * @cond 39 ********************************************************************************************************************* 40 * XMClib v2.1.24 - XMC Peripheral Driver Library 41 * 42 * Copyright (c) 2015-2019, Infineon Technologies AG 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 46 * following conditions are met: 47 * 48 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 49 * disclaimer. 50 * 51 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 52 * disclaimer in the documentation and/or other materials provided with the distribution. 53 * 54 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 55 * products derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 58 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 60 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 * 65 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 66 * Infineon Technologies AG dave@infineon.com). 67 ********************************************************************************************************************* 68 * 69 * Change History 70 * -------------- 71 * 72 * 2015-02-20: 73 * - Initial version 74 * 75 * @endcond 76 * 77 */ 78 79 #ifndef __DWC_OTG_REGS_H__ 80 #define __DWC_OTG_REGS_H__ 81 82 83 /** 84 * @file 85 * 86 * This file contains the data structures for accessing the DWC_otg core registers. 87 * 88 * The application interfaces with the HS OTG core by reading from and 89 * writing to the Control and Status Register (CSR) space through the 90 * AHB Slave interface. These registers are 32 bits wide, and the 91 * addresses are 32-bit-block aligned. 92 * CSRs are classified as follows: 93 * - Core Global Registers 94 * - Device Mode Registers 95 * - Device Global Registers 96 * - Device Endpoint Specific Registers 97 * - Host Mode Registers 98 * - Host Global Registers 99 * - Host Port CSRs 100 * - Host Channel Specific Registers 101 * 102 * Only the Core Global registers can be accessed in both Device and 103 * Host modes. When the HS OTG core is operating in one mode, either 104 * Device or Host, the application must not access registers from the 105 * other mode. When the core switches from one mode to another, the 106 * registers in the new mode of operation must be reprogrammed as they 107 * would be after a power-on reset. 108 */ 109 110 /** Register Definitions */ 111 /** Maximum endpoint channel */ 112 #define MAX_EPS_CHANNELS ( 7U ) 113 /** Maximum periodic fifos in usb core */ 114 #define MAX_PERIO_FIFOS ( 1U ) 115 /** Maximum tx fifos */ 116 #define MAX_TX_FIFOS ( 14U ) 117 /* dwc_dma_t type definition and register header file inclusion */ 118 typedef void* dwc_dma_t; 119 120 /****************************************************************************/ 121 /** DWC_otg Core registers . 122 * The dwc_otg_core_global_regs structure defines the size 123 * and relative field offsets for the Core Global registers. 124 */ 125 typedef struct dwc_otg_core_global_regs { 126 /** OTG Control and Status Register. <i>Offset: 000h</i> */ 127 volatile uint32_t gotgctl; 128 /** OTG Interrupt Register. <i>Offset: 004h</i> */ 129 volatile uint32_t gotgint; 130 /**Core AHB Configuration Register. <i>Offset: 008h</i> */ 131 volatile uint32_t gahbcfg; 132 133 #define DWC_GLBINTRMASK 0x0001 134 #define DWC_DMAENABLE 0x0020 135 #define DWC_NPTXEMPTYLVL_EMPTY 0x0080 136 #define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000 137 #define DWC_PTXEMPTYLVL_EMPTY 0x0100 138 #define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000 139 140 /**Core USB Configuration Register. <i>Offset: 00Ch</i> */ 141 volatile uint32_t gusbcfg; 142 /**Core Reset Register. <i>Offset: 010h</i> */ 143 volatile uint32_t grstctl; 144 /**Core Interrupt Register. <i>Offset: 014h</i> */ 145 volatile uint32_t gintsts; 146 /**Core Interrupt Mask Register. <i>Offset: 018h</i> */ 147 volatile uint32_t gintmsk; 148 /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */ 149 volatile uint32_t grxstsr; 150 /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/ 151 volatile uint32_t grxstsp; 152 /**Receive FIFO Size Register. <i>Offset: 024h</i> */ 153 volatile uint32_t grxfsiz; 154 /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */ 155 volatile uint32_t gnptxfsiz; 156 /**Non Periodic Transmit FIFO/Queue Status Register (Read 157 * Only). <i>Offset: 02Ch</i> */ 158 volatile uint32_t gnptxsts; 159 /**I2C Access Register. <i>Offset: 030h</i> */ 160 volatile uint32_t gi2cctl; 161 /**PHY Vendor Control Register. <i>Offset: 034h</i> */ 162 volatile uint32_t gpvndctl; 163 /**General Purpose Input/Output Register. <i>Offset: 038h</i> */ 164 volatile uint32_t ggpio; 165 /**User ID Register. <i>Offset: 03Ch</i> */ 166 volatile uint32_t guid; 167 /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */ 168 volatile uint32_t gsnpsid; 169 /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */ 170 volatile uint32_t ghwcfg1; 171 /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */ 172 volatile uint32_t ghwcfg2; 173 #define DWC_SLAVE_ONLY_ARCH 0 174 #define DWC_EXT_DMA_ARCH 1 175 #define DWC_INT_DMA_ARCH 2 176 177 #define DWC_MODE_HNP_SRP_CAPABLE 0 178 #define DWC_MODE_SRP_ONLY_CAPABLE 1 179 #define DWC_MODE_NO_HNP_SRP_CAPABLE 2 180 #define DWC_MODE_SRP_CAPABLE_DEVICE 3 181 #define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4 182 #define DWC_MODE_SRP_CAPABLE_HOST 5 183 #define DWC_MODE_NO_SRP_CAPABLE_HOST 6 184 185 /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */ 186 volatile uint32_t ghwcfg3; 187 /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/ 188 volatile uint32_t ghwcfg4; 189 /** Core LPM Configuration register <i>Offset: 054h</i>*/ 190 volatile uint32_t glpmcfg; 191 /** Global PowerDn Register <i>Offset: 058h</i> */ 192 volatile uint32_t gpwrdn; 193 /** Global DFIFO SW Config Register <i>Offset: 05Ch</i> */ 194 volatile uint32_t gdfifocfg; 195 /** ADP Control Register <i>Offset: 060h</i> */ 196 volatile uint32_t adpctl; 197 /** Reserved <i>Offset: 064h-0FFh</i> */ 198 volatile uint32_t reserved39[39]; 199 /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */ 200 volatile uint32_t hptxfsiz; 201 /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, 202 otherwise Device Transmit FIFO#n Register. 203 * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */ 204 volatile uint32_t dtxfsiz[15]; 205 } dwc_otg_core_global_regs_t; 206 207 /** 208 * This union represents the bit fields of the Core OTG Control 209 * and Status Register (GOTGCTL). Set the bits using the bit 210 * fields then write the <i>d32</i> value to the register. 211 */ 212 typedef union gotgctl_data { 213 /** raw register data */ 214 uint32_t d32; 215 /** register bits */ 216 struct { 217 unsigned sesreqscs:1; 218 unsigned sesreq:1; 219 unsigned vbvalidoven:1; 220 unsigned vbvalidovval:1; 221 unsigned avalidoven:1; 222 unsigned avalidovval:1; 223 unsigned bvalidoven:1; 224 unsigned bvalidovval:1; 225 unsigned hstnegscs:1; 226 unsigned hnpreq:1; 227 unsigned hstsethnpen:1; 228 unsigned devhnpen:1; 229 unsigned reserved12_15:4; 230 unsigned conidsts:1; 231 unsigned dbnctime:1; 232 unsigned asesvld:1; 233 unsigned bsesvld:1; 234 unsigned otgver:1; 235 unsigned reserved1:1; 236 unsigned multvalidbc:5; 237 unsigned chirpen:1; 238 unsigned reserved28_31:4; 239 } b; 240 } gotgctl_data_t; 241 242 /** 243 * This union represents the bit fields of the Core OTG Interrupt Register 244 * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i> 245 * value to the register. 246 */ 247 typedef union gotgint_data { 248 /** raw register data */ 249 uint32_t d32; 250 /** register bits */ 251 struct { 252 /** Current Mode */ 253 unsigned reserved0_1:2; 254 255 /** Session End Detected */ 256 unsigned sesenddet:1; 257 258 unsigned reserved3_7:5; 259 260 /** Session Request Success Status Change */ 261 unsigned sesreqsucstschng:1; 262 /** Host Negotiation Success Status Change */ 263 unsigned hstnegsucstschng:1; 264 265 unsigned reserved10_16:7; 266 267 /** Host Negotiation Detected */ 268 unsigned hstnegdet:1; 269 /** A-Device Timeout Change */ 270 unsigned adevtoutchng:1; 271 /** Debounce Done */ 272 unsigned debdone:1; 273 /** Multi-Valued input changed */ 274 unsigned mvic:1; 275 276 277 unsigned reserved31_21:11; 278 279 } b; 280 } gotgint_data_t; 281 282 /** 283 * This union represents the bit fields of the Core AHB Configuration 284 * Register (GAHBCFG). Set/clear the bits using the bit fields then 285 * write the <i>d32</i> value to the register. 286 */ 287 typedef union gahbcfg_data { 288 /** raw register data */ 289 uint32_t d32; 290 /** register bits */ 291 struct { 292 unsigned glblintrmsk:1; 293 #define DWC_GAHBCFG_GLBINT_ENABLE 1 294 295 unsigned hburstlen:4; 296 #define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 297 #define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 298 #define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 299 #define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 300 #define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 301 302 unsigned dmaenable:1; 303 #define DWC_GAHBCFG_DMAENABLE 1 304 unsigned reserved:1; 305 unsigned nptxfemplvl_txfemplvl:1; 306 unsigned ptxfemplvl:1; 307 #define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 308 #define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 309 unsigned reserved9_20:12; 310 unsigned remmemsupp:1; 311 unsigned notialldmawrit:1; 312 unsigned reserved23_31:9; 313 } b; 314 } gahbcfg_data_t; 315 316 /** 317 * This union represents the bit fields of the Core USB Configuration 318 * Register (GUSBCFG). Set the bits using the bit fields then write 319 * the <i>d32</i> value to the register. 320 */ 321 typedef union gusbcfg_data { 322 /** raw register data */ 323 uint32_t d32; 324 /** register bits */ 325 struct { 326 unsigned toutcal:3; 327 unsigned phyif:1; 328 unsigned ulpi_utmi_sel:1; 329 unsigned fsintf:1; 330 unsigned physel:1; 331 unsigned ddrsel:1; 332 unsigned srpcap:1; 333 unsigned hnpcap:1; 334 unsigned usbtrdtim:4; 335 unsigned reserved1:1; 336 unsigned phylpwrclksel:1; 337 unsigned otgutmifssel:1; 338 unsigned ulpi_fsls:1; 339 unsigned ulpi_auto_res:1; 340 unsigned ulpi_clk_sus_m:1; 341 unsigned ulpi_ext_vbus_drv:1; 342 unsigned ulpi_int_vbus_indicator:1; 343 unsigned term_sel_dl_pulse:1; 344 unsigned indicator_complement:1; 345 unsigned indicator_pass_through:1; 346 unsigned ulpi_int_prot_dis:1; 347 unsigned ic_usb_cap:1; 348 unsigned ic_traffic_pull_remove:1; 349 unsigned tx_end_delay:1; 350 unsigned force_host_mode:1; 351 unsigned force_dev_mode:1; 352 unsigned reserved31:1; 353 } b; 354 } gusbcfg_data_t; 355 356 /** 357 * This union represents the bit fields of the Core Reset Register 358 * (GRSTCTL). Set/clear the bits using the bit fields then write the 359 * <i>d32</i> value to the register. 360 */ 361 typedef union grstctl_data { 362 /** raw register data */ 363 uint32_t d32; 364 /** register bits */ 365 struct { 366 /** Core Soft Reset (CSftRst) (Device and Host) 367 * 368 * The application can flush the control logic in the 369 * entire core using this bit. This bit resets the 370 * pipelines in the AHB Clock domain as well as the 371 * PHY Clock domain. 372 * 373 * The state machines are reset to an IDLE state, the 374 * control bits in the CSRs are cleared, all the 375 * transmit FIFOs and the receive FIFO are flushed. 376 * 377 * The status mask bits that control the generation of 378 * the interrupt, are cleared, to clear the 379 * interrupt. The interrupt status bits are not 380 * cleared, so the application can get the status of 381 * any events that occurred in the core after it has 382 * set this bit. 383 * 384 * Any transactions on the AHB are terminated as soon 385 * as possible following the protocol. Any 386 * transactions on the USB are terminated immediately. 387 * 388 * The configuration settings in the CSRs are 389 * unchanged, so the software doesn't have to 390 * reprogram these registers (Device 391 * Configuration/Host Configuration/Core System 392 * Configuration/Core PHY Configuration). 393 * 394 * The application can write to this bit, any time it 395 * wants to reset the core. This is a self clearing 396 * bit and the core clears this bit after all the 397 * necessary logic is reset in the core, which may 398 * take several clocks, depending on the current state 399 * of the core. 400 */ 401 unsigned csftrst:1; 402 /** Hclk Soft Reset 403 * 404 * The application uses this bit to reset the control logic in 405 * the AHB clock domain. Only AHB clock domain pipelines are 406 * reset. 407 */ 408 unsigned hsftrst:1; 409 /** Host Frame Counter Reset (Host Only)<br> 410 * 411 * The application can reset the (micro)frame number 412 * counter inside the core, using this bit. When the 413 * (micro)frame counter is reset, the subsequent SOF 414 * sent out by the core, will have a (micro)frame 415 * number of 0. 416 */ 417 unsigned hstfrm:1; 418 /** In Token Sequence Learning Queue Flush 419 * (INTknQFlsh) (Device Only) 420 */ 421 unsigned intknqflsh:1; 422 /** RxFIFO Flush (RxFFlsh) (Device and Host) 423 * 424 * The application can flush the entire Receive FIFO 425 * using this bit. The application must first 426 * ensure that the core is not in the middle of a 427 * transaction. The application should write into 428 * this bit, only after making sure that neither the 429 * DMA engine is reading from the RxFIFO nor the MAC 430 * is writing the data in to the FIFO. The 431 * application should wait until the bit is cleared 432 * before performing any other operations. This bit 433 * will takes 8 clocks (slowest of PHY or AHB clock) 434 * to clear. 435 */ 436 unsigned rxfflsh:1; 437 /** TxFIFO Flush (TxFFlsh) (Device and Host). 438 * 439 * This bit is used to selectively flush a single or 440 * all transmit FIFOs. The application must first 441 * ensure that the core is not in the middle of a 442 * transaction. The application should write into 443 * this bit, only after making sure that neither the 444 * DMA engine is writing into the TxFIFO nor the MAC 445 * is reading the data out of the FIFO. The 446 * application should wait until the core clears this 447 * bit, before performing any operations. This bit 448 * will takes 8 clocks (slowest of PHY or AHB clock) 449 * to clear. 450 */ 451 unsigned txfflsh:1; 452 453 /** TxFIFO Number (TxFNum) (Device and Host). 454 * 455 * This is the FIFO number which needs to be flushed, 456 * using the TxFIFO Flush bit. This field should not 457 * be changed until the TxFIFO Flush bit is cleared by 458 * the core. 459 * - 0x0 : Non Periodic TxFIFO Flush 460 * - 0x1 : Periodic TxFIFO #1 Flush in device mode 461 * or Periodic TxFIFO in host mode 462 * - 0x2 : Periodic TxFIFO #2 Flush in device mode. 463 * - ... 464 * - 0xF : Periodic TxFIFO #15 Flush in device mode 465 * - 0x10: Flush all the Transmit NonPeriodic and 466 * Transmit Periodic FIFOs in the core 467 */ 468 unsigned txfnum:5; 469 /** Reserved */ 470 unsigned reserved11_29:19; 471 /** DMA Request Signal. Indicated DMA request is in 472 * probress. Used for debug purpose. */ 473 unsigned dmareq:1; 474 /** AHB Master Idle. Indicates the AHB Master State 475 * Machine is in IDLE condition. */ 476 unsigned ahbidle:1; 477 } b; 478 } grstctl_t; 479 480 /** 481 * This union represents the bit fields of the Core Interrupt Mask 482 * Register (GINTMSK). Set/clear the bits using the bit fields then 483 * write the <i>d32</i> value to the register. 484 */ 485 typedef union gintmsk_data { 486 /** raw register data */ 487 uint32_t d32; 488 /** register bits */ 489 struct { 490 unsigned reserved0:1; 491 unsigned modemismatch:1; 492 unsigned otgintr:1; 493 unsigned sofintr:1; 494 unsigned rxstsqlvl:1; 495 unsigned nptxfempty:1; 496 unsigned ginnakeff:1; 497 unsigned goutnakeff:1; 498 unsigned ulpickint:1; 499 unsigned i2cintr:1; 500 unsigned erlysuspend:1; 501 unsigned usbsuspend:1; 502 unsigned usbreset:1; 503 unsigned enumdone:1; 504 unsigned isooutdrop:1; 505 unsigned eopframe:1; 506 unsigned restoredone:1; 507 unsigned epmismatch:1; 508 unsigned inepintr:1; 509 unsigned outepintr:1; 510 unsigned incomplisoin:1; 511 unsigned incomplisoout:1; 512 unsigned fetsusp:1; 513 unsigned resetdet:1; 514 unsigned portintr:1; 515 unsigned hcintr:1; 516 unsigned ptxfempty:1; 517 unsigned lpmtranrcvd:1; 518 unsigned conidstschng:1; 519 unsigned disconnect:1; 520 unsigned sessreqintr:1; 521 unsigned wkupintr:1; 522 } b; 523 } gintmsk_data_t; 524 /** 525 * This union represents the bit fields of the Core Interrupt Register 526 * (GINTSTS). Set/clear the bits using the bit fields then write the 527 * <i>d32</i> value to the register. 528 */ 529 typedef union gintsts_data { 530 /** raw register data */ 531 uint32_t d32; 532 #define DWC_SOF_INTR_MASK 0x0008 533 /** register bits */ 534 struct { 535 #define DWC_HOST_MODE 1 536 unsigned curmode:1; 537 unsigned modemismatch:1; 538 unsigned otgintr:1; 539 unsigned sofintr:1; 540 unsigned rxstsqlvl:1; 541 unsigned nptxfempty:1; 542 unsigned ginnakeff:1; 543 unsigned goutnakeff:1; 544 unsigned ulpickint:1; 545 unsigned i2cintr:1; 546 unsigned erlysuspend:1; 547 unsigned usbsuspend:1; 548 unsigned usbreset:1; 549 unsigned enumdone:1; 550 unsigned isooutdrop:1; 551 unsigned eopframe:1; 552 unsigned restoredone:1; 553 unsigned epmismatch:1; 554 unsigned inepint:1; 555 unsigned outepintr:1; 556 unsigned incomplisoin:1; 557 unsigned incomplisoout:1; 558 unsigned fetsusp:1; 559 unsigned resetdet:1; 560 unsigned portintr:1; 561 unsigned hcintr:1; 562 unsigned ptxfempty:1; 563 unsigned lpmtranrcvd:1; 564 unsigned conidstschng:1; 565 unsigned disconnect:1; 566 unsigned sessreqintr:1; 567 unsigned wkupintr:1; 568 } b; 569 } gintsts_data_t; 570 571 /** 572 * This union represents the bit fields in the Device Receive Status Read and 573 * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i> 574 * element then read out the bits using the <i>b</i>it elements. 575 */ 576 typedef union device_grxsts_data { 577 /** raw register data */ 578 uint32_t d32; 579 /** register bits */ 580 struct { 581 unsigned epnum:4; 582 unsigned bcnt:11; 583 unsigned dpid:2; 584 585 #define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet 586 #define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete 587 588 #define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK 589 #define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete 590 #define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet 591 unsigned pktsts:4; 592 unsigned fn:4; 593 unsigned reserved25_31:7; 594 } b; 595 } device_grxsts_data_t; 596 597 /** 598 * This union represents the bit fields in the Host Receive Status Read and 599 * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i> 600 * element then read out the bits using the <i>b</i>it elements. 601 */ 602 typedef union host_grxsts_data { 603 /** raw register data */ 604 uint32_t d32; 605 /** register bits */ 606 struct { 607 unsigned chnum:4; 608 unsigned bcnt:11; 609 unsigned dpid:2; 610 611 unsigned pktsts:4; 612 #define DWC_GRXSTS_PKTSTS_IN 0x2 613 #define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 614 #define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 615 #define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 616 617 unsigned reserved21_31:11; 618 } b; 619 } host_grxsts_data_t; 620 621 /** 622 * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, 623 * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element then 624 * read out the bits using the <i>b</i>it elements. 625 */ 626 typedef union fifosize_data { 627 /** raw register data */ 628 uint32_t d32; 629 /** register bits */ 630 struct { 631 unsigned startaddr:16; 632 unsigned depth:16; 633 } b; 634 } fifosize_data_t; 635 636 /** 637 * This union represents the bit fields in the Non-Periodic Transmit 638 * FIFO/Queue Status Register (GNPTXSTS). Read the register into the 639 * <i>d32</i> element then read out the bits using the <i>b</i>it 640 * elements. 641 */ 642 typedef union gnptxsts_data { 643 /** raw register data */ 644 uint32_t d32; 645 /** register bits */ 646 struct { 647 unsigned nptxfspcavail:16; 648 unsigned nptxqspcavail:8; 649 /** Top of the Non-Periodic Transmit Request Queue 650 * - bit 24 - Terminate (Last entry for the selected 651 * channel/EP) 652 * - bits 26:25 - Token Type 653 * - 2'b00 - IN/OUT 654 * - 2'b01 - Zero Length OUT 655 * - 2'b10 - PING/Complete Split 656 * - 2'b11 - Channel Halt 657 * - bits 30:27 - Channel/EP Number 658 */ 659 unsigned nptxqtop_terminate:1; 660 unsigned nptxqtop_token:2; 661 unsigned nptxqtop_chnep:4; 662 unsigned reserved:1; 663 } b; 664 } gnptxsts_data_t; 665 666 /** 667 * This union represents the bit fields in the Transmit 668 * FIFO Status Register (DTXFSTS). Read the register into the 669 * <i>d32</i> element then read out the bits using the <i>b</i>it 670 * elements. 671 */ 672 typedef union dtxfsts_data { 673 /** raw register data */ 674 uint32_t d32; 675 /** register bits */ 676 struct { 677 unsigned txfspcavail:16; 678 unsigned reserved:16; 679 } b; 680 } dtxfsts_data_t; 681 682 /** 683 * This union represents the bit fields in the I2C Control Register 684 * (I2CCTL). Read the register into the <i>d32</i> element then read out the 685 * bits using the <i>b</i>it elements. 686 */ 687 typedef union gi2cctl_data { 688 /** raw register data */ 689 uint32_t d32; 690 /** register bits */ 691 struct { 692 unsigned rwdata:8; 693 unsigned regaddr:8; 694 unsigned addr:7; 695 unsigned i2cen:1; 696 unsigned ack:1; 697 unsigned i2csuspctl:1; 698 unsigned i2cdevaddr:2; 699 unsigned i2cdatse0:1; 700 unsigned reserved:1; 701 unsigned rw:1; 702 unsigned bsydne:1; 703 } b; 704 } gi2cctl_data_t; 705 706 /** 707 * This union represents the bit fields in the PHY Vendor Control Register 708 * (GPVNDCTL). Read the register into the <i>d32</i> element then read out the 709 * bits using the <i>b</i>it elements. 710 */ 711 typedef union gpvndctl_data { 712 /** raw register data */ 713 uint32_t d32; 714 /** register bits */ 715 struct { 716 unsigned regdata:8; 717 unsigned vctrl:8; 718 unsigned regaddr16_21:6; 719 unsigned regwr:1; 720 unsigned reserved23_24:2; 721 unsigned newregreq:1; 722 unsigned vstsbsy:1; 723 unsigned vstsdone:1; 724 unsigned reserved28_30:3; 725 unsigned disulpidrvr:1; 726 } b; 727 } gpvndctl_data_t; 728 729 /** 730 * This union represents the bit fields in the General Purpose 731 * Input/Output Register (GGPIO). 732 * Read the register into the <i>d32</i> element then read out the 733 * bits using the <i>b</i>it elements. 734 */ 735 typedef union ggpio_data { 736 /** raw register data */ 737 uint32_t d32; 738 /** register bits */ 739 struct { 740 unsigned gpi:16; 741 unsigned gpo:16; 742 } b; 743 } ggpio_data_t; 744 745 /** 746 * This union represents the bit fields in the User ID Register 747 * (GUID). Read the register into the <i>d32</i> element then read out the 748 * bits using the <i>b</i>it elements. 749 */ 750 typedef union guid_data { 751 /** raw register data */ 752 uint32_t d32; 753 /** register bits */ 754 struct { 755 unsigned rwdata:32; 756 } b; 757 } guid_data_t; 758 759 /** 760 * This union represents the bit fields in the Synopsys ID Register 761 * (GSNPSID). Read the register into the <i>d32</i> element then read out the 762 * bits using the <i>b</i>it elements. 763 */ 764 typedef union gsnpsid_data { 765 /** raw register data */ 766 uint32_t d32; 767 /** register bits */ 768 struct { 769 unsigned rwdata:32; 770 } b; 771 } gsnpsid_data_t; 772 773 /** 774 * This union represents the bit fields in the User HW Config1 775 * Register. Read the register into the <i>d32</i> element then read 776 * out the bits using the <i>b</i>it elements. 777 */ 778 typedef union hwcfg1_data { 779 /** raw register data */ 780 uint32_t d32; 781 /** register bits */ 782 struct { 783 unsigned ep_dir0:2; 784 unsigned ep_dir1:2; 785 unsigned ep_dir2:2; 786 unsigned ep_dir3:2; 787 unsigned ep_dir4:2; 788 unsigned ep_dir5:2; 789 unsigned ep_dir6:2; 790 unsigned ep_dir7:2; 791 unsigned ep_dir8:2; 792 unsigned ep_dir9:2; 793 unsigned ep_dir10:2; 794 unsigned ep_dir11:2; 795 unsigned ep_dir12:2; 796 unsigned ep_dir13:2; 797 unsigned ep_dir14:2; 798 unsigned ep_dir15:2; 799 } b; 800 } hwcfg1_data_t; 801 802 /** 803 * This union represents the bit fields in the User HW Config2 804 * Register. Read the register into the <i>d32</i> element then read 805 * out the bits using the <i>b</i>it elements. 806 */ 807 typedef union hwcfg2_data { 808 /** raw register data */ 809 uint32_t d32; 810 /** register bits */ 811 struct { 812 /* GHWCFG2 */ 813 unsigned op_mode:3; 814 #define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 815 #define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 816 #define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 817 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 818 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 819 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 820 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 821 822 unsigned architecture:2; 823 unsigned point2point:1; 824 unsigned hs_phy_type:2; 825 #define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 826 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 827 #define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 828 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 829 830 unsigned fs_phy_type:2; 831 unsigned num_dev_ep:4; 832 unsigned num_host_chan:4; 833 unsigned perio_ep_supported:1; 834 unsigned dynamic_fifo:1; 835 unsigned multi_proc_int:1; 836 unsigned reserved21:1; 837 unsigned nonperio_tx_q_depth:2; 838 unsigned host_perio_tx_q_depth:2; 839 unsigned dev_token_q_depth:5; 840 unsigned otg_enable_ic_usb:1; 841 } b; 842 } hwcfg2_data_t; 843 844 /** 845 * This union represents the bit fields in the User HW Config3 846 * Register. Read the register into the <i>d32</i> element then read 847 * out the bits using the <i>b</i>it elements. 848 */ 849 typedef union hwcfg3_data { 850 /** raw register data */ 851 uint32_t d32; 852 /** register bits */ 853 struct { 854 /* GHWCFG3 */ 855 unsigned xfer_size_cntr_width:4; 856 unsigned packet_size_cntr_width:3; 857 unsigned otg_func:1; 858 unsigned i2c:1; 859 unsigned vendor_ctrl_if:1; 860 unsigned optional_features:1; 861 unsigned synch_reset_type:1; 862 unsigned adp_supp:1; 863 unsigned otg_enable_hsic:1; 864 unsigned otg_ver_support:1; 865 unsigned otg_lpm_en:1; 866 unsigned dfifo_depth:16; 867 } b; 868 } hwcfg3_data_t; 869 870 /** 871 * This union represents the bit fields in the User HW Config4 872 * Register. Read the register into the <i>d32</i> element then read 873 * out the bits using the <i>b</i>it elements. 874 */ 875 typedef union hwcfg4_data { 876 /** raw register data */ 877 uint32_t d32; 878 /** register bits */ 879 struct { 880 unsigned num_dev_perio_in_ep:4; 881 unsigned power_optimiz:1; 882 unsigned min_ahb_freq:1; 883 unsigned part_power_down:1; 884 unsigned reserved:7; 885 unsigned utmi_phy_data_width:2; 886 unsigned num_dev_mode_ctrl_ep:4; 887 unsigned iddig_filt_en:1; 888 unsigned vbus_valid_filt_en:1; 889 unsigned a_valid_filt_en:1; 890 unsigned b_valid_filt_en:1; 891 unsigned session_end_filt_en:1; 892 unsigned ded_fifo_en:1; 893 unsigned num_in_eps:4; 894 unsigned desc_dma:1; 895 unsigned desc_dma_dyn:1; 896 } b; 897 } hwcfg4_data_t; 898 899 /** 900 * This union represents the bit fields of the Core LPM Configuration 901 * Register (GLPMCFG). Set the bits using bit fields then write 902 * the <i>d32</i> value to the register. 903 */ 904 typedef union glpmctl_data { 905 /** raw register data */ 906 uint32_t d32; 907 /** register bits */ 908 struct { 909 /** LPM-Capable (LPMCap) (Device and Host) 910 * The application uses this bit to control 911 * the DWC_otg core LPM capabilities. 912 */ 913 unsigned lpm_cap_en:1; 914 /** LPM response programmed by application (AppL1Res) (Device) 915 * Handshake response to LPM token pre-programmed 916 * by device application software. 917 */ 918 unsigned appl_resp:1; 919 /** Host Initiated Resume Duration (HIRD) (Device and Host) 920 * In Host mode this field indicates the value of HIRD 921 * to be sent in an LPM transaction. 922 * In Device mode this field is updated with the 923 * Received LPM Token HIRD bmAttribute 924 * when an ACK/NYET/STALL response is sent 925 * to an LPM transaction. 926 */ 927 unsigned hird:4; 928 /** RemoteWakeEnable (bRemoteWake) (Device and Host) 929 * In Host mode this bit indicates the value of remote 930 * wake up to be sent in wIndex field of LPM transaction. 931 * In Device mode this field is updated with the 932 * Received LPM Token bRemoteWake bmAttribute 933 * when an ACK/NYET/STALL response is sent 934 * to an LPM transaction. 935 */ 936 unsigned rem_wkup_en:1; 937 /** Enable utmi_sleep_n (EnblSlpM) (Device and Host) 938 * The application uses this bit to control 939 * the utmi_sleep_n assertion to the PHY when in L1 state. 940 */ 941 unsigned en_utmi_sleep:1; 942 /** HIRD Threshold (HIRD_Thres) (Device and Host) 943 */ 944 unsigned hird_thres:5; 945 /** LPM Response (CoreL1Res) (Device and Host) 946 * In Host mode this bit contains handsake response to 947 * LPM transaction. 948 * In Device mode the response of the core to 949 * LPM transaction received is reflected in these two bits. 950 - 0x0 : ERROR (No handshake response) 951 - 0x1 : STALL 952 - 0x2 : NYET 953 - 0x3 : ACK 954 */ 955 unsigned lpm_resp:2; 956 /** Port Sleep Status (SlpSts) (Device and Host) 957 * This bit is set as long as a Sleep condition 958 * is present on the USB bus. 959 */ 960 unsigned prt_sleep_sts:1; 961 /** Sleep State Resume OK (L1ResumeOK) (Device and Host) 962 * Indicates that the application or host 963 * can start resume from Sleep state. 964 */ 965 unsigned sleep_state_resumeok:1; 966 /** LPM channel Index (LPM_Chnl_Indx) (Host) 967 * The channel number on which the LPM transaction 968 * has to be applied while sending 969 * an LPM transaction to the local device. 970 */ 971 unsigned lpm_chan_index:4; 972 /** LPM Retry Count (LPM_Retry_Cnt) (Host) 973 * Number host retries that would be performed 974 * if the device response was not valid response. 975 */ 976 unsigned retry_count:3; 977 /** Send LPM Transaction (SndLPM) (Host) 978 * When set by application software, 979 * an LPM transaction containing two tokens 980 * is sent. 981 */ 982 unsigned send_lpm:1; 983 /** LPM Retry status (LPM_RetryCnt_Sts) (Host) 984 * Number of LPM Host Retries still remaining 985 * to be transmitted for the current LPM sequence 986 */ 987 unsigned retry_count_sts:3; 988 unsigned reserved28_29:2; 989 /** In host mode once this bit is set, the host 990 * configures to drive the HSIC Idle state on the bus. 991 * It then waits for the device to initiate the Connect sequence. 992 * In device mode once this bit is set, the device waits for 993 * the HSIC Idle line state on the bus. Upon receving the Idle 994 * line state, it initiates the HSIC Connect sequence. 995 */ 996 unsigned hsic_connect:1; 997 /** This bit overrides and functionally inverts 998 * the if_select_hsic input port signal. 999 */ 1000 unsigned inv_sel_hsic:1; 1001 } b; 1002 } glpmcfg_data_t; 1003 1004 /** 1005 * This union represents the bit fields of the Core ADP Timer, Control and 1006 * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write 1007 * the <i>d32</i> value to the register. 1008 */ 1009 typedef union adpctl_data { 1010 /** raw register data */ 1011 uint32_t d32; 1012 /** register bits */ 1013 struct { 1014 /** Probe Discharge (PRB_DSCHG) 1015 * These bits set the times for TADP_DSCHG. 1016 * These bits are defined as follows: 1017 * 2'b00 - 4 msec 1018 * 2'b01 - 8 msec 1019 * 2'b10 - 16 msec 1020 * 2'b11 - 32 msec 1021 */ 1022 unsigned prb_dschg:2; 1023 /** Probe Delta (PRB_DELTA) 1024 * These bits set the resolution for RTIM value. 1025 * The bits are defined in units of 32 kHz clock cycles as follows: 1026 * 2'b00 - 1 cycles 1027 * 2'b01 - 2 cycles 1028 * 2'b10 - 3 cycles 1029 * 2'b11 - 4 cycles 1030 * For example if this value is chosen to 2'b01, it means that RTIM 1031 * increments for every 3(three) 32Khz clock cycles. 1032 */ 1033 unsigned prb_delta:2; 1034 /** Probe Period (PRB_PER) 1035 * These bits sets the TADP_PRD as shown in Figure 4 as follows: 1036 * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec) 1037 * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec) 1038 * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec) 1039 * 2'b11 - Reserved 1040 */ 1041 unsigned prb_per:2; 1042 /** These bits capture the latest time it took for VBUS to ramp from VADP_SINK 1043 * to VADP_PRB. The bits are defined in units of 32 kHz clock cycles as follows: 1044 * 0x000 - 1 cycles 1045 * 0x001 - 2 cycles 1046 * 0x002 - 3 cycles 1047 * etc 1048 * 0x7FF - 2048 cycles 1049 * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec. 1050 */ 1051 unsigned rtim:11; 1052 /** Enable Probe (EnaPrb) 1053 * When programmed to 1'b1, the core performs a probe operation. 1054 * This bit is valid only if OTG_Ver = 1'b1. 1055 */ 1056 unsigned enaprb:1; 1057 /** Enable Sense (EnaSns) 1058 * When programmed to 1'b1, the core performs a Sense operation. 1059 * This bit is valid only if OTG_Ver = 1'b1. 1060 */ 1061 unsigned enasns:1; 1062 /** ADP Reset (ADPRes) 1063 * When set, ADP controller is reset. 1064 * This bit is valid only if OTG_Ver = 1'b1. 1065 */ 1066 unsigned adpres:1; 1067 /** ADP Enable (ADPEn) 1068 * When set, the core performs either ADP probing or sensing 1069 * based on EnaPrb or EnaSns. 1070 * This bit is valid only if OTG_Ver = 1'b1. 1071 */ 1072 unsigned adpen:1; 1073 /** ADP Probe Interrupt (ADP_PRB_INT) 1074 * When this bit is set, it means that the VBUS 1075 * voltage is greater than VADP_PRB or VADP_PRB is reached. 1076 * This bit is valid only if OTG_Ver = 1'b1. 1077 */ 1078 unsigned adp_prb_int:1; 1079 /** 1080 * ADP Sense Interrupt (ADP_SNS_INT) 1081 * When this bit is set, it means that the VBUS voltage is greater than 1082 * VADP_SNS value or VADP_SNS is reached. 1083 * This bit is valid only if OTG_Ver = 1'b1. 1084 */ 1085 unsigned adp_sns_int:1; 1086 /** ADP Tomeout Interrupt (ADP_TMOUT_INT) 1087 * This bit is relevant only for an ADP probe. 1088 * When this bit is set, it means that the ramp time has 1089 * completed ie ADPCTL.RTIM has reached its terminal value 1090 * of 0x7FF. This is a debug feature that allows software 1091 * to read the ramp time after each cycle. 1092 * This bit is valid only if OTG_Ver = 1'b1. 1093 */ 1094 unsigned adp_tmout_int:1; 1095 /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK) 1096 * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT. 1097 * This bit is valid only if OTG_Ver = 1'b1. 1098 */ 1099 unsigned adp_prb_int_msk:1; 1100 /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK) 1101 * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT. 1102 * This bit is valid only if OTG_Ver = 1'b1. 1103 */ 1104 unsigned adp_sns_int_msk:1; 1105 /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK) 1106 * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT. 1107 * This bit is valid only if OTG_Ver = 1'b1. 1108 */ 1109 unsigned adp_tmout_int_msk:1; 1110 /** Access Request 1111 * 2'b00 - Read/Write Valid (updated by the core) 1112 * 2'b01 - Read 1113 * 2'b00 - Write 1114 * 2'b00 - Reserved 1115 */ 1116 unsigned ar:2; 1117 /** Reserved */ 1118 unsigned reserved29_31:3; 1119 } b; 1120 } adpctl_data_t; 1121 1122 //////////////////////////////////////////// 1123 // Device Registers 1124 /** 1125 * Device Global Registers. <i>Offsets 800h-BFFh</i> 1126 * 1127 * The following structures define the size and relative field offsets 1128 * for the Device Mode Registers. 1129 * 1130 * <i>These registers are visible only in Device mode and must not be 1131 * accessed in Host mode, as the results are unknown.</i> 1132 */ 1133 typedef struct dwc_otg_dev_global_regs { 1134 /** Device Configuration Register. <i>Offset 800h</i> */ 1135 volatile uint32_t dcfg; 1136 /** Device Control Register. <i>Offset: 804h</i> */ 1137 volatile uint32_t dctl; 1138 /** Device Status Register (Read Only). <i>Offset: 808h</i> */ 1139 volatile uint32_t dsts; 1140 /** Reserved. <i>Offset: 80Ch</i> */ 1141 uint32_t unused; 1142 /** Device IN Endpoint Common Interrupt Mask 1143 * Register. <i>Offset: 810h</i> */ 1144 volatile uint32_t diepmsk; 1145 /** Device OUT Endpoint Common Interrupt Mask 1146 * Register. <i>Offset: 814h</i> */ 1147 volatile uint32_t doepmsk; 1148 /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */ 1149 volatile uint32_t daint; 1150 /** Device All Endpoints Interrupt Mask Register. <i>Offset: 1151 * 81Ch</i> */ 1152 volatile uint32_t daintmsk; 1153 /** Device IN Token Queue Read Register-1 (Read Only). 1154 * <i>Offset: 820h</i> */ 1155 volatile uint32_t dtknqr1; 1156 /** Device IN Token Queue Read Register-2 (Read Only). 1157 * <i>Offset: 824h</i> */ 1158 volatile uint32_t dtknqr2; 1159 /** Device VBUS discharge Register. <i>Offset: 828h</i> */ 1160 volatile uint32_t dvbusdis; 1161 /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */ 1162 volatile uint32_t dvbuspulse; 1163 /** Device IN Token Queue Read Register-3 (Read Only). / 1164 * Device Thresholding control register (Read/Write) 1165 * <i>Offset: 830h</i> */ 1166 volatile uint32_t dtknqr3_dthrctl; 1167 /** Device IN Token Queue Read Register-4 (Read Only). / 1168 * Device IN EPs empty Inr. Mask Register (Read/Write) 1169 * <i>Offset: 834h</i> */ 1170 volatile uint32_t dtknqr4_fifoemptymsk; 1171 /** Device Each Endpoint Interrupt Register (Read Only). / 1172 * <i>Offset: 838h</i> */ 1173 volatile uint32_t deachint; 1174 /** Device Each Endpoint Interrupt mask Register (Read/Write). / 1175 * <i>Offset: 83Ch</i> */ 1176 volatile uint32_t deachintmsk; 1177 /** Device Each In Endpoint Interrupt mask Register (Read/Write). / 1178 * <i>Offset: 840h</i> */ 1179 volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS]; 1180 /** Device Each Out Endpoint Interrupt mask Register (Read/Write). / 1181 * <i>Offset: 880h</i> */ 1182 volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS]; 1183 } dwc_otg_device_global_regs_t; 1184 1185 /** 1186 * This union represents the bit fields in the Device Configuration 1187 * Register. Read the register into the <i>d32</i> member then 1188 * set/clear the bits using the <i>b</i>it elements. Write the 1189 * <i>d32</i> member to the dcfg register. 1190 */ 1191 typedef union dcfg_data { 1192 /** raw register data */ 1193 uint32_t d32; 1194 /** register bits */ 1195 struct { 1196 /** Device Speed */ 1197 unsigned devspd:2; 1198 /** Non Zero Length Status OUT Handshake */ 1199 unsigned nzstsouthshk:1; 1200 #define DWC_DCFG_SEND_STALL 1 1201 1202 unsigned ena32khzs:1; 1203 /** Device Addresses */ 1204 unsigned devaddr:7; 1205 /** Periodic Frame Interval */ 1206 unsigned perfrint:2; 1207 #define DWC_DCFG_FRAME_INTERVAL_80 0 1208 #define DWC_DCFG_FRAME_INTERVAL_85 1 1209 #define DWC_DCFG_FRAME_INTERVAL_90 2 1210 #define DWC_DCFG_FRAME_INTERVAL_95 3 1211 1212 unsigned reserved13_17:5; 1213 /** In Endpoint Mis-match count */ 1214 unsigned epmscnt:5; 1215 /** Enable Descriptor DMA in Device mode */ 1216 unsigned descdma:1; 1217 unsigned perschintvl:2; 1218 unsigned resvalid:6; 1219 } b; 1220 } dcfg_data_t; 1221 1222 /** 1223 * This union represents the bit fields in the Device Control 1224 * Register. Read the register into the <i>d32</i> member then 1225 * set/clear the bits using the <i>b</i>it elements. 1226 */ 1227 typedef union dctl_data { 1228 /** raw register data */ 1229 uint32_t d32; 1230 /** register bits */ 1231 struct { 1232 /** Remote Wakeup */ 1233 unsigned rmtwkupsig:1; 1234 /** Soft Disconnect */ 1235 unsigned sftdiscon:1; 1236 /** Global Non-Periodic IN NAK Status */ 1237 unsigned gnpinnaksts:1; 1238 /** Global OUT NAK Status */ 1239 unsigned goutnaksts:1; 1240 /** Test Control */ 1241 unsigned tstctl:3; 1242 /** Set Global Non-Periodic IN NAK */ 1243 unsigned sgnpinnak:1; 1244 /** Clear Global Non-Periodic IN NAK */ 1245 unsigned cgnpinnak:1; 1246 /** Set Global OUT NAK */ 1247 unsigned sgoutnak:1; 1248 /** Clear Global OUT NAK */ 1249 unsigned cgoutnak:1; 1250 1251 /** Power-On Programming Done */ 1252 unsigned pwronprgdone:1; 1253 /** Reserved */ 1254 unsigned reserved:1; 1255 /** Global Multi Count */ 1256 unsigned gmc:2; 1257 /** Ignore Frame Number for ISOC EPs */ 1258 unsigned ifrmnum:1; 1259 /** NAK on Babble */ 1260 unsigned nakonbble:1; 1261 1262 unsigned reserved17_31:15; 1263 } b; 1264 } dctl_data_t; 1265 1266 /** 1267 * This union represents the bit fields in the Device Status 1268 * Register. Read the register into the <i>d32</i> member then 1269 * set/clear the bits using the <i>b</i>it elements. 1270 */ 1271 typedef union dsts_data { 1272 /** raw register data */ 1273 uint32_t d32; 1274 /** register bits */ 1275 struct { 1276 /** Suspend Status */ 1277 unsigned suspsts:1; 1278 /** Enumerated Speed */ 1279 unsigned enumspd:2; 1280 #define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 1281 #define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 1282 #define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 1283 #define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 1284 /** Erratic Error */ 1285 unsigned errticerr:1; 1286 unsigned reserved4_7:4; 1287 /** Frame or Microframe Number of the received SOF */ 1288 unsigned soffn:14; 1289 unsigned reserved22_31:10; 1290 } b; 1291 } dsts_data_t; 1292 1293 /** 1294 * This union represents the bit fields in the Device IN EP Interrupt 1295 * Register and the Device IN EP Common Mask Register. 1296 * 1297 * - Read the register into the <i>d32</i> member then set/clear the 1298 * bits using the <i>b</i>it elements. 1299 */ 1300 typedef union diepint_data { 1301 /** raw register data */ 1302 uint32_t d32; 1303 /** register bits */ 1304 struct { 1305 /** Transfer complete mask */ 1306 unsigned xfercompl:1; 1307 /** Endpoint disable mask */ 1308 unsigned epdisabled:1; 1309 /** AHB Error mask */ 1310 unsigned ahberr:1; 1311 /** TimeOUT Handshake mask (non-ISOC EPs) */ 1312 unsigned timeout:1; 1313 /** IN Token received with TxF Empty mask */ 1314 unsigned intktxfemp:1; 1315 /** IN Token Received with EP mismatch mask */ 1316 unsigned intknepmis:1; 1317 /** IN Endpoint NAK Effective mask */ 1318 unsigned inepnakeff:1; 1319 /** Reserved */ 1320 unsigned emptyintr:1; 1321 1322 unsigned txfifoundrn:1; 1323 1324 /** BNA Interrupt mask */ 1325 unsigned bna:1; 1326 1327 unsigned reserved10_12:3; 1328 /** BNA Interrupt mask */ 1329 unsigned nak:1; 1330 1331 unsigned reserved14_31:18; 1332 } b; 1333 } diepint_data_t; 1334 1335 /** 1336 * This union represents the bit fields in the Device IN EP 1337 * Common/Dedicated Interrupt Mask Register. 1338 */ 1339 typedef union diepint_data diepmsk_data_t; 1340 1341 /** 1342 * This union represents the bit fields in the Device OUT EP Interrupt 1343 * Registerand Device OUT EP Common Interrupt Mask Register. 1344 * 1345 * - Read the register into the <i>d32</i> member then set/clear the 1346 * bits using the <i>b</i>it elements. 1347 */ 1348 typedef union doepint_data { 1349 /** raw register data */ 1350 uint32_t d32; 1351 /** register bits */ 1352 struct { 1353 /** Transfer complete */ 1354 unsigned xfercompl:1; 1355 /** Endpoint disable */ 1356 unsigned epdisabled:1; 1357 /** AHB Error */ 1358 unsigned ahberr:1; 1359 /** Setup Phase Done (contorl EPs) */ 1360 unsigned setup:1; 1361 /** OUT Token Received when Endpoint Disabled */ 1362 unsigned outtknepdis:1; 1363 1364 unsigned stsphsercvd:1; 1365 /** Back-to-Back SETUP Packets Received */ 1366 unsigned back2backsetup:1; 1367 1368 unsigned reserved7:1; 1369 /** OUT packet Error */ 1370 unsigned outpkterr:1; 1371 /** BNA Interrupt */ 1372 unsigned bna:1; 1373 1374 unsigned reserved10:1; 1375 /** Packet Drop Status */ 1376 unsigned pktdrpsts:1; 1377 /** Babble Interrupt */ 1378 unsigned babble:1; 1379 /** NAK Interrupt */ 1380 unsigned nak:1; 1381 /** NYET Interrupt */ 1382 unsigned nyet:1; 1383 1384 unsigned reserved15_31:17; 1385 } b; 1386 } doepint_data_t; 1387 1388 /** 1389 * This union represents the bit fields in the Device OUT EP 1390 * Common/Dedicated Interrupt Mask Register. 1391 */ 1392 typedef union doepint_data doepmsk_data_t; 1393 1394 /** 1395 * This union represents the bit fields in the Device All EP Interrupt 1396 * and Mask Registers. 1397 * - Read the register into the <i>d32</i> member then set/clear the 1398 * bits using the <i>b</i>it elements. 1399 */ 1400 typedef union daint_data { 1401 /** raw register data */ 1402 uint32_t d32; 1403 /** register bits */ 1404 struct { 1405 /** IN Endpoint bits */ 1406 unsigned in:16; 1407 /** OUT Endpoint bits */ 1408 unsigned out:16; 1409 } ep; 1410 struct { 1411 /** IN Endpoint bits */ 1412 unsigned inep0:1; 1413 unsigned inep1:1; 1414 unsigned inep2:1; 1415 unsigned inep3:1; 1416 unsigned inep4:1; 1417 unsigned inep5:1; 1418 unsigned inep6:1; 1419 unsigned inep7:1; 1420 unsigned inep8:1; 1421 unsigned inep9:1; 1422 unsigned inep10:1; 1423 unsigned inep11:1; 1424 unsigned inep12:1; 1425 unsigned inep13:1; 1426 unsigned inep14:1; 1427 unsigned inep15:1; 1428 /** OUT Endpoint bits */ 1429 unsigned outep0:1; 1430 unsigned outep1:1; 1431 unsigned outep2:1; 1432 unsigned outep3:1; 1433 unsigned outep4:1; 1434 unsigned outep5:1; 1435 unsigned outep6:1; 1436 unsigned outep7:1; 1437 unsigned outep8:1; 1438 unsigned outep9:1; 1439 unsigned outep10:1; 1440 unsigned outep11:1; 1441 unsigned outep12:1; 1442 unsigned outep13:1; 1443 unsigned outep14:1; 1444 unsigned outep15:1; 1445 } b; 1446 } daint_data_t; 1447 1448 /** 1449 * This union represents the bit fields in the Device IN Token Queue 1450 * Read Registers. 1451 * - Read the register into the <i>d32</i> member. 1452 * - READ-ONLY Register 1453 */ 1454 typedef union dtknq1_data { 1455 /** raw register data */ 1456 uint32_t d32; 1457 /** register bits */ 1458 struct { 1459 /** In Token Queue Write Pointer */ 1460 unsigned intknwptr:5; 1461 /** Reserved */ 1462 unsigned reserved05_06:2; 1463 /** write pointer has wrapped. */ 1464 unsigned wrap_bit:1; 1465 /** EP Numbers of IN Tokens 0 ... 4 */ 1466 unsigned epnums0_5:24; 1467 } b; 1468 } dtknq1_data_t; 1469 1470 /** 1471 * This union represents Threshold control Register 1472 * - Read and write the register into the <i>d32</i> member. 1473 * - READ-WRITABLE Register 1474 */ 1475 typedef union dthrctl_data { 1476 /** raw register data */ 1477 uint32_t d32; 1478 /** register bits */ 1479 struct { 1480 /** non ISO Tx Thr. Enable */ 1481 unsigned non_iso_thr_en:1; 1482 /** ISO Tx Thr. Enable */ 1483 unsigned iso_thr_en:1; 1484 /** Tx Thr. Length */ 1485 unsigned tx_thr_len:9; 1486 /** AHB Threshold ratio */ 1487 unsigned ahb_thr_ratio:2; 1488 /** Reserved */ 1489 unsigned reserved13_15:3; 1490 /** Rx Thr. Enable */ 1491 unsigned rx_thr_en:1; 1492 /** Rx Thr. Length */ 1493 unsigned rx_thr_len:9; 1494 unsigned reserved26:1; 1495 /** Arbiter Parking Enable*/ 1496 unsigned arbprken:1; 1497 /** Reserved */ 1498 unsigned reserved28_31:4; 1499 } b; 1500 } dthrctl_data_t; 1501 1502 /** 1503 * Device Logical IN Endpoint-Specific Registers. <i>Offsets 1504 * 900h-AFCh</i> 1505 * 1506 * There will be one set of endpoint registers per logical endpoint 1507 * implemented. 1508 * 1509 * <i>These registers are visible only in Device mode and must not be 1510 * accessed in Host mode, as the results are unknown.</i> 1511 */ 1512 typedef struct dwc_otg_dev_in_ep_regs { 1513 /** Device IN Endpoint Control Register. <i>Offset:900h + 1514 * (ep_num * 20h) + 00h</i> */ 1515 volatile uint32_t diepctl; 1516 /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */ 1517 uint32_t reserved04; 1518 /** Device IN Endpoint Interrupt Register. <i>Offset:900h + 1519 * (ep_num * 20h) + 08h</i> */ 1520 volatile uint32_t diepint; 1521 /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */ 1522 uint32_t reserved0C; 1523 /** Device IN Endpoint Transfer Size 1524 * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */ 1525 volatile uint32_t dieptsiz; 1526 /** Device IN Endpoint DMA Address Register. <i>Offset:900h + 1527 * (ep_num * 20h) + 14h</i> */ 1528 volatile uint32_t diepdma; 1529 /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h + 1530 * (ep_num * 20h) + 18h</i> */ 1531 volatile uint32_t dtxfsts; 1532 /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h + 1533 * (ep_num * 20h) + 1Ch</i> */ 1534 volatile uint32_t diepdmab; 1535 } dwc_otg_dev_in_ep_regs_t; 1536 1537 /** 1538 * Device Logical OUT Endpoint-Specific Registers. <i>Offsets: 1539 * B00h-CFCh</i> 1540 * 1541 * There will be one set of endpoint registers per logical endpoint 1542 * implemented. 1543 * 1544 * <i>These registers are visible only in Device mode and must not be 1545 * accessed in Host mode, as the results are unknown.</i> 1546 */ 1547 typedef struct dwc_otg_dev_out_ep_regs { 1548 /** Device OUT Endpoint Control Register. <i>Offset:B00h + 1549 * (ep_num * 20h) + 00h</i> */ 1550 volatile uint32_t doepctl; 1551 /** Device OUT Endpoint Frame number Register. <i>Offset: 1552 * B00h + (ep_num * 20h) + 04h</i> */ 1553 volatile uint32_t doepfn; 1554 /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h + 1555 * (ep_num * 20h) + 08h</i> */ 1556 volatile uint32_t doepint; 1557 /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */ 1558 uint32_t reserved0C; 1559 /** Device OUT Endpoint Transfer Size Register. <i>Offset: 1560 * B00h + (ep_num * 20h) + 10h</i> */ 1561 volatile uint32_t doeptsiz; 1562 /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h 1563 * + (ep_num * 20h) + 14h</i> */ 1564 volatile uint32_t doepdma; 1565 /** Reserved. <i>Offset:B00h + * (ep_num * 20h) + 18h</i> */ 1566 uint32_t unused; 1567 /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h 1568 * + (ep_num * 20h) + 1Ch</i> */ 1569 uint32_t doepdmab; 1570 } dwc_otg_dev_out_ep_regs_t; 1571 1572 /** 1573 * This union represents the bit fields in the Device EP Control 1574 * Register. Read the register into the <i>d32</i> member then 1575 * set/clear the bits using the <i>b</i>it elements. 1576 */ 1577 typedef union depctl_data { 1578 /** raw register data */ 1579 uint32_t d32; 1580 /** register bits */ 1581 struct { 1582 /** Maximum Packet Size 1583 * IN/OUT EPn 1584 * IN/OUT EP0 - 2 bits 1585 * 2'b00: 64 Bytes 1586 * 2'b01: 32 1587 * 2'b10: 16 1588 * 2'b11: 8 */ 1589 unsigned mps:11; 1590 #define DWC_DEP0CTL_MPS_64 0 1591 #define DWC_DEP0CTL_MPS_32 1 1592 #define DWC_DEP0CTL_MPS_16 2 1593 #define DWC_DEP0CTL_MPS_8 3 1594 1595 /** Next Endpoint 1596 * IN EPn/IN EP0 1597 * OUT EPn/OUT EP0 - reserved */ 1598 unsigned nextep:4; 1599 1600 /** USB Active Endpoint */ 1601 unsigned usbactep:1; 1602 1603 /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) 1604 * This field contains the PID of the packet going to 1605 * be received or transmitted on this endpoint. The 1606 * application should program the PID of the first 1607 * packet going to be received or transmitted on this 1608 * endpoint , after the endpoint is 1609 * activated. Application use the SetD1PID and 1610 * SetD0PID fields of this register to program either 1611 * D0 or D1 PID. 1612 * 1613 * The encoding for this field is 1614 * - 0: D0 1615 * - 1: D1 1616 */ 1617 unsigned dpid:1; 1618 1619 /** NAK Status */ 1620 unsigned naksts:1; 1621 1622 /** Endpoint Type 1623 * 2'b00: Control 1624 * 2'b01: Isochronous 1625 * 2'b10: Bulk 1626 * 2'b11: Interrupt */ 1627 unsigned eptype:2; 1628 1629 /** Snoop Mode 1630 * OUT EPn/OUT EP0 1631 * IN EPn/IN EP0 - reserved */ 1632 unsigned snp:1; 1633 1634 /** Stall Handshake */ 1635 unsigned stall:1; 1636 1637 /** Tx Fifo Number 1638 * IN EPn/IN EP0 1639 * OUT EPn/OUT EP0 - reserved */ 1640 unsigned txfnum:4; 1641 1642 /** Clear NAK */ 1643 unsigned cnak:1; 1644 /** Set NAK */ 1645 unsigned snak:1; 1646 /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) 1647 * Writing to this field sets the Endpoint DPID (DPID) 1648 * field in this register to DATA0. Set Even 1649 * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) 1650 * Writing to this field sets the Even/Odd 1651 * (micro)frame (EO_FrNum) field to even (micro) 1652 * frame. 1653 */ 1654 unsigned setd0pid:1; 1655 /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) 1656 * Writing to this field sets the Endpoint DPID (DPID) 1657 * field in this register to DATA1 Set Odd 1658 * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) 1659 * Writing to this field sets the Even/Odd 1660 * (micro)frame (EO_FrNum) field to odd (micro) frame. 1661 */ 1662 unsigned setd1pid:1; 1663 1664 /** Endpoint Disable */ 1665 unsigned epdis:1; 1666 /** Endpoint Enable */ 1667 unsigned epena:1; 1668 } b; 1669 } depctl_data_t; 1670 1671 /** 1672 * This union represents the bit fields in the Device EP Transfer 1673 * Size Register. Read the register into the <i>d32</i> member then 1674 * set/clear the bits using the <i>b</i>it elements. 1675 */ 1676 typedef union deptsiz_data { 1677 /** raw register data */ 1678 uint32_t d32; 1679 /** register bits */ 1680 struct { 1681 /** Transfer size */ 1682 unsigned xfersize:19; 1683 /** Packet Count */ 1684 unsigned pktcnt:10; 1685 /** Multi Count - Periodic IN endpoints */ 1686 unsigned mc:2; 1687 unsigned reserved:1; 1688 } b; 1689 } deptsiz_data_t; 1690 1691 /** 1692 * This union represents the bit fields in the Device EP 0 Transfer 1693 * Size Register. Read the register into the <i>d32</i> member then 1694 * set/clear the bits using the <i>b</i>it elements. 1695 */ 1696 typedef union deptsiz0_data { 1697 /** raw register data */ 1698 uint32_t d32; 1699 /** register bits */ 1700 struct { 1701 /** Transfer size */ 1702 unsigned xfersize:7; 1703 /** Reserved */ 1704 unsigned reserved7_18:12; 1705 /** Packet Count */ 1706 unsigned pktcnt:2; 1707 /** Reserved */ 1708 unsigned reserved21_28:8; 1709 /**Setup Packet Count (DOEPTSIZ0 Only) */ 1710 unsigned supcnt:2; 1711 unsigned reserved31; 1712 } b; 1713 } 1714 #if __GNUC__ /*GCC*/ 1715 __attribute__((__may_alias__)) deptsiz0_data_t; 1716 #else 1717 deptsiz0_data_t; 1718 #endif 1719 ///////////////////////////////////////////////// 1720 // DMA Descriptor Specific Structures 1721 // 1722 1723 /** Buffer status definitions */ 1724 1725 #define BS_HOST_READY 0x0 1726 #define BS_DMA_BUSY 0x1 1727 #define BS_DMA_DONE 0x2 1728 #define BS_HOST_BUSY 0x3 1729 1730 /** Receive/Transmit status definitions */ 1731 1732 #define RTS_SUCCESS 0x0 1733 #define RTS_BUFFLUSH 0x1 1734 #define RTS_RESERVED 0x2 1735 #define RTS_BUFERR 0x3 1736 1737 /** 1738 * This union represents the bit fields in the DMA Descriptor 1739 * status quadlet. Read the quadlet into the <i>d32</i> member then 1740 * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and 1741 * <i>b_iso_in</i> elements. 1742 */ 1743 typedef union dev_dma_desc_sts { 1744 /** raw register data */ 1745 uint32_t d32; 1746 /** quadlet bits */ 1747 struct { 1748 /** Received number of bytes */ 1749 unsigned bytes:16; 1750 1751 unsigned reserved16_22:7; 1752 /** Multiple Transfer - only for OUT EPs */ 1753 unsigned mtrf:1; 1754 /** Setup Packet received - only for OUT EPs */ 1755 unsigned sr:1; 1756 /** Interrupt On Complete */ 1757 unsigned ioc:1; 1758 /** Short Packet */ 1759 unsigned sp:1; 1760 /** Last */ 1761 unsigned l:1; 1762 /** Receive Status */ 1763 unsigned sts:2; 1764 /** Buffer Status */ 1765 unsigned bs:2; 1766 } b; 1767 1768 //#ifdef DWC_EN_ISOC 1769 /** iso out quadlet bits */ 1770 struct { 1771 /** Received number of bytes */ 1772 unsigned rxbytes:11; 1773 1774 unsigned reserved11:1; 1775 /** Frame Number */ 1776 unsigned framenum:11; 1777 /** Received ISO Data PID */ 1778 unsigned pid:2; 1779 /** Interrupt On Complete */ 1780 unsigned ioc:1; 1781 /** Short Packet */ 1782 unsigned sp:1; 1783 /** Last */ 1784 unsigned l:1; 1785 /** Receive Status */ 1786 unsigned rxsts:2; 1787 /** Buffer Status */ 1788 unsigned bs:2; 1789 } b_iso_out; 1790 1791 /** iso in quadlet bits */ 1792 struct { 1793 /** Transmited number of bytes */ 1794 unsigned txbytes:12; 1795 /** Frame Number */ 1796 unsigned framenum:11; 1797 /** Transmited ISO Data PID */ 1798 unsigned pid:2; 1799 /** Interrupt On Complete */ 1800 unsigned ioc:1; 1801 /** Short Packet */ 1802 unsigned sp:1; 1803 /** Last */ 1804 unsigned l:1; 1805 /** Transmit Status */ 1806 unsigned txsts:2; 1807 /** Buffer Status */ 1808 unsigned bs:2; 1809 } b_iso_in; 1810 //#endif /* DWC_EN_ISOC */ 1811 } dev_dma_desc_sts_t; 1812 1813 /** 1814 * DMA Descriptor structure 1815 * 1816 * DMA Descriptor structure contains two quadlets: 1817 * Status quadlet and Data buffer pointer. 1818 */ 1819 typedef struct dwc_otg_dev_dma_desc { 1820 /** DMA Descriptor status quadlet */ 1821 dev_dma_desc_sts_t status; 1822 /** DMA Descriptor data buffer pointer */ 1823 uint32_t buf; 1824 } dwc_otg_dev_dma_desc_t; 1825 1826 /** 1827 * The dwc_otg_dev_if structure contains information needed to manage 1828 * the DWC_otg controller acting in device mode. It represents the 1829 * programming view of the device-specific aspects of the controller. 1830 */ 1831 typedef struct dwc_otg_dev_if { 1832 /** Pointer to device Global registers. 1833 * Device Global Registers starting at offset 800h 1834 */ 1835 dwc_otg_device_global_regs_t *dev_global_regs; 1836 #define DWC_DEV_GLOBAL_REG_OFFSET 0x800 1837 1838 /** 1839 * Device Logical IN Endpoint-Specific Registers 900h-AFCh 1840 */ 1841 dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; 1842 #define DWC_DEV_IN_EP_REG_OFFSET 0x900 1843 #define DWC_EP_REG_OFFSET 0x20 1844 1845 /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ 1846 dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; 1847 #define DWC_DEV_OUT_EP_REG_OFFSET 0xB00 1848 1849 /* Device configuration information */ 1850 uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */ 1851 uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */ 1852 uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/ 1853 1854 /** Size of periodic FIFOs (Bytes) */ 1855 uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; 1856 1857 /** Size of Tx FIFOs (Bytes) */ 1858 uint16_t tx_fifo_size[MAX_TX_FIFOS]; 1859 1860 /** Thresholding enable flags and length varaiables **/ 1861 uint16_t rx_thr_en; 1862 uint16_t iso_tx_thr_en; 1863 uint16_t non_iso_tx_thr_en; 1864 1865 uint16_t rx_thr_length; 1866 uint16_t tx_thr_length; 1867 1868 /** 1869 * Pointers to the DMA Descriptors for EP0 Control 1870 * transfers (virtual and physical) 1871 */ 1872 1873 /** 2 descriptors for SETUP packets */ 1874 dwc_dma_t dma_setup_desc_addr[2]; 1875 dwc_otg_dev_dma_desc_t *setup_desc_addr[2]; 1876 1877 /** Pointer to Descriptor with latest SETUP packet */ 1878 dwc_otg_dev_dma_desc_t *psetup; 1879 1880 /** Index of current SETUP handler descriptor */ 1881 uint32_t setup_desc_index; 1882 1883 /** Descriptor for Data In or Status In phases */ 1884 dwc_dma_t dma_in_desc_addr; 1885 dwc_otg_dev_dma_desc_t *in_desc_addr; 1886 1887 /** Descriptor for Data Out or Status Out phases */ 1888 dwc_dma_t dma_out_desc_addr; 1889 dwc_otg_dev_dma_desc_t *out_desc_addr; 1890 1891 /** Setup Packet Detected - if set clear NAK when queueing */ 1892 uint32_t spd; 1893 1894 } dwc_otg_dev_if_t; 1895 1896 ///////////////////////////////////////////////// 1897 // Host Mode Register Structures 1898 // 1899 /** 1900 * The Host Global Registers structure defines the size and relative 1901 * field offsets for the Host Mode Global Registers. Host Global 1902 * Registers offsets 400h-7FFh. 1903 */ 1904 typedef struct dwc_otg_host_global_regs { 1905 /** Host Configuration Register. <i>Offset: 400h</i> */ 1906 volatile uint32_t hcfg; 1907 /** Host Frame Interval Register. <i>Offset: 404h</i> */ 1908 volatile uint32_t hfir; 1909 /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */ 1910 volatile uint32_t hfnum; 1911 /** Reserved. <i>Offset: 40Ch</i> */ 1912 uint32_t reserved40C; 1913 /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */ 1914 volatile uint32_t hptxsts; 1915 /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */ 1916 volatile uint32_t haint; 1917 /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */ 1918 volatile uint32_t haintmsk; 1919 /** Host Frame List Base Address Register . <i>Offset: 41Ch</i> */ 1920 volatile uint32_t hflbaddr; 1921 } dwc_otg_host_global_regs_t; 1922 1923 /** 1924 * This union represents the bit fields in the Host Configuration Register. 1925 * Read the register into the <i>d32</i> member then set/clear the bits using 1926 * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register. 1927 */ 1928 typedef union hcfg_data { 1929 /** raw register data */ 1930 uint32_t d32; 1931 1932 /** register bits */ 1933 struct { 1934 /** FS/LS Phy Clock Select */ 1935 unsigned fslspclksel:2; 1936 #define DWC_HCFG_30_60_MHZ 0 1937 #define DWC_HCFG_48_MHZ 1 1938 #define DWC_HCFG_6_MHZ 2 1939 1940 /** FS/LS Only Support */ 1941 unsigned fslssupp:1; 1942 unsigned reserved3_6:4; 1943 /** Enable 32-KHz Suspend Mode */ 1944 unsigned ena32khzs:1; 1945 /** Resume Validation Periiod */ 1946 unsigned resvalid:8; 1947 unsigned reserved16_22:7; 1948 /** Enable Scatter/gather DMA in Host mode */ 1949 unsigned descdma:1; 1950 /** Frame List Entries */ 1951 unsigned frlisten:2; 1952 /** Enable Periodic Scheduling */ 1953 unsigned perschedena:1; 1954 unsigned reserved27_30:4; 1955 unsigned modechtimen:1; 1956 } b; 1957 } hcfg_data_t; 1958 1959 /** 1960 * This union represents the bit fields in the Host Frame Remaing/Number 1961 * Register. 1962 */ 1963 typedef union hfir_data { 1964 /** raw register data */ 1965 uint32_t d32; 1966 1967 /** register bits */ 1968 struct { 1969 unsigned frint:16; 1970 unsigned hfirrldctrl:1; 1971 unsigned reserved:15; 1972 } b; 1973 } hfir_data_t; 1974 1975 /** 1976 * This union represents the bit fields in the Host Frame Remaing/Number 1977 * Register. 1978 */ 1979 typedef union hfnum_data { 1980 /** raw register data */ 1981 uint32_t d32; 1982 1983 /** register bits */ 1984 struct { 1985 unsigned frnum:16; 1986 #define DWC_HFNUM_MAX_FRNUM 0x3FFF 1987 unsigned frrem:16; 1988 } b; 1989 } hfnum_data_t; 1990 1991 typedef union hptxsts_data { 1992 /** raw register data */ 1993 uint32_t d32; 1994 1995 /** register bits */ 1996 struct { 1997 unsigned ptxfspcavail:16; 1998 unsigned ptxqspcavail:8; 1999 /** Top of the Periodic Transmit Request Queue 2000 * - bit 24 - Terminate (last entry for the selected channel) 2001 * - bits 26:25 - Token Type 2002 * - 2'b00 - Zero length 2003 * - 2'b01 - Ping 2004 * - 2'b10 - Disable 2005 * - bits 30:27 - Channel Number 2006 * - bit 31 - Odd/even microframe 2007 */ 2008 unsigned ptxqtop_terminate:1; 2009 unsigned ptxqtop_token:2; 2010 unsigned ptxqtop_chnum:4; 2011 unsigned ptxqtop_odd:1; 2012 } b; 2013 } hptxsts_data_t; 2014 2015 /** 2016 * This union represents the bit fields in the Host Port Control and Status 2017 * Register. Read the register into the <i>d32</i> member then set/clear the 2018 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the 2019 * hprt0 register. 2020 */ 2021 typedef union hprt0_data { 2022 /** raw register data */ 2023 uint32_t d32; 2024 /** register bits */ 2025 struct { 2026 unsigned prtconnsts:1; 2027 unsigned prtconndet:1; 2028 unsigned prtena:1; 2029 unsigned prtenchng:1; 2030 unsigned prtovrcurract:1; 2031 unsigned prtovrcurrchng:1; 2032 unsigned prtres:1; 2033 unsigned prtsusp:1; 2034 unsigned prtrst:1; 2035 unsigned reserved9:1; 2036 unsigned prtlnsts:2; 2037 unsigned prtpwr:1; 2038 unsigned prttstctl:4; 2039 unsigned prtspd:2; 2040 #define DWC_HPRT0_PRTSPD_HIGH_SPEED 0 2041 #define DWC_HPRT0_PRTSPD_FULL_SPEED 1 2042 #define DWC_HPRT0_PRTSPD_LOW_SPEED 2 2043 unsigned reserved19_31:13; 2044 } b; 2045 } hprt0_data_t; 2046 2047 /** 2048 * This union represents the bit fields in the Host All Interrupt 2049 * Register. 2050 */ 2051 typedef union haint_data { 2052 /** raw register data */ 2053 uint32_t d32; 2054 /** register bits */ 2055 struct { 2056 unsigned ch0:1; 2057 unsigned ch1:1; 2058 unsigned ch2:1; 2059 unsigned ch3:1; 2060 unsigned ch4:1; 2061 unsigned ch5:1; 2062 unsigned ch6:1; 2063 unsigned ch7:1; 2064 unsigned ch8:1; 2065 unsigned ch9:1; 2066 unsigned ch10:1; 2067 unsigned ch11:1; 2068 unsigned ch12:1; 2069 unsigned ch13:1; 2070 unsigned ch14:1; 2071 unsigned ch15:1; 2072 unsigned reserved:16; 2073 } b; 2074 2075 struct { 2076 unsigned chint:16; 2077 unsigned reserved:16; 2078 } b2; 2079 } haint_data_t; 2080 2081 /** 2082 * This union represents the bit fields in the Host All Interrupt 2083 * Register. 2084 */ 2085 typedef union haintmsk_data { 2086 /** raw register data */ 2087 uint32_t d32; 2088 /** register bits */ 2089 struct { 2090 unsigned ch0:1; 2091 unsigned ch1:1; 2092 unsigned ch2:1; 2093 unsigned ch3:1; 2094 unsigned ch4:1; 2095 unsigned ch5:1; 2096 unsigned ch6:1; 2097 unsigned ch7:1; 2098 unsigned ch8:1; 2099 unsigned ch9:1; 2100 unsigned ch10:1; 2101 unsigned ch11:1; 2102 unsigned ch12:1; 2103 unsigned ch13:1; 2104 unsigned ch14:1; 2105 unsigned ch15:1; 2106 unsigned reserved:16; 2107 } b; 2108 2109 struct { 2110 unsigned chint:16; 2111 unsigned reserved:16; 2112 } b2; 2113 } haintmsk_data_t; 2114 2115 /** 2116 * Host Channel Specific Registers. <i>500h-5FCh</i> 2117 */ 2118 typedef struct dwc_otg_hc_regs { 2119 /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */ 2120 volatile uint32_t hcchar; 2121 /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */ 2122 volatile uint32_t hcsplt; 2123 /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */ 2124 volatile uint32_t hcint; 2125 /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */ 2126 volatile uint32_t hcintmsk; 2127 /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */ 2128 volatile uint32_t hctsiz; 2129 /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */ 2130 volatile uint32_t hcdma; 2131 volatile uint32_t reserved; 2132 /** Host Channel 0 DMA Buffer Address Register. <i>Offset: 500h + (chan_num * 20h) + 1Ch</i> */ 2133 volatile uint32_t hcdmab; 2134 } dwc_otg_hc_regs_t; 2135 2136 /** 2137 * This union represents the bit fields in the Host Channel Characteristics 2138 * Register. Read the register into the <i>d32</i> member then set/clear the 2139 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the 2140 * hcchar register. 2141 */ 2142 typedef union hcchar_data { 2143 /** raw register data */ 2144 uint32_t d32; 2145 2146 /** register bits */ 2147 struct { 2148 /** Maximum packet size in bytes */ 2149 unsigned mps:11; 2150 2151 /** Endpoint number */ 2152 unsigned epnum:4; 2153 2154 /** 0: OUT, 1: IN */ 2155 unsigned epdir:1; 2156 2157 unsigned reserved:1; 2158 2159 /** 0: Full/high speed device, 1: Low speed device */ 2160 unsigned lspddev:1; 2161 2162 /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ 2163 unsigned eptype:2; 2164 2165 /** Packets per frame for periodic transfers. 0 is reserved. */ 2166 unsigned multicnt:2; 2167 2168 /** Device address */ 2169 unsigned devaddr:7; 2170 2171 /** 2172 * Frame to transmit periodic transaction. 2173 * 0: even, 1: odd 2174 */ 2175 unsigned oddfrm:1; 2176 2177 /** Channel disable */ 2178 unsigned chdis:1; 2179 2180 /** Channel enable */ 2181 unsigned chen:1; 2182 } b; 2183 } hcchar_data_t; 2184 2185 typedef union hcsplt_data { 2186 /** raw register data */ 2187 uint32_t d32; 2188 2189 /** register bits */ 2190 struct { 2191 /** Port Address */ 2192 unsigned prtaddr:7; 2193 2194 /** Hub Address */ 2195 unsigned hubaddr:7; 2196 2197 /** Transaction Position */ 2198 unsigned xactpos:2; 2199 #define DWC_HCSPLIT_XACTPOS_MID 0 2200 #define DWC_HCSPLIT_XACTPOS_END 1 2201 #define DWC_HCSPLIT_XACTPOS_BEGIN 2 2202 #define DWC_HCSPLIT_XACTPOS_ALL 3 2203 2204 /** Do Complete Split */ 2205 unsigned compsplt:1; 2206 2207 /** Reserved */ 2208 unsigned reserved:14; 2209 2210 /** Split Enble */ 2211 unsigned spltena:1; 2212 } b; 2213 } hcsplt_data_t; 2214 2215 /** 2216 * This union represents the bit fields in the Host All Interrupt 2217 * Register. 2218 */ 2219 typedef union hcint_data { 2220 /** raw register data */ 2221 uint32_t d32; 2222 /** register bits */ 2223 struct { 2224 /** Transfer Complete */ 2225 unsigned xfercomp:1; 2226 /** Channel Halted */ 2227 unsigned chhltd:1; 2228 /** AHB Error */ 2229 unsigned ahberr:1; 2230 /** STALL Response Received */ 2231 unsigned stall:1; 2232 /** NAK Response Received */ 2233 unsigned nak:1; 2234 /** ACK Response Received */ 2235 unsigned ack:1; 2236 /** NYET Response Received */ 2237 unsigned nyet:1; 2238 /** Transaction Err */ 2239 unsigned xacterr:1; 2240 /** Babble Error */ 2241 unsigned bblerr:1; 2242 /** Frame Overrun */ 2243 unsigned frmovrun:1; 2244 /** Data Toggle Error */ 2245 unsigned datatglerr:1; 2246 /** Buffer Not Available (only for DDMA mode) */ 2247 unsigned bna:1; 2248 /** Exessive transaction error (only for DDMA mode) */ 2249 unsigned xcs_xact:1; 2250 /** Frame List Rollover interrupt */ 2251 unsigned frm_list_roll:1; 2252 /** Reserved */ 2253 unsigned reserved14_31:18; 2254 } b; 2255 } hcint_data_t; 2256 2257 /** 2258 * This union represents the bit fields in the Host Channel Interrupt Mask 2259 * Register. Read the register into the <i>d32</i> member then set/clear the 2260 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the 2261 * hcintmsk register. 2262 */ 2263 typedef union hcintmsk_data { 2264 /** raw register data */ 2265 uint32_t d32; 2266 2267 /** register bits */ 2268 struct { 2269 unsigned xfercompl:1; 2270 unsigned chhltd:1; 2271 unsigned ahberr:1; 2272 unsigned stall:1; 2273 unsigned nak:1; 2274 unsigned ack:1; 2275 unsigned nyet:1; 2276 unsigned xacterr:1; 2277 unsigned bblerr:1; 2278 unsigned frmovrun:1; 2279 unsigned datatglerr:1; 2280 unsigned bna:1; 2281 unsigned xcs_xact:1; 2282 unsigned frm_list_roll:1; 2283 unsigned reserved14_31:18; 2284 } b; 2285 } hcintmsk_data_t; 2286 2287 /** 2288 * This union represents the bit fields in the Host Channel Transfer Size 2289 * Register. Read the register into the <i>d32</i> member then set/clear the 2290 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the 2291 * hcchar register. 2292 */ 2293 2294 typedef union hctsiz_data { 2295 /** raw register data */ 2296 uint32_t d32; 2297 2298 /** register bits */ 2299 struct { 2300 /** Total transfer size in bytes */ 2301 unsigned xfersize:19; 2302 2303 /** Data packets to transfer */ 2304 unsigned pktcnt:10; 2305 2306 /** 2307 * Packet ID for next data packet 2308 * 0: DATA0 2309 * 1: DATA2 2310 * 2: DATA1 2311 * 3: MDATA (non-Control), SETUP (Control) 2312 */ 2313 unsigned pid:2; 2314 #define DWC_HCTSIZ_DATA0 0 2315 #define DWC_HCTSIZ_DATA1 2 2316 #define DWC_HCTSIZ_DATA2 1 2317 #define DWC_HCTSIZ_MDATA 3 2318 #define DWC_HCTSIZ_SETUP 3 2319 2320 /** Do PING protocol when 1 */ 2321 unsigned dopng:1; 2322 } b; 2323 2324 /** register bits */ 2325 struct { 2326 /** Scheduling information */ 2327 unsigned schinfo:8; 2328 2329 /** Number of transfer descriptors. 2330 * Max value: 2331 * 64 in general, 2332 * 256 only for HS isochronous endpoint. 2333 */ 2334 unsigned ntd:8; 2335 2336 /** Data packets to transfer */ 2337 unsigned reserved16_28:13; 2338 2339 /** 2340 * Packet ID for next data packet 2341 * 0: DATA0 2342 * 1: DATA2 2343 * 2: DATA1 2344 * 3: MDATA (non-Control) 2345 */ 2346 unsigned pid:2; 2347 2348 /** Do PING protocol when 1 */ 2349 unsigned dopng:1; 2350 } b_ddma; 2351 } hctsiz_data_t; 2352 2353 /** 2354 * This union represents the bit fields in the Host DMA Address 2355 * Register used in Descriptor DMA mode. 2356 */ 2357 typedef union hcdma_data { 2358 /** raw register data */ 2359 uint32_t d32; 2360 /** register bits */ 2361 struct { 2362 unsigned reserved0_2:3; 2363 /** Current Transfer Descriptor. Not used for ISOC */ 2364 unsigned ctd:8; 2365 /** Start Address of Descriptor List */ 2366 unsigned dma_addr:21; 2367 } b; 2368 } hcdma_data_t; 2369 2370 /** 2371 * This union represents the bit fields in the DMA Descriptor 2372 * status quadlet for host mode. Read the quadlet into the <i>d32</i> member then 2373 * set/clear the bits using the <i>b</i>it elements. 2374 */ 2375 typedef union host_dma_desc_sts { 2376 /** raw register data */ 2377 uint32_t d32; 2378 /** quadlet bits */ 2379 2380 /* for non-isochronous */ 2381 struct { 2382 /** Number of bytes */ 2383 unsigned n_bytes:17; 2384 /** QTD offset to jump when Short Packet received - only for IN EPs */ 2385 unsigned qtd_offset:6; 2386 /** 2387 * Set to request the core to jump to alternate QTD if 2388 * Short Packet received - only for IN EPs 2389 */ 2390 unsigned a_qtd:1; 2391 /** 2392 * Setup Packet bit. When set indicates that buffer contains 2393 * setup packet. 2394 */ 2395 unsigned sup:1; 2396 /** Interrupt On Complete */ 2397 unsigned ioc:1; 2398 /** End of List */ 2399 unsigned eol:1; 2400 unsigned reserved27:1; 2401 /** Rx/Tx Status */ 2402 unsigned sts:2; 2403 #define DMA_DESC_STS_PKTERR 1 2404 unsigned reserved30:1; 2405 /** Active Bit */ 2406 unsigned a:1; 2407 } b; 2408 /* for isochronous */ 2409 struct { 2410 /** Number of bytes */ 2411 unsigned n_bytes:12; 2412 unsigned reserved12_24:13; 2413 /** Interrupt On Complete */ 2414 unsigned ioc:1; 2415 unsigned reserved26_27:2; 2416 /** Rx/Tx Status */ 2417 unsigned sts:2; 2418 unsigned reserved30:1; 2419 /** Active Bit */ 2420 unsigned a:1; 2421 } b_isoc; 2422 } host_dma_desc_sts_t; 2423 2424 #define MAX_DMA_DESC_SIZE 131071 2425 #define MAX_DMA_DESC_NUM_GENERIC 64 2426 #define MAX_DMA_DESC_NUM_HS_ISOC 256 2427 #define MAX_FRLIST_EN_NUM 64 2428 /** 2429 * Host-mode DMA Descriptor structure 2430 * 2431 * DMA Descriptor structure contains two quadlets: 2432 * Status quadlet and Data buffer pointer. 2433 */ 2434 typedef struct dwc_otg_host_dma_desc { 2435 /** DMA Descriptor status quadlet */ 2436 host_dma_desc_sts_t status; 2437 /** DMA Descriptor data buffer pointer */ 2438 uint32_t buf; 2439 } dwc_otg_host_dma_desc_t; 2440 2441 /** OTG Host Interface Structure. 2442 * 2443 * The OTG Host Interface Structure structure contains information 2444 * needed to manage the DWC_otg controller acting in host mode. It 2445 * represents the programming view of the host-specific aspects of the 2446 * controller. 2447 */ 2448 typedef struct dwc_otg_host_if { 2449 /** Host Global Registers starting at offset 400h.*/ 2450 dwc_otg_host_global_regs_t *host_global_regs; 2451 #define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 2452 2453 /** Host Port 0 Control and Status Register */ 2454 volatile uint32_t *hprt0; 2455 #define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 2456 2457 /** Host Channel Specific Registers at offsets 500h-5FCh. */ 2458 dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; 2459 #define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 2460 #define DWC_OTG_CHAN_REGS_OFFSET 0x20 2461 2462 /* Host configuration information */ 2463 /** Number of Host Channels (range: 1-16) */ 2464 uint8_t num_host_channels; 2465 /** Periodic EPs supported (0: no, 1: yes) */ 2466 uint8_t perio_eps_supported; 2467 /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */ 2468 uint16_t perio_tx_fifo_size; 2469 2470 } dwc_otg_host_if_t; 2471 2472 /** 2473 * This union represents the bit fields in the Power and Clock Gating Control 2474 * Register. Read the register into the <i>d32</i> member then set/clear the 2475 * bits using the <i>b</i>it elements. 2476 */ 2477 typedef union pcgcctl_data { 2478 /** raw register data */ 2479 uint32_t d32; 2480 2481 /** register bits */ 2482 struct { 2483 /** Stop Pclk */ 2484 unsigned stoppclk:1; 2485 /** Gate Hclk */ 2486 unsigned gatehclk:1; 2487 /** Power Clamp */ 2488 unsigned pwrclmp:1; 2489 /** Reset Power Down Modules */ 2490 unsigned rstpdwnmodule:1; 2491 /** Reserved */ 2492 unsigned reserved:1; 2493 /** Enable Sleep Clock Gating (Enbl_L1Gating) */ 2494 unsigned enbl_sleep_gating:1; 2495 /** PHY In Sleep (PhySleep) */ 2496 unsigned phy_in_sleep:1; 2497 /** Deep Sleep*/ 2498 unsigned deep_sleep:1; 2499 unsigned resetaftsusp:1; 2500 unsigned restoremode:1; 2501 unsigned reserved10_12:3; 2502 unsigned ess_reg_restored:1; 2503 unsigned prt_clk_sel:2; 2504 unsigned port_power:1; 2505 unsigned max_xcvrselect:2; 2506 unsigned max_termsel:1; 2507 unsigned mac_dev_addr:7; 2508 unsigned p2hd_dev_enum_spd:2; 2509 unsigned p2hd_prt_spd:2; 2510 unsigned if_dev_mode:1; 2511 } b; 2512 } pcgcctl_data_t; 2513 2514 /** 2515 * This union represents the bit fields in the Global Data FIFO Software Configuration Register. 2516 * Read the register into the <i>d32</i> member then set/clear the 2517 * bits using the <i>b</i>it elements. 2518 */ 2519 typedef union gdfifocfg_data { 2520 /* raw register data */ 2521 uint32_t d32; 2522 /** register bits */ 2523 struct { 2524 /** OTG Data FIFO depth */ 2525 unsigned gdfifocfg:16; 2526 /** Start address of EP info controller */ 2527 unsigned epinfobase:16; 2528 } b; 2529 } gdfifocfg_data_t; 2530 2531 /** 2532 * This union represents the bit fields in the Global Power Down Register 2533 * Register. Read the register into the <i>d32</i> member then set/clear the 2534 * bits using the <i>b</i>it elements. 2535 */ 2536 typedef union gpwrdn_data { 2537 /* raw register data */ 2538 uint32_t d32; 2539 2540 /** register bits */ 2541 struct { 2542 /** PMU Interrupt Select */ 2543 unsigned pmuintsel:1; 2544 /** PMU Active */ 2545 unsigned pmuactv:1; 2546 /** Restore */ 2547 unsigned restore:1; 2548 /** Power Down Clamp */ 2549 unsigned pwrdnclmp:1; 2550 /** Power Down Reset */ 2551 unsigned pwrdnrstn:1; 2552 /** Power Down Switch */ 2553 unsigned pwrdnswtch:1; 2554 /** Disable VBUS */ 2555 unsigned dis_vbus:1; 2556 /** Line State Change */ 2557 unsigned lnstschng:1; 2558 /** Line state change mask */ 2559 unsigned lnstchng_msk:1; 2560 /** Reset Detected */ 2561 unsigned rst_det:1; 2562 /** Reset Detect mask */ 2563 unsigned rst_det_msk:1; 2564 /** Disconnect Detected */ 2565 unsigned disconn_det:1; 2566 /** Disconnect Detect mask */ 2567 unsigned disconn_det_msk:1; 2568 /** Connect Detected*/ 2569 unsigned connect_det:1; 2570 /** Connect Detected Mask*/ 2571 unsigned connect_det_msk:1; 2572 /** SRP Detected */ 2573 unsigned srp_det:1; 2574 /** SRP Detect mask */ 2575 unsigned srp_det_msk:1; 2576 /** Status Change Interrupt */ 2577 unsigned sts_chngint:1; 2578 /** Status Change Interrupt Mask */ 2579 unsigned sts_chngint_msk:1; 2580 /** Line State */ 2581 unsigned linestate:2; 2582 /** Indicates current mode(status of IDDIG signal) */ 2583 unsigned idsts:1; 2584 /** B Session Valid signal status*/ 2585 unsigned bsessvld:1; 2586 /** ADP Event Detected */ 2587 unsigned adp_int:1; 2588 /** Multi Valued ID pin */ 2589 unsigned mult_val_id_bc:5; 2590 /** Reserved 24_31 */ 2591 unsigned reserved29_31:3; 2592 } b; 2593 } gpwrdn_data_t; 2594 2595 #endif 2596
