Searched refs:control (Results 1 – 25 of 171) sorted by relevance
1234567
| /hal_infineon-3.7.0/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM7/TOOLCHAIN_ARM/ |
| D | xmc7100_x1088_cm7.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
|
| D | xmc7100_x2112_cm7.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
|
| D | xmc7100_x4160_cm7.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
|
| D | xmc7200_x8384_cm7.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
|
| D | xmc7200d_x8384_cm7.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
|
| D | xmc7100d_x2112_cm7.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
|
| D | xmc7100d_x4160_cm7.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
|
| /hal_infineon-3.7.0/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| D | xmc7100_x1088_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
|
| D | xmc7100_x2112_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
|
| D | xmc7100_x4160_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
|
| D | xmc7100d_x2112_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
|
| D | xmc7100d_x4160_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
|
| D | xmc7200_x8384_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
|
| D | xmc7200d_x8384_cm0plus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
|
| /hal_infineon-3.7.0/mtb-template-cat1/files/templates/cat1b/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/ |
| D | cyw20829A0_ns_ram_cbus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM33 core.
|
| D | cyw20829A0_ns_ram_sahb.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM33 core.
|
| D | cyw20829_ns_ram_cbus.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM33 core.
|
| D | cyw20829_ns_ram_sahb.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM33 core.
|
| /hal_infineon-3.7.0/mtb-template-cat1/files/templates/cat1a/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/ |
| D | cyb06xx5_cm4.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
|
| D | cyb06xx5_cm4_dual.sct | 12 ;* input files should be mapped into the output file, and to control the memory
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
|
| /hal_infineon-3.7.0/abstraction-rtos/ |
| D | LICENSE | 16 that control, are controlled by, or are under common control with that entity.
17 For the purposes of this definition, "control" means (i) the power, direct or
51 communication on electronic mailing lists, source code control systems, and
|
| /hal_infineon-3.7.0/mtb-pdl-cat1/ |
| D | LICENSE | 16 that control, are controlled by, or are under common control with that entity.
17 For the purposes of this definition, "control" means (i) the power, direct or
51 communication on electronic mailing lists, source code control systems, and
|
| /hal_infineon-3.7.0/mtb-hal-cat1/ |
| D | LICENSE | 16 that control, are controlled by, or are under common control with that entity.
17 For the purposes of this definition, "control" means (i) the power, direct or
51 communication on electronic mailing lists, source code control systems, and
|
| /hal_infineon-3.7.0/core-lib/ |
| D | LICENSE | 16 that control, are controlled by, or are under common control with that entity.
17 For the purposes of this definition, "control" means (i) the power, direct or
51 communication on electronic mailing lists, source code control systems, and
|
| /hal_infineon-3.7.0/mtb-template-cat1/ |
| D | LICENSE | 16 that control, are controlled by, or are under common control with that entity.
17 For the purposes of this definition, "control" means (i) the power, direct or
51 communication on electronic mailing lists, source code control systems, and
|
1234567
