1 /**
2 * @file xmc_usic.h
3 * @date 2019-07-01
4 *
5 * @cond
6 *********************************************************************************************************************
7 * XMClib v2.1.24 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015-2019, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
22 * products derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
33 * Infineon Technologies AG dave@infineon.com).
34 *********************************************************************************************************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-02-20:
40 * - Initial draft<br>
41 * - Documentation improved <br>
42 *
43 * 2015-05-08:
44 * - Added XMC_USIC_CH_SetInputTriggerCombinationMode() and XMC_USIC_CH_SetTransmitBufferStatus() <br>
45 *
46 * 2015-06-20:
47 * - Removed version macros and declaration of GetDriverVersion API
48 *
49 * 2015-08-17:
50 * - Bug fixed in XMC_USIC_CH_SetTransmitBufferStatus API. OR operator removed.
51 *
52 * 2015-08-24:
53 * - Added APIs for enabling/disabling delay compensation XMC_USIC_CH_DisableDelayCompensation() and
54 * XMC_USIC_CH_DisableDelayCompensation()
55 *
56 * 2015-08-25:
57 * - Added APIs for defining if the data shift unit input is derived
58 * from the input data path DXn or from the selected protocol pre-processors: XMC_USIC_CH_ConnectInputDataShiftToPPP()
59 * and XMC_USIC_CH_ConnectInputDataShiftToDataInput()
60 *
61 * 2015-08-27:
62 * - Fixed bug in XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T value.
63 * - Added APIs for direct TBUF access: XMC_USIC_CH_WriteToTBUF() and XMC_USIC_CH_WriteToTBUFTCI()
64 * - Added APIs for external input for BRG configuration:XMC_USIC_CH_ConfigExternalInputSignalToBRG() and XMC_USIC_CH_SetBRGInputClockSource()
65 *
66 * 2015-08-28:
67 * - Added API for enabling the transfer trigger unit to set bit TCSR.TE if the trigger signal DX2T becomes active. Feature used for RS-232
68 * Clear to Send (CTS) signal: XMC_USIC_CH_EnableTBUFDataValidTrigger() and XMC_USIC_CH_DisableTBUFDataValidTrigger().
69 *
70 * 2016-03-09:
71 * - Optimization of write only registers
72 *
73 * 2016-04-10:
74 * - Added an API to put the data into FIFO when hardware port control is enabled: XMC_USIC_CH_TXFIFO_PutDataHPCMode() <br>
75 *
76 * 2017-02-10:
77 * - Added XMC_USIC_CH_SetShiftDirection() to allow selection of shift direction of the data words for transmision and reception
78 * - Added XMC_USIC_CH_GetCaptureTimerValue() and XMC_USIC_CH_SetFractionalDivider()
79 *
80 * 2017-09-08:
81 * - Fixed value of macro XMC_USIC_CH_SHIFT_DIRECTION_MSB_FIRST used in XMC_USIC_CH_SetShiftDirection()
82 *
83 * 2018-09-29:
84 * - Added XMC_USIC_CH_SetBaudrateEx which uses the integer divider instead of the fractional divider <br>
85 *
86 * 2019-05-07:
87 * - Added XMC_USIC_CH_GetBaudrate(), XMC_USIC_CH_GetSCLKFrequency() and XMC_USIC_CH_GetMCLKFrequency()
88 *
89 * 2019-07-01:
90 * - Changed XMC_USIC_CH_SetBaudrateEx() input parameter types
91 *
92 * @endcond
93 *
94 */
95
96 #ifndef XMC_USIC_H
97 #define XMC_USIC_H
98 /*******************************************************************************
99 * HEADER FILES
100 *******************************************************************************/
101
102 #include "xmc_common.h"
103
104 /**
105 * @addtogroup XMClib XMC Peripheral Library
106 * @{
107 */
108
109 /**
110 * @addtogroup USIC
111 * @brief Universal Serial Interface Channel(USIC) driver for serial communication.
112 *
113 * The Universal Serial Interface Channel(USIC) module is a flexible interface module
114 * covering several serial communication protocols. A USIC module contains two
115 * independent communication channels named USICx_CH0 and USICx_CH1, with x
116 * being the number of the USIC module. The user can program, during run-time, which protocol will be handled
117 * by each communication channel and which pins are used.
118 * The driver provides APIs, configuration structures and enumerations to configure common features of multiple serial
119 * communication protocols.
120 *
121 * USIC driver features:
122 * -# Allows configuration of FIFO for transmit and receive functions.
123 * -# Provides a structure type XMC_USIC_CH_t to represent the USIC channel registers in a programmer
124 friendly format.
125 * -# Allows configuration of automatic update for frame length, word length, slave select or slave address.
126 * -# Allows transmission of data to FIFO using XMC_USIC_CH_TXFIFO_PutData() and XMC_USIC_CH_TXFIFO_PutDataFLEMode()
127 * -# Allows reading of received data in FIFO using XMC_USIC_CH_RXFIFO_GetData()
128 * -# Allows configuration of baudrate using XMC_USIC_CH_SetBaudrate()
129 * -# Provides API to trigger interrupts using XMC_USIC_CH_TriggerServiceRequest()
130 * @{
131 */
132
133 /*******************************************************************************
134 * MACROS
135 *******************************************************************************/
136
137 #define XMC_USIC0 ((XMC_USIC_t *)USIC0_BASE) /**< USIC0 module base address */
138 #define XMC_USIC0_CH0 ((XMC_USIC_CH_t *)USIC0_CH0_BASE) /**< USIC0 channel 0 base address */
139 #define XMC_USIC0_CH1 ((XMC_USIC_CH_t *)USIC0_CH1_BASE) /**< USIC0 channel 1 base address */
140
141 #if defined(USIC1)
142 #define XMC_USIC1 ((XMC_USIC_t *)USIC1_BASE) /**< USIC1 module base address */
143 #define XMC_USIC1_CH0 ((XMC_USIC_CH_t *)USIC1_CH0_BASE) /**< USIC1 channel 0 base address */
144 #define XMC_USIC1_CH1 ((XMC_USIC_CH_t *)USIC1_CH1_BASE) /**< USIC1 channel 1 base address */
145 #endif
146
147 #if defined(USIC2)
148 #define XMC_USIC2 ((XMC_USIC_t *)USIC2_BASE) /**< USIC2 module base address */
149 #define XMC_USIC2_CH0 ((XMC_USIC_CH_t *)USIC2_CH0_BASE) /**< USIC2 channel 0 base address */
150 #define XMC_USIC2_CH1 ((XMC_USIC_CH_t *)USIC2_CH1_BASE) /**< USIC2 channel 1 base address */
151 #endif
152
153 #define USIC_CH_DXCR_DSEL_Msk USIC_CH_DX0CR_DSEL_Msk /**< Common mask for DSEL bitfield mask in DXnCR register */
154 #define USIC_CH_DXCR_DSEL_Pos USIC_CH_DX0CR_DSEL_Pos /**< Common mask for DSEL bitfield position in DXnCR register */
155 #define USIC_CH_DXCR_SFSEL_Pos USIC_CH_DX0CR_SFSEL_Pos /**< Common mask for SFSEL bitfield position in DXnCR register */
156 #define USIC_CH_DXCR_SFSEL_Msk USIC_CH_DX0CR_SFSEL_Msk /**< Common mask for SFSEL bitfield mask in DXnCR register */
157 #define USIC_CH_DXCR_DPOL_Msk USIC_CH_DX0CR_DPOL_Msk /**< Common mask for DPOL bitfield mask in DXnCR register */
158 #define USIC_CH_DXCR_DFEN_Msk USIC_CH_DX0CR_DFEN_Msk /**< Common mask for DFEN bitfield mask in DXnCR register */
159 #define USIC_CH_DXCR_DSEN_Msk USIC_CH_DX0CR_DSEN_Msk /**< Common mask for DSEN bitfield mask in DXnCR register */
160 #define USIC_CH_DXCR_CM_Pos USIC_CH_DX0CR_CM_Pos /**< Common mask for CM bitfield position in DXnCR register */
161 #define USIC_CH_DXCR_CM_Msk USIC_CH_DX0CR_CM_Msk /**< Common mask for CM bitfield mask in DXnCR register */
162 #define USIC_CH_DXCR_INSW_Msk USIC_CH_DX0CR_INSW_Msk /**< Common mask for INSW bitfield mask in DXnCR register */
163 #define USIC_CH_DXCR_INSW_pos USIC_CH_DX0CR_INSW_Pos /**< Common mask for INSW bitfield position in DXnCR register */
164
165 #if UC_FAMILY == XMC1
166 #include "xmc1_usic_map.h"
167 #endif
168
169 #if UC_FAMILY == XMC4
170 #include "xmc4_usic_map.h"
171 #endif
172
173 /*******************************************************************************
174 * ENUMS
175 *******************************************************************************/
176
177 /**
178 * USIC channel driver status
179 */
180 typedef enum XMC_USIC_CH_STATUS
181 {
182 XMC_USIC_CH_STATUS_OK, /**< USIC driver status : OK */
183 XMC_USIC_CH_STATUS_ERROR, /**< USIC driver status : ERROR */
184 XMC_USIC_CH_STATUS_BUSY /**< USIC driver status : BUSY */
185 } XMC_USIC_CH_STATUS_t;
186
187 /**
188 * USIC channel kernel mode
189 */
190 typedef enum XMC_USIC_CH_KERNEL_MODE
191 {
192 XMC_USIC_CH_KERNEL_MODE_RUN_0 = 0x0UL, /**< Run mode 0 (transmission and reception possible)*/
193 XMC_USIC_CH_KERNEL_MODE_RUN_1 = 0x1UL << USIC_CH_KSCFG_NOMCFG_Pos, /**< Run mode 1 (transmission and reception possible)*/
194 XMC_USIC_CH_KERNEL_MODE_STOP_0 = 0x2UL << USIC_CH_KSCFG_NOMCFG_Pos, /**< Stop mode 0 (no transmission, but reception possible)*/
195 XMC_USIC_CH_KERNEL_MODE_STOP_1 = 0x3UL << USIC_CH_KSCFG_NOMCFG_Pos /**< Stop mode 1 (both transmission and reception not possible)*/
196 } XMC_USIC_CH_KERNEL_MODE_t;
197
198 /**
199 * USIC channel operating mode
200 */
201 typedef enum XMC_USIC_CH_OPERATING_MODE
202 {
203 XMC_USIC_CH_OPERATING_MODE_IDLE = 0x0UL, /**< USIC channel idle */
204 XMC_USIC_CH_OPERATING_MODE_SPI = 0x1UL << USIC_CH_CCR_MODE_Pos, /**< SPI mode */
205 XMC_USIC_CH_OPERATING_MODE_UART = 0x2UL << USIC_CH_CCR_MODE_Pos, /**< UART mode */
206 XMC_USIC_CH_OPERATING_MODE_I2S = 0x3UL << USIC_CH_CCR_MODE_Pos, /**< I2S mode */
207 XMC_USIC_CH_OPERATING_MODE_I2C = 0x4UL << USIC_CH_CCR_MODE_Pos /**< I2C mode */
208 } XMC_USIC_CH_OPERATING_MODE_t;
209
210 /**
211 * USIC channel inputs
212 */
213 typedef enum XMC_USIC_CH_INPUT
214 {
215 XMC_USIC_CH_INPUT_DX0, /**< DX0 input */
216 XMC_USIC_CH_INPUT_DX1, /**< DX1 input */
217 XMC_USIC_CH_INPUT_DX2, /**< DX2 input */
218 XMC_USIC_CH_INPUT_DX3, /**< DX3 input */
219 XMC_USIC_CH_INPUT_DX4, /**< DX4 input */
220 XMC_USIC_CH_INPUT_DX5 /**< DX5 input */
221 } XMC_USIC_CH_INPUT_t;
222
223 /**
224 * USIC channel input source sampling frequency
225 */
226 typedef enum XMC_USIC_CH_INPUT_SAMPLING_FREQ
227 {
228 XMC_USIC_CH_INPUT_SAMPLING_FREQ_FPERIPH = 0x0UL, /**< Use fperiph frequency for input source sampling*/
229 XMC_USIC_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER = 0x1UL << USIC_CH_DXCR_SFSEL_Pos /**< Use fFD(fractional divider) frequency for input source sampling*/
230 } XMC_USIC_CH_INPUT_SAMPLING_FREQ_t;
231
232 /**
233 * USIC channel input combination mode
234 */
235 typedef enum XMC_USIC_CH_INPUT_COMBINATION_MODE
236 {
237 XMC_USIC_CH_INPUT_COMBINATION_MODE_TRIGGER_DISABLED = 0x0UL, /**< The trigger activation is disabled.*/
238 XMC_USIC_CH_INPUT_COMBINATION_MODE_RISING_EDGE = 0x1UL, /**< A rising edge activates DXnT*/
239 XMC_USIC_CH_INPUT_COMBINATION_MODE_FALLING_EDGE = 0x2UL, /**< A falling edge activates DXnT*/
240 XMC_USIC_CH_INPUT_COMBINATION_MODE_BOTH_EDGES = 0x3UL, /**< Both edges activate DXnT*/
241 } XMC_USIC_CH_INPUT_COMBINATION_MODE_t;
242
243 /**
244 * USIC channel data transmission start modes.
245 * Data shifted out of the transmit pin depends on the value configured for the
246 * TDEN bitfield of the TCSR register. Following enum values are used for configuring
247 * the TCSR->TDEN bitfield.
248 */
249 typedef enum XMC_USIC_CH_START_TRANSMISION_MODE
250 {
251 XMC_USIC_CH_START_TRANSMISION_DISABLED = 0x0U, /**< Passive data level is sent out on transmission. */
252 XMC_USIC_CH_START_TRANSMISION_ON_TDV = 0x1UL << USIC_CH_TCSR_TDEN_Pos, /**< Transmission of the data word in TBUF can be started if TDV = 1 */
253 XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_0 = 0x2UL << USIC_CH_TCSR_TDEN_Pos, /**< Transmission of the data word in TBUF can be started if TDV = 1 while DX2S_0 */
254 XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_1 = 0x3UL << USIC_CH_TCSR_TDEN_Pos /**< Transmission of the data word in TBUF can be started if TDV = 1 while DX2S_1 */
255 } XMC_USIC_CH_START_TRANSMISION_MODE_t;
256
257 /**
258 * USIC channel interrupt node pointers
259 */
260 typedef enum XMC_USIC_CH_INTERRUPT_NODE_POINTER
261 {
262 XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = USIC_CH_INPR_TSINP_Pos, /**< Node pointer for transmit shift interrupt */
263 XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = USIC_CH_INPR_TBINP_Pos, /**< Node pointer for transmit buffer interrupt */
264 XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE = USIC_CH_INPR_RINP_Pos, /**< Node pointer for receive interrupt */
265 XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = USIC_CH_INPR_AINP_Pos, /**< Node pointer for alternate receive interrupt */
266 XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL = USIC_CH_INPR_PINP_Pos /**< Node pointer for protocol related interrupts */
267 } XMC_USIC_CH_INTERRUPT_NODE_POINTER_t;
268
269 /**
270 * USIC channel events
271 */
272 typedef enum XMC_USIC_CH_EVENT
273 {
274 XMC_USIC_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */
275 XMC_USIC_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */
276 XMC_USIC_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */
277 XMC_USIC_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */
278 XMC_USIC_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */
279 XMC_USIC_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */
280 XMC_USIC_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk /**< Baudrate generator event */
281 } XMC_USIC_CH_EVENT_t;
282
283 /**
284 * USIC channel parity mode
285 */
286 typedef enum XMC_USIC_CH_PARITY_MODE
287 {
288 XMC_USIC_CH_PARITY_MODE_NONE = 0x0UL, /**< Disable parity mode */
289 XMC_USIC_CH_PARITY_MODE_EVEN = 0x2UL << USIC_CH_CCR_PM_Pos, /**< Enable even parity mode */
290 XMC_USIC_CH_PARITY_MODE_ODD = 0x3UL << USIC_CH_CCR_PM_Pos /**< Enable odd parity mode */
291 } XMC_USIC_CH_PARITY_MODE_t;
292
293 /**
294 * USIC channel data output mode
295 */
296 typedef enum XMC_USIC_CH_DATA_OUTPUT_MODE
297 {
298 XMC_USIC_CH_DATA_OUTPUT_MODE_NORMAL = 0x0UL, /**< Data output normal mode */
299 XMC_USIC_CH_DATA_OUTPUT_MODE_INVERTED = 0x1UL << USIC_CH_SCTR_DOCFG_Pos /**< Data output inverted mode */
300 } XMC_USIC_CH_DATA_OUTPUT_MODE_t;
301
302 /**
303 * USIC channel data transmit buffer status
304 */
305 typedef enum XMC_USIC_CH_TBUF_STATUS
306 {
307 XMC_USIC_CH_TBUF_STATUS_IDLE = 0x0UL, /**< Transfer buffer is currently idle*/
308 XMC_USIC_CH_TBUF_STATUS_BUSY = USIC_CH_TCSR_TDV_Msk /**< Transfer buffer is currently busy*/
309 } XMC_USIC_CH_TBUF_STATUS_t;
310
311
312
313 /**
314 * USIC channel data transmit buffer status modification
315 */
316 typedef enum XMC_USIC_CH_TBUF_STATUS_SET
317 {
318 XMC_USIC_CH_TBUF_STATUS_SET_BUSY = 0x1UL, /**< Set Transfer buffer status to busy*/
319 XMC_USIC_CH_TBUF_STATUS_SET_IDLE = 0x2UL /**< Set Transfer buffer status to idle*/
320 } XMC_USIC_CH_TBUF_STATUS_SET_t;
321
322 /**
323 * USIC channel receive buffer status
324 */
325 typedef enum XMC_USIC_CH_RBUF_STATUS
326 {
327 XMC_USIC_CH_RBUF_STATUS_DATA_VALID0 = USIC_CH_RBUFSR_RDV0_Msk, /**< RBUF0 data has not yet been read out*/
328 XMC_USIC_CH_RBUF_STATUS_DATA_VALID1 = USIC_CH_RBUFSR_RDV1_Msk /**< RBUF1 data has not yet been read out*/
329 } XMC_USIC_CH_RBUF_STATUS_t;
330
331 /**
332 * USIC channel output signal passive data level
333 */
334 typedef enum XMC_USCI_CH_PASSIVE_DATA_LEVEL
335 {
336 XMC_USIC_CH_PASSIVE_DATA_LEVEL0 = 0x0UL, /**< Passive level(idle mode signal level) 0 */
337 XMC_USIC_CH_PASSIVE_DATA_LEVEL1 = 0x1UL << USIC_CH_SCTR_PDL_Pos /**< Passive level(idle mode signal level) 1 */
338 } XMC_USIC_CH_PASSIVE_DATA_LEVEL_t;
339
340 /**
341 * USIC channel receive FIFO size
342 */
343 typedef enum XMC_USIC_CH_FIFO_SIZE
344 {
345 XMC_USIC_CH_FIFO_DISABLED = 0x0U, /**< FIFO Disabled */
346 XMC_USIC_CH_FIFO_SIZE_2WORDS = 0x1U, /**< FIFO size: 2 words */
347 XMC_USIC_CH_FIFO_SIZE_4WORDS = 0x2U, /**< FIFO size: 4 words */
348 XMC_USIC_CH_FIFO_SIZE_8WORDS = 0x3U, /**< FIFO size: 8 words */
349 XMC_USIC_CH_FIFO_SIZE_16WORDS = 0x4U, /**< FIFO size: 16 words */
350 XMC_USIC_CH_FIFO_SIZE_32WORDS = 0x5U, /**< FIFO size: 32 words */
351 XMC_USIC_CH_FIFO_SIZE_64WORDS = 0x6U /**< FIFO size: 64 words */
352 } XMC_USIC_CH_FIFO_SIZE_t;
353
354 /**
355 * USIC channel transmit FIFO interrupt node pointers
356 */
357 typedef enum XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER
358 {
359 XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD = USIC_CH_TBCTR_STBINP_Pos, /**< Node pointer for FIFO standard transmit interrupt */
360 XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE = USIC_CH_TBCTR_ATBINP_Pos /**< Node pointer for transmit FIFO error interrupt */
361 } XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t;
362
363 /**
364 * USIC channel transmit FIFO event configuration
365 */
366 typedef enum XMC_USIC_CH_TXFIFO_EVENT_CONF
367 {
368 XMC_USIC_CH_TXFIFO_EVENT_CONF_STANDARD = USIC_CH_TBCTR_STBIEN_Msk, /**< Enable FIFO standard transmit interrupt */
369 XMC_USIC_CH_TXFIFO_EVENT_CONF_ERROR = (int32_t)USIC_CH_TBCTR_TBERIEN_Msk /**< Enable transmit FIFO error interrupt */
370 } XMC_USIC_CH_TXFIFO_EVENT_CONF_t;
371
372 /**
373 * USIC channel transmit FIFO status
374 */
375 typedef enum XMC_USIC_CH_TXFIFO_EVENT
376 {
377 XMC_USIC_CH_TXFIFO_EVENT_STANDARD = USIC_CH_TRBSR_STBI_Msk, /**< Transmit FIFO status: Standard event */
378 XMC_USIC_CH_TXFIFO_EVENT_ERROR = USIC_CH_TRBSR_TBERI_Msk /**< Transmit FIFO status: Error event */
379 } XMC_USIC_CH_TXFIFO_EVENT_t;
380
381 /**
382 * USIC channel receive FIFO interrupt node pointers
383 */
384 typedef enum XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER
385 {
386 XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD = USIC_CH_RBCTR_SRBINP_Pos, /**< Node pointer for FIFO standard receive interrupt */
387 XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE = USIC_CH_RBCTR_ARBINP_Pos /**< Node pointer for FIFO alternative receive interrupt */
388 } XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t;
389
390 /**
391 * USIC channel receive FIFO event configuration
392 */
393 typedef enum XMC_USIC_CH_RXFIFO_EVENT_CONF
394 {
395 XMC_USIC_CH_RXFIFO_EVENT_CONF_STANDARD = USIC_CH_RBCTR_SRBIEN_Msk, /**< Enable FIFO standard receive interrupt */
396 XMC_USIC_CH_RXFIFO_EVENT_CONF_ERROR = (int32_t)USIC_CH_RBCTR_RBERIEN_Msk, /**< Enable receive FIFO error interrupt */
397 XMC_USIC_CH_RXFIFO_EVENT_CONF_ALTERNATE = USIC_CH_RBCTR_ARBIEN_Msk /**< Enable FIFO alternative receive interrupt */
398 } XMC_USIC_CH_RXFIFO_EVENT_CONF_t;
399
400 /**
401 * USIC channel receive FIFO status
402 */
403 typedef enum XMC_USIC_CH_RXFIFO_EVENT
404 {
405 XMC_USIC_CH_RXFIFO_EVENT_STANDARD = USIC_CH_TRBSR_SRBI_Msk, /**< Receive FIFO status: Standard event */
406 XMC_USIC_CH_RXFIFO_EVENT_ERROR = USIC_CH_TRBSR_RBERI_Msk, /**< Receive FIFO status: Error event */
407 XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE = USIC_CH_TRBSR_ARBI_Msk /**< Receive FIFO status: Alternative event */
408 } XMC_USIC_CH_RXFIFO_EVENT_t;
409
410 /**
411 * USIC channel baudrate generator clock source
412 */
413 typedef enum XMC_USIC_CH_BRG_CLOCK_SOURCE
414 {
415 XMC_USIC_CH_BRG_CLOCK_SOURCE_DIVIDER = 0x0UL, /**< Baudrate generator clock source : Source divider. (Internal clock source)*/
416 XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T = 0x2UL << USIC_CH_BRG_CLKSEL_Pos /**< Baudrate generator clock source : DX1T. (External clock source) */
417 } XMC_USIC_CH_BRG_CLOCK_SOURCE_t;
418
419 /**
420 * USIC channel baudrate generator divider mode
421 */
422 typedef enum XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE
423 {
424 XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_DISABLED = 0x0UL, /**< Baudrate generator clock divider: Disabled */
425 XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_NORMAL = 0x1UL << USIC_CH_FDR_DM_Pos, /**< Baudrate generator clock divider: Normal mode */
426 XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL = 0x2UL << USIC_CH_FDR_DM_Pos /**< Baudrate generator clock divider: Fractional mode */
427 } XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t;
428
429 /**
430 * USIC channel baudrate generator master clock passive level
431 */
432 typedef enum XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL
433 {
434 XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_0 = 0x0UL, /**< Baudrate generator master clock passive level(idle mode signal level) 0*/
435 XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_1 = 0x1UL << USIC_CH_BRG_MCLKCFG_Pos /**< Baudrate generator master clock passive level((idle mode signal level)) 1*/
436 } XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t;
437
438 /**
439 * USIC channel baudrate generator shift clock passive level
440 */
441 typedef enum XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL
442 {
443 XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED = 0x0UL, /**< Shift clock passive level 0, delay disabled */
444 XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED = 0x1UL << USIC_CH_BRG_SCLKCFG_Pos, /**< Shift clock passive level 1, delay disabled */
445 XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED = (int32_t)(0x2UL << USIC_CH_BRG_SCLKCFG_Pos), /**< Shift clock passive level 0, delay enabled */
446 XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED = (int32_t)(0x3UL << USIC_CH_BRG_SCLKCFG_Pos) /**< Shift clock passive level 1, delay enabled */
447 } XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t;
448
449 /**
450 * USIC channel baudrate generator shift clock output
451 */
452 typedef enum XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT
453 {
454 XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK = 0x0UL, /**< Baudrate generator shift clock output: SCL.(Internally generated shift clock)*/
455 XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 = 0x1UL << USIC_CH_BRG_SCLKOSEL_Pos /**< Baudrate generator shift clock output: DX1. (External input shift clock)*/
456 } XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t;
457
458 /**
459 * USIC channel shift direction.
460 * Defines the shift direction of the data words for transmission and reception
461 */
462 typedef enum XMC_USIC_CH_SHIFT_DIRECTION
463 {
464 XMC_USIC_CH_SHIFT_DIRECTION_LSB_FIRST = 0x0UL, /**< Shift LSB first. The first data bit of a data word is located at bit position 0. */
465 XMC_USIC_CH_SHIFT_DIRECTION_MSB_FIRST = 0x1UL << USIC_CH_SCTR_SDIR_Pos /**< Shift MSB first. The first data bit of a data word is located at the bit position given by the configured word length. */
466 } XMC_USIC_CH_SHIFT_DIRECTION_t;
467
468
469 /*******************************************************************************
470 * DATA STRUCTURES
471 *******************************************************************************/
472
473 /*Anonymous structure/union guard start*/
474 #if defined(__CC_ARM)
475 #pragma push
476 #pragma anon_unions
477 #elif defined(__TASKING__)
478 #pragma warning 586
479 #endif
480
481 /**
482 * USIC module structure
483 */
484 typedef USIC_GLOBAL_TypeDef XMC_USIC_t;
485
486 /**
487 * USIC channel structure.<br> The members of the structure are same as in the device header file,
488 * except for some registers.
489 * DX0CR, DX1CR, DX2CR, DX3CR, DX4CR and DX5CR are replaced with the array DXCR[6].
490 * TBUF0 to TBUF31 are replaced with TBUF[32].
491 * IN0 to IN31 are replaced with IN[32].
492 */
493 typedef struct XMC_USIC_CH
494 {
495 __I uint32_t RESERVED0;
496 __I uint32_t CCFG; /**< Channel configuration register*/
497 __I uint32_t RESERVED1;
498 __IO uint32_t KSCFG; /**< Kernel state configuration register*/
499 __IO uint32_t FDR; /**< Fractional divider configuration register*/
500 __IO uint32_t BRG; /**< Baud rate generator register*/
501 __IO uint32_t INPR; /**< Interrupt node pointer register*/
502 __IO uint32_t DXCR[6]; /**< Input control registers DX0 to DX5.*/
503 __IO uint32_t SCTR; /**< Shift control register*/
504 __IO uint32_t TCSR;
505
506 union {
507 __IO uint32_t PCR_IICMode; /**< I2C protocol configuration register*/
508 __IO uint32_t PCR_IISMode; /**< I2S protocol configuration register*/
509 __IO uint32_t PCR_SSCMode; /**< SPI protocol configuration register*/
510 __IO uint32_t PCR; /**< Protocol configuration register*/
511 __IO uint32_t PCR_ASCMode; /**< UART protocol configuration register*/
512 };
513 __IO uint32_t CCR; /**< Channel control register*/
514 __IO uint32_t CMTR; /**< Capture mode timer register*/
515
516 union {
517 __IO uint32_t PSR_IICMode; /**< I2C protocol status register*/
518 __IO uint32_t PSR_IISMode; /**< I2S protocol status register*/
519 __IO uint32_t PSR_SSCMode; /**< SPI protocol status register*/
520 __IO uint32_t PSR; /**< Protocol status register*/
521 __IO uint32_t PSR_ASCMode; /**< UART protocol status register*/
522 };
523 __O uint32_t PSCR; /**< Protocol status clear register*/
524 __I uint32_t RBUFSR; /**< Receive buffer status register*/
525 __I uint32_t RBUF; /**< Receive buffer register*/
526 __I uint32_t RBUFD; /**< Debug mode receive buffer register*/
527 __I uint32_t RBUF0; /**< Receive buffer 0*/
528 __I uint32_t RBUF1; /**< Receive buffer 1*/
529 __I uint32_t RBUF01SR; /**< Receive buffer status register*/
530 __O uint32_t FMR; /**< Flag modification register*/
531 __I uint32_t RESERVED2[5];
532 __IO uint32_t TBUF[32]; /**< Tranmsit buffer registers*/
533 __IO uint32_t BYP; /**< FIFO bypass register*/
534 __IO uint32_t BYPCR; /**< FIFO bypass control register*/
535 __IO uint32_t TBCTR; /**< Transmit FIFO control register*/
536 __IO uint32_t RBCTR; /**< Receive FIFO control register*/
537 __I uint32_t TRBPTR; /**< Transmit/recive buffer pointer register*/
538 __IO uint32_t TRBSR; /**< Transmit/receive buffer status register*/
539 __O uint32_t TRBSCR; /**< Transmit/receive buffer status clear register*/
540 __I uint32_t OUTR; /**< Receive FIFO output register*/
541 __I uint32_t OUTDR; /**< Receive FIFO debug output register*/
542 __I uint32_t RESERVED3[23];
543 __O uint32_t IN[32]; /**< Transmit FIFO input register*/
544 } XMC_USIC_CH_t;
545
546
547 /*Anonymous structure/union guard end*/
548 #if defined(__CC_ARM)
549 #pragma pop
550 #elif defined(__TASKING__)
551 #pragma warning restore
552 #endif
553
554 /*******************************************************************************
555 * API PROTOTYPES
556 ******************************************************************************/
557
558 #ifdef __cplusplus
559 extern "C" {
560 #endif
561
XMC_USIC_IsModuleValid(const XMC_USIC_t * const module)562 __STATIC_INLINE bool XMC_USIC_IsModuleValid(const XMC_USIC_t *const module)
563 {
564 bool tmp;
565
566 tmp = (module == XMC_USIC0);
567 #if defined(XMC_USIC1)
568 tmp = tmp || (module == XMC_USIC1);
569 #endif
570 #if defined(XMC_USIC2)
571 tmp = tmp || (module == XMC_USIC2);
572 #endif
573
574 return tmp;
575 }
576
XMC_USIC_IsChannelValid(const XMC_USIC_CH_t * const channel)577 __STATIC_INLINE bool XMC_USIC_IsChannelValid(const XMC_USIC_CH_t *const channel)
578 {
579 bool tmp;
580
581 tmp = ((channel == XMC_USIC0_CH0) || (channel == XMC_USIC0_CH1));
582 #if defined(XMC_USIC1)
583 tmp = tmp || ((channel == XMC_USIC1_CH0) || (channel == XMC_USIC1_CH1));
584 #endif
585 #if defined(XMC_USIC2)
586 tmp = tmp || ((channel == XMC_USIC2_CH0) || (channel == XMC_USIC2_CH1));
587 #endif
588
589 return tmp;
590 }
591
592 /* Common APIs */
593
594 /**
595 * @param usic Pointer to USIC module handler of type @ref XMC_USIC_t.\n
596 * \b Range: @ref XMC_USIC0 to @ref XMC_USIC2 based on device support.
597 * @return None
598 *
599 * \par<b>Description</b><br>
600 * Enables the USIC module.\n\n
601 * Enables the clock for the USIC module by following the
602 * clock enabling sequence for the selected device.
603 *
604 * \par<b>Related APIs:</b><BR>
605 * XMC_USIC_CH_Enable(), XMC_USIC_Disable() \n\n\n
606 */
607 void XMC_USIC_Enable(XMC_USIC_t *const usic);
608 /**
609 * @param usic Pointer to USIC module handler of type @ref XMC_USIC_t.\n
610 * \b Range: @ref XMC_USIC0 to @ref XMC_USIC2 based on device support.
611 * @return None
612 *
613 * \par<b>Description</b><br>
614 * Disables the USIC module.\n\n
615 * Disables the clock for the USIC module by following the clock
616 * disabling sequence for the selected device.
617 *
618 * \par<b>Related APIs:</b><BR>
619 * XMC_USIC_CH_Disable(), XMC_USIC_Enable() \n\n\n
620 */
621 void XMC_USIC_Disable(XMC_USIC_t *const usic);
622 /**
623 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
624 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
625 * @return None
626 *
627 * \par<b>Description</b><br>
628 * Enables the USIC channel. \n\n
629 * USIC channel is enabled by setting the module enable bit in KSCFG register bitfield MODEN.
630 * On enabling, the channel is set to idle mode.
631 *
632 * \par<b>Related APIs:</b><BR>
633 * XMC_USIC_CH_Disable(), XMC_USIC_Enable() \n\n\n
634 */
635 void XMC_USIC_CH_Enable(XMC_USIC_CH_t *const channel);
636 /**
637 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
638 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
639 * @return None
640 *
641 * \par<b>Description</b><br>
642 * Disables the USIC channel.\n\n
643 * USIC channel is disabled by setting the module enable bit(MDEN) to 0 in the register KSCFG.
644 *
645 * \par<b>Related APIs:</b><BR>
646 * XMC_USIC_CH_Enable(), XMC_USIC_Disable() \n\n\n
647 */
648 void XMC_USIC_CH_Disable(XMC_USIC_CH_t *const channel);
649
650 /**
651 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
652 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
653 * @param rate Desired baudrate. \b Range: minimum value = 100, maximum value depends on the peripheral clock frequency \n
654 * and \a oversampling. Maximum baudrate can be derived using the formula: (fperiph * 1023)/(1024 * oversampling)
655 * @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data. \n
656 * This can be related to the number of samples for each logic state of the data signal. \n
657 * \b Range: 1 to 32. Value should be chosen based on the protocol used.
658 * @return Status indicating the baudrate configuration.\n
659 * \b Range: @ref XMC_USIC_CH_STATUS_OK if baudrate is successfully configured,
660 * @ref XMC_USIC_CH_STATUS_ERROR if desired baudrate or oversampling is invalid.
661 *
662 * \par<b>Description</b><br>
663 * Configures the baudrate of the USIC channel. \n\n
664 * Baudrate is configured by considering the peripheral frequency and the desired baudrate.
665 * Optimum values of FDR->STEP and BRG->PDIV are calulated and used for generating the desired
666 * baudrate.
667 *
668 * \par<b>Related APIs:</b><BR>
669 * XMC_USIC_CH_SetStartTransmisionMode(), XMC_USIC_CH_SetInputSource() \n\n\n
670 */
671 XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling);
672
673 /**
674 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
675 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
676 * @param rate Desired baudrate. Only integer dividers of peripheral clock are achievable
677 * @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data. \n
678 * This can be related to the number of samples for each logic state of the data signal. \n
679 * \b Range: 1 to 32. Value should be chosen based on the protocol used.
680 * @return Status indicating the baudrate configuration.\n
681 * \b Range: @ref XMC_USIC_CH_STATUS_OK if baudrate is successfully configured,
682 * @ref XMC_USIC_CH_STATUS_ERROR if desired baudrate or oversampling is invalid.
683 *
684 * \par<b>Description</b><br>
685 * Configures the baudrate of the USIC channel using the integer divider which restrics the achievable baudrate but decreses jitter. \n\n
686 * Baudrate is configured by considering the peripheral frequency and the desired baudrate.
687 * Optimum values of FDR->STEP and BRG->PDIV are calulated and used for generating the desired
688 * baudrate.
689 *
690 * \par<b>Related APIs:</b><BR>
691 * XMC_USIC_CH_SetStartTransmisionMode(), XMC_USIC_CH_SetInputSource() \n\n\n
692 */
693 XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, int32_t rate, int32_t oversampling);
694
695
696 /**
697 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
698 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
699 * @return baudrate currently used by USIC channel for .\n
700 *
701 * \par<b>Description</b><br>
702 * Calculates the current used baudrate (fCTQIN) of a USIC channel. \n\n
703 * @image html ../images/usic_brg.png
704 * @image latex ../images/usic_brg.png
705 *
706 * \par<b>Related APIs:</b><BR>
707 * XMC_USIC_CH_SetBaudrateMode(), XMC_USIC_CH_SetBaudrate(), XMC_USIC_CH_SetBaudrateEx() \n\n\n
708 */
709 uint32_t XMC_USIC_CH_GetBaudrate(XMC_USIC_CH_t *const channel);
710
711 /**
712 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
713 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
714 * @return baudrate currently used by USIC channel.\n
715 *
716 * \par<b>Description</b><br>
717 * Calculates the current used SCLK frequency of a USIC channel. \n\n
718 * @image html ../images/usic_brg.png
719 * @image latex ../images/usic_brg.png
720 *
721 * \par<b>Related APIs:</b><BR>
722 * XMC_USIC_CH_SetBaudrateMode(), XMC_USIC_CH_SetBaudrate(), XMC_USIC_CH_SetBaudrateEx() \n\n\n
723 */
724 uint32_t XMC_USIC_CH_GetSCLKFrequency(XMC_USIC_CH_t *const channel);
725
726 /**
727 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
728 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
729 * @return baudrate currently used by USIC channel.\n
730 *
731 * \par<b>Description</b><br>
732 * Calculates the current used MCLK frequency of a USIC channel. \n\n
733 * @image html ../images/usic_brg.png
734 * @image latex ../images/usic_brg.png
735 *
736 * \par<b>Related APIs:</b><BR>
737 * XMC_USIC_CH_SetBaudrateMode(), XMC_USIC_CH_SetBaudrate(), XMC_USIC_CH_SetBaudrateEx() \n\n\n
738 */
739 uint32_t XMC_USIC_CH_GetMCLKFrequency(XMC_USIC_CH_t *const channel);
740
741 /**
742 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
743 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
744 * @param pdiv Desired divider for the external frequency input. \b Range: minimum value = 1, maximum value = 1024 \n
745 * @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data. \n
746 * This can be related to the number of samples for each logic state of the data signal. \n
747 * \b Range: 1 to 32. Value should be chosen based on the protocol used.
748 * @param combination_mode Selects which edge of the synchronized(and optionally filtered) signal DXnS actives the trigger
749 * output DXnT of the input stage.
750 *
751 * @return None
752 *
753 * \par<b>Description</b><br>
754 * Enables the external frequency input for the Baudrate Generator and configures the divider, oversampling and
755 * the combination mode of the USIC channel. \n\n
756 *
757 * \par<b>Related APIs:</b><BR>
758 * XMC_USIC_CH_SetBRGInputClockSource(), XMC_USIC_CH_SetInputTriggerCombinationMode() \n\n\n
759 */
760 void XMC_USIC_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel,
761 const uint16_t pdiv,
762 const uint32_t oversampling,
763 const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode);
764
765 /**
766 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
767 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
768 * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n
769 * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5
770 * @param source Input source select for the input stage. The table below maps the enum value with the input channel.
771 * <table><tr><td>0</td><td>DXnA</td></tr><tr><td>1</td><td>DXnB</td></tr><tr><td>2</td><td>DXnC</td></tr><tr><td>3</td><td>DXnD</td></tr>
772 * <tr><td>4</td><td>DXnE</td></tr><tr><td>5</td><td>DXnF</td></tr><tr><td>6</td><td>DXnG</td></tr><tr><td>7</td><td>Always 1</td>
773 * </tr></table>
774 * @return None
775 *
776 * \par<b>Description</b><br>
777 * Selects the data source for USIC input stage.\n\n
778 * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the input stages
779 * like DX0CR, DX1CR etc.
780 *
781 * \par<b>Related APIs:</b><BR>
782 * XMC_USIC_CH_EnableInputInversion(), XMC_USIC_CH_EnableInputDigitalFilter(), XMC_USIC_CH_EnableInputSync(),
783 * XMC_USIC_CH_SetInputSamplingFreq()\n\n\n
784 */
XMC_USIC_CH_SetInputSource(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_INPUT_t input,const uint8_t source)785 __STATIC_INLINE void XMC_USIC_CH_SetInputSource(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input, const uint8_t source)
786 {
787 channel->DXCR[input] = (uint32_t)((channel->DXCR[input] & (uint32_t)(~USIC_CH_DXCR_DSEL_Msk)) |
788 ((uint32_t)source << USIC_CH_DXCR_DSEL_Pos));
789 }
790 /**
791 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
792 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
793 * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n
794 * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5
795 * @return None
796 *
797 * \par<b>Description</b><br>
798 * The input of the data shift unit is controlled by the
799 * protocol pre-processor. \n\n
800 *
801 * \par<b>Related APIs:</b><BR>
802 * XMC_USIC_CH_ConnectInputDataShiftToDataInput()\n\n\n
803 */
XMC_USIC_CH_ConnectInputDataShiftToPPP(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_INPUT_t input)804 __STATIC_INLINE void XMC_USIC_CH_ConnectInputDataShiftToPPP(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input)
805 {
806 channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_INSW_Msk;
807 }
808
809 /**
810 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
811 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
812 * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n
813 * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5
814 * @return None
815 *
816 * \par<b>Description</b><br>
817 * The input of the data shift unit is connected to
818 * the selected data input line. \n\n
819 *
820 * This setting is used
821 * if the signals are directly derived from an input
822 * pin without treatment by the protocol preprocessor.
823 * \par<b>Related APIs:</b><BR>
824 * XMC_USIC_CH_ConnectInputDataShiftToPPP()\n\n\n
825 */
XMC_USIC_CH_ConnectInputDataShiftToDataInput(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_INPUT_t input)826 __STATIC_INLINE void XMC_USIC_CH_ConnectInputDataShiftToDataInput(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input)
827 {
828 channel->DXCR[input] |= USIC_CH_DXCR_INSW_Msk;
829 }
830
831 /**
832 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
833 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
834 * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n
835 * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5
836 * @return None
837 *
838 * \par<b>Description</b><br>
839 * Enables input inversion for USIC channel input data signal. \n\n
840 *
841 * Polarity of the input source can be changed to provide inverted data input.
842 * \par<b>Related APIs:</b><BR>
843 * XMC_USIC_CH_DisableInputInversion()\n\n\n
844 */
XMC_USIC_CH_EnableInputInversion(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_INPUT_t input)845 __STATIC_INLINE void XMC_USIC_CH_EnableInputInversion(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input)
846 {
847 channel->DXCR[input] |= USIC_CH_DXCR_DPOL_Msk;
848 }
849
850 /**
851 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
852 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
853 * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n
854 * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5
855 * @return None
856 *
857 * \par<b>Description</b><br>
858 * Disables input inversion for USIC channel. \n\n
859 *
860 * Resets the input data polarity for the USIC channel input data signal.
861 * \par<b>Related APIs:</b><BR>
862 * XMC_USIC_CH_EnableInputInversion()\n\n\n
863 */
XMC_USIC_CH_DisableInputInversion(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_INPUT_t input)864 __STATIC_INLINE void XMC_USIC_CH_DisableInputInversion(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input)
865 {
866 channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_DPOL_Msk;
867 }
868
869 /**
870 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
871 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
872 * @return None
873 *
874 * \par<b>Description</b><br>
875 * Enables delay compensation. \n\n
876 *
877 * Delay compensation can be applied to the receive path.
878 * \par<b>Related APIs:</b><BR>
879 * XMC_USIC_CH_DisableDelayCompensation()\n\n\n
880 */
XMC_USIC_CH_EnableDelayCompensation(XMC_USIC_CH_t * const channel)881 __STATIC_INLINE void XMC_USIC_CH_EnableDelayCompensation(XMC_USIC_CH_t *const channel)
882 {
883 channel->DXCR[1U] |= USIC_CH_DX1CR_DCEN_Msk;
884 }
885
886 /**
887 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
888 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
889 * @return None
890 *
891 * \par<b>Description</b><br>
892 * Disables delay compensation.. \n\n
893 *
894 * \par<b>Related APIs:</b><BR>
895 * XMC_USIC_CH_EnableDelayCompensation()\n\n\n
896 */
XMC_USIC_CH_DisableDelayCompensation(XMC_USIC_CH_t * const channel)897 __STATIC_INLINE void XMC_USIC_CH_DisableDelayCompensation(XMC_USIC_CH_t *const channel)
898 {
899 channel->DXCR[1U] &=(uint32_t)~USIC_CH_DX1CR_DCEN_Msk;
900 }
901
902 /**
903 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
904 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
905 * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n
906 * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5
907 * @return None
908 *
909 * \par<b>Description</b><br>
910 * Enables the input digital filter for USIC channel input data signal. \n\n
911 * Input data signal from the selected multiplexer will be digitally filtered.
912 *
913 * \par<b>Related APIs:</b><BR>
914 * XMC_USIC_CH_DisableInputDigitalFilter()\n\n\n
915 */
XMC_USIC_CH_EnableInputDigitalFilter(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_INPUT_t input)916 __STATIC_INLINE void XMC_USIC_CH_EnableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input)
917 {
918 channel->DXCR[input] |= (uint32_t)USIC_CH_DXCR_DFEN_Msk;
919 }
920 /**
921 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
922 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
923 * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n
924 * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5
925 * @return None
926 *
927 * \par<b>Description</b><br>
928 * Disables the input digital filter for USIC channel input data signal. \n\n
929 * Input data signal from the selected multiplexer will not be digitally filtered.
930 *
931 * \par<b>Related APIs:</b><BR>
932 * XMC_USIC_CH_EnableInputDigitalFilter()\n\n\n
933 */
XMC_USIC_CH_DisableInputDigitalFilter(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_INPUT_t input)934 __STATIC_INLINE void XMC_USIC_CH_DisableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input)
935 {
936 channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_DFEN_Msk;
937 }
938 /**
939 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
940 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
941 * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n
942 * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5
943 * @return None
944 *
945 * \par<b>Description</b><br>
946 * Enables input synchronization for the USIC channel input data signal. \n\n
947 * Input data signal from the selected multiplexer will be synchronized with fPERIPH.
948 * A noisy signal can be synchronized and filtered by enabling the digital filter.
949 *
950 * \par<b>Related APIs:</b><BR>
951 * XMC_USIC_CH_DisableInputSync(), XMC_USIC_CH_EnableInputDigitalFilter()\n\n\n
952 */
XMC_USIC_CH_EnableInputSync(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_INPUT_t input)953 __STATIC_INLINE void XMC_USIC_CH_EnableInputSync(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input)
954 {
955 channel->DXCR[input] |=(uint32_t)USIC_CH_DXCR_DSEN_Msk;
956 }
957 /**
958 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
959 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
960 * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n
961 * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5
962 * @return None
963 *
964 * \par<b>Description</b><br>
965 * Disables input synchronization for the USIC channel input data signal. \n\n
966 * Input data signal from the selected multiplexer will not be synchronized.
967 *
968 * \par<b>Related APIs:</b><BR>
969 * XMC_USIC_CH_EnableInputSync(), XMC_USIC_CH_DisableInputDigitalFilter() \n\n\n
970 */
XMC_USIC_CH_DisableInputSync(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_INPUT_t input)971 __STATIC_INLINE void XMC_USIC_CH_DisableInputSync(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_INPUT_t input)
972 {
973 channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_DSEN_Msk;
974 }
975 /**
976 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
977 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support..
978 * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n
979 * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5
980 * @param sampling_freq Sampling frequency value of type \a XMC_USIC_CH_INPUT_SAMPLING_FREQ_t.
981 * @return None
982 *
983 * \par<b>Description</b><br>
984 * Sets sampling frequency for USIC channel input data signal. \n\n
985 *
986 * \par<b>Related APIs:</b><BR>
987 * XMC_USIC_CH_SetInputSource(), XMC_USIC_CH_EnableInputSync(), XMC_USIC_CH_EnableInputDigitalFilter() \n\n\n
988 */
XMC_USIC_CH_SetInputSamplingFreq(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_INPUT_t input,const XMC_USIC_CH_INPUT_SAMPLING_FREQ_t sampling_freq)989 __STATIC_INLINE void XMC_USIC_CH_SetInputSamplingFreq(XMC_USIC_CH_t *const channel,
990 const XMC_USIC_CH_INPUT_t input,
991 const XMC_USIC_CH_INPUT_SAMPLING_FREQ_t sampling_freq)
992 {
993 channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DXCR_SFSEL_Msk)) |
994 ((uint32_t)sampling_freq);
995 }
996
997 /**
998 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
999 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support..
1000 * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n
1001 * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5
1002 * @param combination_mode Combination mode value of type \a XMC_USIC_CH_INPUT_COMBINATION_MODE_t.
1003 * @return None
1004 *
1005 * \par<b>Description</b><br>
1006 * Selects which edge of the synchronized signal DXnS activates the trigger output DXnT of the input stage. \n\n
1007 *
1008 * \par<b>Related APIs:</b><BR>
1009 * XMC_USIC_CH_SetInputSource(), XMC_USIC_CH_EnableInputSync(), XMC_USIC_CH_EnableInputDigitalFilter() \n\n\n
1010 */
XMC_USIC_CH_SetInputTriggerCombinationMode(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_INPUT_t input,const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode)1011 __STATIC_INLINE void XMC_USIC_CH_SetInputTriggerCombinationMode(XMC_USIC_CH_t *const channel,
1012 const XMC_USIC_CH_INPUT_t input,
1013 const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode)
1014 {
1015 channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DXCR_CM_Msk)) |
1016 ((uint32_t)combination_mode << USIC_CH_DXCR_CM_Pos);
1017 }
1018
1019 /**
1020 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1021 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1022 * @param clock_source clock source for the BRG.
1023 * @return None
1024 *
1025 * \par<b>Description</b><br>
1026 * Sets the clock source for the BRG. \n\n
1027 *
1028 * \par<b>Related APIs:</b><BR>
1029 * XMC_USIC_CH_SetInputTriggerCombinationMode(), XMC_USIC_CH_SetExternalClockBRGDivider()\n\n\n
1030 */
XMC_USIC_CH_SetBRGInputClockSource(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_BRG_CLOCK_SOURCE_t clock_source)1031 __STATIC_INLINE void XMC_USIC_CH_SetBRGInputClockSource(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_BRG_CLOCK_SOURCE_t clock_source)
1032 {
1033 channel->BRG = (uint32_t)(channel->BRG & (~USIC_CH_BRG_CLKSEL_Msk)) | (uint32_t)(clock_source);
1034 }
1035
1036 /**
1037 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1038 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1039 * @param data Data to be transmitted. \n
1040 * \b Range: 16bit unsigned data. minimum= 0, maximum= 65535
1041 * @return None
1042 *
1043 * \par<b>Description</b><br>
1044 * Writes data into the transmit buffer. \n\n
1045 * The data provided is placed in TBUF[0U].
1046 *
1047 *
1048 * \par<b>Related APIs:</b><BR>
1049 * XMC_USIC_CH_WriteToTBUFTCI() \n\n\n
1050 */
XMC_USIC_CH_WriteToTBUF(XMC_USIC_CH_t * const channel,const uint16_t data)1051 __STATIC_INLINE void XMC_USIC_CH_WriteToTBUF(XMC_USIC_CH_t *const channel, const uint16_t data)
1052 {
1053 channel->TBUF[0U] = data;
1054 }
1055
1056 /**
1057 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1058 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1059 * @param data Data to be transmitted.
1060 * @param transmit_control_information transmit control information to be configured while transmitting the data. \n
1061 * \b Range: minimum= 0, maximum= 31.
1062 * @return None
1063 *
1064 * \par<b>Description</b><br>
1065 * Writes data to the transmit buffer in a control mode. \n\n
1066 * When the respective control mode is enabled , this API can be used.
1067 *
1068 *
1069 * \par<b>Related APIs:</b><BR>
1070 * XMC_USIC_CH_WriteToTBUF() \n\n\n
1071 */
XMC_USIC_CH_WriteToTBUFTCI(XMC_USIC_CH_t * const channel,const uint16_t data,const uint32_t transmit_control_information)1072 __STATIC_INLINE void XMC_USIC_CH_WriteToTBUFTCI(XMC_USIC_CH_t *const channel,
1073 const uint16_t data,
1074 const uint32_t transmit_control_information)
1075 {
1076 channel->TBUF[transmit_control_information] = data;
1077 }
1078
1079 /**
1080 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1081 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1082 * @param word_length Number of bits to be configured for a data word. \n
1083 * \b Range: minimum= 1, maximum= 16. \n
1084 * e.g: For word length of 8, \a word_length should be provided as 8.
1085 * @return None
1086 *
1087 * \par<b>Description</b><br>
1088 * Sets the data word length in number of bits. \n\n
1089 * Sets the number of bits to represent a data word. Frame length should be a multiple of word length.
1090 *
1091 * \par<b>Related APIs:</b><BR>
1092 * XMC_USIC_CH_SetFrameLength()\n\n\n
1093 */
XMC_USIC_CH_SetWordLength(XMC_USIC_CH_t * const channel,const uint8_t word_length)1094 __STATIC_INLINE void XMC_USIC_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_length)
1095 {
1096 channel->SCTR = (uint32_t)(channel->SCTR & (~USIC_CH_SCTR_WLE_Msk)) |
1097 (uint32_t)(((uint32_t)word_length - 1UL) << USIC_CH_SCTR_WLE_Pos);
1098 }
1099
1100 /**
1101 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1102 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1103 * @param word_length Number of bits to be configured for a data word. \n
1104 * \b Range: minimum= 1, maximum= 16. \n
1105 * e.g: For word length of 8, \a word_length should be provided as 8.
1106 * @return None
1107 *
1108 * \par<b>Description</b><br>
1109 * Sets the data word length in number of bits. \n\n
1110 * Sets the number of bits to represent a data word. Frame length should be a multiple of word length.
1111 *
1112 * \par<b>Related APIs:</b><BR>
1113 * XMC_USIC_CH_SetFrameLength()\n\n\n
1114 */
XMC_USIC_CH_SetShiftDirection(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_SHIFT_DIRECTION_t shift_direction)1115 __STATIC_INLINE void XMC_USIC_CH_SetShiftDirection(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_SHIFT_DIRECTION_t shift_direction)
1116 {
1117 channel->SCTR = (uint32_t)(channel->SCTR & (~USIC_CH_SCTR_SDIR_Msk)) | (uint32_t)shift_direction;
1118 }
1119
1120
1121 /**
1122 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1123 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1124 * @return Captured counter value
1125 *
1126 *
1127 * \par<b>Description</b><br>
1128 * The value of the counter is captured if one of the trigger signals DX0T or DX1T are activated by the corresponding input stage.
1129 */
XMC_USIC_CH_GetCaptureTimerValue(const XMC_USIC_CH_t * const channel)1130 __STATIC_INLINE uint32_t XMC_USIC_CH_GetCaptureTimerValue(const XMC_USIC_CH_t *const channel)
1131 {
1132 return channel->CMTR;
1133 }
1134
1135 /**
1136 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1137 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1138 * @param mode divider mode ::XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t \n
1139 * @param step divider \n
1140 * \b XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_NORMAL resulting divider = 1023 - step \n
1141 * \b XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL resulting divider = 1023 / step \n
1142 *
1143 * @return None
1144 *
1145 * \par<b>Description</b><br>
1146 * The fractional divider generates its output frequency fFD by either dividing the input frequency fPERIPH by an integer factor n or by multiplication of n/1024.
1147 *
1148 */
XMC_USIC_CH_SetFractionalDivider(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t mode,const uint16_t step)1149 __STATIC_INLINE void XMC_USIC_CH_SetFractionalDivider(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t mode, const uint16_t step)
1150 {
1151 channel->FDR = mode | step;
1152 }
1153
1154 /**
1155 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1156 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1157 * @param frame_length Number of bits in a frame. \n
1158 * \b Range: minimum= 1, maximum= 0x3f. The maximum value for fixed frame size is 0x3f. \n
1159 * e.g: For a frame length of 16, \a frame_length should be provided as 16.
1160 * @return None
1161 *
1162 * \par<b>Description</b><br>
1163 * Define the data frame length.\n\n
1164 * Set the number of bits to be serially transmitted in a frame.
1165 * The frame length should be multiples of word length. If the value is set to 0x40, the frame length
1166 * has to be controlled explicitly.
1167 *
1168 * \par<b>Related APIs:</b><BR>
1169 * XMC_USIC_CH_SetWordLength(), XMC_USIC_CH_EnableFrameLengthControl() \n\n\n
1170 */
XMC_USIC_CH_SetFrameLength(XMC_USIC_CH_t * const channel,const uint8_t frame_length)1171 __STATIC_INLINE void XMC_USIC_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const uint8_t frame_length)
1172 {
1173 channel->SCTR = (uint32_t)(channel->SCTR & (~USIC_CH_SCTR_FLE_Msk)) |
1174 (((uint32_t)frame_length - 0x1U) << USIC_CH_SCTR_FLE_Pos);
1175 }
1176
1177 /**
1178 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1179 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1180 * @param event Bit mask of the channel events to be enabled. Use @ref XMC_USIC_CH_EVENT_t for the bit masks. \n
1181 * \b Range: @ref XMC_USIC_CH_EVENT_RECEIVE_START, @ref XMC_USIC_CH_EVENT_DATA_LOST etc. Multiple events
1182 * can be combined using \a OR operation.
1183 * @return None
1184 *
1185 * \par<b>Description</b><br>
1186 * Enable the channel interrupt events.\n\n
1187 * Common channel events related to serial communication can be configured using this API.
1188 * Multiple events can be combined using the bitwise OR operation and configured in one function call.
1189 * XMC_USIC_CH_EVENT_t enumerates multiple protocol event bitmasks. These enumerations can be used as input to the API.
1190 *
1191 * \par<b>Related APIs:</b><BR>
1192 * XMC_USIC_CH_DisableEvent(), XMC_USIC_CH_SetInterruptNodePointer() \n\n\n
1193 */
XMC_USIC_CH_EnableEvent(XMC_USIC_CH_t * const channel,const uint32_t event)1194 __STATIC_INLINE void XMC_USIC_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
1195 {
1196 channel->CCR |= event;
1197 }
1198
1199 /**
1200 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1201 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1202 * @param event Bit mask of the channel events to be disabled. Use @ref XMC_USIC_CH_EVENT_t for the bit masks. \n
1203 * \b Range: @ref XMC_USIC_CH_EVENT_RECEIVE_START, @ref XMC_USIC_CH_EVENT_DATA_LOST etc. Multiple events
1204 * can be combined using \a OR operation.
1205 * @return None
1206 *
1207 * \par<b>Description</b><br>
1208 * Disable the channel interrupt events. \n\n
1209 * Multiple events can be combined using the bitwise OR operation and configured in one function call.
1210 * XMC_USIC_CH_EVENT_t enumerates multiple protocol event bitmasks. These enumerations can be used as input to the API.
1211 *
1212 * \par<b>Related APIs:</b><BR>
1213 * XMC_USIC_CH_EnableEvent(), XMC_USIC_CH_SetInterruptNodePointer() \n\n\n
1214 */
XMC_USIC_CH_DisableEvent(XMC_USIC_CH_t * const channel,const uint32_t event)1215 __STATIC_INLINE void XMC_USIC_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
1216 {
1217 channel->CCR &= (uint32_t)~event;
1218 }
1219
1220 /**
1221 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1222 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1223 * @param interrupt_node Interrupt node pointer to be configured. \n
1224 * \b Range: @ref XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT,
1225 * @ref XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
1226 * @param service_request Service request number.\n
1227 * \b Range: 0 to 5.
1228 * @return None
1229 *
1230 * \par<b>Description</b><br>
1231 * Sets the interrupt node for USIC channel events. \n\n
1232 * For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5).
1233 * The NVIC node gets linked to the interrupt event by doing so.<br>
1234 * Note: NVIC node should be separately enabled to generate the interrupt.
1235 *
1236 * \par<b>Related APIs:</b><BR>
1237 * XMC_USIC_CH_EnableEvent() \n\n\n
1238 */
1239 void XMC_USIC_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
1240 const XMC_USIC_CH_INTERRUPT_NODE_POINTER_t interrupt_node,
1241 const uint32_t service_request);
1242
1243 /**
1244 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1245 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1246 * @return Stataus @ref XMC_USIC_CH_TBUF_STATUS_IDLE if transmit buffer is free,
1247 * @ref XMC_USIC_CH_TBUF_STATUS_BUSY if transmit buffer is busy.
1248 *
1249 * \par<b>Description</b><br>
1250 * Gets transmit buffer status. \n\n
1251 * Status indicates whether the transmit buffer is free, or busy transmitting data.
1252 * The status depends on the value of TDV flag in TCSR register.
1253 * This status can be used while transmitting data. Transmit data when the transmit buffer
1254 * status is @ref XMC_USIC_CH_TBUF_STATUS_IDLE.
1255 *
1256 * \par<b>Related APIs:</b><BR>
1257 * XMC_USIC_CH_SetDataOutputMode() \n\n\n
1258 */
XMC_USIC_CH_GetTransmitBufferStatus(XMC_USIC_CH_t * const channel)1259 __STATIC_INLINE XMC_USIC_CH_TBUF_STATUS_t XMC_USIC_CH_GetTransmitBufferStatus(XMC_USIC_CH_t *const channel)
1260 {
1261 return (XMC_USIC_CH_TBUF_STATUS_t)(channel->TCSR & USIC_CH_TCSR_TDV_Msk);
1262 }
1263
1264 /**
1265 * @brief API to get receive buffer status
1266 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1267 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1268 * @return Status of data validity check for RBUF0 and RBUF1. \n
1269 * Returned value should be masked with RDV0 and RDV1 bits to know the status. \n
1270 * \b Range: @ref XMC_USIC_CH_RBUF_STATUS_DATA_VALID0, @ref XMC_USIC_CH_RBUF_STATUS_DATA_VALID1.
1271 *
1272 * \par<b>Description</b><br>
1273 * Checks if RBUF0 and RBUF1 have valid unread data. \n\n
1274 * It checks the bits RDV0 and RDV1 of the RBUFSR register.
1275 * Returns the value of RBUFSR masked with bitmasks of RDV0 and RDV1.
1276 * It can be used to decide whether 2bytes has to be read from RBUF or 1 byte.
1277 * If both bitmasks XMC_USIC_CH_RBUF_STATUS_DATA_VALID0 and XMC_USIC_CH_RBUF_STATUS_DATA_VALID1
1278 * are set, then 2 bytes can be read from RBUF. If only either of them is set, then only one byte
1279 * can be read from RBUF.
1280 * \par<b>Related APIs:</b><BR>
1281 * XMC_USIC_CH_GetTransmitBufferStatus() \n\n\n
1282 */
XMC_USIC_CH_GetReceiveBufferStatus(XMC_USIC_CH_t * const channel)1283 __STATIC_INLINE uint32_t XMC_USIC_CH_GetReceiveBufferStatus(XMC_USIC_CH_t *const channel)
1284 {
1285 return ((uint32_t) (channel->RBUFSR & (USIC_CH_RBUFSR_RDV0_Msk | USIC_CH_RBUFSR_RDV1_Msk)));
1286 }
1287
1288
1289 /**
1290 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1291 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1292 * @param start_transmision_mode Transmission mode to be enabled. \n
1293 * \b Range: @ref XMC_USIC_CH_START_TRANSMISION_DISABLED,
1294 * @ref XMC_USIC_CH_START_TRANSMISION_ON_TDV, @ref XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_0,
1295 * @ref XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_1
1296 *
1297 * @return None
1298 *
1299 * \par<b>Description</b><br>
1300 * Configures data transmission. \n\n
1301 * The configuration affects the data shifted on the DOUT0 pin.
1302 *
1303 * \par<b>Related APIs:</b><BR>
1304 * XMC_USIC_CH_GetTransmitBufferStatus(), XMC_USIC_CH_SetDataOutputMode() \n\n\n
1305 */
XMC_USIC_CH_SetStartTransmisionMode(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_START_TRANSMISION_MODE_t start_transmision_mode)1306 __STATIC_INLINE void XMC_USIC_CH_SetStartTransmisionMode(XMC_USIC_CH_t *const channel,
1307 const XMC_USIC_CH_START_TRANSMISION_MODE_t start_transmision_mode)
1308 {
1309 channel->TCSR = (uint32_t)(channel->TCSR & (~USIC_CH_TCSR_TDEN_Msk)) | (uint32_t)start_transmision_mode;
1310 }
1311
1312
1313 /**
1314 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1315 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1316 * @param data_output_mode Data output mode. \n
1317 * \b Range: @ref XMC_USIC_CH_DATA_OUTPUT_MODE_NORMAL, @ref XMC_USIC_CH_DATA_OUTPUT_MODE_INVERTED
1318 * @return None
1319 *
1320 * \par<b>Description</b><br>
1321 * Configures the mode for data output. \n\n
1322 * USIC channel can be configured to shift inverted data or direct data based on the input to the API.
1323 *
1324 * \par<b>Related APIs:</b><BR>
1325 * XMC_USIC_CH_SetStartTransmisionMode() \n\n\n
1326 */
XMC_USIC_CH_SetDataOutputMode(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_DATA_OUTPUT_MODE_t data_output_mode)1327 __STATIC_INLINE void XMC_USIC_CH_SetDataOutputMode(XMC_USIC_CH_t *const channel,
1328 const XMC_USIC_CH_DATA_OUTPUT_MODE_t data_output_mode)
1329 {
1330 channel->SCTR = (uint32_t)(channel->SCTR & (~USIC_CH_SCTR_DOCFG_Msk)) | (uint32_t)data_output_mode;
1331 }
1332
1333 /**
1334 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1335 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1336 * @return None
1337 *
1338 * \par<b>Description</b><br>
1339 * Enables automatic update of frame length. \n\n
1340 * When the automatic update of frame length is enabled, frame length is configured based on the
1341 * index of the TBUF[]/IN[] register array. When the data is written to TBUF[x], frame length is configured
1342 * with the mask value of \a x at the last 5 bit positions. Same logic is applicable if data is written to
1343 * IN[x] register.
1344 *
1345 * \par<b>Related APIs:</b><BR>
1346 * XMC_USIC_CH_DisableFrameLengthControl(), XMC_USIC_CH_TXFIFO_PutDataFLEMode() \n\n\n
1347 */
XMC_USIC_CH_EnableFrameLengthControl(XMC_USIC_CH_t * const channel)1348 __STATIC_INLINE void XMC_USIC_CH_EnableFrameLengthControl(XMC_USIC_CH_t *const channel)
1349 {
1350 channel->TCSR = (uint32_t)(channel->TCSR & (~(USIC_CH_TCSR_WLEMD_Msk |
1351 USIC_CH_TCSR_SELMD_Msk |
1352 USIC_CH_TCSR_WAMD_Msk |
1353 USIC_CH_TCSR_HPCMD_Msk))) |
1354 (uint32_t)USIC_CH_TCSR_FLEMD_Msk;
1355 }
1356
1357 /**
1358 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1359 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1360 * @return None
1361 *
1362 * \par<b>Description</b><br>
1363 * Disables automatic update of frame length. \n\n
1364 * When automatic update of frame length is disabled, frame length has to configured explicitly.
1365 * Frame length remains fixed until it is changed again.
1366 *
1367 * \par<b>Related APIs:</b><BR>
1368 * XMC_USIC_CH_DisableFrameLengthControl(), XMC_USIC_CH_SetFrameLength() \n\n\n
1369 */
XMC_USIC_CH_DisableFrameLengthControl(XMC_USIC_CH_t * const channel)1370 __STATIC_INLINE void XMC_USIC_CH_DisableFrameLengthControl(XMC_USIC_CH_t *const channel)
1371 {
1372 channel->TCSR &= (uint32_t)~USIC_CH_TCSR_FLEMD_Msk;
1373 }
1374
1375 /**
1376 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1377 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1378 * @return None
1379 *
1380 * \par<b>Description</b><br>
1381 * Bit TCSR.TE is set if DX2T becomes active while TDV = 1. \n\n
1382 * Enables the transfer trigger unit to set bit TCSR.TE if the trigger signal DX2T becomes active
1383 * for event driven transfer starts.
1384 *
1385 * \par<b>Related APIs:</b><BR>
1386 * XMC_USIC_CH_DisableTBUFDataValidTrigger()\n\n\n
1387 */
XMC_USIC_CH_EnableTBUFDataValidTrigger(XMC_USIC_CH_t * const channel)1388 __STATIC_INLINE void XMC_USIC_CH_EnableTBUFDataValidTrigger(XMC_USIC_CH_t *const channel)
1389 {
1390 channel->TCSR |= (uint32_t)USIC_CH_TCSR_TDVTR_Msk;
1391 }
1392
1393 /**
1394 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1395 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1396 * @return None
1397 *
1398 * \par<b>Description</b><br>
1399 * Disables the trigger of TDV depending on DX2T signal. \n\n
1400 * Bit TCSR.TE is permanently set.
1401 *
1402 * \par<b>Related APIs:</b><BR>
1403 * XMC_USIC_CH_EnableTBUFDataValidTrigger() \n\n\n
1404 */
XMC_USIC_CH_DisableTBUFDataValidTrigger(XMC_USIC_CH_t * const channel)1405 __STATIC_INLINE void XMC_USIC_CH_DisableTBUFDataValidTrigger(XMC_USIC_CH_t *const channel)
1406 {
1407 channel->TCSR &= (uint32_t)~USIC_CH_TCSR_TDVTR_Msk;
1408 }
1409
1410 /**
1411 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1412 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1413 * @param service_request_line service request number of the event to be triggered. \n
1414 * \b Range: 0 to 5.
1415 * @return None
1416 *
1417 * \par<b>Description</b><br>
1418 * Trigger a USIC interrupt service request.\n\n
1419 * When the USIC service request is triggered, the NVIC interrupt associated with it will be
1420 * generated if enabled.
1421 *
1422 * \par<b>Related APIs:</b><BR>
1423 * XMC_USIC_CH_SetInterruptNodePointer() \n\n\n
1424 */
XMC_USIC_CH_TriggerServiceRequest(XMC_USIC_CH_t * const channel,const uint32_t service_request_line)1425 __STATIC_INLINE void XMC_USIC_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line)
1426 {
1427 channel->FMR = (uint32_t)(USIC_CH_FMR_SIO0_Msk << service_request_line);
1428 }
1429
1430 /**
1431 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1432 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1433 * @param transmit_buffer_status clearing or setting the TDV flag. \n
1434 *
1435 * @return None
1436 *
1437 * \par<b>Description</b><br>
1438 * Modify TCSR.TDV and TCSR.TE to control the start of a data word transmission by software.
1439 *
1440 * \par<b>Related APIs:</b><BR>
1441 * XMC_USIC_CH_GetTransmitBufferStatus() \n\n\n
1442 */
XMC_USIC_CH_SetTransmitBufferStatus(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_TBUF_STATUS_SET_t transmit_buffer_status)1443 __STATIC_INLINE void XMC_USIC_CH_SetTransmitBufferStatus(XMC_USIC_CH_t *const channel,
1444 const XMC_USIC_CH_TBUF_STATUS_SET_t transmit_buffer_status)
1445 {
1446 channel->FMR = (uint32_t)transmit_buffer_status;
1447 }
1448
1449 /**
1450 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1451 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1452 * @param passive_level Value of passive level for the channel. \n
1453 * \b Range: @ref XMC_USIC_CH_PASSIVE_DATA_LEVEL0, @ref XMC_USIC_CH_PASSIVE_DATA_LEVEL1
1454 * @return None
1455 *
1456 * \par<b>Description</b><br>
1457 * Set the passive data level of the output signal. \n\n
1458 * When the USIC channel transmit stage is idle, the output signal level stays at the
1459 * configured passive level.
1460 *
1461 * \par<b>Related APIs:</b><BR>
1462 * XMC_USIC_CH_GetTransmitBufferStatus(), XMC_USIC_CH_SetStartTransmisionMode() \n\n\n
1463 */
XMC_USIC_CH_SetPassiveDataLevel(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_PASSIVE_DATA_LEVEL_t passive_level)1464 __STATIC_INLINE void XMC_USIC_CH_SetPassiveDataLevel(XMC_USIC_CH_t *const channel,
1465 const XMC_USIC_CH_PASSIVE_DATA_LEVEL_t passive_level)
1466 {
1467 channel->SCTR &= (~USIC_CH_SCTR_PDL_Msk);
1468 channel->SCTR |= (uint32_t)passive_level;
1469 }
1470
1471 /* TX FIFO APIs */
1472 /**
1473 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1474 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1475 * @param data_pointer Start position inside the FIFO buffer. \n
1476 * \b Range: 0 to 63.
1477 * @param size Required size of the transmit FIFO. \n
1478 * \b Range: @ref XMC_USIC_CH_FIFO_DISABLED, @ref XMC_USIC_CH_FIFO_SIZE_2WORDS.. @ref XMC_USIC_CH_FIFO_SIZE_64WORDS
1479 * @param limit Threshold of transmit FIFO filling level to be considered for generating events. \n
1480 * \b Range: 0 to \a size -1.
1481 * @return None
1482 *
1483 * \par<b>Description</b><br>
1484 * Initializes the transmit FIFO. \n\n
1485 * Transmit FIFO is a subset of a common FIFO sized 64 words. This FIFO is shared between 2 channels of the USIC module.
1486 * Each channel can share the FIFO for transmission and reception. \a data_pointer represents the start index in the common FIFO,
1487 * from where transmit data can be put, for the selected USIC channel. \a size represents the size of transmit FIFO as a multiple of
1488 * 2. Since the FIFO is shared between 2 USIC channels, FIFO size should be carefully selected. A FIFO standard transmit buffer
1489 * event is generated when the FIFO filling level falls below the \a limit value.
1490 *
1491 * \par<b>Related APIs:</b><BR>
1492 * XMC_USIC_CH_TXFIFO_EnableEvent(), XMC_USIC_CH_TXFIFO_SetInterruptNodePointer() \n\n\n
1493 */
1494 void XMC_USIC_CH_TXFIFO_Configure(XMC_USIC_CH_t *const channel,
1495 const uint32_t data_pointer,
1496 const XMC_USIC_CH_FIFO_SIZE_t size,
1497 const uint32_t limit);
1498
1499 /**
1500 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1501 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1502 * @param size Required size of the transmit FIFO. \n
1503 * \b Range: @ref XMC_USIC_CH_FIFO_DISABLED, @ref XMC_USIC_CH_FIFO_SIZE_2WORDS.. @ref XMC_USIC_CH_FIFO_SIZE_64WORDS
1504 * @param limit Threshold for transmit FIFO filling level to be considered for generating events. \n
1505 * \b Range: 0 to \a size -1.
1506 * @return None
1507 *
1508 * \par<b>Description</b><br>
1509 * Sets the size and trigger limit for the transmit FIFO. \n\n
1510 * The API is not to be called for initializing the transmit FIFO. The API shall be used for the
1511 * runtime change of transmit FIFO trigger limit. FIFO start position will not be affected on execution.
1512 *
1513 * \par<b>Related APIs:</b><BR>
1514 * XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit() \n\n\n
1515 */
1516 void XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel,
1517 const XMC_USIC_CH_FIFO_SIZE_t size,
1518 const uint32_t limit);
1519
1520
1521 /**
1522 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1523 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1524 * @param event Events to be enabled. Multiple events can be bitwise OR combined. @ref XMC_USIC_CH_TXFIFO_EVENT_CONF_t \n
1525 * @return None
1526 *
1527 * \par<b>Description</b><br>
1528 * Enables the interrupt events related to transmit FIFO. \n\n
1529 * Event bitmasks can be constructed using the enumeration @ref XMC_USIC_CH_TXFIFO_EVENT_CONF_t.
1530 * Multiple events can be enabled by providing multiple events in a single call. For providing
1531 * multiple events, combine the events using bitwise OR operation. Events are configured in the TBCTR register.<br>
1532 *
1533 * Note: API only enables the events. For interrupt generation, interrupt node must be configured and NVIC node
1534 * must be enabled.
1535 *
1536 * \par<b>Related APIs:</b><BR>
1537 * XMC_USIC_CH_TXFIFO_SetInterruptNodePointer() \n\n\n
1538 */
XMC_USIC_CH_TXFIFO_EnableEvent(XMC_USIC_CH_t * const channel,const uint32_t event)1539 __STATIC_INLINE void XMC_USIC_CH_TXFIFO_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
1540 {
1541 channel->TBCTR |= event;
1542 }
1543
1544
1545 /**
1546 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1547 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1548 * @param event Events to be disabled. @ref XMC_USIC_CH_TXFIFO_EVENT_CONF_t \n
1549 * @return None
1550 *
1551 * \par<b>Description</b><br>
1552 * Disables the interrupt events related to transmit FIFO. \n\n
1553 * By disabling the interrupt events, generation of interrupt is stopped. User can poll the event
1554 * flags from the status register using the API XMC_USIC_CH_TXFIFO_GetEvent().
1555 * Event bitmasks can be constructed using the enumeration @ref XMC_USIC_CH_TXFIFO_EVENT_CONF_t. For providing
1556 * multiple events, combine the events using bitwise OR operation.
1557 *
1558 * \par<b>Related APIs:</b><BR>
1559 * XMC_USIC_CH_TXFIFO_GetEvent(), XMC_USIC_CH_TXFIFO_EnableEvent() \n\n\n
1560 */
XMC_USIC_CH_TXFIFO_DisableEvent(XMC_USIC_CH_t * const channel,const uint32_t event)1561 __STATIC_INLINE void XMC_USIC_CH_TXFIFO_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
1562 {
1563 channel->TBCTR &= (uint32_t)~event;
1564 }
1565
1566 /**
1567 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1568 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1569 * @param interrupt_node Node pointer representing the transmit FIFO events. \n
1570 * \b Range: @ref XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD,
1571 * @ref XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE
1572 * @param service_request The service request to be used for interrupt generation. \n
1573 * \b Range: 0 to 5.
1574 * @return None
1575 *
1576 * \par<b>Description</b><br>
1577 * Sets an interrupt node for the transmit FIFO events.\n\n
1578 * A node pointer represents one or more interrupt events. Service request represents the interrupt node to be used
1579 * among the 6 interrupt nodes available for USIC module.
1580 * API configures the service request to be used for interrupt generation for the events selected.
1581 * A transmit FIFO event can generate an interrupt only if the interrupt node is configured for the event and
1582 * the interrupt generation is enabled for the event. For example, transmit FIFO standard transmit buffer
1583 * interrupt is generated if the interrupt node for the same is set and interrupt is enabled.<br>
1584 *
1585 * Note: NVIC node should be explicitly enabled for the interrupt generation.
1586 *
1587 * \par<b>Related APIs:</b><BR>
1588 * XMC_USIC_CH_TXFIFO_EnableEvent() \n\n\n
1589 */
1590 void XMC_USIC_CH_TXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
1591 const XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node,
1592 const uint32_t service_request);
1593
1594 /**
1595 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1596 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1597 * @param data Data to be transmitted. \n
1598 * \b Range: 16bit unsigned data. minimum= 0, maximum= 65535
1599 * @return None
1600 *
1601 * \par<b>Description</b><br>
1602 * Writes data into the transmit FIFO. \n\n
1603 * The data provided is placed in the transmit FIFO.
1604 * The transmit FIFO should be configured before calling this API.
1605 *
1606 * \par<b>Related APIs:</b><BR>
1607 * XMC_USIC_CH_TXFIFO_EnableEvent() \n\n\n
1608 */
XMC_USIC_CH_TXFIFO_PutData(XMC_USIC_CH_t * const channel,const uint16_t data)1609 __STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutData(XMC_USIC_CH_t *const channel, const uint16_t data)
1610 {
1611 channel->IN[0] = data;
1612 }
1613
1614 /**
1615 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1616 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1617 * @param data Data to be transmitted.
1618 * @param frame_length Frame length to be configured while transmitting the data. \n
1619 * \b Range: minimum= 0, maximum= 31. e.g: For a frame length of 16, set \a frame_length as 15.
1620 * @return None
1621 *
1622 * \par<b>Description</b><br>
1623 * Writes data to the transmit FIFO in frame length control mode. \n\n
1624 * When frame length control is enabled for dynamic update of frame length, this API can be used.
1625 * \a frame_length represents the frame length to be updated by the peripheral.
1626 * \a frame_length is used as index for the IN[] register array.
1627 *
1628 * \par<b>Related APIs:</b><BR>
1629 * XMC_USIC_CH_EnableFrameLengthControl() \n\n\n
1630 */
XMC_USIC_CH_TXFIFO_PutDataFLEMode(XMC_USIC_CH_t * const channel,const uint16_t data,const uint32_t frame_length)1631 __STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutDataFLEMode(XMC_USIC_CH_t *const channel,
1632 const uint16_t data,
1633 const uint32_t frame_length)
1634 {
1635 channel->IN[frame_length] = data;
1636 }
1637
1638 /**
1639 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1640 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1641 * @param data Data to be transmitted.
1642 * @param frame_length Frame length to be configured while transmitting the data. \n
1643 * \b Range: minimum= 0, maximum= 31. e.g: For a frame length of 16, set \a frame_length as 15.
1644 * @return None
1645 *
1646 * \par<b>Description</b><br>
1647 * Writes data to the transmit FIFO in hardware port control mode. \n\n
1648 * When hardware port control is enabled for dynamic update of frame length, this API can be used.
1649 * \a frame_length represents the frame length to be updated by the peripheral.
1650 * \a frame_length is used as index for the IN[] register array.
1651 *
1652 * \par<b>Related APIs:</b><BR>
1653 * XMC_USIC_CH_EnableFrameLengthControl() \n\n\n
1654 */
XMC_USIC_CH_TXFIFO_PutDataHPCMode(XMC_USIC_CH_t * const channel,const uint16_t data,const uint32_t frame_length)1655 __STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutDataHPCMode(XMC_USIC_CH_t *const channel,
1656 const uint16_t data,
1657 const uint32_t frame_length)
1658 {
1659 channel->IN[frame_length] = data;
1660 }
1661
1662 /**
1663 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1664 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1665 * @return None
1666 *
1667 * \par<b>Description</b><br>
1668 * Clears the contents of transmit FIFO. \n\n
1669 * Transmit FIFO contents will be cleared and the filling level will be reset to 0.
1670 *
1671 * \par<b>Related APIs:</b><BR>
1672 * XMC_USIC_CH_TXFIFO_GetLevel() \n\n\n
1673 */
XMC_USIC_CH_TXFIFO_Flush(XMC_USIC_CH_t * const channel)1674 __STATIC_INLINE void XMC_USIC_CH_TXFIFO_Flush(XMC_USIC_CH_t *const channel)
1675 {
1676 channel->TRBSCR = (uint32_t)USIC_CH_TRBSCR_FLUSHTB_Msk;
1677 }
1678
1679 /**
1680 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1681 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1682 * @return Status \a true if transmit FIFO is full
1683 * \a false if transmit FIFO is not full.
1684 *
1685 * \par<b>Description</b><br>
1686 * Checks if transmit FIFO is full. \n\n
1687 * When the transmit FIFO filling level reaches the configured size, FIFO full flag is set.
1688 * User should not write to the FIFO when the transmit FIFO is full.
1689 *
1690 * \par<b>Related APIs:</b><BR>
1691 * XMC_USIC_CH_TXFIFO_IsEmpty(), XMC_USIC_CH_TXFIFO_Flush() \n\n\n
1692 */
XMC_USIC_CH_TXFIFO_IsFull(XMC_USIC_CH_t * const channel)1693 __STATIC_INLINE bool XMC_USIC_CH_TXFIFO_IsFull(XMC_USIC_CH_t *const channel)
1694 {
1695 return (bool)(channel->TRBSR & USIC_CH_TRBSR_TFULL_Msk);
1696 }
1697
1698 /**
1699 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1700 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1701 * @return Status \a true if transmit FIFO is empty
1702 * \a false if transmit FIFO has some data.
1703 *
1704 * \par<b>Description</b><br>
1705 * Checks if transmit FIFO is empty. \n\n
1706 * When the transmit FIFO is empty, data can be written to FIFO.
1707 * When the last written word to the transmit FIFO is transmitted out of the FIFO,
1708 * FIFO empty flag is set.
1709 *
1710 * \par<b>Related APIs:</b><BR>
1711 * XMC_USIC_CH_TXFIFO_Flush(), XMC_USIC_CH_TXFIFO_PutData() \n\n\n
1712 */
XMC_USIC_CH_TXFIFO_IsEmpty(XMC_USIC_CH_t * const channel)1713 __STATIC_INLINE bool XMC_USIC_CH_TXFIFO_IsEmpty(XMC_USIC_CH_t *const channel)
1714 {
1715 return (bool)(channel->TRBSR & USIC_CH_TRBSR_TEMPTY_Msk);
1716 }
1717
1718 /**
1719 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1720 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1721 * @return Transmit FIFO filling level. \n
1722 * \b Range: minimum= 0(FIFO empty), maximum= transmit FIFO size.
1723 *
1724 * \par<b>Description</b><br>
1725 * Gets the transmit FIFO filling level. \n\n
1726 * For every word written to the FIFO, filling level is updated. The API gives the value
1727 * of this filling level.
1728 *
1729 * \par<b>Related APIs:</b><BR>
1730 * XMC_USIC_CH_TXFIFO_Flush(), XMC_USIC_CH_TXFIFO_PutData() \n\n\n
1731 */
XMC_USIC_CH_TXFIFO_GetLevel(XMC_USIC_CH_t * const channel)1732 __STATIC_INLINE uint32_t XMC_USIC_CH_TXFIFO_GetLevel(XMC_USIC_CH_t *const channel)
1733 {
1734 return ((uint32_t)(channel->TRBSR & USIC_CH_TRBSR_TBFLVL_Msk) >> USIC_CH_TRBSR_TBFLVL_Pos);
1735 }
1736
1737 /**
1738 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1739 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1740 * @return Status of standard transmit and transmit buffer error events. @ref XMC_USIC_CH_TXFIFO_EVENT_t \n
1741 *
1742 * \par<b>Description</b><br>
1743 * Gets the transmit FIFO event status. \n\n
1744 * Gives the status of transmit FIFO standard transmit buffer event and transmit buffer error event.
1745 * The status bits are located at their bit positions in the TRBSR register in the returned value.
1746 * User can make use of the @ref XMC_USIC_CH_TXFIFO_EVENT_t enumeration for checking the status of return value.
1747 * The status can be found by using the bitwise AND operation on the returned value with the enumerated value.<br>
1748 *
1749 * Note: Event status flags should be cleared by the user explicitly.
1750 *
1751 * \par<b>Related APIs:</b><BR>
1752 * XMC_USIC_CH_TXFIFO_ClearEvent() \n\n\n
1753 */
XMC_USIC_CH_TXFIFO_GetEvent(XMC_USIC_CH_t * const channel)1754 __STATIC_INLINE uint32_t XMC_USIC_CH_TXFIFO_GetEvent(XMC_USIC_CH_t *const channel)
1755 {
1756 return (uint32_t)((channel->TRBSR) & (USIC_CH_TRBSR_STBI_Msk |
1757 USIC_CH_TRBSR_TBERI_Msk));
1758 }
1759
1760 /**
1761 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1762 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1763 * @param event Transmit FIFO events to be cleared. \n
1764 * \b Range: @ref XMC_USIC_CH_TXFIFO_EVENT_STANDARD, @ref XMC_USIC_CH_TXFIFO_EVENT_ERROR.
1765 * @return None
1766 *
1767 * \par<b>Description</b><br>
1768 * Clears the transmit FIFO event flags in the status register. \n\n
1769 * USIC channel peripheral does not clear the event flags after they are read.
1770 * This API clears the events provided in the \a mask value.
1771 * XMC_USIC_CH_TXFIFO_EVENT enumeration can be used as input. Multiple events
1772 * can be cleared by providing a mask value obtained by bitwise OR operation of
1773 * multiple event enumerations.
1774 *
1775 * \par<b>Related APIs:</b><BR>
1776 * XMC_USIC_CH_TXFIFO_GetEvent() \n\n\n
1777 */
XMC_USIC_CH_TXFIFO_ClearEvent(XMC_USIC_CH_t * const channel,const uint32_t event)1778 __STATIC_INLINE void XMC_USIC_CH_TXFIFO_ClearEvent(XMC_USIC_CH_t *const channel,
1779 const uint32_t event)
1780 {
1781 channel->TRBSCR = event;
1782 }
1783
1784 /**
1785 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1786 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1787 * @param data_pointer Start position inside the FIFO buffer. \n
1788 * \b Range: 0 to 63.
1789 * @param size Required size of the receive FIFO. \n
1790 * \b Range: @ref XMC_USIC_CH_FIFO_DISABLED, @ref XMC_USIC_CH_FIFO_SIZE_2WORDS.. @ref XMC_USIC_CH_FIFO_SIZE_64WORDS
1791 * @param limit Threshold of receive FIFO filling level to be considered for generating events. \n
1792 * \b Range: 0 to \a size -1.
1793 * @return None
1794 *
1795 * \par<b>Description</b><br>
1796 * Configures the receive FIFO. \n\n
1797 * Receive FIFO is the subset of a common FIFO sized 64 words. This FIFO is shared between 2 channels of the USIC module.
1798 * Each channel can share the FIFO for transmission and reception. \a data_pointer represents the start index in the common FIFO,
1799 * from where received data can be put. \a size represents the size of receive FIFO as a multiple of 2.
1800 * Since the FIFO is shared between 2 USIC channels, FIFO size should be carefully selected. A FIFO standard receive buffer
1801 * event or alternative receive buffer event is generated when the FIFO filling level exceeds the \a limit value.
1802 *
1803 * \par<b>Related APIs:</b><BR>
1804 * XMC_USIC_CH_RXFIFO_EnableEvent(), XMC_USIC_CH_RXFIFO_SetInterruptNodePointer() \n\n\n
1805 */
1806 void XMC_USIC_CH_RXFIFO_Configure(XMC_USIC_CH_t *const channel,
1807 const uint32_t data_pointer,
1808 const XMC_USIC_CH_FIFO_SIZE_t size,
1809 const uint32_t limit);
1810
1811 /**
1812 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1813 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1814 * @param size Required size of the receive FIFO. \n
1815 * \b Range: @ref XMC_USIC_CH_FIFO_DISABLED, @ref XMC_USIC_CH_FIFO_SIZE_2WORDS.. @ref XMC_USIC_CH_FIFO_SIZE_64WORDS
1816 * @param limit Threshold for receive FIFO filling level to be considered for generating events. \n
1817 * \b Range: 0 to \a size -1.
1818 * @return None
1819 *
1820 * \par<b>Description</b><br>
1821 * Sets the size and trigger limit for the receive FIFO. \n\n
1822 * The API is not to be called for initializing the receive FIFO. The API shall be used for the
1823 * runtime change of receive FIFO trigger limit. FIFO start position will not be affected on execution.
1824 *
1825 * \par<b>Related APIs:</b><BR>
1826 * XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit()\ n\n\n
1827 */
1828 void XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel,
1829 const XMC_USIC_CH_FIFO_SIZE_t size,
1830 const uint32_t limit);
1831
1832 /**
1833 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1834 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1835 * @param event Events to be enabled. Multiple events can be bitwise OR combined. @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_t\n
1836 * @return None
1837 *
1838 * \par<b>Description</b><br>
1839 * Enables the interrupt events related to transmit FIFO. \n\n
1840 * Event bitmasks can be constructed using the enumeration @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_t.
1841 * Multiple events can be enabled by providing multiple events in a single call. For providing
1842 * multiple events, combine the events using bitwise OR operation.<br>
1843 *
1844 * Note: API only enables the events. For interrupt generation, interrupt node must be configured and NVIC node
1845 * must be enabled.
1846 *
1847 * \par<b>Related APIs:</b><BR>
1848 * XMC_USIC_CH_RXFIFO_SetInterruptNodePointer() \n\n\n
1849 */
XMC_USIC_CH_RXFIFO_EnableEvent(XMC_USIC_CH_t * const channel,const uint32_t event)1850 __STATIC_INLINE void XMC_USIC_CH_RXFIFO_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
1851 {
1852 channel->RBCTR |= event;
1853 }
1854
1855
1856 /**
1857 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1858 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1859 * @param event Events to be disabled. \n
1860 * \b Range: @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_STANDARD, @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_ERROR,
1861 * @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_ALTERNATE.
1862 * @return None
1863 *
1864 * \par<b>Description</b><br>
1865 * Disables the selected interrupt events related to receive FIFO. \n\n
1866 * By disabling the interrupt events, generation of interrupt is stopped. User can poll the event
1867 * flags from the status register using the API XMC_USIC_CH_RXFIFO_GetEvent().
1868 * Event bitmasks can be constructed using the enumeration \a XMC_USIC_CH_RXFIFO_EVENT_CONF. For providing
1869 * multiple events, combine the events using bitwise OR operation.
1870 *
1871 * \par<b>Related APIs:</b><BR>
1872 * XMC_USIC_CH_RXFIFO_GetEvent(), XMC_USIC_CH_RXFIFO_EnableEvent() \n\n\n
1873 */
XMC_USIC_CH_RXFIFO_DisableEvent(XMC_USIC_CH_t * const channel,const uint32_t event)1874 __STATIC_INLINE void XMC_USIC_CH_RXFIFO_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
1875 {
1876 channel->RBCTR &= (uint32_t)~event;
1877 }
1878
1879 /**
1880 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1881 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1882 * @param interrupt_node Node pointer representing the receive FIFO events. \n
1883 * \b Range: @ref XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD,
1884 * @ref XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE
1885 * @param service_request The service request to be used for interrupt generation.\n
1886 * \b Range: 0 to 5.
1887 * @return None
1888 *
1889 * \par<b>Description</b><br>
1890 * Sets an interrupt node for the receive FIFO events. \n\n
1891 * A node pointer represents one or more interrupt events. Service request represents the interrupt node to be used
1892 * among the 6 interrupt nodes available for USIC module.
1893 * API configures the service request to be used for interrupt generation for the events selected.
1894 * A receive FIFO event can generate an interrupt only if the interrupt node is configured for the event and
1895 * the interrupt generation is enabled for the event. For example, transmit FIFO standard transmit buffer
1896 * interrupt is generated if the interrupt node for the same is set and interrupt is enabled.<br>
1897 *
1898 * Note: NVIC node should be explicitly enabled for the interrupt generation.
1899 *
1900 * \par<b>Related APIs:</b><BR>
1901 * XMC_USIC_CH_RXFIFO_EnableEvent() \n\n\n
1902 */
1903 void XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
1904 const XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node,
1905 const uint32_t service_request);
1906
1907 /**
1908 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1909 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1910 * @return Value read from the receive FIFO. \n
1911 * \b Range: 16bit data. Length of data depends on the word length configuration.
1912 *
1913 * \par<b>Description</b><br>
1914 * Gets data from the receive FIFO. \n\n
1915 * Receive FIFO should be read only if data is availble in the FIFO. This can be checked using
1916 * the API XMC_USIC_CH_RXFIFO_IsEmpty(). Receive FIFO error flag will be set if an attempt is made
1917 * to read from an empty receive FIFO. To read all the received data, user should keep reading data
1918 * until receive FIFO is empty.
1919 *
1920 * \par<b>Related APIs:</b><BR>
1921 * XMC_USIC_CH_RXFIFO_ClearEvent() \n\n\n
1922 */
XMC_USIC_CH_RXFIFO_GetData(XMC_USIC_CH_t * const channel)1923 __STATIC_INLINE uint16_t XMC_USIC_CH_RXFIFO_GetData(XMC_USIC_CH_t *const channel)
1924 {
1925 return (uint16_t)(channel->OUTR);
1926 }
1927
1928 /**
1929 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1930 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1931 * @return None
1932 *
1933 * \par<b>Description</b><br>
1934 * Clears the contents of receive FIFO. \n\n
1935 * Receive FIFO contents will be cleared and the filling level will be reset to 0.
1936 *
1937 * \par<b>Related APIs:</b><BR>
1938 * XMC_USIC_CH_RXFIFO_GetLevel() \n\n\n
1939 */
XMC_USIC_CH_RXFIFO_Flush(XMC_USIC_CH_t * const channel)1940 __STATIC_INLINE void XMC_USIC_CH_RXFIFO_Flush(XMC_USIC_CH_t *const channel)
1941 {
1942 channel->TRBSCR = (uint32_t)USIC_CH_TRBSCR_FLUSHRB_Msk;
1943 }
1944
1945 /**
1946 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1947 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1948 * @return Status \a true if receive FIFO is full
1949 * \a false if receive FIFO is not full.
1950 *
1951 * \par<b>Description</b><br>
1952 * Checks if receive FIFO is full. \n\n
1953 * When the receive FIFO filling level reaches the configured size, FIFO full flag is set.
1954 * Any data received when the receive FIFO is full, is lost.
1955 *
1956 * \par<b>Related APIs:</b><BR>
1957 * XMC_USIC_CH_RXFIFO_IsEmpty(), XMC_USIC_CH_RXFIFO_Flush() \n\n\n
1958 */
XMC_USIC_CH_RXFIFO_IsFull(XMC_USIC_CH_t * const channel)1959 __STATIC_INLINE bool XMC_USIC_CH_RXFIFO_IsFull(XMC_USIC_CH_t *const channel)
1960 {
1961 return (bool)(channel->TRBSR & USIC_CH_TRBSR_RFULL_Msk);
1962 }
1963
1964 /**
1965 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1966 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1967 * @return Status \a true if receive FIFO is empty,
1968 * \a false if receive FIFO has some data.
1969 *
1970 * \par<b>Description</b><br>
1971 * Checks if receive FIFO is empty. \n\n
1972 * When the receive FIFO is empty, received data will be put in receive FIFO.
1973 * When the last received word in the FIFO is read, FIFO empty flag is set. Any attempt
1974 * to read from an empty receive FIFO will set the receive FIFO error flag.
1975 *
1976 * \par<b>Related APIs:</b><BR>
1977 * XMC_USIC_CH_RXFIFO_Flush(), XMC_USIC_CH_RXFIFO_PutData() \n\n\n
1978 */
XMC_USIC_CH_RXFIFO_IsEmpty(XMC_USIC_CH_t * const channel)1979 __STATIC_INLINE bool XMC_USIC_CH_RXFIFO_IsEmpty(XMC_USIC_CH_t *const channel)
1980 {
1981 return (bool)(channel->TRBSR & USIC_CH_TRBSR_REMPTY_Msk);
1982 }
1983
1984 /**
1985 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
1986 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
1987 * @return uint32_t Receive FIFO filling level. \n
1988 * \b Range: minimum= 0(FIFO empty), maximum= receive FIFO size.
1989 *
1990 * \par<b>Description</b><br>
1991 * Gets the receive FIFO filling level. \n\n
1992 * For every word received, the filling level is incremented. The API gives the value
1993 * of this filling level. The filling level is decremented when the data is read out of the
1994 * receive FIFO.
1995 *
1996 * \par<b>Related APIs:</b><BR>
1997 * XMC_USIC_CH_RXFIFO_Flush(), XMC_USIC_CH_RXFIFO_PutData() \n\n\n
1998 */
XMC_USIC_CH_RXFIFO_GetLevel(XMC_USIC_CH_t * const channel)1999 __STATIC_INLINE uint32_t XMC_USIC_CH_RXFIFO_GetLevel(XMC_USIC_CH_t *const channel)
2000 {
2001 return ((uint32_t)(channel->TRBSR & USIC_CH_TRBSR_RBFLVL_Msk) >> USIC_CH_TRBSR_RBFLVL_Pos);
2002 }
2003
2004 /**
2005 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
2006 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
2007 * @return Status of standard receive buffer, alternative receive buffer and receive buffer error events. \n
2008 * \b Range: @ref XMC_USIC_CH_RXFIFO_EVENT_STANDARD, @ref XMC_USIC_CH_RXFIFO_EVENT_ERROR,
2009 * @ref XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE.
2010 *
2011 * \par<b>Description</b><br>
2012 * Gets the receive FIFO events' status. \n\n
2013 * Gives the status of receive FIFO standard receive buffer event, alternative receive buffer event and receive buffer error event.
2014 * The status bits are located at their bitpositions in the TRBSR register in the returned value.
2015 * User can make use of the XMC_USIC_CH_RXFIFO_EVENT enumeration for checking the status of return value.
2016 * The status can be found by using the bitwise AND operation on the returned value with the enumerated value.<br>
2017 *
2018 * Note: Event status flags should be cleared by the user explicitly.
2019 *
2020 * \par<b>Related APIs:</b><BR>
2021 * XMC_USIC_CH_RXFIFO_ClearEvent()\n\n\n
2022 */
XMC_USIC_CH_RXFIFO_GetEvent(XMC_USIC_CH_t * const channel)2023 __STATIC_INLINE uint32_t XMC_USIC_CH_RXFIFO_GetEvent(XMC_USIC_CH_t *const channel)
2024 {
2025 return (uint32_t)((channel->TRBSR) & (USIC_CH_TRBSR_SRBI_Msk |
2026 USIC_CH_TRBSR_RBERI_Msk |
2027 USIC_CH_TRBSR_ARBI_Msk));
2028 }
2029
2030 /**
2031 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
2032 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
2033 * @param event Receive FIFO events to be cleared. \n
2034 * \b Range: @ref XMC_USIC_CH_RXFIFO_EVENT_STANDARD, @ref XMC_USIC_CH_RXFIFO_EVENT_ERROR,
2035 * @ref XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE.
2036 * @return None
2037 *
2038 * \par<b>Description</b><br>
2039 * Clears the receive FIFO event flags in the status register. \n\n
2040 * USIC channel peripheral does not clear the event flags after they are read.
2041 * This API clears the events provided in the \a mask value.
2042 * XMC_USIC_CH_RXFIFO_EVENT enumeration can be used as input. Multiple events
2043 * can be cleared by providing a mask value obtained by bitwise OR operation of
2044 * multiple event enumerations.
2045 *
2046 * \par<b>Related APIs:</b><BR>
2047 * XMC_USIC_CH_RXFIFO_GetEvent() \n\n\n
2048 */
XMC_USIC_CH_RXFIFO_ClearEvent(XMC_USIC_CH_t * const channel,const uint32_t event)2049 __STATIC_INLINE void XMC_USIC_CH_RXFIFO_ClearEvent(XMC_USIC_CH_t *const channel,
2050 const uint32_t event)
2051 {
2052 channel->TRBSCR = event;
2053 }
2054
2055 /**
2056 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
2057 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
2058 * @return None
2059 *
2060 * \par<b>Description</b><br>
2061 * Enables time measurement using the capture mode timer. \n\n
2062 * Time measurement is enabled by setting the timer enable flag in BRG register.
2063 *
2064 * \par<b>Related APIs:</b><BR>
2065 * XMC_USIC_CH_DisableTimeMeasurement() \n\n\n
2066 */
XMC_USIC_CH_EnableTimeMeasurement(XMC_USIC_CH_t * const channel)2067 __STATIC_INLINE void XMC_USIC_CH_EnableTimeMeasurement(XMC_USIC_CH_t *const channel)
2068 {
2069 channel->BRG |= (uint32_t)USIC_CH_BRG_TMEN_Msk;
2070 }
2071
2072 /**
2073 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
2074 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
2075 * @return None
2076 *
2077 * \par<b>Description</b><br>
2078 * Disables time measurement using the capture mode timer. \n\n
2079 * Time measurement is disabled by clearing the timer enable flag in BRG register.
2080 *
2081 * \par<b>Related APIs:</b><BR>
2082 * XMC_USIC_CH_EnableTimeMeasurement() \n\n\n
2083 */
XMC_USIC_CH_DisableTimeMeasurement(XMC_USIC_CH_t * const channel)2084 __STATIC_INLINE void XMC_USIC_CH_DisableTimeMeasurement(XMC_USIC_CH_t *const channel)
2085 {
2086 channel->BRG &= (uint32_t)~USIC_CH_BRG_TMEN_Msk;
2087 }
2088
2089 /**
2090 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
2091 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
2092 * @param passive_level Passive level for the master clock output. \n
2093 * \b Range: @ref XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_0, @ref XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_1.
2094 * @return None
2095 *
2096 * \par<b>Description</b><br>
2097 * Sets the idle mode pin level for the master clock output. \n
2098 */
XMC_USIC_CH_SetMclkOutputPassiveLevel(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t passive_level)2099 __STATIC_INLINE void XMC_USIC_CH_SetMclkOutputPassiveLevel(XMC_USIC_CH_t *const channel,
2100 const XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t passive_level)
2101 {
2102 channel->BRG = (uint32_t)(channel->BRG & (~USIC_CH_BRG_MCLKCFG_Msk)) | (uint32_t)passive_level;
2103 }
2104 /**
2105 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
2106 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
2107 * @param passive_level Passive level for the clock output. \n
2108 * \b Range: @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED,
2109 * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED,
2110 * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED,
2111 * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED,
2112 * @param clock_output Shift clock source selection. \n
2113 * \b Range: Use @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK,
2114 * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1
2115 * @return None
2116 *
2117 * \par<b>Description</b><br>
2118 * Sets the idle mode shift clock output level and selects the shift clock source. \n\n
2119 * Shift clock idle mode output level can be set to logic high or low. Shift clock output can be configured to have a
2120 * delay of half shift clock period. Both the configurations are available as enumeration values defined with type
2121 * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t.
2122 * This value should be configured based on the slave device requirement.
2123 * Shift clock source can be selected between internal clock(master) and external input(slave).
2124 *
2125 */
XMC_USIC_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t passive_level,const XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output)2126 __STATIC_INLINE void XMC_USIC_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t *const channel,
2127 const XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t passive_level,
2128 const XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output)
2129 {
2130 channel->BRG = (uint32_t)(channel->BRG & (~(USIC_CH_BRG_SCLKCFG_Msk |
2131 USIC_CH_BRG_SCLKOSEL_Msk))) |
2132 (uint32_t)passive_level |
2133 (uint32_t)clock_output;
2134 }
2135
2136 /**
2137 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
2138 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref XMC_USIC2_CH1 based on device support.
2139 * @param mode USIC channel operation mode. \n
2140 * \b Range: @ref XMC_USIC_CH_OPERATING_MODE_IDLE, @ref XMC_USIC_CH_OPERATING_MODE_SPI,
2141 * @ref XMC_USIC_CH_OPERATING_MODE_UART, @ref XMC_USIC_CH_OPERATING_MODE_I2S,
2142 * @ref XMC_USIC_CH_OPERATING_MODE_I2C.
2143 * @return None
2144 *
2145 * \par<b>Description</b><br>
2146 * Sets the USIC channel operation mode.\n\n
2147 * A USIC channel can support multiple serial communication protocols like UART, SPI, I2C and I2S.
2148 * The API sets the input operation mode to the USIC channel.
2149 *
2150 * \par<b>Related APIs:</b><BR>
2151 * XMC_USIC_Enable(), XMC_USIC_CH_Enable() \n\n\n
2152 */
XMC_USIC_CH_SetMode(XMC_USIC_CH_t * const channel,const XMC_USIC_CH_OPERATING_MODE_t mode)2153 __STATIC_INLINE void XMC_USIC_CH_SetMode(XMC_USIC_CH_t *const channel, const XMC_USIC_CH_OPERATING_MODE_t mode)
2154 {
2155 channel->CCR = (uint32_t)(channel->CCR & (~(USIC_CH_CCR_MODE_Msk))) | (uint32_t)mode;
2156 }
2157 #ifdef __cplusplus
2158 }
2159 #endif
2160
2161 /**
2162 * @}
2163 */
2164
2165 /**
2166 * @}
2167 */
2168
2169 #endif
2170
