Home
last modified time | relevance | path

Searched refs:TX_FIFO_WR (Results 1 – 12 of 12) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/ip/
Dcyip_tdm.h55 __OM uint32_t TX_FIFO_WR; /*!< 0x00000088 TX FIFO write */ member
Dcyip_scb_v4.h72 __OM uint32_t TX_FIFO_WR; /*!< 0x00000240 Transmitter FIFO write */ member
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_i2s.h58 __OM uint32_t TX_FIFO_WR; /*!< 0x00000208 TX FIFO write */ member
Dcyip_scb.h66 __OM uint32_t TX_FIFO_WR; /*!< 0x00000240 Transmitter FIFO write */ member
Dcyip_ble.h73 __OM uint32_t TX_FIFO_WR; /*!< 0x0000001C Transmitter FIFO write register. */ member
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_i2s_v2.h59 __OM uint32_t TX_FIFO_WR; /*!< 0x00000208 TX FIFO write */ member
Dcyip_scb_v2.h68 __OM uint32_t TX_FIFO_WR; /*!< 0x00000240 Transmitter FIFO write */ member
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h938 #define REG_I2S_TX_FIFO_WR(base) (((I2S_V1_Type*)(base))->TX_FIFO_WR)
1160 #define SCB_TX_FIFO_WR(base) (((CySCB_V1_Type*) (base))->TX_FIFO_WR)
1211 #define BLE_RCB_TX_FIFO_WR (((BLE_V1_Type *) BLE_BASE)->RCB.TX_FIFO_WR)
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h1613 #define REG_I2S_TX_FIFO_WR(base) (((I2S_Type*)(base))->TX_FIFO_WR)
1808 #define SCB_TX_FIFO_WR(base) (((CySCB_Type*) (base))->TX_FIFO_WR)
1869 #define BLE_RCB_TX_FIFO_WR (((BLE_V1_Type *) BLE_BASE)->RCB.TX_FIFO_WR)
/hal_infineon-3.7.0/mtb-hal-cat1/source/
Dcyhal_audio_common.c2390 .dst_addr = (uint32_t)(&(obj->base->TX_FIFO_WR)),
2392 .dst_addr = (uint32_t)(&(obj->base->TDM_TX_STRUCT.TX_FIFO_WR)),
Dcyhal_uart.c1331 .dst_addr = (uint32_t)&obj->base->TX_FIFO_WR, in _cyhal_uart_dma_write_async()
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h491 #define SCB_TX_FIFO_WR(base) (((CySCB_Type*) (base))->TX_FIFO_WR)
1718 …STRUCT_TX_FIFO_WR(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_FIFO_WR)