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Searched refs:TRIG_OUT_MUX_2_TCPWM0_TR_IN11 (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dpsoc6_03_config.h929 TRIG_OUT_MUX_2_TCPWM0_TR_IN11 = 0x4000020Bu, /* tcpwm[0].tr_in[11] */ enumerator
Dpsoc6_04_config.h879 TRIG_OUT_MUX_2_TCPWM0_TR_IN11 = 0x4000020Bu, /* tcpwm[0].tr_all_cnt_in[11] */ enumerator
Dpsoc6_02_config.h1376 TRIG_OUT_MUX_2_TCPWM0_TR_IN11 = 0x4000020Bu, /* tcpwm[0].tr_in[11] */ enumerator