1 /***************************************************************************//** 2 * \file psoc6_02_config.h 3 * 4 * \brief 5 * PSoC6_02 device configuration header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _PSOC6_02_CONFIG_H_ 28 #define _PSOC6_02_CONFIG_H_ 29 30 /* Clock Connections */ 31 typedef enum 32 { 33 PCLK_SCB0_CLOCK = 0x0000u, /* scb[0].clock */ 34 PCLK_SCB1_CLOCK = 0x0001u, /* scb[1].clock */ 35 PCLK_SCB2_CLOCK = 0x0002u, /* scb[2].clock */ 36 PCLK_SCB3_CLOCK = 0x0003u, /* scb[3].clock */ 37 PCLK_SCB4_CLOCK = 0x0004u, /* scb[4].clock */ 38 PCLK_SCB5_CLOCK = 0x0005u, /* scb[5].clock */ 39 PCLK_SCB6_CLOCK = 0x0006u, /* scb[6].clock */ 40 PCLK_SCB7_CLOCK = 0x0007u, /* scb[7].clock */ 41 PCLK_SCB8_CLOCK = 0x0008u, /* scb[8].clock */ 42 PCLK_SCB9_CLOCK = 0x0009u, /* scb[9].clock */ 43 PCLK_SCB10_CLOCK = 0x000Au, /* scb[10].clock */ 44 PCLK_SCB11_CLOCK = 0x000Bu, /* scb[11].clock */ 45 PCLK_SCB12_CLOCK = 0x000Cu, /* scb[12].clock */ 46 PCLK_SMARTIO8_CLOCK = 0x000Du, /* smartio[8].clock */ 47 PCLK_SMARTIO9_CLOCK = 0x000Eu, /* smartio[9].clock */ 48 PCLK_TCPWM0_CLOCKS0 = 0x000Fu, /* tcpwm[0].clocks[0] */ 49 PCLK_TCPWM0_CLOCKS1 = 0x0010u, /* tcpwm[0].clocks[1] */ 50 PCLK_TCPWM0_CLOCKS2 = 0x0011u, /* tcpwm[0].clocks[2] */ 51 PCLK_TCPWM0_CLOCKS3 = 0x0012u, /* tcpwm[0].clocks[3] */ 52 PCLK_TCPWM0_CLOCKS4 = 0x0013u, /* tcpwm[0].clocks[4] */ 53 PCLK_TCPWM0_CLOCKS5 = 0x0014u, /* tcpwm[0].clocks[5] */ 54 PCLK_TCPWM0_CLOCKS6 = 0x0015u, /* tcpwm[0].clocks[6] */ 55 PCLK_TCPWM0_CLOCKS7 = 0x0016u, /* tcpwm[0].clocks[7] */ 56 PCLK_TCPWM1_CLOCKS0 = 0x0017u, /* tcpwm[1].clocks[0] */ 57 PCLK_TCPWM1_CLOCKS1 = 0x0018u, /* tcpwm[1].clocks[1] */ 58 PCLK_TCPWM1_CLOCKS2 = 0x0019u, /* tcpwm[1].clocks[2] */ 59 PCLK_TCPWM1_CLOCKS3 = 0x001Au, /* tcpwm[1].clocks[3] */ 60 PCLK_TCPWM1_CLOCKS4 = 0x001Bu, /* tcpwm[1].clocks[4] */ 61 PCLK_TCPWM1_CLOCKS5 = 0x001Cu, /* tcpwm[1].clocks[5] */ 62 PCLK_TCPWM1_CLOCKS6 = 0x001Du, /* tcpwm[1].clocks[6] */ 63 PCLK_TCPWM1_CLOCKS7 = 0x001Eu, /* tcpwm[1].clocks[7] */ 64 PCLK_TCPWM1_CLOCKS8 = 0x001Fu, /* tcpwm[1].clocks[8] */ 65 PCLK_TCPWM1_CLOCKS9 = 0x0020u, /* tcpwm[1].clocks[9] */ 66 PCLK_TCPWM1_CLOCKS10 = 0x0021u, /* tcpwm[1].clocks[10] */ 67 PCLK_TCPWM1_CLOCKS11 = 0x0022u, /* tcpwm[1].clocks[11] */ 68 PCLK_TCPWM1_CLOCKS12 = 0x0023u, /* tcpwm[1].clocks[12] */ 69 PCLK_TCPWM1_CLOCKS13 = 0x0024u, /* tcpwm[1].clocks[13] */ 70 PCLK_TCPWM1_CLOCKS14 = 0x0025u, /* tcpwm[1].clocks[14] */ 71 PCLK_TCPWM1_CLOCKS15 = 0x0026u, /* tcpwm[1].clocks[15] */ 72 PCLK_TCPWM1_CLOCKS16 = 0x0027u, /* tcpwm[1].clocks[16] */ 73 PCLK_TCPWM1_CLOCKS17 = 0x0028u, /* tcpwm[1].clocks[17] */ 74 PCLK_TCPWM1_CLOCKS18 = 0x0029u, /* tcpwm[1].clocks[18] */ 75 PCLK_TCPWM1_CLOCKS19 = 0x002Au, /* tcpwm[1].clocks[19] */ 76 PCLK_TCPWM1_CLOCKS20 = 0x002Bu, /* tcpwm[1].clocks[20] */ 77 PCLK_TCPWM1_CLOCKS21 = 0x002Cu, /* tcpwm[1].clocks[21] */ 78 PCLK_TCPWM1_CLOCKS22 = 0x002Du, /* tcpwm[1].clocks[22] */ 79 PCLK_TCPWM1_CLOCKS23 = 0x002Eu, /* tcpwm[1].clocks[23] */ 80 PCLK_CSD_CLOCK = 0x002Fu, /* csd.clock */ 81 PCLK_LCD_CLOCK = 0x0030u, /* lcd.clock */ 82 PCLK_PROFILE_CLOCK_PROFILE = 0x0031u, /* profile.clock_profile */ 83 PCLK_CPUSS_CLOCK_TRACE_IN = 0x0032u, /* cpuss.clock_trace_in */ 84 PCLK_PASS_CLOCK_PUMP_PERI = 0x0033u, /* pass.clock_pump_peri */ 85 PCLK_PASS_CLOCK_SAR = 0x0034u, /* pass.clock_sar */ 86 PCLK_USB_CLOCK_DEV_BRS = 0x0035u /* usb.clock_dev_brs */ 87 } en_clk_dst_t; 88 89 /* Trigger Group */ 90 /* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. 91 * Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details. 92 */ 93 /* Trigger Group Inputs */ 94 /* Trigger Input Group 0 - P-DMA0 Request Assignments */ 95 typedef enum 96 { 97 TRIG_IN_MUX_0_PDMA0_TR_OUT0 = 0x00000001u, /* cpuss.dw0_tr_out[0] */ 98 TRIG_IN_MUX_0_PDMA0_TR_OUT1 = 0x00000002u, /* cpuss.dw0_tr_out[1] */ 99 TRIG_IN_MUX_0_PDMA0_TR_OUT2 = 0x00000003u, /* cpuss.dw0_tr_out[2] */ 100 TRIG_IN_MUX_0_PDMA0_TR_OUT3 = 0x00000004u, /* cpuss.dw0_tr_out[3] */ 101 TRIG_IN_MUX_0_PDMA0_TR_OUT4 = 0x00000005u, /* cpuss.dw0_tr_out[4] */ 102 TRIG_IN_MUX_0_PDMA0_TR_OUT5 = 0x00000006u, /* cpuss.dw0_tr_out[5] */ 103 TRIG_IN_MUX_0_PDMA0_TR_OUT6 = 0x00000007u, /* cpuss.dw0_tr_out[6] */ 104 TRIG_IN_MUX_0_PDMA0_TR_OUT7 = 0x00000008u, /* cpuss.dw0_tr_out[7] */ 105 TRIG_IN_MUX_0_PDMA1_TR_OUT0 = 0x00000009u, /* cpuss.dw1_tr_out[0] */ 106 TRIG_IN_MUX_0_PDMA1_TR_OUT1 = 0x0000000Au, /* cpuss.dw1_tr_out[1] */ 107 TRIG_IN_MUX_0_PDMA1_TR_OUT2 = 0x0000000Bu, /* cpuss.dw1_tr_out[2] */ 108 TRIG_IN_MUX_0_PDMA1_TR_OUT3 = 0x0000000Cu, /* cpuss.dw1_tr_out[3] */ 109 TRIG_IN_MUX_0_PDMA1_TR_OUT4 = 0x0000000Du, /* cpuss.dw1_tr_out[4] */ 110 TRIG_IN_MUX_0_PDMA1_TR_OUT5 = 0x0000000Eu, /* cpuss.dw1_tr_out[5] */ 111 TRIG_IN_MUX_0_PDMA1_TR_OUT6 = 0x0000000Fu, /* cpuss.dw1_tr_out[6] */ 112 TRIG_IN_MUX_0_PDMA1_TR_OUT7 = 0x00000010u, /* cpuss.dw1_tr_out[7] */ 113 TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW0 = 0x00000011u, /* tcpwm[0].tr_overflow[0] */ 114 TRIG_IN_MUX_0_TCPWM0_TR_COMPARE_MATCH0 = 0x00000012u, /* tcpwm[0].tr_compare_match[0] */ 115 TRIG_IN_MUX_0_TCPWM0_TR_UNDERFLOW0 = 0x00000013u, /* tcpwm[0].tr_underflow[0] */ 116 TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW1 = 0x00000014u, /* tcpwm[0].tr_overflow[1] */ 117 TRIG_IN_MUX_0_TCPWM0_TR_COMPARE_MATCH1 = 0x00000015u, /* tcpwm[0].tr_compare_match[1] */ 118 TRIG_IN_MUX_0_TCPWM0_TR_UNDERFLOW1 = 0x00000016u, /* tcpwm[0].tr_underflow[1] */ 119 TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW2 = 0x00000017u, /* tcpwm[0].tr_overflow[2] */ 120 TRIG_IN_MUX_0_TCPWM0_TR_COMPARE_MATCH2 = 0x00000018u, /* tcpwm[0].tr_compare_match[2] */ 121 TRIG_IN_MUX_0_TCPWM0_TR_UNDERFLOW2 = 0x00000019u, /* tcpwm[0].tr_underflow[2] */ 122 TRIG_IN_MUX_0_TCPWM0_TR_OVERFLOW3 = 0x0000001Au, /* tcpwm[0].tr_overflow[3] */ 123 TRIG_IN_MUX_0_TCPWM0_TR_COMPARE_MATCH3 = 0x0000001Bu, /* tcpwm[0].tr_compare_match[3] */ 124 TRIG_IN_MUX_0_TCPWM0_TR_UNDERFLOW3 = 0x0000001Cu, /* tcpwm[0].tr_underflow[3] */ 125 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW0 = 0x0000001Du, /* tcpwm[1].tr_overflow[0] */ 126 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH0 = 0x0000001Eu, /* tcpwm[1].tr_compare_match[0] */ 127 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW0 = 0x0000001Fu, /* tcpwm[1].tr_underflow[0] */ 128 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW1 = 0x00000020u, /* tcpwm[1].tr_overflow[1] */ 129 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH1 = 0x00000021u, /* tcpwm[1].tr_compare_match[1] */ 130 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW1 = 0x00000022u, /* tcpwm[1].tr_underflow[1] */ 131 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW2 = 0x00000023u, /* tcpwm[1].tr_overflow[2] */ 132 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH2 = 0x00000024u, /* tcpwm[1].tr_compare_match[2] */ 133 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW2 = 0x00000025u, /* tcpwm[1].tr_underflow[2] */ 134 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW3 = 0x00000026u, /* tcpwm[1].tr_overflow[3] */ 135 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH3 = 0x00000027u, /* tcpwm[1].tr_compare_match[3] */ 136 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW3 = 0x00000028u, /* tcpwm[1].tr_underflow[3] */ 137 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW4 = 0x00000029u, /* tcpwm[1].tr_overflow[4] */ 138 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH4 = 0x0000002Au, /* tcpwm[1].tr_compare_match[4] */ 139 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW4 = 0x0000002Bu, /* tcpwm[1].tr_underflow[4] */ 140 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW5 = 0x0000002Cu, /* tcpwm[1].tr_overflow[5] */ 141 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH5 = 0x0000002Du, /* tcpwm[1].tr_compare_match[5] */ 142 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW5 = 0x0000002Eu, /* tcpwm[1].tr_underflow[5] */ 143 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW6 = 0x0000002Fu, /* tcpwm[1].tr_overflow[6] */ 144 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH6 = 0x00000030u, /* tcpwm[1].tr_compare_match[6] */ 145 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW6 = 0x00000031u, /* tcpwm[1].tr_underflow[6] */ 146 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW7 = 0x00000032u, /* tcpwm[1].tr_overflow[7] */ 147 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH7 = 0x00000033u, /* tcpwm[1].tr_compare_match[7] */ 148 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW7 = 0x00000034u, /* tcpwm[1].tr_underflow[7] */ 149 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW8 = 0x00000035u, /* tcpwm[1].tr_overflow[8] */ 150 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH8 = 0x00000036u, /* tcpwm[1].tr_compare_match[8] */ 151 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW8 = 0x00000037u, /* tcpwm[1].tr_underflow[8] */ 152 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW9 = 0x00000038u, /* tcpwm[1].tr_overflow[9] */ 153 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH9 = 0x00000039u, /* tcpwm[1].tr_compare_match[9] */ 154 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW9 = 0x0000003Au, /* tcpwm[1].tr_underflow[9] */ 155 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW10 = 0x0000003Bu, /* tcpwm[1].tr_overflow[10] */ 156 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH10 = 0x0000003Cu, /* tcpwm[1].tr_compare_match[10] */ 157 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW10 = 0x0000003Du, /* tcpwm[1].tr_underflow[10] */ 158 TRIG_IN_MUX_0_TCPWM1_TR_OVERFLOW11 = 0x0000003Eu, /* tcpwm[1].tr_overflow[11] */ 159 TRIG_IN_MUX_0_TCPWM1_TR_COMPARE_MATCH11 = 0x0000003Fu, /* tcpwm[1].tr_compare_match[11] */ 160 TRIG_IN_MUX_0_TCPWM1_TR_UNDERFLOW11 = 0x00000040u, /* tcpwm[1].tr_underflow[11] */ 161 TRIG_IN_MUX_0_MDMA_TR_OUT0 = 0x00000041u, /* cpuss.dmac_tr_out[0] */ 162 TRIG_IN_MUX_0_MDMA_TR_OUT1 = 0x00000042u, /* cpuss.dmac_tr_out[1] */ 163 TRIG_IN_MUX_0_MDMA_TR_OUT2 = 0x00000043u, /* cpuss.dmac_tr_out[2] */ 164 TRIG_IN_MUX_0_MDMA_TR_OUT3 = 0x00000044u, /* cpuss.dmac_tr_out[3] */ 165 TRIG_IN_MUX_0_HSIOM_TR_OUT0 = 0x00000045u, /* peri.tr_io_input[0] */ 166 TRIG_IN_MUX_0_HSIOM_TR_OUT1 = 0x00000046u, /* peri.tr_io_input[1] */ 167 TRIG_IN_MUX_0_HSIOM_TR_OUT2 = 0x00000047u, /* peri.tr_io_input[2] */ 168 TRIG_IN_MUX_0_HSIOM_TR_OUT3 = 0x00000048u, /* peri.tr_io_input[3] */ 169 TRIG_IN_MUX_0_HSIOM_TR_OUT4 = 0x00000049u, /* peri.tr_io_input[4] */ 170 TRIG_IN_MUX_0_HSIOM_TR_OUT5 = 0x0000004Au, /* peri.tr_io_input[5] */ 171 TRIG_IN_MUX_0_HSIOM_TR_OUT6 = 0x0000004Bu, /* peri.tr_io_input[6] */ 172 TRIG_IN_MUX_0_HSIOM_TR_OUT7 = 0x0000004Cu, /* peri.tr_io_input[7] */ 173 TRIG_IN_MUX_0_HSIOM_TR_OUT8 = 0x0000004Du, /* peri.tr_io_input[8] */ 174 TRIG_IN_MUX_0_HSIOM_TR_OUT9 = 0x0000004Eu, /* peri.tr_io_input[9] */ 175 TRIG_IN_MUX_0_HSIOM_TR_OUT10 = 0x0000004Fu, /* peri.tr_io_input[10] */ 176 TRIG_IN_MUX_0_HSIOM_TR_OUT11 = 0x00000050u, /* peri.tr_io_input[11] */ 177 TRIG_IN_MUX_0_HSIOM_TR_OUT12 = 0x00000051u, /* peri.tr_io_input[12] */ 178 TRIG_IN_MUX_0_HSIOM_TR_OUT13 = 0x00000052u, /* peri.tr_io_input[13] */ 179 TRIG_IN_MUX_0_CTI_TR_OUT0 = 0x00000053u, /* cpuss.cti_tr_out[0] */ 180 TRIG_IN_MUX_0_CTI_TR_OUT1 = 0x00000054u, /* cpuss.cti_tr_out[1] */ 181 TRIG_IN_MUX_0_FAULT_TR_OUT0 = 0x00000055u, /* cpuss.tr_fault[0] */ 182 TRIG_IN_MUX_0_FAULT_TR_OUT1 = 0x00000056u /* cpuss.tr_fault[1] */ 183 } en_trig_input_pdma0_tr_t; 184 185 /* Trigger Input Group 1 - P-DMA1 Request Assignments */ 186 typedef enum 187 { 188 TRIG_IN_MUX_1_PDMA0_TR_OUT0 = 0x00000101u, /* cpuss.dw0_tr_out[0] */ 189 TRIG_IN_MUX_1_PDMA0_TR_OUT1 = 0x00000102u, /* cpuss.dw0_tr_out[1] */ 190 TRIG_IN_MUX_1_PDMA0_TR_OUT2 = 0x00000103u, /* cpuss.dw0_tr_out[2] */ 191 TRIG_IN_MUX_1_PDMA0_TR_OUT3 = 0x00000104u, /* cpuss.dw0_tr_out[3] */ 192 TRIG_IN_MUX_1_PDMA0_TR_OUT4 = 0x00000105u, /* cpuss.dw0_tr_out[4] */ 193 TRIG_IN_MUX_1_PDMA0_TR_OUT5 = 0x00000106u, /* cpuss.dw0_tr_out[5] */ 194 TRIG_IN_MUX_1_PDMA0_TR_OUT6 = 0x00000107u, /* cpuss.dw0_tr_out[6] */ 195 TRIG_IN_MUX_1_PDMA0_TR_OUT7 = 0x00000108u, /* cpuss.dw0_tr_out[7] */ 196 TRIG_IN_MUX_1_PDMA1_TR_OUT0 = 0x00000109u, /* cpuss.dw1_tr_out[0] */ 197 TRIG_IN_MUX_1_PDMA1_TR_OUT1 = 0x0000010Au, /* cpuss.dw1_tr_out[1] */ 198 TRIG_IN_MUX_1_PDMA1_TR_OUT2 = 0x0000010Bu, /* cpuss.dw1_tr_out[2] */ 199 TRIG_IN_MUX_1_PDMA1_TR_OUT3 = 0x0000010Cu, /* cpuss.dw1_tr_out[3] */ 200 TRIG_IN_MUX_1_PDMA1_TR_OUT4 = 0x0000010Du, /* cpuss.dw1_tr_out[4] */ 201 TRIG_IN_MUX_1_PDMA1_TR_OUT5 = 0x0000010Eu, /* cpuss.dw1_tr_out[5] */ 202 TRIG_IN_MUX_1_PDMA1_TR_OUT6 = 0x0000010Fu, /* cpuss.dw1_tr_out[6] */ 203 TRIG_IN_MUX_1_PDMA1_TR_OUT7 = 0x00000110u, /* cpuss.dw1_tr_out[7] */ 204 TRIG_IN_MUX_1_TCPWM0_TR_OVERFLOW4 = 0x00000111u, /* tcpwm[0].tr_overflow[4] */ 205 TRIG_IN_MUX_1_TCPWM0_TR_COMPARE_MATCH4 = 0x00000112u, /* tcpwm[0].tr_compare_match[4] */ 206 TRIG_IN_MUX_1_TCPWM0_TR_UNDERFLOW4 = 0x00000113u, /* tcpwm[0].tr_underflow[4] */ 207 TRIG_IN_MUX_1_TCPWM0_TR_OVERFLOW5 = 0x00000114u, /* tcpwm[0].tr_overflow[5] */ 208 TRIG_IN_MUX_1_TCPWM0_TR_COMPARE_MATCH5 = 0x00000115u, /* tcpwm[0].tr_compare_match[5] */ 209 TRIG_IN_MUX_1_TCPWM0_TR_UNDERFLOW5 = 0x00000116u, /* tcpwm[0].tr_underflow[5] */ 210 TRIG_IN_MUX_1_TCPWM0_TR_OVERFLOW6 = 0x00000117u, /* tcpwm[0].tr_overflow[6] */ 211 TRIG_IN_MUX_1_TCPWM0_TR_COMPARE_MATCH6 = 0x00000118u, /* tcpwm[0].tr_compare_match[6] */ 212 TRIG_IN_MUX_1_TCPWM0_TR_UNDERFLOW6 = 0x00000119u, /* tcpwm[0].tr_underflow[6] */ 213 TRIG_IN_MUX_1_TCPWM0_TR_OVERFLOW7 = 0x0000011Au, /* tcpwm[0].tr_overflow[7] */ 214 TRIG_IN_MUX_1_TCPWM0_TR_COMPARE_MATCH7 = 0x0000011Bu, /* tcpwm[0].tr_compare_match[7] */ 215 TRIG_IN_MUX_1_TCPWM0_TR_UNDERFLOW7 = 0x0000011Cu, /* tcpwm[0].tr_underflow[7] */ 216 TRIG_IN_MUX_1_TCPWM1_TR_OVERFLOW12 = 0x0000011Du, /* tcpwm[1].tr_overflow[12] */ 217 TRIG_IN_MUX_1_TCPWM1_TR_COMPARE_MATCH12 = 0x0000011Eu, /* tcpwm[1].tr_compare_match[12] */ 218 TRIG_IN_MUX_1_TCPWM1_TR_UNDERFLOW12 = 0x0000011Fu, /* tcpwm[1].tr_underflow[12] */ 219 TRIG_IN_MUX_1_TCPWM1_TR_OVERFLOW13 = 0x00000120u, /* tcpwm[1].tr_overflow[13] */ 220 TRIG_IN_MUX_1_TCPWM1_TR_COMPARE_MATCH13 = 0x00000121u, /* tcpwm[1].tr_compare_match[13] */ 221 TRIG_IN_MUX_1_TCPWM1_TR_UNDERFLOW13 = 0x00000122u, /* tcpwm[1].tr_underflow[13] */ 222 TRIG_IN_MUX_1_TCPWM1_TR_OVERFLOW14 = 0x00000123u, /* tcpwm[1].tr_overflow[14] */ 223 TRIG_IN_MUX_1_TCPWM1_TR_COMPARE_MATCH14 = 0x00000124u, /* tcpwm[1].tr_compare_match[14] */ 224 TRIG_IN_MUX_1_TCPWM1_TR_UNDERFLOW14 = 0x00000125u, /* tcpwm[1].tr_underflow[14] */ 225 TRIG_IN_MUX_1_TCPWM1_TR_OVERFLOW15 = 0x00000126u, /* tcpwm[1].tr_overflow[15] */ 226 TRIG_IN_MUX_1_TCPWM1_TR_COMPARE_MATCH15 = 0x00000127u, /* tcpwm[1].tr_compare_match[15] */ 227 TRIG_IN_MUX_1_TCPWM1_TR_UNDERFLOW15 = 0x00000128u, /* tcpwm[1].tr_underflow[15] */ 228 TRIG_IN_MUX_1_TCPWM1_TR_OVERFLOW16 = 0x00000129u, /* tcpwm[1].tr_overflow[16] */ 229 TRIG_IN_MUX_1_TCPWM1_TR_COMPARE_MATCH16 = 0x0000012Au, /* tcpwm[1].tr_compare_match[16] */ 230 TRIG_IN_MUX_1_TCPWM1_TR_UNDERFLOW16 = 0x0000012Bu, /* tcpwm[1].tr_underflow[16] */ 231 TRIG_IN_MUX_1_TCPWM1_TR_OVERFLOW17 = 0x0000012Cu, /* tcpwm[1].tr_overflow[17] */ 232 TRIG_IN_MUX_1_TCPWM1_TR_COMPARE_MATCH17 = 0x0000012Du, /* tcpwm[1].tr_compare_match[17] */ 233 TRIG_IN_MUX_1_TCPWM1_TR_UNDERFLOW17 = 0x0000012Eu, /* tcpwm[1].tr_underflow[17] */ 234 TRIG_IN_MUX_1_TCPWM1_TR_OVERFLOW18 = 0x0000012Fu, /* tcpwm[1].tr_overflow[18] */ 235 TRIG_IN_MUX_1_TCPWM1_TR_COMPARE_MATCH18 = 0x00000130u, /* tcpwm[1].tr_compare_match[18] */ 236 TRIG_IN_MUX_1_TCPWM1_TR_UNDERFLOW18 = 0x00000131u, /* tcpwm[1].tr_underflow[18] */ 237 TRIG_IN_MUX_1_TCPWM1_TR_OVERFLOW19 = 0x00000132u, /* tcpwm[1].tr_overflow[19] */ 238 TRIG_IN_MUX_1_TCPWM1_TR_COMPARE_MATCH19 = 0x00000133u, /* tcpwm[1].tr_compare_match[19] */ 239 TRIG_IN_MUX_1_TCPWM1_TR_UNDERFLOW19 = 0x00000134u, /* tcpwm[1].tr_underflow[19] */ 240 TRIG_IN_MUX_1_TCPWM1_TR_OVERFLOW20 = 0x00000135u, /* tcpwm[1].tr_overflow[20] */ 241 TRIG_IN_MUX_1_TCPWM1_TR_COMPARE_MATCH20 = 0x00000136u, /* tcpwm[1].tr_compare_match[20] */ 242 TRIG_IN_MUX_1_TCPWM1_TR_UNDERFLOW20 = 0x00000137u, /* tcpwm[1].tr_underflow[20] */ 243 TRIG_IN_MUX_1_TCPWM1_TR_OVERFLOW21 = 0x00000138u, /* tcpwm[1].tr_overflow[21] */ 244 TRIG_IN_MUX_1_TCPWM1_TR_COMPARE_MATCH21 = 0x00000139u, /* tcpwm[1].tr_compare_match[21] */ 245 TRIG_IN_MUX_1_TCPWM1_TR_UNDERFLOW21 = 0x0000013Au, /* tcpwm[1].tr_underflow[21] */ 246 TRIG_IN_MUX_1_TCPWM1_TR_OVERFLOW22 = 0x0000013Bu, /* tcpwm[1].tr_overflow[22] */ 247 TRIG_IN_MUX_1_TCPWM1_TR_COMPARE_MATCH22 = 0x0000013Cu, /* tcpwm[1].tr_compare_match[22] */ 248 TRIG_IN_MUX_1_TCPWM1_TR_UNDERFLOW22 = 0x0000013Du, /* tcpwm[1].tr_underflow[22] */ 249 TRIG_IN_MUX_1_TCPWM1_TR_OVERFLOW23 = 0x0000013Eu, /* tcpwm[1].tr_overflow[23] */ 250 TRIG_IN_MUX_1_TCPWM1_TR_COMPARE_MATCH23 = 0x0000013Fu, /* tcpwm[1].tr_compare_match[23] */ 251 TRIG_IN_MUX_1_TCPWM1_TR_UNDERFLOW23 = 0x00000140u, /* tcpwm[1].tr_underflow[23] */ 252 TRIG_IN_MUX_1_MDMA_TR_OUT0 = 0x00000141u, /* cpuss.dmac_tr_out[0] */ 253 TRIG_IN_MUX_1_MDMA_TR_OUT1 = 0x00000142u, /* cpuss.dmac_tr_out[1] */ 254 TRIG_IN_MUX_1_MDMA_TR_OUT2 = 0x00000143u, /* cpuss.dmac_tr_out[2] */ 255 TRIG_IN_MUX_1_MDMA_TR_OUT3 = 0x00000144u, /* cpuss.dmac_tr_out[3] */ 256 TRIG_IN_MUX_1_CSD_DONE = 0x00000145u, /* csd.tr_adc_done */ 257 TRIG_IN_MUX_1_HSIOM_TR_OUT14 = 0x00000146u, /* peri.tr_io_input[14] */ 258 TRIG_IN_MUX_1_HSIOM_TR_OUT15 = 0x00000147u, /* peri.tr_io_input[15] */ 259 TRIG_IN_MUX_1_HSIOM_TR_OUT16 = 0x00000148u, /* peri.tr_io_input[16] */ 260 TRIG_IN_MUX_1_HSIOM_TR_OUT17 = 0x00000149u, /* peri.tr_io_input[17] */ 261 TRIG_IN_MUX_1_HSIOM_TR_OUT18 = 0x0000014Au, /* peri.tr_io_input[18] */ 262 TRIG_IN_MUX_1_HSIOM_TR_OUT19 = 0x0000014Bu, /* peri.tr_io_input[19] */ 263 TRIG_IN_MUX_1_HSIOM_TR_OUT20 = 0x0000014Cu, /* peri.tr_io_input[20] */ 264 TRIG_IN_MUX_1_HSIOM_TR_OUT21 = 0x0000014Du, /* peri.tr_io_input[21] */ 265 TRIG_IN_MUX_1_HSIOM_TR_OUT22 = 0x0000014Eu, /* peri.tr_io_input[22] */ 266 TRIG_IN_MUX_1_HSIOM_TR_OUT23 = 0x0000014Fu, /* peri.tr_io_input[23] */ 267 TRIG_IN_MUX_1_HSIOM_TR_OUT24 = 0x00000150u, /* peri.tr_io_input[24] */ 268 TRIG_IN_MUX_1_HSIOM_TR_OUT25 = 0x00000151u, /* peri.tr_io_input[25] */ 269 TRIG_IN_MUX_1_HSIOM_TR_OUT26 = 0x00000152u, /* peri.tr_io_input[26] */ 270 TRIG_IN_MUX_1_HSIOM_TR_OUT27 = 0x00000153u, /* peri.tr_io_input[27] */ 271 TRIG_IN_MUX_1_LPCOMP_DSI_COMP0 = 0x00000154u, /* lpcomp.dsi_comp0 */ 272 TRIG_IN_MUX_1_LPCOMP_DSI_COMP1 = 0x00000155u /* lpcomp.dsi_comp1 */ 273 } en_trig_input_pdma1_tr_t; 274 275 /* Trigger Input Group 2 - TCPWM0 trigger multiplexer */ 276 typedef enum 277 { 278 TRIG_IN_MUX_2_PDMA0_TR_OUT0 = 0x00000201u, /* cpuss.dw0_tr_out[0] */ 279 TRIG_IN_MUX_2_PDMA0_TR_OUT1 = 0x00000202u, /* cpuss.dw0_tr_out[1] */ 280 TRIG_IN_MUX_2_PDMA0_TR_OUT2 = 0x00000203u, /* cpuss.dw0_tr_out[2] */ 281 TRIG_IN_MUX_2_PDMA0_TR_OUT3 = 0x00000204u, /* cpuss.dw0_tr_out[3] */ 282 TRIG_IN_MUX_2_PDMA0_TR_OUT4 = 0x00000205u, /* cpuss.dw0_tr_out[4] */ 283 TRIG_IN_MUX_2_PDMA0_TR_OUT5 = 0x00000206u, /* cpuss.dw0_tr_out[5] */ 284 TRIG_IN_MUX_2_PDMA0_TR_OUT6 = 0x00000207u, /* cpuss.dw0_tr_out[6] */ 285 TRIG_IN_MUX_2_PDMA0_TR_OUT7 = 0x00000208u, /* cpuss.dw0_tr_out[7] */ 286 TRIG_IN_MUX_2_TCPWM0_TR_OVERFLOW0 = 0x00000209u, /* tcpwm[0].tr_overflow[0] */ 287 TRIG_IN_MUX_2_TCPWM0_TR_COMPARE_MATCH0 = 0x0000020Au, /* tcpwm[0].tr_compare_match[0] */ 288 TRIG_IN_MUX_2_TCPWM0_TR_UNDERFLOW0 = 0x0000020Bu, /* tcpwm[0].tr_underflow[0] */ 289 TRIG_IN_MUX_2_TCPWM0_TR_OVERFLOW1 = 0x0000020Cu, /* tcpwm[0].tr_overflow[1] */ 290 TRIG_IN_MUX_2_TCPWM0_TR_COMPARE_MATCH1 = 0x0000020Du, /* tcpwm[0].tr_compare_match[1] */ 291 TRIG_IN_MUX_2_TCPWM0_TR_UNDERFLOW1 = 0x0000020Eu, /* tcpwm[0].tr_underflow[1] */ 292 TRIG_IN_MUX_2_TCPWM0_TR_OVERFLOW2 = 0x0000020Fu, /* tcpwm[0].tr_overflow[2] */ 293 TRIG_IN_MUX_2_TCPWM0_TR_COMPARE_MATCH2 = 0x00000210u, /* tcpwm[0].tr_compare_match[2] */ 294 TRIG_IN_MUX_2_TCPWM0_TR_UNDERFLOW2 = 0x00000211u, /* tcpwm[0].tr_underflow[2] */ 295 TRIG_IN_MUX_2_TCPWM0_TR_OVERFLOW3 = 0x00000212u, /* tcpwm[0].tr_overflow[3] */ 296 TRIG_IN_MUX_2_TCPWM0_TR_COMPARE_MATCH3 = 0x00000213u, /* tcpwm[0].tr_compare_match[3] */ 297 TRIG_IN_MUX_2_TCPWM0_TR_UNDERFLOW3 = 0x00000214u, /* tcpwm[0].tr_underflow[3] */ 298 TRIG_IN_MUX_2_TCPWM0_TR_OVERFLOW4 = 0x00000215u, /* tcpwm[0].tr_overflow[4] */ 299 TRIG_IN_MUX_2_TCPWM0_TR_COMPARE_MATCH4 = 0x00000216u, /* tcpwm[0].tr_compare_match[4] */ 300 TRIG_IN_MUX_2_TCPWM0_TR_UNDERFLOW4 = 0x00000217u, /* tcpwm[0].tr_underflow[4] */ 301 TRIG_IN_MUX_2_TCPWM0_TR_OVERFLOW5 = 0x00000218u, /* tcpwm[0].tr_overflow[5] */ 302 TRIG_IN_MUX_2_TCPWM0_TR_COMPARE_MATCH5 = 0x00000219u, /* tcpwm[0].tr_compare_match[5] */ 303 TRIG_IN_MUX_2_TCPWM0_TR_UNDERFLOW5 = 0x0000021Au, /* tcpwm[0].tr_underflow[5] */ 304 TRIG_IN_MUX_2_TCPWM0_TR_OVERFLOW6 = 0x0000021Bu, /* tcpwm[0].tr_overflow[6] */ 305 TRIG_IN_MUX_2_TCPWM0_TR_COMPARE_MATCH6 = 0x0000021Cu, /* tcpwm[0].tr_compare_match[6] */ 306 TRIG_IN_MUX_2_TCPWM0_TR_UNDERFLOW6 = 0x0000021Du, /* tcpwm[0].tr_underflow[6] */ 307 TRIG_IN_MUX_2_TCPWM0_TR_OVERFLOW7 = 0x0000021Eu, /* tcpwm[0].tr_overflow[7] */ 308 TRIG_IN_MUX_2_TCPWM0_TR_COMPARE_MATCH7 = 0x0000021Fu, /* tcpwm[0].tr_compare_match[7] */ 309 TRIG_IN_MUX_2_TCPWM0_TR_UNDERFLOW7 = 0x00000220u, /* tcpwm[0].tr_underflow[7] */ 310 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW0 = 0x00000221u, /* tcpwm[1].tr_overflow[0] */ 311 TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH0 = 0x00000222u, /* tcpwm[1].tr_compare_match[0] */ 312 TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW0 = 0x00000223u, /* tcpwm[1].tr_underflow[0] */ 313 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW1 = 0x00000224u, /* tcpwm[1].tr_overflow[1] */ 314 TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH1 = 0x00000225u, /* tcpwm[1].tr_compare_match[1] */ 315 TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW1 = 0x00000226u, /* tcpwm[1].tr_underflow[1] */ 316 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW2 = 0x00000227u, /* tcpwm[1].tr_overflow[2] */ 317 TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH2 = 0x00000228u, /* tcpwm[1].tr_compare_match[2] */ 318 TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW2 = 0x00000229u, /* tcpwm[1].tr_underflow[2] */ 319 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW3 = 0x0000022Au, /* tcpwm[1].tr_overflow[3] */ 320 TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH3 = 0x0000022Bu, /* tcpwm[1].tr_compare_match[3] */ 321 TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW3 = 0x0000022Cu, /* tcpwm[1].tr_underflow[3] */ 322 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW4 = 0x0000022Du, /* tcpwm[1].tr_overflow[4] */ 323 TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH4 = 0x0000022Eu, /* tcpwm[1].tr_compare_match[4] */ 324 TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW4 = 0x0000022Fu, /* tcpwm[1].tr_underflow[4] */ 325 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW5 = 0x00000230u, /* tcpwm[1].tr_overflow[5] */ 326 TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH5 = 0x00000231u, /* tcpwm[1].tr_compare_match[5] */ 327 TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW5 = 0x00000232u, /* tcpwm[1].tr_underflow[5] */ 328 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW6 = 0x00000233u, /* tcpwm[1].tr_overflow[6] */ 329 TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH6 = 0x00000234u, /* tcpwm[1].tr_compare_match[6] */ 330 TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW6 = 0x00000235u, /* tcpwm[1].tr_underflow[6] */ 331 TRIG_IN_MUX_2_TCPWM1_TR_OVERFLOW7 = 0x00000236u, /* tcpwm[1].tr_overflow[7] */ 332 TRIG_IN_MUX_2_TCPWM1_TR_COMPARE_MATCH7 = 0x00000237u, /* tcpwm[1].tr_compare_match[7] */ 333 TRIG_IN_MUX_2_TCPWM1_TR_UNDERFLOW7 = 0x00000238u, /* tcpwm[1].tr_underflow[7] */ 334 TRIG_IN_MUX_2_MDMA_TR_OUT0 = 0x00000239u, /* cpuss.dmac_tr_out[0] */ 335 TRIG_IN_MUX_2_MDMA_TR_OUT1 = 0x0000023Au, /* cpuss.dmac_tr_out[1] */ 336 TRIG_IN_MUX_2_MDMA_TR_OUT2 = 0x0000023Bu, /* cpuss.dmac_tr_out[2] */ 337 TRIG_IN_MUX_2_MDMA_TR_OUT3 = 0x0000023Cu, /* cpuss.dmac_tr_out[3] */ 338 TRIG_IN_MUX_2_SCB_I2C_SCL0 = 0x0000023Du, /* scb[0].tr_i2c_scl_filtered */ 339 TRIG_IN_MUX_2_SCB_TX0 = 0x0000023Eu, /* scb[0].tr_tx_req */ 340 TRIG_IN_MUX_2_SCB_RX0 = 0x0000023Fu, /* scb[0].tr_rx_req */ 341 TRIG_IN_MUX_2_SCB_I2C_SCL1 = 0x00000240u, /* scb[1].tr_i2c_scl_filtered */ 342 TRIG_IN_MUX_2_SCB_TX1 = 0x00000241u, /* scb[1].tr_tx_req */ 343 TRIG_IN_MUX_2_SCB_RX1 = 0x00000242u, /* scb[1].tr_rx_req */ 344 TRIG_IN_MUX_2_SCB_I2C_SCL2 = 0x00000243u, /* scb[2].tr_i2c_scl_filtered */ 345 TRIG_IN_MUX_2_SCB_TX2 = 0x00000244u, /* scb[2].tr_tx_req */ 346 TRIG_IN_MUX_2_SCB_RX2 = 0x00000245u, /* scb[2].tr_rx_req */ 347 TRIG_IN_MUX_2_SCB_I2C_SCL3 = 0x00000246u, /* scb[3].tr_i2c_scl_filtered */ 348 TRIG_IN_MUX_2_SCB_TX3 = 0x00000247u, /* scb[3].tr_tx_req */ 349 TRIG_IN_MUX_2_SCB_RX3 = 0x00000248u, /* scb[3].tr_rx_req */ 350 TRIG_IN_MUX_2_SCB_I2C_SCL4 = 0x00000249u, /* scb[4].tr_i2c_scl_filtered */ 351 TRIG_IN_MUX_2_SCB_TX4 = 0x0000024Au, /* scb[4].tr_tx_req */ 352 TRIG_IN_MUX_2_SCB_RX4 = 0x0000024Bu, /* scb[4].tr_rx_req */ 353 TRIG_IN_MUX_2_SCB_I2C_SCL5 = 0x0000024Cu, /* scb[5].tr_i2c_scl_filtered */ 354 TRIG_IN_MUX_2_SCB_TX5 = 0x0000024Du, /* scb[5].tr_tx_req */ 355 TRIG_IN_MUX_2_SCB_RX5 = 0x0000024Eu, /* scb[5].tr_rx_req */ 356 TRIG_IN_MUX_2_SCB_I2C_SCL6 = 0x0000024Fu, /* scb[6].tr_i2c_scl_filtered */ 357 TRIG_IN_MUX_2_SCB_TX6 = 0x00000250u, /* scb[6].tr_tx_req */ 358 TRIG_IN_MUX_2_SCB_RX6 = 0x00000251u, /* scb[6].tr_rx_req */ 359 TRIG_IN_MUX_2_SCB_I2C_SCL7 = 0x00000252u, /* scb[7].tr_i2c_scl_filtered */ 360 TRIG_IN_MUX_2_SCB_TX7 = 0x00000253u, /* scb[7].tr_tx_req */ 361 TRIG_IN_MUX_2_SCB_RX7 = 0x00000254u, /* scb[7].tr_rx_req */ 362 TRIG_IN_MUX_2_SCB_I2C_SCL8 = 0x00000255u, /* scb[8].tr_i2c_scl_filtered */ 363 TRIG_IN_MUX_2_SCB_TX8 = 0x00000256u, /* scb[8].tr_tx_req */ 364 TRIG_IN_MUX_2_SCB_RX8 = 0x00000257u, /* scb[8].tr_rx_req */ 365 TRIG_IN_MUX_2_SCB_I2C_SCL9 = 0x00000258u, /* scb[9].tr_i2c_scl_filtered */ 366 TRIG_IN_MUX_2_SCB_TX9 = 0x00000259u, /* scb[9].tr_tx_req */ 367 TRIG_IN_MUX_2_SCB_RX9 = 0x0000025Au, /* scb[9].tr_rx_req */ 368 TRIG_IN_MUX_2_SCB_I2C_SCL10 = 0x0000025Bu, /* scb[10].tr_i2c_scl_filtered */ 369 TRIG_IN_MUX_2_SCB_TX10 = 0x0000025Cu, /* scb[10].tr_tx_req */ 370 TRIG_IN_MUX_2_SCB_RX10 = 0x0000025Du, /* scb[10].tr_rx_req */ 371 TRIG_IN_MUX_2_SCB_I2C_SCL11 = 0x0000025Eu, /* scb[11].tr_i2c_scl_filtered */ 372 TRIG_IN_MUX_2_SCB_TX11 = 0x0000025Fu, /* scb[11].tr_tx_req */ 373 TRIG_IN_MUX_2_SCB_RX11 = 0x00000260u, /* scb[11].tr_rx_req */ 374 TRIG_IN_MUX_2_SCB_I2C_SCL12 = 0x00000261u, /* scb[12].tr_i2c_scl_filtered */ 375 TRIG_IN_MUX_2_SCB_TX12 = 0x00000262u, /* scb[12].tr_tx_req */ 376 TRIG_IN_MUX_2_SCB_RX12 = 0x00000263u, /* scb[12].tr_rx_req */ 377 TRIG_IN_MUX_2_SMIF_TX = 0x00000264u, /* smif.tr_tx_req */ 378 TRIG_IN_MUX_2_SMIF_RX = 0x00000265u, /* smif.tr_rx_req */ 379 TRIG_IN_MUX_2_USB_DMA0 = 0x00000266u, /* usb.dma_req[0] */ 380 TRIG_IN_MUX_2_USB_DMA1 = 0x00000267u, /* usb.dma_req[1] */ 381 TRIG_IN_MUX_2_USB_DMA2 = 0x00000268u, /* usb.dma_req[2] */ 382 TRIG_IN_MUX_2_USB_DMA3 = 0x00000269u, /* usb.dma_req[3] */ 383 TRIG_IN_MUX_2_USB_DMA4 = 0x0000026Au, /* usb.dma_req[4] */ 384 TRIG_IN_MUX_2_USB_DMA5 = 0x0000026Bu, /* usb.dma_req[5] */ 385 TRIG_IN_MUX_2_USB_DMA6 = 0x0000026Cu, /* usb.dma_req[6] */ 386 TRIG_IN_MUX_2_USB_DMA7 = 0x0000026Du, /* usb.dma_req[7] */ 387 TRIG_IN_MUX_2_I2S_TX0 = 0x0000026Eu, /* audioss[0].tr_i2s_tx_req */ 388 TRIG_IN_MUX_2_I2S_RX0 = 0x0000026Fu, /* audioss[0].tr_i2s_rx_req */ 389 TRIG_IN_MUX_2_PDM_RX0 = 0x00000270u, /* audioss[0].tr_pdm_rx_req */ 390 TRIG_IN_MUX_2_I2S_TX1 = 0x00000271u, /* audioss[1].tr_i2s_tx_req */ 391 TRIG_IN_MUX_2_I2S_RX1 = 0x00000272u, /* audioss[1].tr_i2s_rx_req */ 392 TRIG_IN_MUX_2_PASS_SAR_DONE = 0x00000273u, /* pass.tr_sar_out */ 393 TRIG_IN_MUX_2_CSD_SENSE = 0x00000274u, /* csd.dsi_sense_out */ 394 TRIG_IN_MUX_2_HSIOM_TR_OUT0 = 0x00000275u, /* peri.tr_io_input[0] */ 395 TRIG_IN_MUX_2_HSIOM_TR_OUT1 = 0x00000276u, /* peri.tr_io_input[1] */ 396 TRIG_IN_MUX_2_HSIOM_TR_OUT2 = 0x00000277u, /* peri.tr_io_input[2] */ 397 TRIG_IN_MUX_2_HSIOM_TR_OUT3 = 0x00000278u, /* peri.tr_io_input[3] */ 398 TRIG_IN_MUX_2_HSIOM_TR_OUT4 = 0x00000279u, /* peri.tr_io_input[4] */ 399 TRIG_IN_MUX_2_HSIOM_TR_OUT5 = 0x0000027Au, /* peri.tr_io_input[5] */ 400 TRIG_IN_MUX_2_HSIOM_TR_OUT6 = 0x0000027Bu, /* peri.tr_io_input[6] */ 401 TRIG_IN_MUX_2_HSIOM_TR_OUT7 = 0x0000027Cu, /* peri.tr_io_input[7] */ 402 TRIG_IN_MUX_2_HSIOM_TR_OUT8 = 0x0000027Du, /* peri.tr_io_input[8] */ 403 TRIG_IN_MUX_2_HSIOM_TR_OUT9 = 0x0000027Eu, /* peri.tr_io_input[9] */ 404 TRIG_IN_MUX_2_HSIOM_TR_OUT10 = 0x0000027Fu, /* peri.tr_io_input[10] */ 405 TRIG_IN_MUX_2_HSIOM_TR_OUT11 = 0x00000280u, /* peri.tr_io_input[11] */ 406 TRIG_IN_MUX_2_HSIOM_TR_OUT12 = 0x00000281u, /* peri.tr_io_input[12] */ 407 TRIG_IN_MUX_2_HSIOM_TR_OUT13 = 0x00000282u, /* peri.tr_io_input[13] */ 408 TRIG_IN_MUX_2_CTI_TR_OUT0 = 0x00000283u, /* cpuss.cti_tr_out[0] */ 409 TRIG_IN_MUX_2_CTI_TR_OUT1 = 0x00000284u, /* cpuss.cti_tr_out[1] */ 410 TRIG_IN_MUX_2_LPCOMP_DSI_COMP0 = 0x00000285u, /* lpcomp.dsi_comp0 */ 411 TRIG_IN_MUX_2_LPCOMP_DSI_COMP1 = 0x00000286u /* lpcomp.dsi_comp1 */ 412 } en_trig_input_tcpwm0_t; 413 414 /* Trigger Input Group 3 - TCPWM1 trigger multiplexer */ 415 typedef enum 416 { 417 TRIG_IN_MUX_3_PDMA1_TR_OUT0 = 0x00000301u, /* cpuss.dw1_tr_out[0] */ 418 TRIG_IN_MUX_3_PDMA1_TR_OUT1 = 0x00000302u, /* cpuss.dw1_tr_out[1] */ 419 TRIG_IN_MUX_3_PDMA1_TR_OUT2 = 0x00000303u, /* cpuss.dw1_tr_out[2] */ 420 TRIG_IN_MUX_3_PDMA1_TR_OUT3 = 0x00000304u, /* cpuss.dw1_tr_out[3] */ 421 TRIG_IN_MUX_3_PDMA1_TR_OUT4 = 0x00000305u, /* cpuss.dw1_tr_out[4] */ 422 TRIG_IN_MUX_3_PDMA1_TR_OUT5 = 0x00000306u, /* cpuss.dw1_tr_out[5] */ 423 TRIG_IN_MUX_3_PDMA1_TR_OUT6 = 0x00000307u, /* cpuss.dw1_tr_out[6] */ 424 TRIG_IN_MUX_3_PDMA1_TR_OUT7 = 0x00000308u, /* cpuss.dw1_tr_out[7] */ 425 TRIG_IN_MUX_3_TCPWM0_TR_OVERFLOW0 = 0x00000309u, /* tcpwm[0].tr_overflow[0] */ 426 TRIG_IN_MUX_3_TCPWM0_TR_COMPARE_MATCH0 = 0x0000030Au, /* tcpwm[0].tr_compare_match[0] */ 427 TRIG_IN_MUX_3_TCPWM0_TR_UNDERFLOW0 = 0x0000030Bu, /* tcpwm[0].tr_underflow[0] */ 428 TRIG_IN_MUX_3_TCPWM0_TR_OVERFLOW1 = 0x0000030Cu, /* tcpwm[0].tr_overflow[1] */ 429 TRIG_IN_MUX_3_TCPWM0_TR_COMPARE_MATCH1 = 0x0000030Du, /* tcpwm[0].tr_compare_match[1] */ 430 TRIG_IN_MUX_3_TCPWM0_TR_UNDERFLOW1 = 0x0000030Eu, /* tcpwm[0].tr_underflow[1] */ 431 TRIG_IN_MUX_3_TCPWM0_TR_OVERFLOW2 = 0x0000030Fu, /* tcpwm[0].tr_overflow[2] */ 432 TRIG_IN_MUX_3_TCPWM0_TR_COMPARE_MATCH2 = 0x00000310u, /* tcpwm[0].tr_compare_match[2] */ 433 TRIG_IN_MUX_3_TCPWM0_TR_UNDERFLOW2 = 0x00000311u, /* tcpwm[0].tr_underflow[2] */ 434 TRIG_IN_MUX_3_TCPWM0_TR_OVERFLOW3 = 0x00000312u, /* tcpwm[0].tr_overflow[3] */ 435 TRIG_IN_MUX_3_TCPWM0_TR_COMPARE_MATCH3 = 0x00000313u, /* tcpwm[0].tr_compare_match[3] */ 436 TRIG_IN_MUX_3_TCPWM0_TR_UNDERFLOW3 = 0x00000314u, /* tcpwm[0].tr_underflow[3] */ 437 TRIG_IN_MUX_3_TCPWM0_TR_OVERFLOW4 = 0x00000315u, /* tcpwm[0].tr_overflow[4] */ 438 TRIG_IN_MUX_3_TCPWM0_TR_COMPARE_MATCH4 = 0x00000316u, /* tcpwm[0].tr_compare_match[4] */ 439 TRIG_IN_MUX_3_TCPWM0_TR_UNDERFLOW4 = 0x00000317u, /* tcpwm[0].tr_underflow[4] */ 440 TRIG_IN_MUX_3_TCPWM0_TR_OVERFLOW5 = 0x00000318u, /* tcpwm[0].tr_overflow[5] */ 441 TRIG_IN_MUX_3_TCPWM0_TR_COMPARE_MATCH5 = 0x00000319u, /* tcpwm[0].tr_compare_match[5] */ 442 TRIG_IN_MUX_3_TCPWM0_TR_UNDERFLOW5 = 0x0000031Au, /* tcpwm[0].tr_underflow[5] */ 443 TRIG_IN_MUX_3_TCPWM0_TR_OVERFLOW6 = 0x0000031Bu, /* tcpwm[0].tr_overflow[6] */ 444 TRIG_IN_MUX_3_TCPWM0_TR_COMPARE_MATCH6 = 0x0000031Cu, /* tcpwm[0].tr_compare_match[6] */ 445 TRIG_IN_MUX_3_TCPWM0_TR_UNDERFLOW6 = 0x0000031Du, /* tcpwm[0].tr_underflow[6] */ 446 TRIG_IN_MUX_3_TCPWM0_TR_OVERFLOW7 = 0x0000031Eu, /* tcpwm[0].tr_overflow[7] */ 447 TRIG_IN_MUX_3_TCPWM0_TR_COMPARE_MATCH7 = 0x0000031Fu, /* tcpwm[0].tr_compare_match[7] */ 448 TRIG_IN_MUX_3_TCPWM0_TR_UNDERFLOW7 = 0x00000320u, /* tcpwm[0].tr_underflow[7] */ 449 TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW0 = 0x00000321u, /* tcpwm[1].tr_overflow[0] */ 450 TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH0 = 0x00000322u, /* tcpwm[1].tr_compare_match[0] */ 451 TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW0 = 0x00000323u, /* tcpwm[1].tr_underflow[0] */ 452 TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW1 = 0x00000324u, /* tcpwm[1].tr_overflow[1] */ 453 TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH1 = 0x00000325u, /* tcpwm[1].tr_compare_match[1] */ 454 TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW1 = 0x00000326u, /* tcpwm[1].tr_underflow[1] */ 455 TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW2 = 0x00000327u, /* tcpwm[1].tr_overflow[2] */ 456 TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH2 = 0x00000328u, /* tcpwm[1].tr_compare_match[2] */ 457 TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW2 = 0x00000329u, /* tcpwm[1].tr_underflow[2] */ 458 TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW3 = 0x0000032Au, /* tcpwm[1].tr_overflow[3] */ 459 TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH3 = 0x0000032Bu, /* tcpwm[1].tr_compare_match[3] */ 460 TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW3 = 0x0000032Cu, /* tcpwm[1].tr_underflow[3] */ 461 TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW4 = 0x0000032Du, /* tcpwm[1].tr_overflow[4] */ 462 TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH4 = 0x0000032Eu, /* tcpwm[1].tr_compare_match[4] */ 463 TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW4 = 0x0000032Fu, /* tcpwm[1].tr_underflow[4] */ 464 TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW5 = 0x00000330u, /* tcpwm[1].tr_overflow[5] */ 465 TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH5 = 0x00000331u, /* tcpwm[1].tr_compare_match[5] */ 466 TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW5 = 0x00000332u, /* tcpwm[1].tr_underflow[5] */ 467 TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW6 = 0x00000333u, /* tcpwm[1].tr_overflow[6] */ 468 TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH6 = 0x00000334u, /* tcpwm[1].tr_compare_match[6] */ 469 TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW6 = 0x00000335u, /* tcpwm[1].tr_underflow[6] */ 470 TRIG_IN_MUX_3_TCPWM1_TR_OVERFLOW7 = 0x00000336u, /* tcpwm[1].tr_overflow[7] */ 471 TRIG_IN_MUX_3_TCPWM1_TR_COMPARE_MATCH7 = 0x00000337u, /* tcpwm[1].tr_compare_match[7] */ 472 TRIG_IN_MUX_3_TCPWM1_TR_UNDERFLOW7 = 0x00000338u, /* tcpwm[1].tr_underflow[7] */ 473 TRIG_IN_MUX_3_MDMA_TR_OUT0 = 0x00000339u, /* cpuss.dmac_tr_out[0] */ 474 TRIG_IN_MUX_3_MDMA_TR_OUT1 = 0x0000033Au, /* cpuss.dmac_tr_out[1] */ 475 TRIG_IN_MUX_3_MDMA_TR_OUT2 = 0x0000033Bu, /* cpuss.dmac_tr_out[2] */ 476 TRIG_IN_MUX_3_MDMA_TR_OUT3 = 0x0000033Cu, /* cpuss.dmac_tr_out[3] */ 477 TRIG_IN_MUX_3_SCB_I2C_SCL0 = 0x0000033Du, /* scb[0].tr_i2c_scl_filtered */ 478 TRIG_IN_MUX_3_SCB_TX0 = 0x0000033Eu, /* scb[0].tr_tx_req */ 479 TRIG_IN_MUX_3_SCB_RX0 = 0x0000033Fu, /* scb[0].tr_rx_req */ 480 TRIG_IN_MUX_3_SCB_I2C_SCL1 = 0x00000340u, /* scb[1].tr_i2c_scl_filtered */ 481 TRIG_IN_MUX_3_SCB_TX1 = 0x00000341u, /* scb[1].tr_tx_req */ 482 TRIG_IN_MUX_3_SCB_RX1 = 0x00000342u, /* scb[1].tr_rx_req */ 483 TRIG_IN_MUX_3_SCB_I2C_SCL2 = 0x00000343u, /* scb[2].tr_i2c_scl_filtered */ 484 TRIG_IN_MUX_3_SCB_TX2 = 0x00000344u, /* scb[2].tr_tx_req */ 485 TRIG_IN_MUX_3_SCB_RX2 = 0x00000345u, /* scb[2].tr_rx_req */ 486 TRIG_IN_MUX_3_SCB_I2C_SCL3 = 0x00000346u, /* scb[3].tr_i2c_scl_filtered */ 487 TRIG_IN_MUX_3_SCB_TX3 = 0x00000347u, /* scb[3].tr_tx_req */ 488 TRIG_IN_MUX_3_SCB_RX3 = 0x00000348u, /* scb[3].tr_rx_req */ 489 TRIG_IN_MUX_3_SCB_I2C_SCL4 = 0x00000349u, /* scb[4].tr_i2c_scl_filtered */ 490 TRIG_IN_MUX_3_SCB_TX4 = 0x0000034Au, /* scb[4].tr_tx_req */ 491 TRIG_IN_MUX_3_SCB_RX4 = 0x0000034Bu, /* scb[4].tr_rx_req */ 492 TRIG_IN_MUX_3_SCB_I2C_SCL5 = 0x0000034Cu, /* scb[5].tr_i2c_scl_filtered */ 493 TRIG_IN_MUX_3_SCB_TX5 = 0x0000034Du, /* scb[5].tr_tx_req */ 494 TRIG_IN_MUX_3_SCB_RX5 = 0x0000034Eu, /* scb[5].tr_rx_req */ 495 TRIG_IN_MUX_3_SCB_I2C_SCL6 = 0x0000034Fu, /* scb[6].tr_i2c_scl_filtered */ 496 TRIG_IN_MUX_3_SCB_TX6 = 0x00000350u, /* scb[6].tr_tx_req */ 497 TRIG_IN_MUX_3_SCB_RX6 = 0x00000351u, /* scb[6].tr_rx_req */ 498 TRIG_IN_MUX_3_SCB_I2C_SCL7 = 0x00000352u, /* scb[7].tr_i2c_scl_filtered */ 499 TRIG_IN_MUX_3_SCB_TX7 = 0x00000353u, /* scb[7].tr_tx_req */ 500 TRIG_IN_MUX_3_SCB_RX7 = 0x00000354u, /* scb[7].tr_rx_req */ 501 TRIG_IN_MUX_3_SCB_I2C_SCL8 = 0x00000355u, /* scb[8].tr_i2c_scl_filtered */ 502 TRIG_IN_MUX_3_SCB_TX8 = 0x00000356u, /* scb[8].tr_tx_req */ 503 TRIG_IN_MUX_3_SCB_RX8 = 0x00000357u, /* scb[8].tr_rx_req */ 504 TRIG_IN_MUX_3_SCB_I2C_SCL9 = 0x00000358u, /* scb[9].tr_i2c_scl_filtered */ 505 TRIG_IN_MUX_3_SCB_TX9 = 0x00000359u, /* scb[9].tr_tx_req */ 506 TRIG_IN_MUX_3_SCB_RX9 = 0x0000035Au, /* scb[9].tr_rx_req */ 507 TRIG_IN_MUX_3_SCB_I2C_SCL10 = 0x0000035Bu, /* scb[10].tr_i2c_scl_filtered */ 508 TRIG_IN_MUX_3_SCB_TX10 = 0x0000035Cu, /* scb[10].tr_tx_req */ 509 TRIG_IN_MUX_3_SCB_RX10 = 0x0000035Du, /* scb[10].tr_rx_req */ 510 TRIG_IN_MUX_3_SCB_I2C_SCL11 = 0x0000035Eu, /* scb[11].tr_i2c_scl_filtered */ 511 TRIG_IN_MUX_3_SCB_TX11 = 0x0000035Fu, /* scb[11].tr_tx_req */ 512 TRIG_IN_MUX_3_SCB_RX11 = 0x00000360u, /* scb[11].tr_rx_req */ 513 TRIG_IN_MUX_3_SCB_I2C_SCL12 = 0x00000361u, /* scb[12].tr_i2c_scl_filtered */ 514 TRIG_IN_MUX_3_SCB_TX12 = 0x00000362u, /* scb[12].tr_tx_req */ 515 TRIG_IN_MUX_3_SCB_RX12 = 0x00000363u, /* scb[12].tr_rx_req */ 516 TRIG_IN_MUX_3_SMIF_TX = 0x00000364u, /* smif.tr_tx_req */ 517 TRIG_IN_MUX_3_SMIF_RX = 0x00000365u, /* smif.tr_rx_req */ 518 TRIG_IN_MUX_3_USB_DMA0 = 0x00000366u, /* usb.dma_req[0] */ 519 TRIG_IN_MUX_3_USB_DMA1 = 0x00000367u, /* usb.dma_req[1] */ 520 TRIG_IN_MUX_3_USB_DMA2 = 0x00000368u, /* usb.dma_req[2] */ 521 TRIG_IN_MUX_3_USB_DMA3 = 0x00000369u, /* usb.dma_req[3] */ 522 TRIG_IN_MUX_3_USB_DMA4 = 0x0000036Au, /* usb.dma_req[4] */ 523 TRIG_IN_MUX_3_USB_DMA5 = 0x0000036Bu, /* usb.dma_req[5] */ 524 TRIG_IN_MUX_3_USB_DMA6 = 0x0000036Cu, /* usb.dma_req[6] */ 525 TRIG_IN_MUX_3_USB_DMA7 = 0x0000036Du, /* usb.dma_req[7] */ 526 TRIG_IN_MUX_3_I2S_TX0 = 0x0000036Eu, /* audioss[0].tr_i2s_tx_req */ 527 TRIG_IN_MUX_3_I2S_RX0 = 0x0000036Fu, /* audioss[0].tr_i2s_rx_req */ 528 TRIG_IN_MUX_3_PDM_RX0 = 0x00000370u, /* audioss[0].tr_pdm_rx_req */ 529 TRIG_IN_MUX_3_I2S_TX1 = 0x00000371u, /* audioss[1].tr_i2s_tx_req */ 530 TRIG_IN_MUX_3_I2S_RX1 = 0x00000372u, /* audioss[1].tr_i2s_rx_req */ 531 TRIG_IN_MUX_3_PASS_SAR_DONE = 0x00000373u, /* pass.tr_sar_out */ 532 TRIG_IN_MUX_3_CSD_SENSE = 0x00000374u, /* csd.dsi_sense_out */ 533 TRIG_IN_MUX_3_HSIOM_TR_OUT0 = 0x00000375u, /* peri.tr_io_input[14] */ 534 TRIG_IN_MUX_3_HSIOM_TR_OUT1 = 0x00000376u, /* peri.tr_io_input[15] */ 535 TRIG_IN_MUX_3_HSIOM_TR_OUT2 = 0x00000377u, /* peri.tr_io_input[16] */ 536 TRIG_IN_MUX_3_HSIOM_TR_OUT3 = 0x00000378u, /* peri.tr_io_input[17] */ 537 TRIG_IN_MUX_3_HSIOM_TR_OUT4 = 0x00000379u, /* peri.tr_io_input[18] */ 538 TRIG_IN_MUX_3_HSIOM_TR_OUT5 = 0x0000037Au, /* peri.tr_io_input[19] */ 539 TRIG_IN_MUX_3_HSIOM_TR_OUT6 = 0x0000037Bu, /* peri.tr_io_input[20] */ 540 TRIG_IN_MUX_3_HSIOM_TR_OUT7 = 0x0000037Cu, /* peri.tr_io_input[21] */ 541 TRIG_IN_MUX_3_HSIOM_TR_OUT8 = 0x0000037Du, /* peri.tr_io_input[22] */ 542 TRIG_IN_MUX_3_HSIOM_TR_OUT9 = 0x0000037Eu, /* peri.tr_io_input[23] */ 543 TRIG_IN_MUX_3_HSIOM_TR_OUT10 = 0x0000037Fu, /* peri.tr_io_input[24] */ 544 TRIG_IN_MUX_3_HSIOM_TR_OUT11 = 0x00000380u, /* peri.tr_io_input[25] */ 545 TRIG_IN_MUX_3_HSIOM_TR_OUT12 = 0x00000381u, /* peri.tr_io_input[26] */ 546 TRIG_IN_MUX_3_HSIOM_TR_OUT13 = 0x00000382u, /* peri.tr_io_input[27] */ 547 TRIG_IN_MUX_3_FAULT_TR_OUT0 = 0x00000383u, /* cpuss.tr_fault[0] */ 548 TRIG_IN_MUX_3_FAULT_TR_OUT1 = 0x00000384u, /* cpuss.tr_fault[1] */ 549 TRIG_IN_MUX_3_LPCOMP_DSI_COMP0 = 0x00000385u, /* lpcomp.dsi_comp0 */ 550 TRIG_IN_MUX_3_LPCOMP_DSI_COMP1 = 0x00000386u /* lpcomp.dsi_comp1 */ 551 } en_trig_input_tcpwm1_t; 552 553 /* Trigger Input Group 4 - HSIOM trigger multiplexer */ 554 typedef enum 555 { 556 TRIG_IN_MUX_4_PDMA0_TR_OUT0 = 0x00000401u, /* cpuss.dw0_tr_out[0] */ 557 TRIG_IN_MUX_4_PDMA0_TR_OUT1 = 0x00000402u, /* cpuss.dw0_tr_out[1] */ 558 TRIG_IN_MUX_4_PDMA0_TR_OUT2 = 0x00000403u, /* cpuss.dw0_tr_out[2] */ 559 TRIG_IN_MUX_4_PDMA0_TR_OUT3 = 0x00000404u, /* cpuss.dw0_tr_out[3] */ 560 TRIG_IN_MUX_4_PDMA0_TR_OUT4 = 0x00000405u, /* cpuss.dw0_tr_out[4] */ 561 TRIG_IN_MUX_4_PDMA0_TR_OUT5 = 0x00000406u, /* cpuss.dw0_tr_out[5] */ 562 TRIG_IN_MUX_4_PDMA0_TR_OUT6 = 0x00000407u, /* cpuss.dw0_tr_out[6] */ 563 TRIG_IN_MUX_4_PDMA0_TR_OUT7 = 0x00000408u, /* cpuss.dw0_tr_out[7] */ 564 TRIG_IN_MUX_4_PDMA0_TR_OUT8 = 0x00000409u, /* cpuss.dw0_tr_out[8] */ 565 TRIG_IN_MUX_4_PDMA0_TR_OUT9 = 0x0000040Au, /* cpuss.dw0_tr_out[9] */ 566 TRIG_IN_MUX_4_PDMA0_TR_OUT10 = 0x0000040Bu, /* cpuss.dw0_tr_out[10] */ 567 TRIG_IN_MUX_4_PDMA0_TR_OUT11 = 0x0000040Cu, /* cpuss.dw0_tr_out[11] */ 568 TRIG_IN_MUX_4_PDMA0_TR_OUT12 = 0x0000040Du, /* cpuss.dw0_tr_out[12] */ 569 TRIG_IN_MUX_4_PDMA0_TR_OUT13 = 0x0000040Eu, /* cpuss.dw0_tr_out[13] */ 570 TRIG_IN_MUX_4_PDMA0_TR_OUT14 = 0x0000040Fu, /* cpuss.dw0_tr_out[14] */ 571 TRIG_IN_MUX_4_PDMA0_TR_OUT15 = 0x00000410u, /* cpuss.dw0_tr_out[15] */ 572 TRIG_IN_MUX_4_PDMA0_TR_OUT16 = 0x00000411u, /* cpuss.dw0_tr_out[16] */ 573 TRIG_IN_MUX_4_PDMA0_TR_OUT17 = 0x00000412u, /* cpuss.dw0_tr_out[17] */ 574 TRIG_IN_MUX_4_PDMA0_TR_OUT18 = 0x00000413u, /* cpuss.dw0_tr_out[18] */ 575 TRIG_IN_MUX_4_PDMA0_TR_OUT19 = 0x00000414u, /* cpuss.dw0_tr_out[19] */ 576 TRIG_IN_MUX_4_PDMA0_TR_OUT20 = 0x00000415u, /* cpuss.dw0_tr_out[20] */ 577 TRIG_IN_MUX_4_PDMA0_TR_OUT21 = 0x00000416u, /* cpuss.dw0_tr_out[21] */ 578 TRIG_IN_MUX_4_PDMA0_TR_OUT22 = 0x00000417u, /* cpuss.dw0_tr_out[22] */ 579 TRIG_IN_MUX_4_PDMA0_TR_OUT23 = 0x00000418u, /* cpuss.dw0_tr_out[23] */ 580 TRIG_IN_MUX_4_PDMA0_TR_OUT24 = 0x00000419u, /* cpuss.dw0_tr_out[24] */ 581 TRIG_IN_MUX_4_PDMA0_TR_OUT25 = 0x0000041Au, /* cpuss.dw0_tr_out[25] */ 582 TRIG_IN_MUX_4_PDMA0_TR_OUT26 = 0x0000041Bu, /* cpuss.dw0_tr_out[26] */ 583 TRIG_IN_MUX_4_PDMA0_TR_OUT27 = 0x0000041Cu, /* cpuss.dw0_tr_out[27] */ 584 TRIG_IN_MUX_4_PDMA0_TR_OUT28 = 0x0000041Du, /* cpuss.dw0_tr_out[28] */ 585 TRIG_IN_MUX_4_PDMA1_TR_OUT0 = 0x0000041Eu, /* cpuss.dw1_tr_out[0] */ 586 TRIG_IN_MUX_4_PDMA1_TR_OUT1 = 0x0000041Fu, /* cpuss.dw1_tr_out[1] */ 587 TRIG_IN_MUX_4_PDMA1_TR_OUT2 = 0x00000420u, /* cpuss.dw1_tr_out[2] */ 588 TRIG_IN_MUX_4_PDMA1_TR_OUT3 = 0x00000421u, /* cpuss.dw1_tr_out[3] */ 589 TRIG_IN_MUX_4_PDMA1_TR_OUT4 = 0x00000422u, /* cpuss.dw1_tr_out[4] */ 590 TRIG_IN_MUX_4_PDMA1_TR_OUT5 = 0x00000423u, /* cpuss.dw1_tr_out[5] */ 591 TRIG_IN_MUX_4_PDMA1_TR_OUT6 = 0x00000424u, /* cpuss.dw1_tr_out[6] */ 592 TRIG_IN_MUX_4_PDMA1_TR_OUT7 = 0x00000425u, /* cpuss.dw1_tr_out[7] */ 593 TRIG_IN_MUX_4_PDMA1_TR_OUT8 = 0x00000426u, /* cpuss.dw1_tr_out[8] */ 594 TRIG_IN_MUX_4_PDMA1_TR_OUT9 = 0x00000427u, /* cpuss.dw1_tr_out[9] */ 595 TRIG_IN_MUX_4_PDMA1_TR_OUT10 = 0x00000428u, /* cpuss.dw1_tr_out[10] */ 596 TRIG_IN_MUX_4_PDMA1_TR_OUT11 = 0x00000429u, /* cpuss.dw1_tr_out[11] */ 597 TRIG_IN_MUX_4_PDMA1_TR_OUT12 = 0x0000042Au, /* cpuss.dw1_tr_out[12] */ 598 TRIG_IN_MUX_4_PDMA1_TR_OUT13 = 0x0000042Bu, /* cpuss.dw1_tr_out[13] */ 599 TRIG_IN_MUX_4_PDMA1_TR_OUT14 = 0x0000042Cu, /* cpuss.dw1_tr_out[14] */ 600 TRIG_IN_MUX_4_PDMA1_TR_OUT15 = 0x0000042Du, /* cpuss.dw1_tr_out[15] */ 601 TRIG_IN_MUX_4_PDMA1_TR_OUT16 = 0x0000042Eu, /* cpuss.dw1_tr_out[16] */ 602 TRIG_IN_MUX_4_PDMA1_TR_OUT17 = 0x0000042Fu, /* cpuss.dw1_tr_out[17] */ 603 TRIG_IN_MUX_4_PDMA1_TR_OUT18 = 0x00000430u, /* cpuss.dw1_tr_out[18] */ 604 TRIG_IN_MUX_4_PDMA1_TR_OUT19 = 0x00000431u, /* cpuss.dw1_tr_out[19] */ 605 TRIG_IN_MUX_4_PDMA1_TR_OUT20 = 0x00000432u, /* cpuss.dw1_tr_out[20] */ 606 TRIG_IN_MUX_4_PDMA1_TR_OUT21 = 0x00000433u, /* cpuss.dw1_tr_out[21] */ 607 TRIG_IN_MUX_4_PDMA1_TR_OUT22 = 0x00000434u, /* cpuss.dw1_tr_out[22] */ 608 TRIG_IN_MUX_4_PDMA1_TR_OUT23 = 0x00000435u, /* cpuss.dw1_tr_out[23] */ 609 TRIG_IN_MUX_4_PDMA1_TR_OUT24 = 0x00000436u, /* cpuss.dw1_tr_out[24] */ 610 TRIG_IN_MUX_4_PDMA1_TR_OUT25 = 0x00000437u, /* cpuss.dw1_tr_out[25] */ 611 TRIG_IN_MUX_4_PDMA1_TR_OUT26 = 0x00000438u, /* cpuss.dw1_tr_out[26] */ 612 TRIG_IN_MUX_4_PDMA1_TR_OUT27 = 0x00000439u, /* cpuss.dw1_tr_out[27] */ 613 TRIG_IN_MUX_4_PDMA1_TR_OUT28 = 0x0000043Au, /* cpuss.dw1_tr_out[28] */ 614 TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW0 = 0x0000043Bu, /* tcpwm[0].tr_overflow[0] */ 615 TRIG_IN_MUX_4_TCPWM0_TR_COMPARE_MATCH0 = 0x0000043Cu, /* tcpwm[0].tr_compare_match[0] */ 616 TRIG_IN_MUX_4_TCPWM0_TR_UNDERFLOW0 = 0x0000043Du, /* tcpwm[0].tr_underflow[0] */ 617 TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW1 = 0x0000043Eu, /* tcpwm[0].tr_overflow[1] */ 618 TRIG_IN_MUX_4_TCPWM0_TR_COMPARE_MATCH1 = 0x0000043Fu, /* tcpwm[0].tr_compare_match[1] */ 619 TRIG_IN_MUX_4_TCPWM0_TR_UNDERFLOW1 = 0x00000440u, /* tcpwm[0].tr_underflow[1] */ 620 TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW2 = 0x00000441u, /* tcpwm[0].tr_overflow[2] */ 621 TRIG_IN_MUX_4_TCPWM0_TR_COMPARE_MATCH2 = 0x00000442u, /* tcpwm[0].tr_compare_match[2] */ 622 TRIG_IN_MUX_4_TCPWM0_TR_UNDERFLOW2 = 0x00000443u, /* tcpwm[0].tr_underflow[2] */ 623 TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW3 = 0x00000444u, /* tcpwm[0].tr_overflow[3] */ 624 TRIG_IN_MUX_4_TCPWM0_TR_COMPARE_MATCH3 = 0x00000445u, /* tcpwm[0].tr_compare_match[3] */ 625 TRIG_IN_MUX_4_TCPWM0_TR_UNDERFLOW3 = 0x00000446u, /* tcpwm[0].tr_underflow[3] */ 626 TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW4 = 0x00000447u, /* tcpwm[0].tr_overflow[4] */ 627 TRIG_IN_MUX_4_TCPWM0_TR_COMPARE_MATCH4 = 0x00000448u, /* tcpwm[0].tr_compare_match[4] */ 628 TRIG_IN_MUX_4_TCPWM0_TR_UNDERFLOW4 = 0x00000449u, /* tcpwm[0].tr_underflow[4] */ 629 TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW5 = 0x0000044Au, /* tcpwm[0].tr_overflow[5] */ 630 TRIG_IN_MUX_4_TCPWM0_TR_COMPARE_MATCH5 = 0x0000044Bu, /* tcpwm[0].tr_compare_match[5] */ 631 TRIG_IN_MUX_4_TCPWM0_TR_UNDERFLOW5 = 0x0000044Cu, /* tcpwm[0].tr_underflow[5] */ 632 TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW6 = 0x0000044Du, /* tcpwm[0].tr_overflow[6] */ 633 TRIG_IN_MUX_4_TCPWM0_TR_COMPARE_MATCH6 = 0x0000044Eu, /* tcpwm[0].tr_compare_match[6] */ 634 TRIG_IN_MUX_4_TCPWM0_TR_UNDERFLOW6 = 0x0000044Fu, /* tcpwm[0].tr_underflow[6] */ 635 TRIG_IN_MUX_4_TCPWM0_TR_OVERFLOW7 = 0x00000450u, /* tcpwm[0].tr_overflow[7] */ 636 TRIG_IN_MUX_4_TCPWM0_TR_COMPARE_MATCH7 = 0x00000451u, /* tcpwm[0].tr_compare_match[7] */ 637 TRIG_IN_MUX_4_TCPWM0_TR_UNDERFLOW7 = 0x00000452u, /* tcpwm[0].tr_underflow[7] */ 638 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW0 = 0x00000453u, /* tcpwm[1].tr_overflow[0] */ 639 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH0 = 0x00000454u, /* tcpwm[1].tr_compare_match[0] */ 640 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW0 = 0x00000455u, /* tcpwm[1].tr_underflow[0] */ 641 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW1 = 0x00000456u, /* tcpwm[1].tr_overflow[1] */ 642 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH1 = 0x00000457u, /* tcpwm[1].tr_compare_match[1] */ 643 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW1 = 0x00000458u, /* tcpwm[1].tr_underflow[1] */ 644 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW2 = 0x00000459u, /* tcpwm[1].tr_overflow[2] */ 645 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH2 = 0x0000045Au, /* tcpwm[1].tr_compare_match[2] */ 646 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW2 = 0x0000045Bu, /* tcpwm[1].tr_underflow[2] */ 647 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW3 = 0x0000045Cu, /* tcpwm[1].tr_overflow[3] */ 648 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH3 = 0x0000045Du, /* tcpwm[1].tr_compare_match[3] */ 649 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW3 = 0x0000045Eu, /* tcpwm[1].tr_underflow[3] */ 650 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW4 = 0x0000045Fu, /* tcpwm[1].tr_overflow[4] */ 651 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH4 = 0x00000460u, /* tcpwm[1].tr_compare_match[4] */ 652 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW4 = 0x00000461u, /* tcpwm[1].tr_underflow[4] */ 653 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW5 = 0x00000462u, /* tcpwm[1].tr_overflow[5] */ 654 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH5 = 0x00000463u, /* tcpwm[1].tr_compare_match[5] */ 655 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW5 = 0x00000464u, /* tcpwm[1].tr_underflow[5] */ 656 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW6 = 0x00000465u, /* tcpwm[1].tr_overflow[6] */ 657 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH6 = 0x00000466u, /* tcpwm[1].tr_compare_match[6] */ 658 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW6 = 0x00000467u, /* tcpwm[1].tr_underflow[6] */ 659 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW7 = 0x00000468u, /* tcpwm[1].tr_overflow[7] */ 660 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH7 = 0x00000469u, /* tcpwm[1].tr_compare_match[7] */ 661 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW7 = 0x0000046Au, /* tcpwm[1].tr_underflow[7] */ 662 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW8 = 0x0000046Bu, /* tcpwm[1].tr_overflow[8] */ 663 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH8 = 0x0000046Cu, /* tcpwm[1].tr_compare_match[8] */ 664 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW8 = 0x0000046Du, /* tcpwm[1].tr_underflow[8] */ 665 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW9 = 0x0000046Eu, /* tcpwm[1].tr_overflow[9] */ 666 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH9 = 0x0000046Fu, /* tcpwm[1].tr_compare_match[9] */ 667 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW9 = 0x00000470u, /* tcpwm[1].tr_underflow[9] */ 668 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW10 = 0x00000471u, /* tcpwm[1].tr_overflow[10] */ 669 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH10 = 0x00000472u, /* tcpwm[1].tr_compare_match[10] */ 670 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW10 = 0x00000473u, /* tcpwm[1].tr_underflow[10] */ 671 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW11 = 0x00000474u, /* tcpwm[1].tr_overflow[11] */ 672 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH11 = 0x00000475u, /* tcpwm[1].tr_compare_match[11] */ 673 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW11 = 0x00000476u, /* tcpwm[1].tr_underflow[11] */ 674 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW12 = 0x00000477u, /* tcpwm[1].tr_overflow[12] */ 675 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH12 = 0x00000478u, /* tcpwm[1].tr_compare_match[12] */ 676 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW12 = 0x00000479u, /* tcpwm[1].tr_underflow[12] */ 677 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW13 = 0x0000047Au, /* tcpwm[1].tr_overflow[13] */ 678 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH13 = 0x0000047Bu, /* tcpwm[1].tr_compare_match[13] */ 679 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW13 = 0x0000047Cu, /* tcpwm[1].tr_underflow[13] */ 680 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW14 = 0x0000047Du, /* tcpwm[1].tr_overflow[14] */ 681 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH14 = 0x0000047Eu, /* tcpwm[1].tr_compare_match[14] */ 682 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW14 = 0x0000047Fu, /* tcpwm[1].tr_underflow[14] */ 683 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW15 = 0x00000480u, /* tcpwm[1].tr_overflow[15] */ 684 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH15 = 0x00000481u, /* tcpwm[1].tr_compare_match[15] */ 685 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW15 = 0x00000482u, /* tcpwm[1].tr_underflow[15] */ 686 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW16 = 0x00000483u, /* tcpwm[1].tr_overflow[16] */ 687 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH16 = 0x00000484u, /* tcpwm[1].tr_compare_match[16] */ 688 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW16 = 0x00000485u, /* tcpwm[1].tr_underflow[16] */ 689 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW17 = 0x00000486u, /* tcpwm[1].tr_overflow[17] */ 690 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH17 = 0x00000487u, /* tcpwm[1].tr_compare_match[17] */ 691 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW17 = 0x00000488u, /* tcpwm[1].tr_underflow[17] */ 692 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW18 = 0x00000489u, /* tcpwm[1].tr_overflow[18] */ 693 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH18 = 0x0000048Au, /* tcpwm[1].tr_compare_match[18] */ 694 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW18 = 0x0000048Bu, /* tcpwm[1].tr_underflow[18] */ 695 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW19 = 0x0000048Cu, /* tcpwm[1].tr_overflow[19] */ 696 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH19 = 0x0000048Du, /* tcpwm[1].tr_compare_match[19] */ 697 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW19 = 0x0000048Eu, /* tcpwm[1].tr_underflow[19] */ 698 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW20 = 0x0000048Fu, /* tcpwm[1].tr_overflow[20] */ 699 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH20 = 0x00000490u, /* tcpwm[1].tr_compare_match[20] */ 700 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW20 = 0x00000491u, /* tcpwm[1].tr_underflow[20] */ 701 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW21 = 0x00000492u, /* tcpwm[1].tr_overflow[21] */ 702 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH21 = 0x00000493u, /* tcpwm[1].tr_compare_match[21] */ 703 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW21 = 0x00000494u, /* tcpwm[1].tr_underflow[21] */ 704 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW22 = 0x00000495u, /* tcpwm[1].tr_overflow[22] */ 705 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH22 = 0x00000496u, /* tcpwm[1].tr_compare_match[22] */ 706 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW22 = 0x00000497u, /* tcpwm[1].tr_underflow[22] */ 707 TRIG_IN_MUX_4_TCPWM1_TR_OVERFLOW23 = 0x00000498u, /* tcpwm[1].tr_overflow[23] */ 708 TRIG_IN_MUX_4_TCPWM1_TR_COMPARE_MATCH23 = 0x00000499u, /* tcpwm[1].tr_compare_match[23] */ 709 TRIG_IN_MUX_4_TCPWM1_TR_UNDERFLOW23 = 0x0000049Au, /* tcpwm[1].tr_underflow[23] */ 710 TRIG_IN_MUX_4_MDMA_TR_OUT0 = 0x0000049Bu, /* cpuss.dmac_tr_out[0] */ 711 TRIG_IN_MUX_4_MDMA_TR_OUT1 = 0x0000049Cu, /* cpuss.dmac_tr_out[1] */ 712 TRIG_IN_MUX_4_MDMA_TR_OUT2 = 0x0000049Du, /* cpuss.dmac_tr_out[2] */ 713 TRIG_IN_MUX_4_MDMA_TR_OUT3 = 0x0000049Eu, /* cpuss.dmac_tr_out[3] */ 714 TRIG_IN_MUX_4_SCB_I2C_SCL0 = 0x0000049Fu, /* scb[0].tr_i2c_scl_filtered */ 715 TRIG_IN_MUX_4_SCB_TX0 = 0x000004A0u, /* scb[0].tr_tx_req */ 716 TRIG_IN_MUX_4_SCB_RX0 = 0x000004A1u, /* scb[0].tr_rx_req */ 717 TRIG_IN_MUX_4_SCB_I2C_SCL1 = 0x000004A2u, /* scb[1].tr_i2c_scl_filtered */ 718 TRIG_IN_MUX_4_SCB_TX1 = 0x000004A3u, /* scb[1].tr_tx_req */ 719 TRIG_IN_MUX_4_SCB_RX1 = 0x000004A4u, /* scb[1].tr_rx_req */ 720 TRIG_IN_MUX_4_SCB_I2C_SCL2 = 0x000004A5u, /* scb[2].tr_i2c_scl_filtered */ 721 TRIG_IN_MUX_4_SCB_TX2 = 0x000004A6u, /* scb[2].tr_tx_req */ 722 TRIG_IN_MUX_4_SCB_RX2 = 0x000004A7u, /* scb[2].tr_rx_req */ 723 TRIG_IN_MUX_4_SCB_I2C_SCL3 = 0x000004A8u, /* scb[3].tr_i2c_scl_filtered */ 724 TRIG_IN_MUX_4_SCB_TX3 = 0x000004A9u, /* scb[3].tr_tx_req */ 725 TRIG_IN_MUX_4_SCB_RX3 = 0x000004AAu, /* scb[3].tr_rx_req */ 726 TRIG_IN_MUX_4_SCB_I2C_SCL4 = 0x000004ABu, /* scb[4].tr_i2c_scl_filtered */ 727 TRIG_IN_MUX_4_SCB_TX4 = 0x000004ACu, /* scb[4].tr_tx_req */ 728 TRIG_IN_MUX_4_SCB_RX4 = 0x000004ADu, /* scb[4].tr_rx_req */ 729 TRIG_IN_MUX_4_SCB_I2C_SCL5 = 0x000004AEu, /* scb[5].tr_i2c_scl_filtered */ 730 TRIG_IN_MUX_4_SCB_TX5 = 0x000004AFu, /* scb[5].tr_tx_req */ 731 TRIG_IN_MUX_4_SCB_RX5 = 0x000004B0u, /* scb[5].tr_rx_req */ 732 TRIG_IN_MUX_4_SCB_I2C_SCL6 = 0x000004B1u, /* scb[6].tr_i2c_scl_filtered */ 733 TRIG_IN_MUX_4_SCB_TX6 = 0x000004B2u, /* scb[6].tr_tx_req */ 734 TRIG_IN_MUX_4_SCB_RX6 = 0x000004B3u, /* scb[6].tr_rx_req */ 735 TRIG_IN_MUX_4_SCB_I2C_SCL7 = 0x000004B4u, /* scb[7].tr_i2c_scl_filtered */ 736 TRIG_IN_MUX_4_SCB_TX7 = 0x000004B5u, /* scb[7].tr_tx_req */ 737 TRIG_IN_MUX_4_SCB_RX7 = 0x000004B6u, /* scb[7].tr_rx_req */ 738 TRIG_IN_MUX_4_SCB_I2C_SCL8 = 0x000004B7u, /* scb[8].tr_i2c_scl_filtered */ 739 TRIG_IN_MUX_4_SCB_TX8 = 0x000004B8u, /* scb[8].tr_tx_req */ 740 TRIG_IN_MUX_4_SCB_RX8 = 0x000004B9u, /* scb[8].tr_rx_req */ 741 TRIG_IN_MUX_4_SCB_I2C_SCL9 = 0x000004BAu, /* scb[9].tr_i2c_scl_filtered */ 742 TRIG_IN_MUX_4_SCB_TX9 = 0x000004BBu, /* scb[9].tr_tx_req */ 743 TRIG_IN_MUX_4_SCB_RX9 = 0x000004BCu, /* scb[9].tr_rx_req */ 744 TRIG_IN_MUX_4_SCB_I2C_SCL10 = 0x000004BDu, /* scb[10].tr_i2c_scl_filtered */ 745 TRIG_IN_MUX_4_SCB_TX10 = 0x000004BEu, /* scb[10].tr_tx_req */ 746 TRIG_IN_MUX_4_SCB_RX10 = 0x000004BFu, /* scb[10].tr_rx_req */ 747 TRIG_IN_MUX_4_SCB_I2C_SCL11 = 0x000004C0u, /* scb[11].tr_i2c_scl_filtered */ 748 TRIG_IN_MUX_4_SCB_TX11 = 0x000004C1u, /* scb[11].tr_tx_req */ 749 TRIG_IN_MUX_4_SCB_RX11 = 0x000004C2u, /* scb[11].tr_rx_req */ 750 TRIG_IN_MUX_4_SCB_I2C_SCL12 = 0x000004C3u, /* scb[12].tr_i2c_scl_filtered */ 751 TRIG_IN_MUX_4_SCB_TX12 = 0x000004C4u, /* scb[12].tr_tx_req */ 752 TRIG_IN_MUX_4_SCB_RX12 = 0x000004C5u, /* scb[12].tr_rx_req */ 753 TRIG_IN_MUX_4_SMIF_TX = 0x000004C6u, /* smif.tr_tx_req */ 754 TRIG_IN_MUX_4_SMIF_RX = 0x000004C7u, /* smif.tr_rx_req */ 755 TRIG_IN_MUX_4_USB_DMA0 = 0x000004C8u, /* usb.dma_req[0] */ 756 TRIG_IN_MUX_4_USB_DMA1 = 0x000004C9u, /* usb.dma_req[1] */ 757 TRIG_IN_MUX_4_USB_DMA2 = 0x000004CAu, /* usb.dma_req[2] */ 758 TRIG_IN_MUX_4_USB_DMA3 = 0x000004CBu, /* usb.dma_req[3] */ 759 TRIG_IN_MUX_4_USB_DMA4 = 0x000004CCu, /* usb.dma_req[4] */ 760 TRIG_IN_MUX_4_USB_DMA5 = 0x000004CDu, /* usb.dma_req[5] */ 761 TRIG_IN_MUX_4_USB_DMA6 = 0x000004CEu, /* usb.dma_req[6] */ 762 TRIG_IN_MUX_4_USB_DMA7 = 0x000004CFu, /* usb.dma_req[7] */ 763 TRIG_IN_MUX_4_I2S_TX0 = 0x000004D0u, /* audioss[0].tr_i2s_tx_req */ 764 TRIG_IN_MUX_4_I2S_RX0 = 0x000004D1u, /* audioss[0].tr_i2s_rx_req */ 765 TRIG_IN_MUX_4_PDM_RX0 = 0x000004D2u, /* audioss[0].tr_pdm_rx_req */ 766 TRIG_IN_MUX_4_I2S_TX1 = 0x000004D3u, /* audioss[1].tr_i2s_tx_req */ 767 TRIG_IN_MUX_4_I2S_RX1 = 0x000004D4u, /* audioss[1].tr_i2s_rx_req */ 768 TRIG_IN_MUX_4_CSD_SENSE = 0x000004D5u, /* csd.dsi_sense_out */ 769 TRIG_IN_MUX_4_CSD_SAMPLE = 0x000004D6u, /* csd.dsi_sample_out */ 770 TRIG_IN_MUX_4_CSD_ADC_DONE = 0x000004D7u, /* csd.tr_adc_done */ 771 TRIG_IN_MUX_4_PASS_SAR_DONE = 0x000004D8u, /* pass.tr_sar_out */ 772 TRIG_IN_MUX_4_FAULT_TR_OUT0 = 0x000004D9u, /* cpuss.tr_fault[0] */ 773 TRIG_IN_MUX_4_FAULT_TR_OUT1 = 0x000004DAu, /* cpuss.tr_fault[1] */ 774 TRIG_IN_MUX_4_CTI_TR_OUT0 = 0x000004DBu, /* cpuss.cti_tr_out[0] */ 775 TRIG_IN_MUX_4_CTI_TR_OUT1 = 0x000004DCu, /* cpuss.cti_tr_out[1] */ 776 TRIG_IN_MUX_4_LPCOMP_DSI_COMP0 = 0x000004DDu, /* lpcomp.dsi_comp0 */ 777 TRIG_IN_MUX_4_LPCOMP_DSI_COMP1 = 0x000004DEu /* lpcomp.dsi_comp1 */ 778 } en_trig_input_hsiom_t; 779 780 /* Trigger Input Group 5 - CPUSS Debug and Profiler trigger multiplexer */ 781 typedef enum 782 { 783 TRIG_IN_MUX_5_PDMA0_TR_OUT0 = 0x00000501u, /* cpuss.dw0_tr_out[0] */ 784 TRIG_IN_MUX_5_PDMA0_TR_OUT1 = 0x00000502u, /* cpuss.dw0_tr_out[1] */ 785 TRIG_IN_MUX_5_PDMA0_TR_OUT2 = 0x00000503u, /* cpuss.dw0_tr_out[2] */ 786 TRIG_IN_MUX_5_PDMA0_TR_OUT3 = 0x00000504u, /* cpuss.dw0_tr_out[3] */ 787 TRIG_IN_MUX_5_PDMA0_TR_OUT4 = 0x00000505u, /* cpuss.dw0_tr_out[4] */ 788 TRIG_IN_MUX_5_PDMA0_TR_OUT5 = 0x00000506u, /* cpuss.dw0_tr_out[5] */ 789 TRIG_IN_MUX_5_PDMA0_TR_OUT6 = 0x00000507u, /* cpuss.dw0_tr_out[6] */ 790 TRIG_IN_MUX_5_PDMA0_TR_OUT7 = 0x00000508u, /* cpuss.dw0_tr_out[7] */ 791 TRIG_IN_MUX_5_PDMA0_TR_OUT8 = 0x00000509u, /* cpuss.dw0_tr_out[8] */ 792 TRIG_IN_MUX_5_PDMA0_TR_OUT9 = 0x0000050Au, /* cpuss.dw0_tr_out[9] */ 793 TRIG_IN_MUX_5_PDMA0_TR_OUT10 = 0x0000050Bu, /* cpuss.dw0_tr_out[10] */ 794 TRIG_IN_MUX_5_PDMA0_TR_OUT11 = 0x0000050Cu, /* cpuss.dw0_tr_out[11] */ 795 TRIG_IN_MUX_5_PDMA0_TR_OUT12 = 0x0000050Du, /* cpuss.dw0_tr_out[12] */ 796 TRIG_IN_MUX_5_PDMA0_TR_OUT13 = 0x0000050Eu, /* cpuss.dw0_tr_out[13] */ 797 TRIG_IN_MUX_5_PDMA0_TR_OUT14 = 0x0000050Fu, /* cpuss.dw0_tr_out[14] */ 798 TRIG_IN_MUX_5_PDMA0_TR_OUT15 = 0x00000510u, /* cpuss.dw0_tr_out[15] */ 799 TRIG_IN_MUX_5_PDMA0_TR_OUT16 = 0x00000511u, /* cpuss.dw0_tr_out[16] */ 800 TRIG_IN_MUX_5_PDMA0_TR_OUT17 = 0x00000512u, /* cpuss.dw0_tr_out[17] */ 801 TRIG_IN_MUX_5_PDMA0_TR_OUT18 = 0x00000513u, /* cpuss.dw0_tr_out[18] */ 802 TRIG_IN_MUX_5_PDMA0_TR_OUT19 = 0x00000514u, /* cpuss.dw0_tr_out[19] */ 803 TRIG_IN_MUX_5_PDMA0_TR_OUT20 = 0x00000515u, /* cpuss.dw0_tr_out[20] */ 804 TRIG_IN_MUX_5_PDMA0_TR_OUT21 = 0x00000516u, /* cpuss.dw0_tr_out[21] */ 805 TRIG_IN_MUX_5_PDMA0_TR_OUT22 = 0x00000517u, /* cpuss.dw0_tr_out[22] */ 806 TRIG_IN_MUX_5_PDMA0_TR_OUT23 = 0x00000518u, /* cpuss.dw0_tr_out[23] */ 807 TRIG_IN_MUX_5_PDMA0_TR_OUT24 = 0x00000519u, /* cpuss.dw0_tr_out[24] */ 808 TRIG_IN_MUX_5_PDMA0_TR_OUT25 = 0x0000051Au, /* cpuss.dw0_tr_out[25] */ 809 TRIG_IN_MUX_5_PDMA0_TR_OUT26 = 0x0000051Bu, /* cpuss.dw0_tr_out[26] */ 810 TRIG_IN_MUX_5_PDMA0_TR_OUT27 = 0x0000051Cu, /* cpuss.dw0_tr_out[27] */ 811 TRIG_IN_MUX_5_PDMA0_TR_OUT28 = 0x0000051Du, /* cpuss.dw0_tr_out[28] */ 812 TRIG_IN_MUX_5_PDMA1_TR_OUT0 = 0x0000051Eu, /* cpuss.dw1_tr_out[0] */ 813 TRIG_IN_MUX_5_PDMA1_TR_OUT1 = 0x0000051Fu, /* cpuss.dw1_tr_out[1] */ 814 TRIG_IN_MUX_5_PDMA1_TR_OUT2 = 0x00000520u, /* cpuss.dw1_tr_out[2] */ 815 TRIG_IN_MUX_5_PDMA1_TR_OUT3 = 0x00000521u, /* cpuss.dw1_tr_out[3] */ 816 TRIG_IN_MUX_5_PDMA1_TR_OUT4 = 0x00000522u, /* cpuss.dw1_tr_out[4] */ 817 TRIG_IN_MUX_5_PDMA1_TR_OUT5 = 0x00000523u, /* cpuss.dw1_tr_out[5] */ 818 TRIG_IN_MUX_5_PDMA1_TR_OUT6 = 0x00000524u, /* cpuss.dw1_tr_out[6] */ 819 TRIG_IN_MUX_5_PDMA1_TR_OUT7 = 0x00000525u, /* cpuss.dw1_tr_out[7] */ 820 TRIG_IN_MUX_5_PDMA1_TR_OUT8 = 0x00000526u, /* cpuss.dw1_tr_out[8] */ 821 TRIG_IN_MUX_5_PDMA1_TR_OUT9 = 0x00000527u, /* cpuss.dw1_tr_out[9] */ 822 TRIG_IN_MUX_5_PDMA1_TR_OUT10 = 0x00000528u, /* cpuss.dw1_tr_out[10] */ 823 TRIG_IN_MUX_5_PDMA1_TR_OUT11 = 0x00000529u, /* cpuss.dw1_tr_out[11] */ 824 TRIG_IN_MUX_5_PDMA1_TR_OUT12 = 0x0000052Au, /* cpuss.dw1_tr_out[12] */ 825 TRIG_IN_MUX_5_PDMA1_TR_OUT13 = 0x0000052Bu, /* cpuss.dw1_tr_out[13] */ 826 TRIG_IN_MUX_5_PDMA1_TR_OUT14 = 0x0000052Cu, /* cpuss.dw1_tr_out[14] */ 827 TRIG_IN_MUX_5_PDMA1_TR_OUT15 = 0x0000052Du, /* cpuss.dw1_tr_out[15] */ 828 TRIG_IN_MUX_5_PDMA1_TR_OUT16 = 0x0000052Eu, /* cpuss.dw1_tr_out[16] */ 829 TRIG_IN_MUX_5_PDMA1_TR_OUT17 = 0x0000052Fu, /* cpuss.dw1_tr_out[17] */ 830 TRIG_IN_MUX_5_PDMA1_TR_OUT18 = 0x00000530u, /* cpuss.dw1_tr_out[18] */ 831 TRIG_IN_MUX_5_PDMA1_TR_OUT19 = 0x00000531u, /* cpuss.dw1_tr_out[19] */ 832 TRIG_IN_MUX_5_PDMA1_TR_OUT20 = 0x00000532u, /* cpuss.dw1_tr_out[20] */ 833 TRIG_IN_MUX_5_PDMA1_TR_OUT21 = 0x00000533u, /* cpuss.dw1_tr_out[21] */ 834 TRIG_IN_MUX_5_PDMA1_TR_OUT22 = 0x00000534u, /* cpuss.dw1_tr_out[22] */ 835 TRIG_IN_MUX_5_PDMA1_TR_OUT23 = 0x00000535u, /* cpuss.dw1_tr_out[23] */ 836 TRIG_IN_MUX_5_PDMA1_TR_OUT24 = 0x00000536u, /* cpuss.dw1_tr_out[24] */ 837 TRIG_IN_MUX_5_PDMA1_TR_OUT25 = 0x00000537u, /* cpuss.dw1_tr_out[25] */ 838 TRIG_IN_MUX_5_PDMA1_TR_OUT26 = 0x00000538u, /* cpuss.dw1_tr_out[26] */ 839 TRIG_IN_MUX_5_PDMA1_TR_OUT27 = 0x00000539u, /* cpuss.dw1_tr_out[27] */ 840 TRIG_IN_MUX_5_PDMA1_TR_OUT28 = 0x0000053Au, /* cpuss.dw1_tr_out[28] */ 841 TRIG_IN_MUX_5_TCPWM0_TR_OVERFLOW0 = 0x0000053Bu, /* tcpwm[0].tr_overflow[0] */ 842 TRIG_IN_MUX_5_TCPWM0_TR_COMPARE_MATCH0 = 0x0000053Cu, /* tcpwm[0].tr_compare_match[0] */ 843 TRIG_IN_MUX_5_TCPWM0_TR_UNDERFLOW0 = 0x0000053Du, /* tcpwm[0].tr_underflow[0] */ 844 TRIG_IN_MUX_5_TCPWM0_TR_OVERFLOW1 = 0x0000053Eu, /* tcpwm[0].tr_overflow[1] */ 845 TRIG_IN_MUX_5_TCPWM0_TR_COMPARE_MATCH1 = 0x0000053Fu, /* tcpwm[0].tr_compare_match[1] */ 846 TRIG_IN_MUX_5_TCPWM0_TR_UNDERFLOW1 = 0x00000540u, /* tcpwm[0].tr_underflow[1] */ 847 TRIG_IN_MUX_5_TCPWM0_TR_OVERFLOW2 = 0x00000541u, /* tcpwm[0].tr_overflow[2] */ 848 TRIG_IN_MUX_5_TCPWM0_TR_COMPARE_MATCH2 = 0x00000542u, /* tcpwm[0].tr_compare_match[2] */ 849 TRIG_IN_MUX_5_TCPWM0_TR_UNDERFLOW2 = 0x00000543u, /* tcpwm[0].tr_underflow[2] */ 850 TRIG_IN_MUX_5_TCPWM0_TR_OVERFLOW3 = 0x00000544u, /* tcpwm[0].tr_overflow[3] */ 851 TRIG_IN_MUX_5_TCPWM0_TR_COMPARE_MATCH3 = 0x00000545u, /* tcpwm[0].tr_compare_match[3] */ 852 TRIG_IN_MUX_5_TCPWM0_TR_UNDERFLOW3 = 0x00000546u, /* tcpwm[0].tr_underflow[3] */ 853 TRIG_IN_MUX_5_TCPWM0_TR_OVERFLOW4 = 0x00000547u, /* tcpwm[0].tr_overflow[4] */ 854 TRIG_IN_MUX_5_TCPWM0_TR_COMPARE_MATCH4 = 0x00000548u, /* tcpwm[0].tr_compare_match[4] */ 855 TRIG_IN_MUX_5_TCPWM0_TR_UNDERFLOW4 = 0x00000549u, /* tcpwm[0].tr_underflow[4] */ 856 TRIG_IN_MUX_5_TCPWM0_TR_OVERFLOW5 = 0x0000054Au, /* tcpwm[0].tr_overflow[5] */ 857 TRIG_IN_MUX_5_TCPWM0_TR_COMPARE_MATCH5 = 0x0000054Bu, /* tcpwm[0].tr_compare_match[5] */ 858 TRIG_IN_MUX_5_TCPWM0_TR_UNDERFLOW5 = 0x0000054Cu, /* tcpwm[0].tr_underflow[5] */ 859 TRIG_IN_MUX_5_TCPWM0_TR_OVERFLOW6 = 0x0000054Du, /* tcpwm[0].tr_overflow[6] */ 860 TRIG_IN_MUX_5_TCPWM0_TR_COMPARE_MATCH6 = 0x0000054Eu, /* tcpwm[0].tr_compare_match[6] */ 861 TRIG_IN_MUX_5_TCPWM0_TR_UNDERFLOW6 = 0x0000054Fu, /* tcpwm[0].tr_underflow[6] */ 862 TRIG_IN_MUX_5_TCPWM0_TR_OVERFLOW7 = 0x00000550u, /* tcpwm[0].tr_overflow[7] */ 863 TRIG_IN_MUX_5_TCPWM0_TR_COMPARE_MATCH7 = 0x00000551u, /* tcpwm[0].tr_compare_match[7] */ 864 TRIG_IN_MUX_5_TCPWM0_TR_UNDERFLOW7 = 0x00000552u, /* tcpwm[0].tr_underflow[7] */ 865 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW0 = 0x00000553u, /* tcpwm[1].tr_overflow[0] */ 866 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH0 = 0x00000554u, /* tcpwm[1].tr_compare_match[0] */ 867 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW0 = 0x00000555u, /* tcpwm[1].tr_underflow[0] */ 868 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW1 = 0x00000556u, /* tcpwm[1].tr_overflow[1] */ 869 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH1 = 0x00000557u, /* tcpwm[1].tr_compare_match[1] */ 870 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW1 = 0x00000558u, /* tcpwm[1].tr_underflow[1] */ 871 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW2 = 0x00000559u, /* tcpwm[1].tr_overflow[2] */ 872 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH2 = 0x0000055Au, /* tcpwm[1].tr_compare_match[2] */ 873 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW2 = 0x0000055Bu, /* tcpwm[1].tr_underflow[2] */ 874 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW3 = 0x0000055Cu, /* tcpwm[1].tr_overflow[3] */ 875 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH3 = 0x0000055Du, /* tcpwm[1].tr_compare_match[3] */ 876 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW3 = 0x0000055Eu, /* tcpwm[1].tr_underflow[3] */ 877 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW4 = 0x0000055Fu, /* tcpwm[1].tr_overflow[4] */ 878 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH4 = 0x00000560u, /* tcpwm[1].tr_compare_match[4] */ 879 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW4 = 0x00000561u, /* tcpwm[1].tr_underflow[4] */ 880 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW5 = 0x00000562u, /* tcpwm[1].tr_overflow[5] */ 881 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH5 = 0x00000563u, /* tcpwm[1].tr_compare_match[5] */ 882 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW5 = 0x00000564u, /* tcpwm[1].tr_underflow[5] */ 883 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW6 = 0x00000565u, /* tcpwm[1].tr_overflow[6] */ 884 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH6 = 0x00000566u, /* tcpwm[1].tr_compare_match[6] */ 885 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW6 = 0x00000567u, /* tcpwm[1].tr_underflow[6] */ 886 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW7 = 0x00000568u, /* tcpwm[1].tr_overflow[7] */ 887 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH7 = 0x00000569u, /* tcpwm[1].tr_compare_match[7] */ 888 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW7 = 0x0000056Au, /* tcpwm[1].tr_underflow[7] */ 889 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW8 = 0x0000056Bu, /* tcpwm[1].tr_overflow[8] */ 890 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH8 = 0x0000056Cu, /* tcpwm[1].tr_compare_match[8] */ 891 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW8 = 0x0000056Du, /* tcpwm[1].tr_underflow[8] */ 892 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW9 = 0x0000056Eu, /* tcpwm[1].tr_overflow[9] */ 893 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH9 = 0x0000056Fu, /* tcpwm[1].tr_compare_match[9] */ 894 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW9 = 0x00000570u, /* tcpwm[1].tr_underflow[9] */ 895 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW10 = 0x00000571u, /* tcpwm[1].tr_overflow[10] */ 896 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH10 = 0x00000572u, /* tcpwm[1].tr_compare_match[10] */ 897 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW10 = 0x00000573u, /* tcpwm[1].tr_underflow[10] */ 898 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW11 = 0x00000574u, /* tcpwm[1].tr_overflow[11] */ 899 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH11 = 0x00000575u, /* tcpwm[1].tr_compare_match[11] */ 900 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW11 = 0x00000576u, /* tcpwm[1].tr_underflow[11] */ 901 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW12 = 0x00000577u, /* tcpwm[1].tr_overflow[12] */ 902 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH12 = 0x00000578u, /* tcpwm[1].tr_compare_match[12] */ 903 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW12 = 0x00000579u, /* tcpwm[1].tr_underflow[12] */ 904 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW13 = 0x0000057Au, /* tcpwm[1].tr_overflow[13] */ 905 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH13 = 0x0000057Bu, /* tcpwm[1].tr_compare_match[13] */ 906 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW13 = 0x0000057Cu, /* tcpwm[1].tr_underflow[13] */ 907 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW14 = 0x0000057Du, /* tcpwm[1].tr_overflow[14] */ 908 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH14 = 0x0000057Eu, /* tcpwm[1].tr_compare_match[14] */ 909 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW14 = 0x0000057Fu, /* tcpwm[1].tr_underflow[14] */ 910 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW15 = 0x00000580u, /* tcpwm[1].tr_overflow[15] */ 911 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH15 = 0x00000581u, /* tcpwm[1].tr_compare_match[15] */ 912 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW15 = 0x00000582u, /* tcpwm[1].tr_underflow[15] */ 913 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW16 = 0x00000583u, /* tcpwm[1].tr_overflow[16] */ 914 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH16 = 0x00000584u, /* tcpwm[1].tr_compare_match[16] */ 915 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW16 = 0x00000585u, /* tcpwm[1].tr_underflow[16] */ 916 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW17 = 0x00000586u, /* tcpwm[1].tr_overflow[17] */ 917 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH17 = 0x00000587u, /* tcpwm[1].tr_compare_match[17] */ 918 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW17 = 0x00000588u, /* tcpwm[1].tr_underflow[17] */ 919 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW18 = 0x00000589u, /* tcpwm[1].tr_overflow[18] */ 920 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH18 = 0x0000058Au, /* tcpwm[1].tr_compare_match[18] */ 921 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW18 = 0x0000058Bu, /* tcpwm[1].tr_underflow[18] */ 922 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW19 = 0x0000058Cu, /* tcpwm[1].tr_overflow[19] */ 923 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH19 = 0x0000058Du, /* tcpwm[1].tr_compare_match[19] */ 924 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW19 = 0x0000058Eu, /* tcpwm[1].tr_underflow[19] */ 925 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW20 = 0x0000058Fu, /* tcpwm[1].tr_overflow[20] */ 926 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH20 = 0x00000590u, /* tcpwm[1].tr_compare_match[20] */ 927 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW20 = 0x00000591u, /* tcpwm[1].tr_underflow[20] */ 928 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW21 = 0x00000592u, /* tcpwm[1].tr_overflow[21] */ 929 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH21 = 0x00000593u, /* tcpwm[1].tr_compare_match[21] */ 930 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW21 = 0x00000594u, /* tcpwm[1].tr_underflow[21] */ 931 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW22 = 0x00000595u, /* tcpwm[1].tr_overflow[22] */ 932 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH22 = 0x00000596u, /* tcpwm[1].tr_compare_match[22] */ 933 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW22 = 0x00000597u, /* tcpwm[1].tr_underflow[22] */ 934 TRIG_IN_MUX_5_TCPWM1_TR_OVERFLOW23 = 0x00000598u, /* tcpwm[1].tr_overflow[23] */ 935 TRIG_IN_MUX_5_TCPWM1_TR_COMPARE_MATCH23 = 0x00000599u, /* tcpwm[1].tr_compare_match[23] */ 936 TRIG_IN_MUX_5_TCPWM1_TR_UNDERFLOW23 = 0x0000059Au, /* tcpwm[1].tr_underflow[23] */ 937 TRIG_IN_MUX_5_MDMA_TR_OUT0 = 0x0000059Bu, /* cpuss.dmac_tr_out[0] */ 938 TRIG_IN_MUX_5_MDMA_TR_OUT1 = 0x0000059Cu, /* cpuss.dmac_tr_out[1] */ 939 TRIG_IN_MUX_5_MDMA_TR_OUT2 = 0x0000059Du, /* cpuss.dmac_tr_out[2] */ 940 TRIG_IN_MUX_5_MDMA_TR_OUT3 = 0x0000059Eu, /* cpuss.dmac_tr_out[3] */ 941 TRIG_IN_MUX_5_SCB_I2C_SCL0 = 0x0000059Fu, /* scb[0].tr_i2c_scl_filtered */ 942 TRIG_IN_MUX_5_SCB_TX0 = 0x000005A0u, /* scb[0].tr_tx_req */ 943 TRIG_IN_MUX_5_SCB_RX0 = 0x000005A1u, /* scb[0].tr_rx_req */ 944 TRIG_IN_MUX_5_SCB_I2C_SCL1 = 0x000005A2u, /* scb[1].tr_i2c_scl_filtered */ 945 TRIG_IN_MUX_5_SCB_TX1 = 0x000005A3u, /* scb[1].tr_tx_req */ 946 TRIG_IN_MUX_5_SCB_RX1 = 0x000005A4u, /* scb[1].tr_rx_req */ 947 TRIG_IN_MUX_5_SCB_I2C_SCL2 = 0x000005A5u, /* scb[2].tr_i2c_scl_filtered */ 948 TRIG_IN_MUX_5_SCB_TX2 = 0x000005A6u, /* scb[2].tr_tx_req */ 949 TRIG_IN_MUX_5_SCB_RX2 = 0x000005A7u, /* scb[2].tr_rx_req */ 950 TRIG_IN_MUX_5_SCB_I2C_SCL3 = 0x000005A8u, /* scb[3].tr_i2c_scl_filtered */ 951 TRIG_IN_MUX_5_SCB_TX3 = 0x000005A9u, /* scb[3].tr_tx_req */ 952 TRIG_IN_MUX_5_SCB_RX3 = 0x000005AAu, /* scb[3].tr_rx_req */ 953 TRIG_IN_MUX_5_SCB_I2C_SCL4 = 0x000005ABu, /* scb[4].tr_i2c_scl_filtered */ 954 TRIG_IN_MUX_5_SCB_TX4 = 0x000005ACu, /* scb[4].tr_tx_req */ 955 TRIG_IN_MUX_5_SCB_RX4 = 0x000005ADu, /* scb[4].tr_rx_req */ 956 TRIG_IN_MUX_5_SCB_I2C_SCL5 = 0x000005AEu, /* scb[5].tr_i2c_scl_filtered */ 957 TRIG_IN_MUX_5_SCB_TX5 = 0x000005AFu, /* scb[5].tr_tx_req */ 958 TRIG_IN_MUX_5_SCB_RX5 = 0x000005B0u, /* scb[5].tr_rx_req */ 959 TRIG_IN_MUX_5_SCB_I2C_SCL6 = 0x000005B1u, /* scb[6].tr_i2c_scl_filtered */ 960 TRIG_IN_MUX_5_SCB_TX6 = 0x000005B2u, /* scb[6].tr_tx_req */ 961 TRIG_IN_MUX_5_SCB_RX6 = 0x000005B3u, /* scb[6].tr_rx_req */ 962 TRIG_IN_MUX_5_SCB_I2C_SCL7 = 0x000005B4u, /* scb[7].tr_i2c_scl_filtered */ 963 TRIG_IN_MUX_5_SCB_TX7 = 0x000005B5u, /* scb[7].tr_tx_req */ 964 TRIG_IN_MUX_5_SCB_RX7 = 0x000005B6u, /* scb[7].tr_rx_req */ 965 TRIG_IN_MUX_5_SCB_I2C_SCL8 = 0x000005B7u, /* scb[8].tr_i2c_scl_filtered */ 966 TRIG_IN_MUX_5_SCB_TX8 = 0x000005B8u, /* scb[8].tr_tx_req */ 967 TRIG_IN_MUX_5_SCB_RX8 = 0x000005B9u, /* scb[8].tr_rx_req */ 968 TRIG_IN_MUX_5_SCB_I2C_SCL9 = 0x000005BAu, /* scb[9].tr_i2c_scl_filtered */ 969 TRIG_IN_MUX_5_SCB_TX9 = 0x000005BBu, /* scb[9].tr_tx_req */ 970 TRIG_IN_MUX_5_SCB_RX9 = 0x000005BCu, /* scb[9].tr_rx_req */ 971 TRIG_IN_MUX_5_SCB_I2C_SCL10 = 0x000005BDu, /* scb[10].tr_i2c_scl_filtered */ 972 TRIG_IN_MUX_5_SCB_TX10 = 0x000005BEu, /* scb[10].tr_tx_req */ 973 TRIG_IN_MUX_5_SCB_RX10 = 0x000005BFu, /* scb[10].tr_rx_req */ 974 TRIG_IN_MUX_5_SCB_I2C_SCL11 = 0x000005C0u, /* scb[11].tr_i2c_scl_filtered */ 975 TRIG_IN_MUX_5_SCB_TX11 = 0x000005C1u, /* scb[11].tr_tx_req */ 976 TRIG_IN_MUX_5_SCB_RX11 = 0x000005C2u, /* scb[11].tr_rx_req */ 977 TRIG_IN_MUX_5_SCB_I2C_SCL12 = 0x000005C3u, /* scb[12].tr_i2c_scl_filtered */ 978 TRIG_IN_MUX_5_SCB_TX12 = 0x000005C4u, /* scb[12].tr_tx_req */ 979 TRIG_IN_MUX_5_SCB_RX12 = 0x000005C5u, /* scb[12].tr_rx_req */ 980 TRIG_IN_MUX_5_SMIF_TX = 0x000005C6u, /* smif.tr_tx_req */ 981 TRIG_IN_MUX_5_SMIF_RX = 0x000005C7u, /* smif.tr_rx_req */ 982 TRIG_IN_MUX_5_USB_DMA0 = 0x000005C8u, /* usb.dma_req[0] */ 983 TRIG_IN_MUX_5_USB_DMA1 = 0x000005C9u, /* usb.dma_req[1] */ 984 TRIG_IN_MUX_5_USB_DMA2 = 0x000005CAu, /* usb.dma_req[2] */ 985 TRIG_IN_MUX_5_USB_DMA3 = 0x000005CBu, /* usb.dma_req[3] */ 986 TRIG_IN_MUX_5_USB_DMA4 = 0x000005CCu, /* usb.dma_req[4] */ 987 TRIG_IN_MUX_5_USB_DMA5 = 0x000005CDu, /* usb.dma_req[5] */ 988 TRIG_IN_MUX_5_USB_DMA6 = 0x000005CEu, /* usb.dma_req[6] */ 989 TRIG_IN_MUX_5_USB_DMA7 = 0x000005CFu, /* usb.dma_req[7] */ 990 TRIG_IN_MUX_5_I2S_TX0 = 0x000005D0u, /* audioss[0].tr_i2s_tx_req */ 991 TRIG_IN_MUX_5_I2S_RX0 = 0x000005D1u, /* audioss[0].tr_i2s_rx_req */ 992 TRIG_IN_MUX_5_PDM_RX0 = 0x000005D2u, /* audioss[0].tr_pdm_rx_req */ 993 TRIG_IN_MUX_5_I2S_TX1 = 0x000005D3u, /* audioss[1].tr_i2s_tx_req */ 994 TRIG_IN_MUX_5_I2S_RX1 = 0x000005D4u, /* audioss[1].tr_i2s_rx_req */ 995 TRIG_IN_MUX_5_CSD_SENSE = 0x000005D5u, /* csd.dsi_sense_out */ 996 TRIG_IN_MUX_5_CSD_SAMPLE = 0x000005D6u, /* csd.dsi_sample_out */ 997 TRIG_IN_MUX_5_CSD_ADC_DONE = 0x000005D7u, /* csd.tr_adc_done */ 998 TRIG_IN_MUX_5_PASS_SAR_DONE = 0x000005D8u, /* pass.tr_sar_out */ 999 TRIG_IN_MUX_5_HSIOM_TR_OUT0 = 0x000005D9u, /* peri.tr_io_input[0] */ 1000 TRIG_IN_MUX_5_HSIOM_TR_OUT1 = 0x000005DAu, /* peri.tr_io_input[1] */ 1001 TRIG_IN_MUX_5_HSIOM_TR_OUT2 = 0x000005DBu, /* peri.tr_io_input[2] */ 1002 TRIG_IN_MUX_5_HSIOM_TR_OUT3 = 0x000005DCu, /* peri.tr_io_input[3] */ 1003 TRIG_IN_MUX_5_HSIOM_TR_OUT4 = 0x000005DDu, /* peri.tr_io_input[4] */ 1004 TRIG_IN_MUX_5_HSIOM_TR_OUT5 = 0x000005DEu, /* peri.tr_io_input[5] */ 1005 TRIG_IN_MUX_5_HSIOM_TR_OUT6 = 0x000005DFu, /* peri.tr_io_input[6] */ 1006 TRIG_IN_MUX_5_HSIOM_TR_OUT7 = 0x000005E0u, /* peri.tr_io_input[7] */ 1007 TRIG_IN_MUX_5_HSIOM_TR_OUT8 = 0x000005E1u, /* peri.tr_io_input[8] */ 1008 TRIG_IN_MUX_5_HSIOM_TR_OUT9 = 0x000005E2u, /* peri.tr_io_input[9] */ 1009 TRIG_IN_MUX_5_HSIOM_TR_OUT10 = 0x000005E3u, /* peri.tr_io_input[10] */ 1010 TRIG_IN_MUX_5_HSIOM_TR_OUT11 = 0x000005E4u, /* peri.tr_io_input[11] */ 1011 TRIG_IN_MUX_5_HSIOM_TR_OUT12 = 0x000005E5u, /* peri.tr_io_input[12] */ 1012 TRIG_IN_MUX_5_HSIOM_TR_OUT13 = 0x000005E6u, /* peri.tr_io_input[13] */ 1013 TRIG_IN_MUX_5_HSIOM_TR_OUT14 = 0x000005E7u, /* peri.tr_io_input[14] */ 1014 TRIG_IN_MUX_5_HSIOM_TR_OUT15 = 0x000005E8u, /* peri.tr_io_input[15] */ 1015 TRIG_IN_MUX_5_HSIOM_TR_OUT16 = 0x000005E9u, /* peri.tr_io_input[16] */ 1016 TRIG_IN_MUX_5_HSIOM_TR_OUT17 = 0x000005EAu, /* peri.tr_io_input[17] */ 1017 TRIG_IN_MUX_5_HSIOM_TR_OUT18 = 0x000005EBu, /* peri.tr_io_input[18] */ 1018 TRIG_IN_MUX_5_HSIOM_TR_OUT19 = 0x000005ECu, /* peri.tr_io_input[19] */ 1019 TRIG_IN_MUX_5_HSIOM_TR_OUT20 = 0x000005EDu, /* peri.tr_io_input[20] */ 1020 TRIG_IN_MUX_5_HSIOM_TR_OUT21 = 0x000005EEu, /* peri.tr_io_input[21] */ 1021 TRIG_IN_MUX_5_HSIOM_TR_OUT22 = 0x000005EFu, /* peri.tr_io_input[22] */ 1022 TRIG_IN_MUX_5_HSIOM_TR_OUT23 = 0x000005F0u, /* peri.tr_io_input[23] */ 1023 TRIG_IN_MUX_5_HSIOM_TR_OUT24 = 0x000005F1u, /* peri.tr_io_input[24] */ 1024 TRIG_IN_MUX_5_HSIOM_TR_OUT25 = 0x000005F2u, /* peri.tr_io_input[25] */ 1025 TRIG_IN_MUX_5_HSIOM_TR_OUT26 = 0x000005F3u, /* peri.tr_io_input[26] */ 1026 TRIG_IN_MUX_5_HSIOM_TR_OUT27 = 0x000005F4u, /* peri.tr_io_input[27] */ 1027 TRIG_IN_MUX_5_FAULT_TR_OUT0 = 0x000005F5u, /* cpuss.tr_fault[0] */ 1028 TRIG_IN_MUX_5_FAULT_TR_OUT1 = 0x000005F6u, /* cpuss.tr_fault[1] */ 1029 TRIG_IN_MUX_5_CTI_TR_OUT0 = 0x000005F7u, /* cpuss.cti_tr_out[0] */ 1030 TRIG_IN_MUX_5_CTI_TR_OUT1 = 0x000005F8u, /* cpuss.cti_tr_out[1] */ 1031 TRIG_IN_MUX_5_LPCOMP_DSI_COMP0 = 0x000005F9u, /* lpcomp.dsi_comp0 */ 1032 TRIG_IN_MUX_5_LPCOMP_DSI_COMP1 = 0x000005FAu /* lpcomp.dsi_comp1 */ 1033 } en_trig_input_cpuss_cti_t; 1034 1035 /* Trigger Input Group 6 - MDMA trigger multiplexer */ 1036 typedef enum 1037 { 1038 TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW0 = 0x00000601u, /* tcpwm[1].tr_overflow[0] */ 1039 TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH0 = 0x00000602u, /* tcpwm[1].tr_compare_match[0] */ 1040 TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW0 = 0x00000603u, /* tcpwm[1].tr_underflow[0] */ 1041 TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW1 = 0x00000604u, /* tcpwm[1].tr_overflow[1] */ 1042 TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH1 = 0x00000605u, /* tcpwm[1].tr_compare_match[1] */ 1043 TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW1 = 0x00000606u, /* tcpwm[1].tr_underflow[1] */ 1044 TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW2 = 0x00000607u, /* tcpwm[1].tr_overflow[2] */ 1045 TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH2 = 0x00000608u, /* tcpwm[1].tr_compare_match[2] */ 1046 TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW2 = 0x00000609u, /* tcpwm[1].tr_underflow[2] */ 1047 TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW3 = 0x0000060Au, /* tcpwm[1].tr_overflow[3] */ 1048 TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH3 = 0x0000060Bu, /* tcpwm[1].tr_compare_match[3] */ 1049 TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW3 = 0x0000060Cu, /* tcpwm[1].tr_underflow[3] */ 1050 TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW4 = 0x0000060Du, /* tcpwm[1].tr_overflow[4] */ 1051 TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH4 = 0x0000060Eu, /* tcpwm[1].tr_compare_match[4] */ 1052 TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW4 = 0x0000060Fu, /* tcpwm[1].tr_underflow[4] */ 1053 TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW5 = 0x00000610u, /* tcpwm[1].tr_overflow[5] */ 1054 TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH5 = 0x00000611u, /* tcpwm[1].tr_compare_match[5] */ 1055 TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW5 = 0x00000612u, /* tcpwm[1].tr_underflow[5] */ 1056 TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW6 = 0x00000613u, /* tcpwm[1].tr_overflow[6] */ 1057 TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH6 = 0x00000614u, /* tcpwm[1].tr_compare_match[6] */ 1058 TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW6 = 0x00000615u, /* tcpwm[1].tr_underflow[6] */ 1059 TRIG_IN_MUX_6_TCPWM1_TR_OVERFLOW7 = 0x00000616u, /* tcpwm[1].tr_overflow[7] */ 1060 TRIG_IN_MUX_6_TCPWM1_TR_COMPARE_MATCH7 = 0x00000617u, /* tcpwm[1].tr_compare_match[7] */ 1061 TRIG_IN_MUX_6_TCPWM1_TR_UNDERFLOW7 = 0x00000618u, /* tcpwm[1].tr_underflow[7] */ 1062 TRIG_IN_MUX_6_SMIF_TX = 0x00000619u, /* smif.tr_tx_req */ 1063 TRIG_IN_MUX_6_SMIF_RX = 0x0000061Au /* smif.tr_rx_req */ 1064 } en_trig_input_mdma_t; 1065 1066 /* Trigger Input Group 7 - PERI Freeze trigger multiplexer */ 1067 typedef enum 1068 { 1069 TRIG_IN_MUX_7_CTI_TR_OUT0 = 0x00000701u, /* cpuss.cti_tr_out[0] */ 1070 TRIG_IN_MUX_7_CTI_TR_OUT1 = 0x00000702u /* cpuss.cti_tr_out[1] */ 1071 } en_trig_input_peri_freeze_t; 1072 1073 /* Trigger Input Group 8 - Capsense trigger multiplexer */ 1074 typedef enum 1075 { 1076 TRIG_IN_MUX_8_TCPWM0_TR_OVERFLOW0 = 0x00000801u, /* tcpwm[0].tr_overflow[0] */ 1077 TRIG_IN_MUX_8_TCPWM0_TR_COMPARE_MATCH0 = 0x00000802u, /* tcpwm[0].tr_compare_match[0] */ 1078 TRIG_IN_MUX_8_TCPWM0_TR_UNDERFLOW0 = 0x00000803u, /* tcpwm[0].tr_underflow[0] */ 1079 TRIG_IN_MUX_8_TCPWM0_TR_OVERFLOW1 = 0x00000804u, /* tcpwm[0].tr_overflow[1] */ 1080 TRIG_IN_MUX_8_TCPWM0_TR_COMPARE_MATCH1 = 0x00000805u, /* tcpwm[0].tr_compare_match[1] */ 1081 TRIG_IN_MUX_8_TCPWM0_TR_UNDERFLOW1 = 0x00000806u, /* tcpwm[0].tr_underflow[1] */ 1082 TRIG_IN_MUX_8_TCPWM0_TR_OVERFLOW2 = 0x00000807u, /* tcpwm[0].tr_overflow[2] */ 1083 TRIG_IN_MUX_8_TCPWM0_TR_COMPARE_MATCH2 = 0x00000808u, /* tcpwm[0].tr_compare_match[2] */ 1084 TRIG_IN_MUX_8_TCPWM0_TR_UNDERFLOW2 = 0x00000809u, /* tcpwm[0].tr_underflow[2] */ 1085 TRIG_IN_MUX_8_TCPWM0_TR_OVERFLOW3 = 0x0000080Au, /* tcpwm[0].tr_overflow[3] */ 1086 TRIG_IN_MUX_8_TCPWM0_TR_COMPARE_MATCH3 = 0x0000080Bu, /* tcpwm[0].tr_compare_match[3] */ 1087 TRIG_IN_MUX_8_TCPWM0_TR_UNDERFLOW3 = 0x0000080Cu, /* tcpwm[0].tr_underflow[3] */ 1088 TRIG_IN_MUX_8_TCPWM0_TR_OVERFLOW4 = 0x0000080Du, /* tcpwm[0].tr_overflow[4] */ 1089 TRIG_IN_MUX_8_TCPWM0_TR_COMPARE_MATCH4 = 0x0000080Eu, /* tcpwm[0].tr_compare_match[4] */ 1090 TRIG_IN_MUX_8_TCPWM0_TR_UNDERFLOW4 = 0x0000080Fu, /* tcpwm[0].tr_underflow[4] */ 1091 TRIG_IN_MUX_8_TCPWM0_TR_OVERFLOW5 = 0x00000810u, /* tcpwm[0].tr_overflow[5] */ 1092 TRIG_IN_MUX_8_TCPWM0_TR_COMPARE_MATCH5 = 0x00000811u, /* tcpwm[0].tr_compare_match[5] */ 1093 TRIG_IN_MUX_8_TCPWM0_TR_UNDERFLOW5 = 0x00000812u, /* tcpwm[0].tr_underflow[5] */ 1094 TRIG_IN_MUX_8_TCPWM0_TR_OVERFLOW6 = 0x00000813u, /* tcpwm[0].tr_overflow[6] */ 1095 TRIG_IN_MUX_8_TCPWM0_TR_COMPARE_MATCH6 = 0x00000814u, /* tcpwm[0].tr_compare_match[6] */ 1096 TRIG_IN_MUX_8_TCPWM0_TR_UNDERFLOW6 = 0x00000815u, /* tcpwm[0].tr_underflow[6] */ 1097 TRIG_IN_MUX_8_TCPWM0_TR_OVERFLOW7 = 0x00000816u, /* tcpwm[0].tr_overflow[7] */ 1098 TRIG_IN_MUX_8_TCPWM0_TR_COMPARE_MATCH7 = 0x00000817u, /* tcpwm[0].tr_compare_match[7] */ 1099 TRIG_IN_MUX_8_TCPWM0_TR_UNDERFLOW7 = 0x00000818u, /* tcpwm[0].tr_underflow[7] */ 1100 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW0 = 0x00000819u, /* tcpwm[1].tr_overflow[0] */ 1101 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH0 = 0x0000081Au, /* tcpwm[1].tr_compare_match[0] */ 1102 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW0 = 0x0000081Bu, /* tcpwm[1].tr_underflow[0] */ 1103 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW1 = 0x0000081Cu, /* tcpwm[1].tr_overflow[1] */ 1104 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH1 = 0x0000081Du, /* tcpwm[1].tr_compare_match[1] */ 1105 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW1 = 0x0000081Eu, /* tcpwm[1].tr_underflow[1] */ 1106 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW2 = 0x0000081Fu, /* tcpwm[1].tr_overflow[2] */ 1107 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH2 = 0x00000820u, /* tcpwm[1].tr_compare_match[2] */ 1108 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW2 = 0x00000821u, /* tcpwm[1].tr_underflow[2] */ 1109 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW3 = 0x00000822u, /* tcpwm[1].tr_overflow[3] */ 1110 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH3 = 0x00000823u, /* tcpwm[1].tr_compare_match[3] */ 1111 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW3 = 0x00000824u, /* tcpwm[1].tr_underflow[3] */ 1112 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW4 = 0x00000825u, /* tcpwm[1].tr_overflow[4] */ 1113 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH4 = 0x00000826u, /* tcpwm[1].tr_compare_match[4] */ 1114 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW4 = 0x00000827u, /* tcpwm[1].tr_underflow[4] */ 1115 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW5 = 0x00000828u, /* tcpwm[1].tr_overflow[5] */ 1116 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH5 = 0x00000829u, /* tcpwm[1].tr_compare_match[5] */ 1117 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW5 = 0x0000082Au, /* tcpwm[1].tr_underflow[5] */ 1118 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW6 = 0x0000082Bu, /* tcpwm[1].tr_overflow[6] */ 1119 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH6 = 0x0000082Cu, /* tcpwm[1].tr_compare_match[6] */ 1120 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW6 = 0x0000082Du, /* tcpwm[1].tr_underflow[6] */ 1121 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW7 = 0x0000082Eu, /* tcpwm[1].tr_overflow[7] */ 1122 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH7 = 0x0000082Fu, /* tcpwm[1].tr_compare_match[7] */ 1123 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW7 = 0x00000830u, /* tcpwm[1].tr_underflow[7] */ 1124 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW8 = 0x00000831u, /* tcpwm[1].tr_overflow[8] */ 1125 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH8 = 0x00000832u, /* tcpwm[1].tr_compare_match[8] */ 1126 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW8 = 0x00000833u, /* tcpwm[1].tr_underflow[8] */ 1127 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW9 = 0x00000834u, /* tcpwm[1].tr_overflow[9] */ 1128 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH9 = 0x00000835u, /* tcpwm[1].tr_compare_match[9] */ 1129 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW9 = 0x00000836u, /* tcpwm[1].tr_underflow[9] */ 1130 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW10 = 0x00000837u, /* tcpwm[1].tr_overflow[10] */ 1131 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH10 = 0x00000838u, /* tcpwm[1].tr_compare_match[10] */ 1132 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW10 = 0x00000839u, /* tcpwm[1].tr_underflow[10] */ 1133 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW11 = 0x0000083Au, /* tcpwm[1].tr_overflow[11] */ 1134 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH11 = 0x0000083Bu, /* tcpwm[1].tr_compare_match[11] */ 1135 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW11 = 0x0000083Cu, /* tcpwm[1].tr_underflow[11] */ 1136 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW12 = 0x0000083Du, /* tcpwm[1].tr_overflow[12] */ 1137 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH12 = 0x0000083Eu, /* tcpwm[1].tr_compare_match[12] */ 1138 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW12 = 0x0000083Fu, /* tcpwm[1].tr_underflow[12] */ 1139 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW13 = 0x00000840u, /* tcpwm[1].tr_overflow[13] */ 1140 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH13 = 0x00000841u, /* tcpwm[1].tr_compare_match[13] */ 1141 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW13 = 0x00000842u, /* tcpwm[1].tr_underflow[13] */ 1142 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW14 = 0x00000843u, /* tcpwm[1].tr_overflow[14] */ 1143 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH14 = 0x00000844u, /* tcpwm[1].tr_compare_match[14] */ 1144 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW14 = 0x00000845u, /* tcpwm[1].tr_underflow[14] */ 1145 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW15 = 0x00000846u, /* tcpwm[1].tr_overflow[15] */ 1146 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH15 = 0x00000847u, /* tcpwm[1].tr_compare_match[15] */ 1147 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW15 = 0x00000848u, /* tcpwm[1].tr_underflow[15] */ 1148 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW16 = 0x00000849u, /* tcpwm[1].tr_overflow[16] */ 1149 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH16 = 0x0000084Au, /* tcpwm[1].tr_compare_match[16] */ 1150 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW16 = 0x0000084Bu, /* tcpwm[1].tr_underflow[16] */ 1151 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW17 = 0x0000084Cu, /* tcpwm[1].tr_overflow[17] */ 1152 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH17 = 0x0000084Du, /* tcpwm[1].tr_compare_match[17] */ 1153 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW17 = 0x0000084Eu, /* tcpwm[1].tr_underflow[17] */ 1154 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW18 = 0x0000084Fu, /* tcpwm[1].tr_overflow[18] */ 1155 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH18 = 0x00000850u, /* tcpwm[1].tr_compare_match[18] */ 1156 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW18 = 0x00000851u, /* tcpwm[1].tr_underflow[18] */ 1157 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW19 = 0x00000852u, /* tcpwm[1].tr_overflow[19] */ 1158 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH19 = 0x00000853u, /* tcpwm[1].tr_compare_match[19] */ 1159 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW19 = 0x00000854u, /* tcpwm[1].tr_underflow[19] */ 1160 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW20 = 0x00000855u, /* tcpwm[1].tr_overflow[20] */ 1161 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH20 = 0x00000856u, /* tcpwm[1].tr_compare_match[20] */ 1162 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW20 = 0x00000857u, /* tcpwm[1].tr_underflow[20] */ 1163 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW21 = 0x00000858u, /* tcpwm[1].tr_overflow[21] */ 1164 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH21 = 0x00000859u, /* tcpwm[1].tr_compare_match[21] */ 1165 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW21 = 0x0000085Au, /* tcpwm[1].tr_underflow[21] */ 1166 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW22 = 0x0000085Bu, /* tcpwm[1].tr_overflow[22] */ 1167 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH22 = 0x0000085Cu, /* tcpwm[1].tr_compare_match[22] */ 1168 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW22 = 0x0000085Du, /* tcpwm[1].tr_underflow[22] */ 1169 TRIG_IN_MUX_8_TCPWM1_TR_OVERFLOW23 = 0x0000085Eu, /* tcpwm[1].tr_overflow[23] */ 1170 TRIG_IN_MUX_8_TCPWM1_TR_COMPARE_MATCH23 = 0x0000085Fu, /* tcpwm[1].tr_compare_match[23] */ 1171 TRIG_IN_MUX_8_TCPWM1_TR_UNDERFLOW23 = 0x00000860u, /* tcpwm[1].tr_underflow[23] */ 1172 TRIG_IN_MUX_8_HSIOM_TR_OUT0 = 0x00000861u, /* peri.tr_io_input[0] */ 1173 TRIG_IN_MUX_8_HSIOM_TR_OUT1 = 0x00000862u, /* peri.tr_io_input[1] */ 1174 TRIG_IN_MUX_8_HSIOM_TR_OUT2 = 0x00000863u, /* peri.tr_io_input[2] */ 1175 TRIG_IN_MUX_8_HSIOM_TR_OUT3 = 0x00000864u, /* peri.tr_io_input[3] */ 1176 TRIG_IN_MUX_8_HSIOM_TR_OUT4 = 0x00000865u, /* peri.tr_io_input[4] */ 1177 TRIG_IN_MUX_8_HSIOM_TR_OUT5 = 0x00000866u, /* peri.tr_io_input[5] */ 1178 TRIG_IN_MUX_8_HSIOM_TR_OUT6 = 0x00000867u, /* peri.tr_io_input[6] */ 1179 TRIG_IN_MUX_8_HSIOM_TR_OUT7 = 0x00000868u, /* peri.tr_io_input[7] */ 1180 TRIG_IN_MUX_8_HSIOM_TR_OUT8 = 0x00000869u, /* peri.tr_io_input[8] */ 1181 TRIG_IN_MUX_8_HSIOM_TR_OUT9 = 0x0000086Au, /* peri.tr_io_input[9] */ 1182 TRIG_IN_MUX_8_HSIOM_TR_OUT10 = 0x0000086Bu, /* peri.tr_io_input[10] */ 1183 TRIG_IN_MUX_8_HSIOM_TR_OUT11 = 0x0000086Cu, /* peri.tr_io_input[11] */ 1184 TRIG_IN_MUX_8_HSIOM_TR_OUT12 = 0x0000086Du, /* peri.tr_io_input[12] */ 1185 TRIG_IN_MUX_8_HSIOM_TR_OUT13 = 0x0000086Eu, /* peri.tr_io_input[13] */ 1186 TRIG_IN_MUX_8_HSIOM_TR_OUT14 = 0x0000086Fu, /* peri.tr_io_input[14] */ 1187 TRIG_IN_MUX_8_HSIOM_TR_OUT15 = 0x00000870u, /* peri.tr_io_input[15] */ 1188 TRIG_IN_MUX_8_HSIOM_TR_OUT16 = 0x00000871u, /* peri.tr_io_input[16] */ 1189 TRIG_IN_MUX_8_HSIOM_TR_OUT17 = 0x00000872u, /* peri.tr_io_input[17] */ 1190 TRIG_IN_MUX_8_HSIOM_TR_OUT18 = 0x00000873u, /* peri.tr_io_input[18] */ 1191 TRIG_IN_MUX_8_HSIOM_TR_OUT19 = 0x00000874u, /* peri.tr_io_input[19] */ 1192 TRIG_IN_MUX_8_HSIOM_TR_OUT20 = 0x00000875u, /* peri.tr_io_input[20] */ 1193 TRIG_IN_MUX_8_HSIOM_TR_OUT21 = 0x00000876u, /* peri.tr_io_input[21] */ 1194 TRIG_IN_MUX_8_HSIOM_TR_OUT22 = 0x00000877u, /* peri.tr_io_input[22] */ 1195 TRIG_IN_MUX_8_HSIOM_TR_OUT23 = 0x00000878u, /* peri.tr_io_input[23] */ 1196 TRIG_IN_MUX_8_HSIOM_TR_OUT24 = 0x00000879u, /* peri.tr_io_input[24] */ 1197 TRIG_IN_MUX_8_HSIOM_TR_OUT25 = 0x0000087Au, /* peri.tr_io_input[25] */ 1198 TRIG_IN_MUX_8_HSIOM_TR_OUT26 = 0x0000087Bu, /* peri.tr_io_input[26] */ 1199 TRIG_IN_MUX_8_HSIOM_TR_OUT27 = 0x0000087Cu, /* peri.tr_io_input[27] */ 1200 TRIG_IN_MUX_8_LPCOMP_DSI_COMP0 = 0x0000087Du, /* lpcomp.dsi_comp0 */ 1201 TRIG_IN_MUX_8_LPCOMP_DSI_COMP1 = 0x0000087Eu /* lpcomp.dsi_comp1 */ 1202 } en_trig_input_csd_t; 1203 1204 /* Trigger Input Group 9 - ADC trigger multiplexer */ 1205 typedef enum 1206 { 1207 TRIG_IN_MUX_9_TCPWM0_TR_OVERFLOW0 = 0x00000901u, /* tcpwm[0].tr_overflow[0] */ 1208 TRIG_IN_MUX_9_TCPWM0_TR_COMPARE_MATCH0 = 0x00000902u, /* tcpwm[0].tr_compare_match[0] */ 1209 TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW0 = 0x00000903u, /* tcpwm[0].tr_underflow[0] */ 1210 TRIG_IN_MUX_9_TCPWM0_TR_OVERFLOW1 = 0x00000904u, /* tcpwm[0].tr_overflow[1] */ 1211 TRIG_IN_MUX_9_TCPWM0_TR_COMPARE_MATCH1 = 0x00000905u, /* tcpwm[0].tr_compare_match[1] */ 1212 TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW1 = 0x00000906u, /* tcpwm[0].tr_underflow[1] */ 1213 TRIG_IN_MUX_9_TCPWM0_TR_OVERFLOW2 = 0x00000907u, /* tcpwm[0].tr_overflow[2] */ 1214 TRIG_IN_MUX_9_TCPWM0_TR_COMPARE_MATCH2 = 0x00000908u, /* tcpwm[0].tr_compare_match[2] */ 1215 TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW2 = 0x00000909u, /* tcpwm[0].tr_underflow[2] */ 1216 TRIG_IN_MUX_9_TCPWM0_TR_OVERFLOW3 = 0x0000090Au, /* tcpwm[0].tr_overflow[3] */ 1217 TRIG_IN_MUX_9_TCPWM0_TR_COMPARE_MATCH3 = 0x0000090Bu, /* tcpwm[0].tr_compare_match[3] */ 1218 TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW3 = 0x0000090Cu, /* tcpwm[0].tr_underflow[3] */ 1219 TRIG_IN_MUX_9_TCPWM0_TR_OVERFLOW4 = 0x0000090Du, /* tcpwm[0].tr_overflow[4] */ 1220 TRIG_IN_MUX_9_TCPWM0_TR_COMPARE_MATCH4 = 0x0000090Eu, /* tcpwm[0].tr_compare_match[4] */ 1221 TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW4 = 0x0000090Fu, /* tcpwm[0].tr_underflow[4] */ 1222 TRIG_IN_MUX_9_TCPWM0_TR_OVERFLOW5 = 0x00000910u, /* tcpwm[0].tr_overflow[5] */ 1223 TRIG_IN_MUX_9_TCPWM0_TR_COMPARE_MATCH5 = 0x00000911u, /* tcpwm[0].tr_compare_match[5] */ 1224 TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW5 = 0x00000912u, /* tcpwm[0].tr_underflow[5] */ 1225 TRIG_IN_MUX_9_TCPWM0_TR_OVERFLOW6 = 0x00000913u, /* tcpwm[0].tr_overflow[6] */ 1226 TRIG_IN_MUX_9_TCPWM0_TR_COMPARE_MATCH6 = 0x00000914u, /* tcpwm[0].tr_compare_match[6] */ 1227 TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW6 = 0x00000915u, /* tcpwm[0].tr_underflow[6] */ 1228 TRIG_IN_MUX_9_TCPWM0_TR_OVERFLOW7 = 0x00000916u, /* tcpwm[0].tr_overflow[7] */ 1229 TRIG_IN_MUX_9_TCPWM0_TR_COMPARE_MATCH7 = 0x00000917u, /* tcpwm[0].tr_compare_match[7] */ 1230 TRIG_IN_MUX_9_TCPWM0_TR_UNDERFLOW7 = 0x00000918u, /* tcpwm[0].tr_underflow[7] */ 1231 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW0 = 0x00000919u, /* tcpwm[1].tr_overflow[0] */ 1232 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH0 = 0x0000091Au, /* tcpwm[1].tr_compare_match[0] */ 1233 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW0 = 0x0000091Bu, /* tcpwm[1].tr_underflow[0] */ 1234 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW1 = 0x0000091Cu, /* tcpwm[1].tr_overflow[1] */ 1235 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH1 = 0x0000091Du, /* tcpwm[1].tr_compare_match[1] */ 1236 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW1 = 0x0000091Eu, /* tcpwm[1].tr_underflow[1] */ 1237 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW2 = 0x0000091Fu, /* tcpwm[1].tr_overflow[2] */ 1238 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH2 = 0x00000920u, /* tcpwm[1].tr_compare_match[2] */ 1239 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW2 = 0x00000921u, /* tcpwm[1].tr_underflow[2] */ 1240 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW3 = 0x00000922u, /* tcpwm[1].tr_overflow[3] */ 1241 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH3 = 0x00000923u, /* tcpwm[1].tr_compare_match[3] */ 1242 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW3 = 0x00000924u, /* tcpwm[1].tr_underflow[3] */ 1243 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW4 = 0x00000925u, /* tcpwm[1].tr_overflow[4] */ 1244 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH4 = 0x00000926u, /* tcpwm[1].tr_compare_match[4] */ 1245 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW4 = 0x00000927u, /* tcpwm[1].tr_underflow[4] */ 1246 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW5 = 0x00000928u, /* tcpwm[1].tr_overflow[5] */ 1247 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH5 = 0x00000929u, /* tcpwm[1].tr_compare_match[5] */ 1248 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW5 = 0x0000092Au, /* tcpwm[1].tr_underflow[5] */ 1249 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW6 = 0x0000092Bu, /* tcpwm[1].tr_overflow[6] */ 1250 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH6 = 0x0000092Cu, /* tcpwm[1].tr_compare_match[6] */ 1251 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW6 = 0x0000092Du, /* tcpwm[1].tr_underflow[6] */ 1252 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW7 = 0x0000092Eu, /* tcpwm[1].tr_overflow[7] */ 1253 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH7 = 0x0000092Fu, /* tcpwm[1].tr_compare_match[7] */ 1254 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW7 = 0x00000930u, /* tcpwm[1].tr_underflow[7] */ 1255 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW8 = 0x00000931u, /* tcpwm[1].tr_overflow[8] */ 1256 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH8 = 0x00000932u, /* tcpwm[1].tr_compare_match[8] */ 1257 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW8 = 0x00000933u, /* tcpwm[1].tr_underflow[8] */ 1258 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW9 = 0x00000934u, /* tcpwm[1].tr_overflow[9] */ 1259 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH9 = 0x00000935u, /* tcpwm[1].tr_compare_match[9] */ 1260 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW9 = 0x00000936u, /* tcpwm[1].tr_underflow[9] */ 1261 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW10 = 0x00000937u, /* tcpwm[1].tr_overflow[10] */ 1262 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH10 = 0x00000938u, /* tcpwm[1].tr_compare_match[10] */ 1263 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW10 = 0x00000939u, /* tcpwm[1].tr_underflow[10] */ 1264 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW11 = 0x0000093Au, /* tcpwm[1].tr_overflow[11] */ 1265 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH11 = 0x0000093Bu, /* tcpwm[1].tr_compare_match[11] */ 1266 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW11 = 0x0000093Cu, /* tcpwm[1].tr_underflow[11] */ 1267 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW12 = 0x0000093Du, /* tcpwm[1].tr_overflow[12] */ 1268 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH12 = 0x0000093Eu, /* tcpwm[1].tr_compare_match[12] */ 1269 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW12 = 0x0000093Fu, /* tcpwm[1].tr_underflow[12] */ 1270 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW13 = 0x00000940u, /* tcpwm[1].tr_overflow[13] */ 1271 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH13 = 0x00000941u, /* tcpwm[1].tr_compare_match[13] */ 1272 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW13 = 0x00000942u, /* tcpwm[1].tr_underflow[13] */ 1273 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW14 = 0x00000943u, /* tcpwm[1].tr_overflow[14] */ 1274 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH14 = 0x00000944u, /* tcpwm[1].tr_compare_match[14] */ 1275 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW14 = 0x00000945u, /* tcpwm[1].tr_underflow[14] */ 1276 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW15 = 0x00000946u, /* tcpwm[1].tr_overflow[15] */ 1277 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH15 = 0x00000947u, /* tcpwm[1].tr_compare_match[15] */ 1278 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW15 = 0x00000948u, /* tcpwm[1].tr_underflow[15] */ 1279 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW16 = 0x00000949u, /* tcpwm[1].tr_overflow[16] */ 1280 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH16 = 0x0000094Au, /* tcpwm[1].tr_compare_match[16] */ 1281 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW16 = 0x0000094Bu, /* tcpwm[1].tr_underflow[16] */ 1282 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW17 = 0x0000094Cu, /* tcpwm[1].tr_overflow[17] */ 1283 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH17 = 0x0000094Du, /* tcpwm[1].tr_compare_match[17] */ 1284 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW17 = 0x0000094Eu, /* tcpwm[1].tr_underflow[17] */ 1285 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW18 = 0x0000094Fu, /* tcpwm[1].tr_overflow[18] */ 1286 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH18 = 0x00000950u, /* tcpwm[1].tr_compare_match[18] */ 1287 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW18 = 0x00000951u, /* tcpwm[1].tr_underflow[18] */ 1288 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW19 = 0x00000952u, /* tcpwm[1].tr_overflow[19] */ 1289 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH19 = 0x00000953u, /* tcpwm[1].tr_compare_match[19] */ 1290 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW19 = 0x00000954u, /* tcpwm[1].tr_underflow[19] */ 1291 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW20 = 0x00000955u, /* tcpwm[1].tr_overflow[20] */ 1292 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH20 = 0x00000956u, /* tcpwm[1].tr_compare_match[20] */ 1293 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW20 = 0x00000957u, /* tcpwm[1].tr_underflow[20] */ 1294 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW21 = 0x00000958u, /* tcpwm[1].tr_overflow[21] */ 1295 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH21 = 0x00000959u, /* tcpwm[1].tr_compare_match[21] */ 1296 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW21 = 0x0000095Au, /* tcpwm[1].tr_underflow[21] */ 1297 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW22 = 0x0000095Bu, /* tcpwm[1].tr_overflow[22] */ 1298 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH22 = 0x0000095Cu, /* tcpwm[1].tr_compare_match[22] */ 1299 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW22 = 0x0000095Du, /* tcpwm[1].tr_underflow[22] */ 1300 TRIG_IN_MUX_9_TCPWM1_TR_OVERFLOW23 = 0x0000095Eu, /* tcpwm[1].tr_overflow[23] */ 1301 TRIG_IN_MUX_9_TCPWM1_TR_COMPARE_MATCH23 = 0x0000095Fu, /* tcpwm[1].tr_compare_match[23] */ 1302 TRIG_IN_MUX_9_TCPWM1_TR_UNDERFLOW23 = 0x00000960u, /* tcpwm[1].tr_underflow[23] */ 1303 TRIG_IN_MUX_9_HSIOM_TR_OUT0 = 0x00000961u, /* peri.tr_io_input[0] */ 1304 TRIG_IN_MUX_9_HSIOM_TR_OUT1 = 0x00000962u, /* peri.tr_io_input[1] */ 1305 TRIG_IN_MUX_9_HSIOM_TR_OUT2 = 0x00000963u, /* peri.tr_io_input[2] */ 1306 TRIG_IN_MUX_9_HSIOM_TR_OUT3 = 0x00000964u, /* peri.tr_io_input[3] */ 1307 TRIG_IN_MUX_9_HSIOM_TR_OUT4 = 0x00000965u, /* peri.tr_io_input[4] */ 1308 TRIG_IN_MUX_9_HSIOM_TR_OUT5 = 0x00000966u, /* peri.tr_io_input[5] */ 1309 TRIG_IN_MUX_9_HSIOM_TR_OUT6 = 0x00000967u, /* peri.tr_io_input[6] */ 1310 TRIG_IN_MUX_9_HSIOM_TR_OUT7 = 0x00000968u, /* peri.tr_io_input[7] */ 1311 TRIG_IN_MUX_9_HSIOM_TR_OUT8 = 0x00000969u, /* peri.tr_io_input[8] */ 1312 TRIG_IN_MUX_9_HSIOM_TR_OUT9 = 0x0000096Au, /* peri.tr_io_input[9] */ 1313 TRIG_IN_MUX_9_HSIOM_TR_OUT10 = 0x0000096Bu, /* peri.tr_io_input[10] */ 1314 TRIG_IN_MUX_9_HSIOM_TR_OUT11 = 0x0000096Cu, /* peri.tr_io_input[11] */ 1315 TRIG_IN_MUX_9_HSIOM_TR_OUT12 = 0x0000096Du, /* peri.tr_io_input[12] */ 1316 TRIG_IN_MUX_9_HSIOM_TR_OUT13 = 0x0000096Eu, /* peri.tr_io_input[13] */ 1317 TRIG_IN_MUX_9_HSIOM_TR_OUT14 = 0x0000096Fu, /* peri.tr_io_input[14] */ 1318 TRIG_IN_MUX_9_HSIOM_TR_OUT15 = 0x00000970u, /* peri.tr_io_input[15] */ 1319 TRIG_IN_MUX_9_HSIOM_TR_OUT16 = 0x00000971u, /* peri.tr_io_input[16] */ 1320 TRIG_IN_MUX_9_HSIOM_TR_OUT17 = 0x00000972u, /* peri.tr_io_input[17] */ 1321 TRIG_IN_MUX_9_HSIOM_TR_OUT18 = 0x00000973u, /* peri.tr_io_input[18] */ 1322 TRIG_IN_MUX_9_HSIOM_TR_OUT19 = 0x00000974u, /* peri.tr_io_input[19] */ 1323 TRIG_IN_MUX_9_HSIOM_TR_OUT20 = 0x00000975u, /* peri.tr_io_input[20] */ 1324 TRIG_IN_MUX_9_HSIOM_TR_OUT21 = 0x00000976u, /* peri.tr_io_input[21] */ 1325 TRIG_IN_MUX_9_HSIOM_TR_OUT22 = 0x00000977u, /* peri.tr_io_input[22] */ 1326 TRIG_IN_MUX_9_HSIOM_TR_OUT23 = 0x00000978u, /* peri.tr_io_input[23] */ 1327 TRIG_IN_MUX_9_HSIOM_TR_OUT24 = 0x00000979u, /* peri.tr_io_input[24] */ 1328 TRIG_IN_MUX_9_HSIOM_TR_OUT25 = 0x0000097Au, /* peri.tr_io_input[25] */ 1329 TRIG_IN_MUX_9_HSIOM_TR_OUT26 = 0x0000097Bu, /* peri.tr_io_input[26] */ 1330 TRIG_IN_MUX_9_HSIOM_TR_OUT27 = 0x0000097Cu, /* peri.tr_io_input[27] */ 1331 TRIG_IN_MUX_9_LPCOMP_DSI_COMP0 = 0x0000097Du, /* lpcomp.dsi_comp0 */ 1332 TRIG_IN_MUX_9_LPCOMP_DSI_COMP1 = 0x0000097Eu /* lpcomp.dsi_comp1 */ 1333 } en_trig_input_sar_adc_start_t; 1334 1335 /* Trigger Group Outputs */ 1336 /* Trigger Output Group 0 - P-DMA0 Request Assignments */ 1337 typedef enum 1338 { 1339 TRIG_OUT_MUX_0_PDMA0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ 1340 TRIG_OUT_MUX_0_PDMA0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ 1341 TRIG_OUT_MUX_0_PDMA0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ 1342 TRIG_OUT_MUX_0_PDMA0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */ 1343 TRIG_OUT_MUX_0_PDMA0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */ 1344 TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ 1345 TRIG_OUT_MUX_0_PDMA0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */ 1346 TRIG_OUT_MUX_0_PDMA0_TR_IN7 = 0x40000007u /* cpuss.dw0_tr_in[7] */ 1347 } en_trig_output_pdma0_tr_t; 1348 1349 /* Trigger Output Group 1 - P-DMA1 Request Assignments */ 1350 typedef enum 1351 { 1352 TRIG_OUT_MUX_1_PDMA1_TR_IN0 = 0x40000100u, /* cpuss.dw1_tr_in[0] */ 1353 TRIG_OUT_MUX_1_PDMA1_TR_IN1 = 0x40000101u, /* cpuss.dw1_tr_in[1] */ 1354 TRIG_OUT_MUX_1_PDMA1_TR_IN2 = 0x40000102u, /* cpuss.dw1_tr_in[2] */ 1355 TRIG_OUT_MUX_1_PDMA1_TR_IN3 = 0x40000103u, /* cpuss.dw1_tr_in[3] */ 1356 TRIG_OUT_MUX_1_PDMA1_TR_IN4 = 0x40000104u, /* cpuss.dw1_tr_in[4] */ 1357 TRIG_OUT_MUX_1_PDMA1_TR_IN5 = 0x40000105u, /* cpuss.dw1_tr_in[5] */ 1358 TRIG_OUT_MUX_1_PDMA1_TR_IN6 = 0x40000106u, /* cpuss.dw1_tr_in[6] */ 1359 TRIG_OUT_MUX_1_PDMA1_TR_IN7 = 0x40000107u /* cpuss.dw1_tr_in[7] */ 1360 } en_trig_output_pdma1_tr_t; 1361 1362 /* Trigger Output Group 2 - TCPWM0 trigger multiplexer */ 1363 typedef enum 1364 { 1365 TRIG_OUT_MUX_2_TCPWM0_TR_IN0 = 0x40000200u, /* tcpwm[0].tr_in[0] */ 1366 TRIG_OUT_MUX_2_TCPWM0_TR_IN1 = 0x40000201u, /* tcpwm[0].tr_in[1] */ 1367 TRIG_OUT_MUX_2_TCPWM0_TR_IN2 = 0x40000202u, /* tcpwm[0].tr_in[2] */ 1368 TRIG_OUT_MUX_2_TCPWM0_TR_IN3 = 0x40000203u, /* tcpwm[0].tr_in[3] */ 1369 TRIG_OUT_MUX_2_TCPWM0_TR_IN4 = 0x40000204u, /* tcpwm[0].tr_in[4] */ 1370 TRIG_OUT_MUX_2_TCPWM0_TR_IN5 = 0x40000205u, /* tcpwm[0].tr_in[5] */ 1371 TRIG_OUT_MUX_2_TCPWM0_TR_IN6 = 0x40000206u, /* tcpwm[0].tr_in[6] */ 1372 TRIG_OUT_MUX_2_TCPWM0_TR_IN7 = 0x40000207u, /* tcpwm[0].tr_in[7] */ 1373 TRIG_OUT_MUX_2_TCPWM0_TR_IN8 = 0x40000208u, /* tcpwm[0].tr_in[8] */ 1374 TRIG_OUT_MUX_2_TCPWM0_TR_IN9 = 0x40000209u, /* tcpwm[0].tr_in[9] */ 1375 TRIG_OUT_MUX_2_TCPWM0_TR_IN10 = 0x4000020Au, /* tcpwm[0].tr_in[10] */ 1376 TRIG_OUT_MUX_2_TCPWM0_TR_IN11 = 0x4000020Bu, /* tcpwm[0].tr_in[11] */ 1377 TRIG_OUT_MUX_2_TCPWM0_TR_IN12 = 0x4000020Cu, /* tcpwm[0].tr_in[12] */ 1378 TRIG_OUT_MUX_2_TCPWM0_TR_IN13 = 0x4000020Du /* tcpwm[0].tr_in[13] */ 1379 } en_trig_output_tcpwm0_t; 1380 1381 /* Trigger Output Group 3 - TCPWM1 trigger multiplexer */ 1382 typedef enum 1383 { 1384 TRIG_OUT_MUX_3_TCPWM1_TR_IN0 = 0x40000300u, /* tcpwm[1].tr_in[0] */ 1385 TRIG_OUT_MUX_3_TCPWM1_TR_IN1 = 0x40000301u, /* tcpwm[1].tr_in[1] */ 1386 TRIG_OUT_MUX_3_TCPWM1_TR_IN2 = 0x40000302u, /* tcpwm[1].tr_in[2] */ 1387 TRIG_OUT_MUX_3_TCPWM1_TR_IN3 = 0x40000303u, /* tcpwm[1].tr_in[3] */ 1388 TRIG_OUT_MUX_3_TCPWM1_TR_IN4 = 0x40000304u, /* tcpwm[1].tr_in[4] */ 1389 TRIG_OUT_MUX_3_TCPWM1_TR_IN5 = 0x40000305u, /* tcpwm[1].tr_in[5] */ 1390 TRIG_OUT_MUX_3_TCPWM1_TR_IN6 = 0x40000306u, /* tcpwm[1].tr_in[6] */ 1391 TRIG_OUT_MUX_3_TCPWM1_TR_IN7 = 0x40000307u, /* tcpwm[1].tr_in[7] */ 1392 TRIG_OUT_MUX_3_TCPWM1_TR_IN8 = 0x40000308u, /* tcpwm[1].tr_in[8] */ 1393 TRIG_OUT_MUX_3_TCPWM1_TR_IN9 = 0x40000309u, /* tcpwm[1].tr_in[9] */ 1394 TRIG_OUT_MUX_3_TCPWM1_TR_IN10 = 0x4000030Au, /* tcpwm[1].tr_in[10] */ 1395 TRIG_OUT_MUX_3_TCPWM1_TR_IN11 = 0x4000030Bu, /* tcpwm[1].tr_in[11] */ 1396 TRIG_OUT_MUX_3_TCPWM1_TR_IN12 = 0x4000030Cu, /* tcpwm[1].tr_in[12] */ 1397 TRIG_OUT_MUX_3_TCPWM1_TR_IN13 = 0x4000030Du /* tcpwm[1].tr_in[13] */ 1398 } en_trig_output_tcpwm1_t; 1399 1400 /* Trigger Output Group 4 - HSIOM trigger multiplexer */ 1401 typedef enum 1402 { 1403 TRIG_OUT_MUX_4_HSIOM_TR_IO_OUTPUT0 = 0x40000400u, /* peri.tr_io_output[0] */ 1404 TRIG_OUT_MUX_4_HSIOM_TR_IO_OUTPUT1 = 0x40000401u /* peri.tr_io_output[1] */ 1405 } en_trig_output_hsiom_t; 1406 1407 /* Trigger Output Group 5 - CPUSS Debug and Profiler trigger multiplexer */ 1408 typedef enum 1409 { 1410 TRIG_OUT_MUX_5_CPUSS_CTI_TR_IN0 = 0x40000500u, /* cpuss.cti_tr_in[0] */ 1411 TRIG_OUT_MUX_5_CPUSS_CTI_TR_IN1 = 0x40000501u, /* cpuss.cti_tr_in[1] */ 1412 TRIG_OUT_MUX_5_PROFILE_TR_START = 0x40000502u, /* profile.tr_start */ 1413 TRIG_OUT_MUX_5_PROFILE_TR_STOP = 0x40000503u /* profile.tr_stop */ 1414 } en_trig_output_cpuss_cti_t; 1415 1416 /* Trigger Output Group 6 - MDMA trigger multiplexer */ 1417 typedef enum 1418 { 1419 TRIG_OUT_MUX_6_MDMA_TR_IN0 = 0x40000600u, /* cpuss.dmac_tr_in[0] */ 1420 TRIG_OUT_MUX_6_MDMA_TR_IN1 = 0x40000601u, /* cpuss.dmac_tr_in[1] */ 1421 TRIG_OUT_MUX_6_MDMA_TR_IN2 = 0x40000602u, /* cpuss.dmac_tr_in[2] */ 1422 TRIG_OUT_MUX_6_MDMA_TR_IN3 = 0x40000603u /* cpuss.dmac_tr_in[3] */ 1423 } en_trig_output_mdma_t; 1424 1425 /* Trigger Output Group 7 - PERI Freeze trigger multiplexer */ 1426 typedef enum 1427 { 1428 TRIG_OUT_MUX_7_DEBUG_FREEZE_TR_IN = 0x40000700u /* peri.tr_dbg_freeze */ 1429 } en_trig_output_peri_freeze_t; 1430 1431 /* Trigger Output Group 8 - Capsense trigger multiplexer */ 1432 typedef enum 1433 { 1434 TRIG_OUT_MUX_8_CSD_DSI_START = 0x40000800u /* csd.dsi_start */ 1435 } en_trig_output_csd_t; 1436 1437 /* Trigger Output Group 9 - ADC trigger multiplexer */ 1438 typedef enum 1439 { 1440 TRIG_OUT_MUX_9_PASS_TR_SAR_IN = 0x40000900u /* pass.tr_sar_in */ 1441 } en_trig_output_sar_adc_start_t; 1442 1443 /* Trigger Output Group 0 - SCB PDMA0 Triggers (OneToOne) */ 1444 typedef enum 1445 { 1446 TRIG_OUT_1TO1_0_SCB0_TX_TO_PDMA0_TR_IN16 = 0x40001000u, /* From scb[0].tr_tx_req to cpuss.dw0_tr_in[16] */ 1447 TRIG_OUT_1TO1_0_SCB0_RX_TO_PDMA0_TR_IN17 = 0x40001001u, /* From scb[0].tr_rx_req to cpuss.dw0_tr_in[17] */ 1448 TRIG_OUT_1TO1_0_SCB1_TX_TO_PDMA0_TR_IN18 = 0x40001002u, /* From scb[1].tr_tx_req to cpuss.dw0_tr_in[18] */ 1449 TRIG_OUT_1TO1_0_SCB1_RX_TO_PDMA0_TR_IN19 = 0x40001003u, /* From scb[1].tr_rx_req to cpuss.dw0_tr_in[19] */ 1450 TRIG_OUT_1TO1_0_SCB2_TX_TO_PDMA0_TR_IN20 = 0x40001004u, /* From scb[2].tr_tx_req to cpuss.dw0_tr_in[20] */ 1451 TRIG_OUT_1TO1_0_SCB2_RX_TO_PDMA0_TR_IN21 = 0x40001005u, /* From scb[2].tr_rx_req to cpuss.dw0_tr_in[21] */ 1452 TRIG_OUT_1TO1_0_SCB3_TX_TO_PDMA0_TR_IN22 = 0x40001006u, /* From scb[3].tr_tx_req to cpuss.dw0_tr_in[22] */ 1453 TRIG_OUT_1TO1_0_SCB3_RX_TO_PDMA0_TR_IN23 = 0x40001007u, /* From scb[3].tr_rx_req to cpuss.dw0_tr_in[23] */ 1454 TRIG_OUT_1TO1_0_SCB4_TX_TO_PDMA0_TR_IN24 = 0x40001008u, /* From scb[4].tr_tx_req to cpuss.dw0_tr_in[24] */ 1455 TRIG_OUT_1TO1_0_SCB4_RX_TO_PDMA0_TR_IN25 = 0x40001009u, /* From scb[4].tr_rx_req to cpuss.dw0_tr_in[25] */ 1456 TRIG_OUT_1TO1_0_SCB5_TX_TO_PDMA0_TR_IN26 = 0x4000100Au, /* From scb[5].tr_tx_req to cpuss.dw0_tr_in[26] */ 1457 TRIG_OUT_1TO1_0_SCB5_RX_TO_PDMA0_TR_IN27 = 0x4000100Bu /* From scb[5].tr_rx_req to cpuss.dw0_tr_in[27] */ 1458 } en_trig_output_1to1_scb_pdma0_tr_t; 1459 1460 /* Trigger Output Group 1 - SCB PDMA1 Triggers (OneToOne) */ 1461 typedef enum 1462 { 1463 TRIG_OUT_1TO1_1_SCB6_TX_TO_PDMA1_TR_IN8 = 0x40001100u, /* From scb[6].tr_tx_req to cpuss.dw1_tr_in[8] */ 1464 TRIG_OUT_1TO1_1_SCB6_RX_TO_PDMA1_TR_IN9 = 0x40001101u, /* From scb[6].tr_rx_req to cpuss.dw1_tr_in[9] */ 1465 TRIG_OUT_1TO1_1_SCB7_TX_TO_PDMA1_TR_IN10 = 0x40001102u, /* From scb[7].tr_tx_req to cpuss.dw1_tr_in[10] */ 1466 TRIG_OUT_1TO1_1_SCB7_RX_TO_PDMA1_TR_IN11 = 0x40001103u, /* From scb[7].tr_rx_req to cpuss.dw1_tr_in[11] */ 1467 TRIG_OUT_1TO1_1_SCB8_TX_TO_PDMA1_TR_IN12 = 0x40001104u, /* From scb[8].tr_tx_req to cpuss.dw1_tr_in[12] */ 1468 TRIG_OUT_1TO1_1_SCB8_RX_TO_PDMA1_TR_IN13 = 0x40001105u, /* From scb[8].tr_rx_req to cpuss.dw1_tr_in[13] */ 1469 TRIG_OUT_1TO1_1_SCB9_TX_TO_PDMA1_TR_IN14 = 0x40001106u, /* From scb[9].tr_tx_req to cpuss.dw1_tr_in[14] */ 1470 TRIG_OUT_1TO1_1_SCB9_RX_TO_PDMA1_TR_IN15 = 0x40001107u, /* From scb[9].tr_rx_req to cpuss.dw1_tr_in[15] */ 1471 TRIG_OUT_1TO1_1_SCB10_TX_TO_PDMA1_TR_IN16 = 0x40001108u, /* From scb[10].tr_tx_req to cpuss.dw1_tr_in[16] */ 1472 TRIG_OUT_1TO1_1_SCB10_RX_TO_PDMA1_TR_IN17 = 0x40001109u, /* From scb[10].tr_rx_req to cpuss.dw1_tr_in[17] */ 1473 TRIG_OUT_1TO1_1_SCB11_TX_TO_PDMA1_TR_IN18 = 0x4000110Au, /* From scb[11].tr_tx_req to cpuss.dw1_tr_in[18] */ 1474 TRIG_OUT_1TO1_1_SCB11_RX_TO_PDMA1_TR_IN19 = 0x4000110Bu, /* From scb[11].tr_rx_req to cpuss.dw1_tr_in[19] */ 1475 TRIG_OUT_1TO1_1_SCB12_TX_TO_PDMA1_TR_IN20 = 0x4000110Cu, /* From scb[12].tr_tx_req to cpuss.dw1_tr_in[20] */ 1476 TRIG_OUT_1TO1_1_SCB12_RX_TO_PDMA1_TR_IN21 = 0x4000110Du /* From scb[12].tr_rx_req to cpuss.dw1_tr_in[21] */ 1477 } en_trig_output_1to1_scb_pdma1_tr_t; 1478 1479 /* Trigger Output Group 2 - PASS to PDMA0 direct connect (OneToOne) */ 1480 typedef enum 1481 { 1482 TRIG_OUT_1TO1_2_PASS_SAR_DONE_TO_PDMA0_TR_IN28 = 0x40001200u /* From pass.tr_sar_out to cpuss.dw0_tr_in[28] */ 1483 } en_trig_output_1to1_sar_to_pdma0_t; 1484 1485 /* Trigger Output Group 3 - (OneToOne) */ 1486 typedef enum 1487 { 1488 TRIG_OUT_1TO1_3_SMIF_TX_TO_PDMA1_TR_IN22 = 0x40001300u, /* From smif.tr_tx_req to cpuss.dw1_tr_in[22] */ 1489 TRIG_OUT_1TO1_3_SMIF_RX_TO_PDMA1_TR_IN23 = 0x40001301u /* From smif.tr_rx_req to cpuss.dw1_tr_in[23] */ 1490 } en_trig_output_1to1_smif_to_pdma1_t; 1491 1492 /* Trigger Output Group 4 - I2S and PDM PDMA triggers (OneToOne) */ 1493 typedef enum 1494 { 1495 TRIG_OUT_1TO1_4_I2S0_TX_TO_PDMA1_TR_IN24 = 0x40001400u, /* From audioss[0].tr_i2s_tx_req to cpuss.dw1_tr_in[24] */ 1496 TRIG_OUT_1TO1_4_I2S0_RX_TO_PDMA1_TR_IN25 = 0x40001401u, /* From audioss[0].tr_i2s_rx_req to cpuss.dw1_tr_in[25] */ 1497 TRIG_OUT_1TO1_4_PDM0_RX_TO_PDMA1_TR_IN26 = 0x40001402u, /* From audioss[0].tr_pdm_rx_req to cpuss.dw1_tr_in[26] */ 1498 TRIG_OUT_1TO1_4_I2S1_TX_TO_PDMA1_TR_IN27 = 0x40001403u, /* From audioss[1].tr_i2s_tx_req to cpuss.dw1_tr_in[27] */ 1499 TRIG_OUT_1TO1_4_I2S1_RX_TO_PDMA1_TR_IN28 = 0x40001404u /* From audioss[1].tr_i2s_rx_req to cpuss.dw1_tr_in[28] */ 1500 } en_trig_output_1to1_audioss_pdma1_tr_t; 1501 1502 /* Trigger Output Group 5 - USB PDMA0 Triggers (OneToOne) */ 1503 typedef enum 1504 { 1505 TRIG_OUT_1TO1_5_USB_DMA0_TO_PDMA0_TR_IN8 = 0x40001500u, /* From usb.dma_req[0] to cpuss.dw0_tr_in[8] */ 1506 TRIG_OUT_1TO1_5_USB_DMA1_TO_PDMA0_TR_IN9 = 0x40001501u, /* From usb.dma_req[1] to cpuss.dw0_tr_in[9] */ 1507 TRIG_OUT_1TO1_5_USB_DMA2_TO_PDMA0_TR_IN10 = 0x40001502u, /* From usb.dma_req[2] to cpuss.dw0_tr_in[10] */ 1508 TRIG_OUT_1TO1_5_USB_DMA3_TO_PDMA0_TR_IN11 = 0x40001503u, /* From usb.dma_req[3] to cpuss.dw0_tr_in[11] */ 1509 TRIG_OUT_1TO1_5_USB_DMA4_TO_PDMA0_TR_IN12 = 0x40001504u, /* From usb.dma_req[4] to cpuss.dw0_tr_in[12] */ 1510 TRIG_OUT_1TO1_5_USB_DMA5_TO_PDMA0_TR_IN13 = 0x40001505u, /* From usb.dma_req[5] to cpuss.dw0_tr_in[13] */ 1511 TRIG_OUT_1TO1_5_USB_DMA6_TO_PDMA0_TR_IN14 = 0x40001506u, /* From usb.dma_req[6] to cpuss.dw0_tr_in[14] */ 1512 TRIG_OUT_1TO1_5_USB_DMA7_TO_PDMA0_TR_IN15 = 0x40001507u /* From usb.dma_req[7] to cpuss.dw0_tr_in[15] */ 1513 } en_trig_output_1to1_usb_pdma0_tr_t; 1514 1515 /* Trigger Output Group 6 - USB PDMA0 Acknowledge Triggers (OneToOne) */ 1516 typedef enum 1517 { 1518 TRIG_OUT_1TO1_6_PDMA0_TR_OUT8_TO_USB_ACK0 = 0x40001600u, /* From cpuss.dw0_tr_out[8] to usb.dma_burstend[0] */ 1519 TRIG_OUT_1TO1_6_PDMA0_TR_OUT9_TO_USB_ACK1 = 0x40001601u, /* From cpuss.dw0_tr_out[9] to usb.dma_burstend[1] */ 1520 TRIG_OUT_1TO1_6_PDMA0_TR_OUT10_TO_USB_ACK2 = 0x40001602u, /* From cpuss.dw0_tr_out[10] to usb.dma_burstend[2] */ 1521 TRIG_OUT_1TO1_6_PDMA0_TR_OUT11_TO_USB_ACK3 = 0x40001603u, /* From cpuss.dw0_tr_out[11] to usb.dma_burstend[3] */ 1522 TRIG_OUT_1TO1_6_PDMA0_TR_OUT12_TO_USB_ACK4 = 0x40001604u, /* From cpuss.dw0_tr_out[12] to usb.dma_burstend[4] */ 1523 TRIG_OUT_1TO1_6_PDMA0_TR_OUT13_TO_USB_ACK5 = 0x40001605u, /* From cpuss.dw0_tr_out[13] to usb.dma_burstend[5] */ 1524 TRIG_OUT_1TO1_6_PDMA0_TR_OUT14_TO_USB_ACK6 = 0x40001606u, /* From cpuss.dw0_tr_out[14] to usb.dma_burstend[6] */ 1525 TRIG_OUT_1TO1_6_PDMA0_TR_OUT15_TO_USB_ACK7 = 0x40001607u /* From cpuss.dw0_tr_out[15] to usb.dma_burstend[7] */ 1526 } en_trig_output_1to1_usb_pdma0_ack_tr_t; 1527 1528 /* Level or edge detection setting for a trigger mux */ 1529 typedef enum 1530 { 1531 /* The trigger is a simple level output */ 1532 TRIGGER_TYPE_LEVEL = 0u, 1533 /* The trigger is synchronized to the consumer blocks clock 1534 and a two cycle pulse is generated on this clock */ 1535 TRIGGER_TYPE_EDGE = 1u 1536 } en_trig_type_t; 1537 1538 /* Trigger Type Defines */ 1539 /* AUDIOSS Trigger Types */ 1540 #define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ TRIGGER_TYPE_LEVEL 1541 #define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ TRIGGER_TYPE_LEVEL 1542 #define TRIGGER_TYPE_AUDIOSS_TR_PDM_RX_REQ TRIGGER_TYPE_LEVEL 1543 /* CPUSS Trigger Types */ 1544 #define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE 1545 #define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE 1546 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1547 #define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE 1548 #define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE 1549 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1550 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE 1551 #define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE 1552 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1553 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE 1554 #define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE 1555 #define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE 1556 /* CSD Trigger Types */ 1557 #define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE 1558 /* LPCOMP Trigger Types */ 1559 #define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL 1560 #define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL 1561 /* PASS Trigger Types */ 1562 #define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL 1563 #define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE 1564 #define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE 1565 /* PERI Trigger Types */ 1566 #define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL 1567 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL 1568 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE 1569 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL 1570 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE 1571 /* PROFILE Trigger Types */ 1572 #define TRIGGER_TYPE_PROFILE_TR_START TRIGGER_TYPE_EDGE 1573 #define TRIGGER_TYPE_PROFILE_TR_STOP TRIGGER_TYPE_EDGE 1574 /* SCB Trigger Types */ 1575 #define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL 1576 #define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL 1577 #define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL 1578 /* SMIF Trigger Types */ 1579 #define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL 1580 #define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL 1581 /* TCPWM Trigger Types */ 1582 #define TRIGGER_TYPE_TCPWM_LINE TRIGGER_TYPE_LEVEL 1583 #define TRIGGER_TYPE_TCPWM_LINE_COMPL TRIGGER_TYPE_LEVEL 1584 #define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH TRIGGER_TYPE_EDGE 1585 #define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL TRIGGER_TYPE_LEVEL 1586 #define TRIGGER_TYPE_TCPWM_TR_IN__EDGE TRIGGER_TYPE_EDGE 1587 #define TRIGGER_TYPE_TCPWM_TR_OVERFLOW TRIGGER_TYPE_EDGE 1588 #define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW TRIGGER_TYPE_EDGE 1589 /* USB Trigger Types */ 1590 #define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE 1591 #define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE 1592 1593 /* Fault connections */ 1594 typedef enum 1595 { 1596 CPUSS_MPU_VIO_0 = 0x0000u, 1597 CPUSS_MPU_VIO_1 = 0x0001u, 1598 CPUSS_MPU_VIO_2 = 0x0002u, 1599 CPUSS_MPU_VIO_3 = 0x0003u, 1600 CPUSS_MPU_VIO_4 = 0x0004u, 1601 CPUSS_MPU_VIO_5 = 0x0005u, 1602 CPUSS_MPU_VIO_6 = 0x0006u, 1603 CPUSS_MPU_VIO_15 = 0x000Fu, 1604 CPUSS_MPU_VIO_16 = 0x0010u, 1605 CPUSS_MPU_VIO_17 = 0x0011u, 1606 CPUSS_MPU_VIO_18 = 0x0012u, 1607 PERI_MS_VIO_0 = 0x001Cu, 1608 PERI_MS_VIO_1 = 0x001Du, 1609 PERI_MS_VIO_2 = 0x001Eu, 1610 PERI_MS_VIO_3 = 0x001Fu, 1611 PERI_GROUP_VIO_0 = 0x0020u, 1612 PERI_GROUP_VIO_1 = 0x0021u, 1613 PERI_GROUP_VIO_2 = 0x0022u, 1614 PERI_GROUP_VIO_3 = 0x0023u, 1615 PERI_GROUP_VIO_4 = 0x0024u, 1616 PERI_GROUP_VIO_6 = 0x0026u, 1617 PERI_GROUP_VIO_9 = 0x0029u, 1618 PERI_GROUP_VIO_10 = 0x002Au, 1619 CPUSS_FLASHC_MAIN_BUS_ERR = 0x0030u 1620 } en_sysfault_source_t; 1621 1622 /* Monitor Signal Defines */ 1623 typedef enum 1624 { 1625 PROFILE_ONE = 0, /* profile.one */ 1626 CPUSS_MONITOR_CM0 = 1, /* cpuss.monitor_cm0 */ 1627 CPUSS_MONITOR_CM4 = 2, /* cpuss.monitor_cm4 */ 1628 CPUSS_MONITOR_MAIN_FLASH = 3, /* cpuss.monitor_main_flash */ 1629 CPUSS_MONITOR_WORK_FLASH = 4, /* cpuss.monitor_work_flash */ 1630 CPUSS_MONITOR_DW0_AHB = 5, /* cpuss.monitor_dw0_ahb */ 1631 CPUSS_MONITOR_DW1_AHB = 6, /* cpuss.monitor_dw1_ahb */ 1632 CPUSS_MONITOR_DMAC_AHB = 7, /* cpuss.monitor_dmac_ahb */ 1633 CPUSS_MONITOR_CRYPTO = 8, /* cpuss.monitor_crypto */ 1634 USB_MONITOR_AHB = 9, /* usb.monitor_ahb */ 1635 SCB0_MONITOR_AHB = 10, /* scb[0].monitor_ahb */ 1636 SCB1_MONITOR_AHB = 11, /* scb[1].monitor_ahb */ 1637 SCB2_MONITOR_AHB = 12, /* scb[2].monitor_ahb */ 1638 SCB3_MONITOR_AHB = 13, /* scb[3].monitor_ahb */ 1639 SCB4_MONITOR_AHB = 14, /* scb[4].monitor_ahb */ 1640 SCB5_MONITOR_AHB = 15, /* scb[5].monitor_ahb */ 1641 SCB6_MONITOR_AHB = 16, /* scb[6].monitor_ahb */ 1642 SCB7_MONITOR_AHB = 17, /* scb[7].monitor_ahb */ 1643 SCB8_MONITOR_AHB = 18, /* scb[8].monitor_ahb */ 1644 SCB9_MONITOR_AHB = 19, /* scb[9].monitor_ahb */ 1645 SCB10_MONITOR_AHB = 20, /* scb[10].monitor_ahb */ 1646 SCB11_MONITOR_AHB = 21, /* scb[11].monitor_ahb */ 1647 SCB12_MONITOR_AHB = 22, /* scb[12].monitor_ahb */ 1648 SMIF_MONITOR_SMIF_SPI_SELECT0 = 23, /* smif.monitor_smif_spi_select[0] */ 1649 SMIF_MONITOR_SMIF_SPI_SELECT1 = 24, /* smif.monitor_smif_spi_select[1] */ 1650 SMIF_MONITOR_SMIF_SPI_SELECT2 = 25, /* smif.monitor_smif_spi_select[2] */ 1651 SMIF_MONITOR_SMIF_SPI_SELECT3 = 26, /* smif.monitor_smif_spi_select[3] */ 1652 SMIF_MONITOR_SMIF_SPI_SELECT_ANY = 27, /* smif.monitor_smif_spi_select_any */ 1653 SDHC0_MONITOR_CORE_MASTER_WR = 28, /* sdhc[0].monitor_core_master_wr */ 1654 SDHC0_MONITOR_CORE_MASTER_RD = 29, /* sdhc[0].monitor_core_master_rd */ 1655 SDHC1_MONITOR_CORE_MASTER_WR = 30, /* sdhc[1].monitor_core_master_wr */ 1656 SDHC1_MONITOR_CORE_MASTER_RD = 31 /* sdhc[1].monitor_core_master_rd */ 1657 } en_ep_mon_sel_t; 1658 1659 /* Total count of Energy Profiler monitor signal connections */ 1660 #define EP_MONITOR_COUNT 32u 1661 1662 /* Bus masters */ 1663 typedef enum 1664 { 1665 CPUSS_MS_ID_CM0 = 0, 1666 CPUSS_MS_ID_CRYPTO = 1, 1667 CPUSS_MS_ID_DW0 = 2, 1668 CPUSS_MS_ID_DW1 = 3, 1669 CPUSS_MS_ID_DMAC = 4, 1670 CPUSS_MS_ID_SLOW0 = 5, 1671 CPUSS_MS_ID_SLOW1 = 6, 1672 CPUSS_MS_ID_CM4 = 14, 1673 CPUSS_MS_ID_TC = 15 1674 } en_prot_master_t; 1675 1676 /* Pointer to device configuration structure */ 1677 #define CY_DEVICE_CFG (&cy_deviceIpBlockCfgPSoC6_02) 1678 1679 /* Include IP definitions */ 1680 #include "ip/cyip_sflash.h" 1681 #include "ip/cyip_peri_v2.h" 1682 #include "ip/cyip_peri_ms_v2.h" 1683 #include "ip/cyip_crypto_v2.h" 1684 #include "ip/cyip_cpuss_v2.h" 1685 #include "ip/cyip_fault_v2.h" 1686 #include "ip/cyip_ipc_v2.h" 1687 #include "ip/cyip_prot_v2.h" 1688 #include "ip/cyip_flashc_v2.h" 1689 #include "ip/cyip_srss.h" 1690 #include "ip/cyip_backup.h" 1691 #include "ip/cyip_dw_v2.h" 1692 #include "ip/cyip_dmac_v2.h" 1693 #include "ip/cyip_efuse.h" 1694 #include "ip/cyip_efuse_data_psoc6_02.h" 1695 #include "ip/cyip_profile.h" 1696 #include "ip/cyip_hsiom_v2.h" 1697 #include "ip/cyip_gpio_v2.h" 1698 #include "ip/cyip_smartio_v2.h" 1699 #include "ip/cyip_lpcomp.h" 1700 #include "ip/cyip_csd.h" 1701 #include "ip/cyip_tcpwm.h" 1702 #include "ip/cyip_lcd.h" 1703 #include "ip/cyip_usbfs.h" 1704 #include "ip/cyip_smif.h" 1705 #include "ip/cyip_sdhc.h" 1706 #include "ip/cyip_scb.h" 1707 #include "ip/cyip_ctbm.h" 1708 #include "ip/cyip_ctdac.h" 1709 #include "ip/cyip_sar.h" 1710 #include "ip/cyip_pass.h" 1711 #include "ip/cyip_pdm.h" 1712 #include "ip/cyip_i2s.h" 1713 1714 /* IP type definitions */ 1715 typedef SFLASH_V1_Type SFLASH_Type; 1716 typedef PERI_GR_V2_Type PERI_GR_Type; 1717 typedef PERI_TR_GR_V2_Type PERI_TR_GR_Type; 1718 typedef PERI_TR_1TO1_GR_V2_Type PERI_TR_1TO1_GR_Type; 1719 typedef PERI_V2_Type PERI_Type; 1720 typedef PERI_MS_PPU_PR_V2_Type PERI_MS_PPU_PR_Type; 1721 typedef PERI_MS_PPU_FX_V2_Type PERI_MS_PPU_FX_Type; 1722 typedef PERI_MS_V2_Type PERI_MS_Type; 1723 typedef CRYPTO_V2_Type CRYPTO_Type; 1724 typedef CPUSS_V2_Type CPUSS_Type; 1725 typedef FAULT_STRUCT_V2_Type FAULT_STRUCT_Type; 1726 typedef FAULT_V2_Type FAULT_Type; 1727 typedef IPC_STRUCT_V2_Type IPC_STRUCT_Type; 1728 typedef IPC_INTR_STRUCT_V2_Type IPC_INTR_STRUCT_Type; 1729 typedef IPC_V2_Type IPC_Type; 1730 typedef PROT_SMPU_SMPU_STRUCT_V2_Type PROT_SMPU_SMPU_STRUCT_Type; 1731 typedef PROT_SMPU_V2_Type PROT_SMPU_Type; 1732 typedef PROT_MPU_MPU_STRUCT_V2_Type PROT_MPU_MPU_STRUCT_Type; 1733 typedef PROT_MPU_V2_Type PROT_MPU_Type; 1734 typedef PROT_V2_Type PROT_Type; 1735 typedef FLASHC_FM_CTL_V2_Type FLASHC_FM_CTL_Type; 1736 typedef FLASHC_V2_Type FLASHC_Type; 1737 typedef MCWDT_STRUCT_V1_Type MCWDT_STRUCT_Type; 1738 typedef SRSS_V1_Type SRSS_Type; 1739 typedef BACKUP_V1_Type BACKUP_Type; 1740 typedef DW_CH_STRUCT_V2_Type DW_CH_STRUCT_Type; 1741 typedef DW_V2_Type DW_Type; 1742 typedef DMAC_CH_V2_Type DMAC_CH_Type; 1743 typedef DMAC_V2_Type DMAC_Type; 1744 typedef EFUSE_V1_Type EFUSE_Type; 1745 typedef PROFILE_CNT_STRUCT_V1_Type PROFILE_CNT_STRUCT_Type; 1746 typedef PROFILE_V1_Type PROFILE_Type; 1747 typedef HSIOM_PRT_V2_Type HSIOM_PRT_Type; 1748 typedef HSIOM_V2_Type HSIOM_Type; 1749 typedef GPIO_PRT_V2_Type GPIO_PRT_Type; 1750 typedef GPIO_V2_Type GPIO_Type; 1751 typedef SMARTIO_PRT_V2_Type SMARTIO_PRT_Type; 1752 typedef SMARTIO_V2_Type SMARTIO_Type; 1753 typedef LPCOMP_V1_Type LPCOMP_Type; 1754 typedef CSD_V1_Type CSD_Type; 1755 typedef TCPWM_CNT_V1_Type TCPWM_CNT_Type; 1756 typedef TCPWM_V1_Type TCPWM_Type; 1757 typedef LCD_V1_Type LCD_Type; 1758 typedef USBFS_USBDEV_V1_Type USBFS_USBDEV_Type; 1759 typedef USBFS_USBLPM_V1_Type USBFS_USBLPM_Type; 1760 typedef USBFS_USBHOST_V1_Type USBFS_USBHOST_Type; 1761 typedef USBFS_V1_Type USBFS_Type; 1762 typedef SMIF_DEVICE_V1_Type SMIF_DEVICE_Type; 1763 typedef SMIF_V1_Type SMIF_Type; 1764 typedef SDHC_WRAP_V1_Type SDHC_WRAP_Type; 1765 typedef SDHC_CORE_V1_Type SDHC_CORE_Type; 1766 typedef SDHC_V1_Type SDHC_Type; 1767 typedef CySCB_V1_Type CySCB_Type; 1768 typedef CTBM_V1_Type CTBM_Type; 1769 typedef CTDAC_V1_Type CTDAC_Type; 1770 typedef SAR_V1_Type SAR_Type; 1771 typedef PASS_AREF_V1_Type PASS_AREF_Type; 1772 typedef PASS_V1_Type PASS_Type; 1773 typedef PDM_V1_Type PDM_Type; 1774 typedef I2S_V1_Type I2S_Type; 1775 1776 /* Parameter Defines */ 1777 /* I2S capable? (0=No,1=Yes) */ 1778 #define AUDIOSS0_I2S 1u 1779 /* PDM capable? (0=No,1=Yes) */ 1780 #define AUDIOSS0_PDM 1u 1781 /* I2S capable? (0=No,1=Yes) */ 1782 #define AUDIOSS1_I2S 1u 1783 /* PDM capable? (0=No,1=Yes) */ 1784 #define AUDIOSS1_PDM 0u 1785 /* UDB present or not ('0': no, '1': yes) */ 1786 #define CPUSS_UDB_PRESENT 0u 1787 /* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the 1788 chips which doesn't use mxdft. */ 1789 #define CPUSS_MBIST_MMIO_PRESENT 1u 1790 /* System RAM 0 size in kilobytes */ 1791 #define CPUSS_SRAM0_SIZE 512u 1792 /* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System 1793 SRAM0 is implemented with 8 32KB macros. */ 1794 #define CPUSS_RAMC0_MACRO_NR 16u 1795 /* System RAM 1 present or not (0=No, 1=Yes) */ 1796 #define CPUSS_RAMC1_PRESENT 1u 1797 /* System RAM 1 size in kilobytes */ 1798 #define CPUSS_SRAM1_SIZE 256u 1799 /* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System 1800 RAM 1 is implemented with 8 32KB macros. */ 1801 #define CPUSS_RAMC1_MACRO_NR 8u 1802 /* System RAM 2 present or not (0=No, 1=Yes) */ 1803 #define CPUSS_RAMC2_PRESENT 1u 1804 /* System RAM 2 size in kilobytes */ 1805 #define CPUSS_SRAM2_SIZE 256u 1806 /* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System 1807 RAM 2 is implemented with 8 32KB macros. */ 1808 #define CPUSS_RAMC2_MACRO_NR 8u 1809 /* System SRAM(s) ECC present or not ('0': no, '1': yes) */ 1810 #define CPUSS_RAMC_ECC_PRESENT 0u 1811 /* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ 1812 #define CPUSS_RAMC_ECC_ADDR_PRESENT 0u 1813 /* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ 1814 #define CPUSS_ECC_PRESENT 0u 1815 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 1816 #define CPUSS_DW_ECC_PRESENT 0u 1817 /* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ 1818 #define CPUSS_DW_ECC_ADDR_PRESENT 0u 1819 /* System ROM size in KB */ 1820 #define CPUSS_ROM_SIZE 64u 1821 /* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM 1822 is implemented with 4 128KB macros. */ 1823 #define CPUSS_ROMC_MACRO_NR 1u 1824 /* Flash memory type ('0' : SONOS, '1': ECT) */ 1825 #define CPUSS_FLASHC_ECT 0u 1826 /* Flash main region size in KB */ 1827 #define CPUSS_FLASH_SIZE 2048u 1828 /* Flash work region size in KB (EEPROM emulation, data) */ 1829 #define CPUSS_WFLASH_SIZE 32u 1830 /* Flash supervisory region size in KB */ 1831 #define CPUSS_SFLASH_SIZE 32u 1832 /* Flash data output word size (in Bytes) */ 1833 #define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u 1834 /* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special 1835 sectors present in Flash. Part of main sector 0 is allowcated for Supervisory 1836 Flash, and no Work Flash present. */ 1837 #define CPUSS_FLASHC_SONOS_RWW 1u 1838 /* SONOS Flash, number of main sectors. */ 1839 #define CPUSS_FLASHC_SONOS_MAIN_SECTORS 8u 1840 /* SONOS Flash, number of rows per main sector. */ 1841 #define CPUSS_FLASHC_SONOS_MAIN_ROWS 512u 1842 /* SONOS Flash, number of words per row of main sector. */ 1843 #define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u 1844 /* SONOS Flash, number of special sectors. */ 1845 #define CPUSS_FLASHC_SONOS_SPL_SECTORS 2u 1846 /* SONOS Flash, number of rows per special sector. */ 1847 #define CPUSS_FLASHC_SONOS_SPL_ROWS 64u 1848 /* Flash memory ECC present or not ('0': no, '1': yes) */ 1849 #define CPUSS_FLASHC_FLASH_ECC_PRESENT 0u 1850 /* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ 1851 #define CPUSS_FLASHC_RAM_ECC_PRESENT 0u 1852 /* Number of external slaves directly connected to slow AHB-Lite infrastructure. 1853 Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. 1854 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave 1855 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK 1856 parameters (for the slaves present) should be derived from the Memory Map. */ 1857 #define CPUSS_SLOW_SL_PRESENT 1u 1858 /* Number of external slaves directly connected to fast AHB-Lite infrastructure. 1859 Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. 1860 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave 1861 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK 1862 parameters (for the slaves present) should be derived from the Memory Map. */ 1863 #define CPUSS_FAST_SL_PRESENT 1u 1864 /* Number of external masters driving the slow AHB-Lite infrastructure. Maximum 1865 number of masters supported is 2. Width of this parameter is 2-bits. 1-bit 1866 mask for each master indicating present or not. Example: 2'b01 - master 0 is 1867 present. */ 1868 #define CPUSS_SLOW_MS_PRESENT 3u 1869 /* System interrupt functionality present or not ('0': no; '1': yes). Not used for 1870 CM0+ PCU, which always uses system interrupt functionality. */ 1871 #define CPUSS_SYSTEM_IRQ_PRESENT 0u 1872 /* Number of total interrupt request inputs to CPUSS */ 1873 #define CPUSS_SYSTEM_INT_NR 168u 1874 /* Number of DeepSleep wakeup interrupt inputs to CPUSS */ 1875 #define CPUSS_SYSTEM_DPSLP_INT_NR 39u 1876 /* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 1877 levels of priority 8 = 256 levels of priority */ 1878 #define CPUSS_CM4_LVL_WIDTH 3u 1879 /* CM4 Floating point unit present or not (0=No, 1=Yes) */ 1880 #define CPUSS_CM4_FPU_PRESENT 1u 1881 /* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 1882 breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 1883 watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ 1884 #define CPUSS_DEBUG_LVL 3u 1885 /* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + 1886 ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace 1887 level is not supported in CPUSS. */ 1888 #define CPUSS_TRACE_LVL 2u 1889 /* Embedded Trace Buffer present or not (0=No, 1=Yes) */ 1890 #define CPUSS_ETB_PRESENT 0u 1891 /* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 1892 #define CPUSS_MTB_SRAM_SIZE 4u 1893 /* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ 1894 #define CPUSS_ETB_SRAM_SIZE 8u 1895 /* PTM interface present (0=No, 1=Yes) */ 1896 #define CPUSS_PTM_PRESENT 0u 1897 /* Width of the PTM interface in bits ([2,32]) */ 1898 #define CPUSS_PTM_WIDTH 1u 1899 /* Width of the TPIU interface in bits ([1,4]) */ 1900 #define CPUSS_TPIU_WIDTH 4u 1901 /* CoreSight Part Identification Number */ 1902 #define CPUSS_JEPID 52u 1903 /* CoreSight Part Identification Number */ 1904 #define CPUSS_JEPCONTINUATION 0u 1905 /* CoreSight Part Identification Number */ 1906 #define CPUSS_FAMILYID 258u 1907 /* ROM trim register width (for ARM 3, for Synopsys 5) */ 1908 #define CPUSS_ROM_TRIM_WIDTH 5u 1909 /* ROM trim register default (for both ARM and Synopsys 0x0000_0012) */ 1910 #define CPUSS_ROM_TRIM_DEFAULT 18u 1911 /* RAM trim register width (for ARM 8, for Synopsys 15) */ 1912 #define CPUSS_RAM_TRIM_WIDTH 15u 1913 /* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ 1914 #define CPUSS_RAM_TRIM_DEFAULT 0x00006012u 1915 /* Cryptography IP present or not (0=No, 1=Yes) */ 1916 #define CPUSS_CRYPTO_PRESENT 1u 1917 /* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 1918 #define CPUSS_SW_TR_PRESENT 0u 1919 /* DataWire 0 present or not (0=No, 1=Yes) */ 1920 #define CPUSS_DW0_PRESENT 1u 1921 /* Number of DataWire 0 channels (8, 16 or 32) */ 1922 #define CPUSS_DW0_CH_NR 29u 1923 /* DataWire 1 present or not (0=No, 1=Yes) */ 1924 #define CPUSS_DW1_PRESENT 1u 1925 /* Number of DataWire 1 channels (8, 16 or 32) */ 1926 #define CPUSS_DW1_CH_NR 29u 1927 /* DMA controller present or not ('0': no, '1': yes) */ 1928 #define CPUSS_DMAC_PRESENT 1u 1929 /* Number of DMA controller channels ([1, 8]) */ 1930 #define CPUSS_DMAC_CH_NR 4u 1931 /* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ 1932 #define CPUSS_CH_SW_TR_PRESENT 0u 1933 /* See MMIO2 instantiation or not */ 1934 #define CPUSS_CHIP_TOP_PROFILER_PRESENT 1u 1935 /* ETAS Calibration support pin out present (automotive only) */ 1936 #define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u 1937 /* TRACE_LVL>0 */ 1938 #define CPUSS_CHIP_TOP_TRACE_PRESENT 1u 1939 /* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ 1940 #define CPUSS_CH_STRUCT_SW_TR_PRESENT 0u 1941 /* Number of DataWire controllers present (max 2) (same as DW.NR above) */ 1942 #define CPUSS_CPUSS_DW_DW_NR 2u 1943 /* Number of channels in each DataWire controller */ 1944 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 29u 1945 /* Width of a channel number in bits */ 1946 #define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 5u 1947 /* Number of channels in each DataWire controller */ 1948 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 29u 1949 /* Width of a channel number in bits */ 1950 #define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 5u 1951 /* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ 1952 #define CPUSS_CRYPTO_ECC_PRESENT 0u 1953 /* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ 1954 #define CPUSS_CRYPTO_ECC_ADDR_PRESENT 0u 1955 /* AES cipher support ('0': no, '1': yes) */ 1956 #define CPUSS_CRYPTO_AES 1u 1957 /* (Tripple) DES cipher support ('0': no, '1': yes) */ 1958 #define CPUSS_CRYPTO_DES 1u 1959 /* Chacha support ('0': no, '1': yes) */ 1960 #define CPUSS_CRYPTO_CHACHA 1u 1961 /* Pseudo random number generation support ('0': no, '1': yes) */ 1962 #define CPUSS_CRYPTO_PR 1u 1963 /* SHA1 hash support ('0': no, '1': yes) */ 1964 #define CPUSS_CRYPTO_SHA1 1u 1965 /* SHA2 hash support ('0': no, '1': yes) */ 1966 #define CPUSS_CRYPTO_SHA2 1u 1967 /* SHA3 hash support ('0': no, '1': yes) */ 1968 #define CPUSS_CRYPTO_SHA3 1u 1969 /* Cyclic Redundancy Check support ('0': no, '1': yes) */ 1970 #define CPUSS_CRYPTO_CRC 1u 1971 /* True random number generation support ('0': no, '1': yes) */ 1972 #define CPUSS_CRYPTO_TR 1u 1973 /* Vector unit support ('0': no, '1': yes) */ 1974 #define CPUSS_CRYPTO_VU 1u 1975 /* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ 1976 #define CPUSS_CRYPTO_GCM 1u 1977 /* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, 1978 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 1979 kB and 16 kB memory buffer) */ 1980 #define CPUSS_CRYPTO_BUFF_SIZE 1024u 1981 /* Number of DMA controller channels ([1, 8]) */ 1982 #define CPUSS_DMAC_CH_NR 4u 1983 /* Number of DataWire controllers present (max 2) */ 1984 #define CPUSS_DW_NR 2u 1985 /* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ 1986 #define CPUSS_DW_ECC_PRESENT 0u 1987 /* Number of fault structures. Legal range [1, 4] */ 1988 #define CPUSS_FAULT_FAULT_NR 2u 1989 /* Number of Flash BIST_DATA registers */ 1990 #define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u 1991 /* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ 1992 #define CPUSS_FLASHC_PA_SIZE 128u 1993 /* SONOS Flash is used or not ('0': no, '1': yes) */ 1994 #define CPUSS_FLASHC_FLASHC_IS_SONOS 1u 1995 /* eCT Flash is used or not ('0': no, '1': yes) */ 1996 #define CPUSS_FLASHC_FLASHC_IS_ECT 0u 1997 /* Number of IPC structures. Legal range [1, 16] */ 1998 #define CPUSS_IPC_IPC_NR 16u 1999 /* Number of IPC interrupt structures. Legal range [1, 16] */ 2000 #define CPUSS_IPC_IPC_IRQ_NR 16u 2001 /* Master 0 protect contexts minus one */ 2002 #define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u 2003 /* Master 1 protect contexts minus one */ 2004 #define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u 2005 /* Master 2 protect contexts minus one */ 2006 #define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u 2007 /* Master 3 protect contexts minus one */ 2008 #define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u 2009 /* Master 4 protect contexts minus one */ 2010 #define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u 2011 /* Master 5 protect contexts minus one */ 2012 #define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 7u 2013 /* Master 6 protect contexts minus one */ 2014 #define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 7u 2015 /* Master 7 protect contexts minus one */ 2016 #define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u 2017 /* Master 8 protect contexts minus one */ 2018 #define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u 2019 /* Master 9 protect contexts minus one */ 2020 #define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u 2021 /* Master 10 protect contexts minus one */ 2022 #define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u 2023 /* Master 11 protect contexts minus one */ 2024 #define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u 2025 /* Master 12 protect contexts minus one */ 2026 #define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u 2027 /* Master 13 protect contexts minus one */ 2028 #define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u 2029 /* Master 14 protect contexts minus one */ 2030 #define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u 2031 /* Master 15 protect contexts minus one */ 2032 #define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u 2033 /* Number of SMPU protection structures */ 2034 #define CPUSS_PROT_SMPU_STRUCT_NR 16u 2035 /* Number of protection contexts supported minus 1. Legal range [1,16] */ 2036 #define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u 2037 /* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ 2038 #define EFUSE_EFUSE_NR 4u 2039 /* Number of GPIO ports in range 0..31 */ 2040 #define IOSS_GPIO_GPIO_PORT_NR_0_31 15u 2041 /* Number of GPIO ports in range 32..63 */ 2042 #define IOSS_GPIO_GPIO_PORT_NR_32_63 0u 2043 /* Number of GPIO ports in range 64..95 */ 2044 #define IOSS_GPIO_GPIO_PORT_NR_64_95 0u 2045 /* Number of GPIO ports in range 96..127 */ 2046 #define IOSS_GPIO_GPIO_PORT_NR_96_127 0u 2047 /* Number of ports in device */ 2048 #define IOSS_GPIO_GPIO_PORT_NR 15u 2049 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2050 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO 1u 2051 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2052 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SIO 0u 2053 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2054 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_AUTOLVL 0u 2055 /* Indicates that pin #0 exists for this port with slew control feature */ 2056 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO0 1u 2057 /* Indicates that pin #1 exists for this port with slew control feature */ 2058 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO1 1u 2059 /* Indicates that pin #2 exists for this port with slew control feature */ 2060 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO2 1u 2061 /* Indicates that pin #3 exists for this port with slew control feature */ 2062 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO3 1u 2063 /* Indicates that pin #4 exists for this port with slew control feature */ 2064 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO4 1u 2065 /* Indicates that pin #5 exists for this port with slew control feature */ 2066 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO5 1u 2067 /* Indicates that pin #6 exists for this port with slew control feature */ 2068 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO6 0u 2069 /* Indicates that pin #7 exists for this port with slew control feature */ 2070 #define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO7 0u 2071 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2072 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO 1u 2073 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2074 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SIO 0u 2075 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2076 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_AUTOLVL 0u 2077 /* Indicates that pin #0 exists for this port with slew control feature */ 2078 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO0 1u 2079 /* Indicates that pin #1 exists for this port with slew control feature */ 2080 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO1 1u 2081 /* Indicates that pin #2 exists for this port with slew control feature */ 2082 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO2 1u 2083 /* Indicates that pin #3 exists for this port with slew control feature */ 2084 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO3 1u 2085 /* Indicates that pin #4 exists for this port with slew control feature */ 2086 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO4 1u 2087 /* Indicates that pin #5 exists for this port with slew control feature */ 2088 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO5 1u 2089 /* Indicates that pin #6 exists for this port with slew control feature */ 2090 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO6 0u 2091 /* Indicates that pin #7 exists for this port with slew control feature */ 2092 #define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO7 0u 2093 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2094 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO 1u 2095 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2096 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SIO 0u 2097 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2098 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_AUTOLVL 0u 2099 /* Indicates that pin #0 exists for this port with slew control feature */ 2100 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO0 1u 2101 /* Indicates that pin #1 exists for this port with slew control feature */ 2102 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO1 1u 2103 /* Indicates that pin #2 exists for this port with slew control feature */ 2104 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO2 1u 2105 /* Indicates that pin #3 exists for this port with slew control feature */ 2106 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO3 1u 2107 /* Indicates that pin #4 exists for this port with slew control feature */ 2108 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO4 1u 2109 /* Indicates that pin #5 exists for this port with slew control feature */ 2110 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO5 1u 2111 /* Indicates that pin #6 exists for this port with slew control feature */ 2112 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO6 1u 2113 /* Indicates that pin #7 exists for this port with slew control feature */ 2114 #define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO7 1u 2115 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2116 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO 1u 2117 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2118 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SIO 0u 2119 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2120 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_AUTOLVL 0u 2121 /* Indicates that pin #0 exists for this port with slew control feature */ 2122 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO0 1u 2123 /* Indicates that pin #1 exists for this port with slew control feature */ 2124 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO1 1u 2125 /* Indicates that pin #2 exists for this port with slew control feature */ 2126 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO2 1u 2127 /* Indicates that pin #3 exists for this port with slew control feature */ 2128 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO3 1u 2129 /* Indicates that pin #4 exists for this port with slew control feature */ 2130 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO4 1u 2131 /* Indicates that pin #5 exists for this port with slew control feature */ 2132 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO5 1u 2133 /* Indicates that pin #6 exists for this port with slew control feature */ 2134 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO6 0u 2135 /* Indicates that pin #7 exists for this port with slew control feature */ 2136 #define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO7 0u 2137 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2138 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO 1u 2139 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2140 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SIO 0u 2141 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2142 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_AUTOLVL 0u 2143 /* Indicates that pin #0 exists for this port with slew control feature */ 2144 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO0 1u 2145 /* Indicates that pin #1 exists for this port with slew control feature */ 2146 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO1 1u 2147 /* Indicates that pin #2 exists for this port with slew control feature */ 2148 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO2 1u 2149 /* Indicates that pin #3 exists for this port with slew control feature */ 2150 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO3 1u 2151 /* Indicates that pin #4 exists for this port with slew control feature */ 2152 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO4 0u 2153 /* Indicates that pin #5 exists for this port with slew control feature */ 2154 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO5 0u 2155 /* Indicates that pin #6 exists for this port with slew control feature */ 2156 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO6 0u 2157 /* Indicates that pin #7 exists for this port with slew control feature */ 2158 #define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO7 0u 2159 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2160 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO 1u 2161 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2162 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SIO 0u 2163 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2164 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_AUTOLVL 0u 2165 /* Indicates that pin #0 exists for this port with slew control feature */ 2166 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO0 1u 2167 /* Indicates that pin #1 exists for this port with slew control feature */ 2168 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO1 1u 2169 /* Indicates that pin #2 exists for this port with slew control feature */ 2170 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO2 1u 2171 /* Indicates that pin #3 exists for this port with slew control feature */ 2172 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO3 1u 2173 /* Indicates that pin #4 exists for this port with slew control feature */ 2174 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO4 1u 2175 /* Indicates that pin #5 exists for this port with slew control feature */ 2176 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO5 1u 2177 /* Indicates that pin #6 exists for this port with slew control feature */ 2178 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO6 1u 2179 /* Indicates that pin #7 exists for this port with slew control feature */ 2180 #define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO7 1u 2181 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2182 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_GPIO 1u 2183 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2184 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SIO 0u 2185 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2186 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_AUTOLVL 0u 2187 /* Indicates that pin #0 exists for this port with slew control feature */ 2188 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO0 1u 2189 /* Indicates that pin #1 exists for this port with slew control feature */ 2190 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO1 1u 2191 /* Indicates that pin #2 exists for this port with slew control feature */ 2192 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO2 1u 2193 /* Indicates that pin #3 exists for this port with slew control feature */ 2194 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO3 1u 2195 /* Indicates that pin #4 exists for this port with slew control feature */ 2196 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO4 1u 2197 /* Indicates that pin #5 exists for this port with slew control feature */ 2198 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO5 1u 2199 /* Indicates that pin #6 exists for this port with slew control feature */ 2200 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO6 1u 2201 /* Indicates that pin #7 exists for this port with slew control feature */ 2202 #define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO7 1u 2203 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2204 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_GPIO 1u 2205 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2206 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SIO 0u 2207 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2208 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_AUTOLVL 0u 2209 /* Indicates that pin #0 exists for this port with slew control feature */ 2210 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO0 1u 2211 /* Indicates that pin #1 exists for this port with slew control feature */ 2212 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO1 1u 2213 /* Indicates that pin #2 exists for this port with slew control feature */ 2214 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO2 1u 2215 /* Indicates that pin #3 exists for this port with slew control feature */ 2216 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO3 1u 2217 /* Indicates that pin #4 exists for this port with slew control feature */ 2218 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO4 1u 2219 /* Indicates that pin #5 exists for this port with slew control feature */ 2220 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO5 1u 2221 /* Indicates that pin #6 exists for this port with slew control feature */ 2222 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO6 1u 2223 /* Indicates that pin #7 exists for this port with slew control feature */ 2224 #define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO7 1u 2225 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2226 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_GPIO 1u 2227 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2228 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SIO 0u 2229 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2230 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_AUTOLVL 0u 2231 /* Indicates that pin #0 exists for this port with slew control feature */ 2232 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO0 1u 2233 /* Indicates that pin #1 exists for this port with slew control feature */ 2234 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO1 1u 2235 /* Indicates that pin #2 exists for this port with slew control feature */ 2236 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO2 1u 2237 /* Indicates that pin #3 exists for this port with slew control feature */ 2238 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO3 1u 2239 /* Indicates that pin #4 exists for this port with slew control feature */ 2240 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO4 1u 2241 /* Indicates that pin #5 exists for this port with slew control feature */ 2242 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO5 1u 2243 /* Indicates that pin #6 exists for this port with slew control feature */ 2244 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO6 1u 2245 /* Indicates that pin #7 exists for this port with slew control feature */ 2246 #define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO7 1u 2247 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2248 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_GPIO 1u 2249 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2250 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SIO 0u 2251 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2252 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_AUTOLVL 0u 2253 /* Indicates that pin #0 exists for this port with slew control feature */ 2254 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO0 1u 2255 /* Indicates that pin #1 exists for this port with slew control feature */ 2256 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO1 1u 2257 /* Indicates that pin #2 exists for this port with slew control feature */ 2258 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO2 1u 2259 /* Indicates that pin #3 exists for this port with slew control feature */ 2260 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO3 1u 2261 /* Indicates that pin #4 exists for this port with slew control feature */ 2262 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO4 1u 2263 /* Indicates that pin #5 exists for this port with slew control feature */ 2264 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO5 1u 2265 /* Indicates that pin #6 exists for this port with slew control feature */ 2266 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO6 1u 2267 /* Indicates that pin #7 exists for this port with slew control feature */ 2268 #define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO7 1u 2269 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2270 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_GPIO 1u 2271 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2272 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SIO 0u 2273 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2274 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_AUTOLVL 0u 2275 /* Indicates that pin #0 exists for this port with slew control feature */ 2276 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO0 1u 2277 /* Indicates that pin #1 exists for this port with slew control feature */ 2278 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO1 1u 2279 /* Indicates that pin #2 exists for this port with slew control feature */ 2280 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO2 1u 2281 /* Indicates that pin #3 exists for this port with slew control feature */ 2282 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO3 1u 2283 /* Indicates that pin #4 exists for this port with slew control feature */ 2284 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO4 1u 2285 /* Indicates that pin #5 exists for this port with slew control feature */ 2286 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO5 1u 2287 /* Indicates that pin #6 exists for this port with slew control feature */ 2288 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO6 1u 2289 /* Indicates that pin #7 exists for this port with slew control feature */ 2290 #define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO7 1u 2291 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2292 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_GPIO 1u 2293 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2294 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SIO 0u 2295 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2296 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_AUTOLVL 0u 2297 /* Indicates that pin #0 exists for this port with slew control feature */ 2298 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO0 1u 2299 /* Indicates that pin #1 exists for this port with slew control feature */ 2300 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO1 1u 2301 /* Indicates that pin #2 exists for this port with slew control feature */ 2302 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO2 1u 2303 /* Indicates that pin #3 exists for this port with slew control feature */ 2304 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO3 1u 2305 /* Indicates that pin #4 exists for this port with slew control feature */ 2306 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO4 1u 2307 /* Indicates that pin #5 exists for this port with slew control feature */ 2308 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO5 1u 2309 /* Indicates that pin #6 exists for this port with slew control feature */ 2310 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO6 1u 2311 /* Indicates that pin #7 exists for this port with slew control feature */ 2312 #define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO7 1u 2313 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2314 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_GPIO 1u 2315 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2316 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SIO 0u 2317 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2318 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_AUTOLVL 0u 2319 /* Indicates that pin #0 exists for this port with slew control feature */ 2320 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO0 1u 2321 /* Indicates that pin #1 exists for this port with slew control feature */ 2322 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO1 1u 2323 /* Indicates that pin #2 exists for this port with slew control feature */ 2324 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO2 1u 2325 /* Indicates that pin #3 exists for this port with slew control feature */ 2326 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO3 1u 2327 /* Indicates that pin #4 exists for this port with slew control feature */ 2328 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO4 1u 2329 /* Indicates that pin #5 exists for this port with slew control feature */ 2330 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO5 1u 2331 /* Indicates that pin #6 exists for this port with slew control feature */ 2332 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO6 1u 2333 /* Indicates that pin #7 exists for this port with slew control feature */ 2334 #define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO7 1u 2335 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2336 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_GPIO 1u 2337 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2338 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SIO 0u 2339 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2340 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_AUTOLVL 0u 2341 /* Indicates that pin #0 exists for this port with slew control feature */ 2342 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO0 1u 2343 /* Indicates that pin #1 exists for this port with slew control feature */ 2344 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO1 1u 2345 /* Indicates that pin #2 exists for this port with slew control feature */ 2346 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO2 1u 2347 /* Indicates that pin #3 exists for this port with slew control feature */ 2348 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO3 1u 2349 /* Indicates that pin #4 exists for this port with slew control feature */ 2350 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO4 1u 2351 /* Indicates that pin #5 exists for this port with slew control feature */ 2352 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO5 1u 2353 /* Indicates that pin #6 exists for this port with slew control feature */ 2354 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO6 1u 2355 /* Indicates that pin #7 exists for this port with slew control feature */ 2356 #define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO7 1u 2357 /* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ 2358 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_GPIO 0u 2359 /* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ 2360 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SIO 0u 2361 /* Indicates port is a GPIO port including the "AUTO" input threshold */ 2362 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_AUTOLVL 0u 2363 /* Indicates that pin #0 exists for this port with slew control feature */ 2364 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO0 1u 2365 /* Indicates that pin #1 exists for this port with slew control feature */ 2366 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO1 1u 2367 /* Indicates that pin #2 exists for this port with slew control feature */ 2368 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO2 0u 2369 /* Indicates that pin #3 exists for this port with slew control feature */ 2370 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO3 0u 2371 /* Indicates that pin #4 exists for this port with slew control feature */ 2372 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO4 0u 2373 /* Indicates that pin #5 exists for this port with slew control feature */ 2374 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO5 0u 2375 /* Indicates that pin #6 exists for this port with slew control feature */ 2376 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO6 0u 2377 /* Indicates that pin #7 exists for this port with slew control feature */ 2378 #define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO7 0u 2379 /* Number of AMUX splitter cells */ 2380 #define IOSS_HSIOM_AMUX_SPLIT_NR 8u 2381 /* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ 2382 #define IOSS_HSIOM_HSIOM_PORT_NR 15u 2383 /* Number of PWR/GND MONITOR CELLs in the device */ 2384 #define IOSS_HSIOM_MONITOR_NR 0u 2385 /* Number of PWR/GND MONITOR CELLs in range 0..31 */ 2386 #define IOSS_HSIOM_MONITOR_NR_0_31 0u 2387 /* Number of PWR/GND MONITOR CELLs in range 32..63 */ 2388 #define IOSS_HSIOM_MONITOR_NR_32_63 0u 2389 /* Number of PWR/GND MONITOR CELLs in range 64..95 */ 2390 #define IOSS_HSIOM_MONITOR_NR_64_95 0u 2391 /* Number of PWR/GND MONITOR CELLs in range 96..127 */ 2392 #define IOSS_HSIOM_MONITOR_NR_96_127 0u 2393 /* Indicates the presence of alternate JTAG interface */ 2394 #define IOSS_HSIOM_ALTJTAG_PRESENT 0u 2395 /* Mask of SMARTIO instances presence */ 2396 #define IOSS_SMARTIO_SMARTIO_MASK 768u 2397 /* Number of ports supoprting up to 4 COMs */ 2398 #define LCD_NUMPORTS 8u 2399 /* Number of ports supporting up to 8 COMs */ 2400 #define LCD_NUMPORTS8 8u 2401 /* Number of ports supporting up to 16 COMs */ 2402 #define LCD_NUMPORTS16 0u 2403 /* Max number of LCD commons supported */ 2404 #define LCD_CHIP_TOP_COM_NR 8u 2405 /* Max number of LCD pins (total) supported */ 2406 #define LCD_CHIP_TOP_PIN_NR 62u 2407 /* Number of IREF outputs from AREF */ 2408 #define PASS_NR_IREFS 4u 2409 /* Number of CTBs in the Subsystem */ 2410 #define PASS_NR_CTBS 0u 2411 /* Number of CTDACs in the Subsystem */ 2412 #define PASS_NR_CTDACS 0u 2413 /* CTB0 Exists */ 2414 #define PASS_CTB0_EXISTS 0u 2415 /* CTB1 Exists */ 2416 #define PASS_CTB1_EXISTS 0u 2417 /* CTB2 Exists */ 2418 #define PASS_CTB2_EXISTS 0u 2419 /* CTB3 Exists */ 2420 #define PASS_CTB3_EXISTS 0u 2421 /* CTDAC0 Exists */ 2422 #define PASS_CTDAC0_EXISTS 0u 2423 /* CTDAC1 Exists */ 2424 #define PASS_CTDAC1_EXISTS 0u 2425 /* CTDAC2 Exists */ 2426 #define PASS_CTDAC2_EXISTS 0u 2427 /* CTDAC3 Exists */ 2428 #define PASS_CTDAC3_EXISTS 0u 2429 #define PASS_CTBM_CTDAC_PRESENT 0u 2430 /* Number of SAR channels */ 2431 #define PASS_SAR_SAR_CHANNELS 16u 2432 /* Averaging logic present in SAR */ 2433 #define PASS_SAR_SAR_AVERAGE 1u 2434 /* Range detect logic present in SAR */ 2435 #define PASS_SAR_SAR_RANGEDET 1u 2436 /* Support for UAB sampling */ 2437 #define PASS_SAR_SAR_UAB 0u 2438 /* The number of protection contexts ([2, 16]). */ 2439 #define PERI_PC_NR 8u 2440 /* Master interface presence mask (4 bits) */ 2441 #define PERI_MS_PRESENT 15u 2442 /* Protection structures SRAM ECC present or not ('0': no, '1': yes) */ 2443 #define PERI_ECC_PRESENT 0u 2444 /* Protection structures SRAM address ECC present or not ('0': no, '1': yes) */ 2445 #define PERI_ECC_ADDR_PRESENT 0u 2446 /* Clock control functionality present ('0': no, '1': yes) */ 2447 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2448 /* Slave present (0:No, 1:Yes) */ 2449 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2450 /* Slave present (0:No, 1:Yes) */ 2451 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2452 /* Slave present (0:No, 1:Yes) */ 2453 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2454 /* Slave present (0:No, 1:Yes) */ 2455 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2456 /* Slave present (0:No, 1:Yes) */ 2457 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2458 /* Slave present (0:No, 1:Yes) */ 2459 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2460 /* Slave present (0:No, 1:Yes) */ 2461 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2462 /* Slave present (0:No, 1:Yes) */ 2463 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2464 /* Slave present (0:No, 1:Yes) */ 2465 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2466 /* Slave present (0:No, 1:Yes) */ 2467 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2468 /* Slave present (0:No, 1:Yes) */ 2469 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2470 /* Slave present (0:No, 1:Yes) */ 2471 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2472 /* Slave present (0:No, 1:Yes) */ 2473 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2474 /* Slave present (0:No, 1:Yes) */ 2475 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2476 /* Slave present (0:No, 1:Yes) */ 2477 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2478 /* Slave present (0:No, 1:Yes) */ 2479 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2480 /* Clock control functionality present ('0': no, '1': yes) */ 2481 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2482 /* Slave present (0:No, 1:Yes) */ 2483 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2484 /* Slave present (0:No, 1:Yes) */ 2485 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2486 /* Slave present (0:No, 1:Yes) */ 2487 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2488 /* Slave present (0:No, 1:Yes) */ 2489 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2490 /* Slave present (0:No, 1:Yes) */ 2491 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2492 /* Slave present (0:No, 1:Yes) */ 2493 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2494 /* Slave present (0:No, 1:Yes) */ 2495 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2496 /* Slave present (0:No, 1:Yes) */ 2497 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2498 /* Slave present (0:No, 1:Yes) */ 2499 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2500 /* Slave present (0:No, 1:Yes) */ 2501 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2502 /* Slave present (0:No, 1:Yes) */ 2503 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2504 /* Slave present (0:No, 1:Yes) */ 2505 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2506 /* Slave present (0:No, 1:Yes) */ 2507 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2508 /* Slave present (0:No, 1:Yes) */ 2509 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2510 /* Slave present (0:No, 1:Yes) */ 2511 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2512 /* Slave present (0:No, 1:Yes) */ 2513 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2514 /* Clock control functionality present ('0': no, '1': yes) */ 2515 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u 2516 /* Slave present (0:No, 1:Yes) */ 2517 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2518 /* Slave present (0:No, 1:Yes) */ 2519 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2520 /* Slave present (0:No, 1:Yes) */ 2521 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2522 /* Slave present (0:No, 1:Yes) */ 2523 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u 2524 /* Slave present (0:No, 1:Yes) */ 2525 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u 2526 /* Slave present (0:No, 1:Yes) */ 2527 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2528 /* Slave present (0:No, 1:Yes) */ 2529 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u 2530 /* Slave present (0:No, 1:Yes) */ 2531 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u 2532 /* Slave present (0:No, 1:Yes) */ 2533 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u 2534 /* Slave present (0:No, 1:Yes) */ 2535 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u 2536 /* Slave present (0:No, 1:Yes) */ 2537 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 1u 2538 /* Slave present (0:No, 1:Yes) */ 2539 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2540 /* Slave present (0:No, 1:Yes) */ 2541 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 1u 2542 /* Slave present (0:No, 1:Yes) */ 2543 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 1u 2544 /* Slave present (0:No, 1:Yes) */ 2545 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2546 /* Slave present (0:No, 1:Yes) */ 2547 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2548 /* Clock control functionality present ('0': no, '1': yes) */ 2549 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2550 /* Slave present (0:No, 1:Yes) */ 2551 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2552 /* Slave present (0:No, 1:Yes) */ 2553 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2554 /* Slave present (0:No, 1:Yes) */ 2555 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2556 /* Slave present (0:No, 1:Yes) */ 2557 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2558 /* Slave present (0:No, 1:Yes) */ 2559 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2560 /* Slave present (0:No, 1:Yes) */ 2561 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 1u 2562 /* Slave present (0:No, 1:Yes) */ 2563 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 1u 2564 /* Slave present (0:No, 1:Yes) */ 2565 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2566 /* Slave present (0:No, 1:Yes) */ 2567 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 1u 2568 /* Slave present (0:No, 1:Yes) */ 2569 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 1u 2570 /* Slave present (0:No, 1:Yes) */ 2571 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2572 /* Slave present (0:No, 1:Yes) */ 2573 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 1u 2574 /* Slave present (0:No, 1:Yes) */ 2575 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2576 /* Slave present (0:No, 1:Yes) */ 2577 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2578 /* Slave present (0:No, 1:Yes) */ 2579 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2580 /* Slave present (0:No, 1:Yes) */ 2581 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 1u 2582 /* Clock control functionality present ('0': no, '1': yes) */ 2583 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2584 /* Slave present (0:No, 1:Yes) */ 2585 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2586 /* Slave present (0:No, 1:Yes) */ 2587 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2588 /* Slave present (0:No, 1:Yes) */ 2589 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2590 /* Slave present (0:No, 1:Yes) */ 2591 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2592 /* Slave present (0:No, 1:Yes) */ 2593 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2594 /* Slave present (0:No, 1:Yes) */ 2595 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2596 /* Slave present (0:No, 1:Yes) */ 2597 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 1u 2598 /* Slave present (0:No, 1:Yes) */ 2599 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 1u 2600 /* Slave present (0:No, 1:Yes) */ 2601 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2602 /* Slave present (0:No, 1:Yes) */ 2603 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2604 /* Slave present (0:No, 1:Yes) */ 2605 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2606 /* Slave present (0:No, 1:Yes) */ 2607 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2608 /* Slave present (0:No, 1:Yes) */ 2609 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2610 /* Slave present (0:No, 1:Yes) */ 2611 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2612 /* Slave present (0:No, 1:Yes) */ 2613 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2614 /* Slave present (0:No, 1:Yes) */ 2615 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2616 /* Clock control functionality present ('0': no, '1': yes) */ 2617 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2618 /* Slave present (0:No, 1:Yes) */ 2619 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2620 /* Slave present (0:No, 1:Yes) */ 2621 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2622 /* Slave present (0:No, 1:Yes) */ 2623 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2624 /* Slave present (0:No, 1:Yes) */ 2625 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2626 /* Slave present (0:No, 1:Yes) */ 2627 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2628 /* Slave present (0:No, 1:Yes) */ 2629 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2630 /* Slave present (0:No, 1:Yes) */ 2631 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2632 /* Slave present (0:No, 1:Yes) */ 2633 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2634 /* Slave present (0:No, 1:Yes) */ 2635 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2636 /* Slave present (0:No, 1:Yes) */ 2637 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2638 /* Slave present (0:No, 1:Yes) */ 2639 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2640 /* Slave present (0:No, 1:Yes) */ 2641 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2642 /* Slave present (0:No, 1:Yes) */ 2643 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2644 /* Slave present (0:No, 1:Yes) */ 2645 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2646 /* Slave present (0:No, 1:Yes) */ 2647 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2648 /* Slave present (0:No, 1:Yes) */ 2649 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2650 /* Clock control functionality present ('0': no, '1': yes) */ 2651 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2652 /* Slave present (0:No, 1:Yes) */ 2653 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2654 /* Slave present (0:No, 1:Yes) */ 2655 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2656 /* Slave present (0:No, 1:Yes) */ 2657 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2658 /* Slave present (0:No, 1:Yes) */ 2659 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 1u 2660 /* Slave present (0:No, 1:Yes) */ 2661 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u 2662 /* Slave present (0:No, 1:Yes) */ 2663 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u 2664 /* Slave present (0:No, 1:Yes) */ 2665 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u 2666 /* Slave present (0:No, 1:Yes) */ 2667 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 1u 2668 /* Slave present (0:No, 1:Yes) */ 2669 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 1u 2670 /* Slave present (0:No, 1:Yes) */ 2671 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 1u 2672 /* Slave present (0:No, 1:Yes) */ 2673 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 1u 2674 /* Slave present (0:No, 1:Yes) */ 2675 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 1u 2676 /* Slave present (0:No, 1:Yes) */ 2677 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 1u 2678 /* Slave present (0:No, 1:Yes) */ 2679 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2680 /* Slave present (0:No, 1:Yes) */ 2681 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2682 /* Slave present (0:No, 1:Yes) */ 2683 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2684 /* Clock control functionality present ('0': no, '1': yes) */ 2685 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2686 /* Slave present (0:No, 1:Yes) */ 2687 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2688 /* Slave present (0:No, 1:Yes) */ 2689 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2690 /* Slave present (0:No, 1:Yes) */ 2691 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2692 /* Slave present (0:No, 1:Yes) */ 2693 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2694 /* Slave present (0:No, 1:Yes) */ 2695 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2696 /* Slave present (0:No, 1:Yes) */ 2697 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2698 /* Slave present (0:No, 1:Yes) */ 2699 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2700 /* Slave present (0:No, 1:Yes) */ 2701 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2702 /* Slave present (0:No, 1:Yes) */ 2703 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2704 /* Slave present (0:No, 1:Yes) */ 2705 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2706 /* Slave present (0:No, 1:Yes) */ 2707 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2708 /* Slave present (0:No, 1:Yes) */ 2709 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2710 /* Slave present (0:No, 1:Yes) */ 2711 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2712 /* Slave present (0:No, 1:Yes) */ 2713 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2714 /* Slave present (0:No, 1:Yes) */ 2715 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2716 /* Slave present (0:No, 1:Yes) */ 2717 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2718 /* Clock control functionality present ('0': no, '1': yes) */ 2719 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2720 /* Slave present (0:No, 1:Yes) */ 2721 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2722 /* Slave present (0:No, 1:Yes) */ 2723 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2724 /* Slave present (0:No, 1:Yes) */ 2725 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2726 /* Slave present (0:No, 1:Yes) */ 2727 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2728 /* Slave present (0:No, 1:Yes) */ 2729 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2730 /* Slave present (0:No, 1:Yes) */ 2731 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2732 /* Slave present (0:No, 1:Yes) */ 2733 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2734 /* Slave present (0:No, 1:Yes) */ 2735 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2736 /* Slave present (0:No, 1:Yes) */ 2737 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2738 /* Slave present (0:No, 1:Yes) */ 2739 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2740 /* Slave present (0:No, 1:Yes) */ 2741 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2742 /* Slave present (0:No, 1:Yes) */ 2743 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2744 /* Slave present (0:No, 1:Yes) */ 2745 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2746 /* Slave present (0:No, 1:Yes) */ 2747 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2748 /* Slave present (0:No, 1:Yes) */ 2749 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2750 /* Slave present (0:No, 1:Yes) */ 2751 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2752 /* Clock control functionality present ('0': no, '1': yes) */ 2753 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2754 /* Slave present (0:No, 1:Yes) */ 2755 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u 2756 /* Slave present (0:No, 1:Yes) */ 2757 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2758 /* Slave present (0:No, 1:Yes) */ 2759 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2760 /* Slave present (0:No, 1:Yes) */ 2761 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2762 /* Slave present (0:No, 1:Yes) */ 2763 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2764 /* Slave present (0:No, 1:Yes) */ 2765 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2766 /* Slave present (0:No, 1:Yes) */ 2767 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2768 /* Slave present (0:No, 1:Yes) */ 2769 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2770 /* Slave present (0:No, 1:Yes) */ 2771 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2772 /* Slave present (0:No, 1:Yes) */ 2773 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2774 /* Slave present (0:No, 1:Yes) */ 2775 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2776 /* Slave present (0:No, 1:Yes) */ 2777 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2778 /* Slave present (0:No, 1:Yes) */ 2779 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2780 /* Slave present (0:No, 1:Yes) */ 2781 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2782 /* Slave present (0:No, 1:Yes) */ 2783 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2784 /* Slave present (0:No, 1:Yes) */ 2785 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2786 /* Clock control functionality present ('0': no, '1': yes) */ 2787 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2788 /* Slave present (0:No, 1:Yes) */ 2789 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2790 /* Slave present (0:No, 1:Yes) */ 2791 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 1u 2792 /* Slave present (0:No, 1:Yes) */ 2793 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 1u 2794 /* Slave present (0:No, 1:Yes) */ 2795 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 1u 2796 /* Slave present (0:No, 1:Yes) */ 2797 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2798 /* Slave present (0:No, 1:Yes) */ 2799 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2800 /* Slave present (0:No, 1:Yes) */ 2801 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2802 /* Slave present (0:No, 1:Yes) */ 2803 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2804 /* Slave present (0:No, 1:Yes) */ 2805 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2806 /* Slave present (0:No, 1:Yes) */ 2807 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2808 /* Slave present (0:No, 1:Yes) */ 2809 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2810 /* Slave present (0:No, 1:Yes) */ 2811 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2812 /* Slave present (0:No, 1:Yes) */ 2813 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2814 /* Slave present (0:No, 1:Yes) */ 2815 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2816 /* Slave present (0:No, 1:Yes) */ 2817 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2818 /* Slave present (0:No, 1:Yes) */ 2819 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2820 /* Clock control functionality present ('0': no, '1': yes) */ 2821 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2822 /* Slave present (0:No, 1:Yes) */ 2823 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2824 /* Slave present (0:No, 1:Yes) */ 2825 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2826 /* Slave present (0:No, 1:Yes) */ 2827 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2828 /* Slave present (0:No, 1:Yes) */ 2829 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2830 /* Slave present (0:No, 1:Yes) */ 2831 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2832 /* Slave present (0:No, 1:Yes) */ 2833 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2834 /* Slave present (0:No, 1:Yes) */ 2835 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2836 /* Slave present (0:No, 1:Yes) */ 2837 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2838 /* Slave present (0:No, 1:Yes) */ 2839 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2840 /* Slave present (0:No, 1:Yes) */ 2841 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2842 /* Slave present (0:No, 1:Yes) */ 2843 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2844 /* Slave present (0:No, 1:Yes) */ 2845 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2846 /* Slave present (0:No, 1:Yes) */ 2847 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2848 /* Slave present (0:No, 1:Yes) */ 2849 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2850 /* Slave present (0:No, 1:Yes) */ 2851 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2852 /* Slave present (0:No, 1:Yes) */ 2853 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2854 /* Clock control functionality present ('0': no, '1': yes) */ 2855 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2856 /* Slave present (0:No, 1:Yes) */ 2857 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2858 /* Slave present (0:No, 1:Yes) */ 2859 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2860 /* Slave present (0:No, 1:Yes) */ 2861 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2862 /* Slave present (0:No, 1:Yes) */ 2863 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2864 /* Slave present (0:No, 1:Yes) */ 2865 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2866 /* Slave present (0:No, 1:Yes) */ 2867 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2868 /* Slave present (0:No, 1:Yes) */ 2869 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2870 /* Slave present (0:No, 1:Yes) */ 2871 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2872 /* Slave present (0:No, 1:Yes) */ 2873 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2874 /* Slave present (0:No, 1:Yes) */ 2875 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2876 /* Slave present (0:No, 1:Yes) */ 2877 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2878 /* Slave present (0:No, 1:Yes) */ 2879 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2880 /* Slave present (0:No, 1:Yes) */ 2881 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2882 /* Slave present (0:No, 1:Yes) */ 2883 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2884 /* Slave present (0:No, 1:Yes) */ 2885 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2886 /* Slave present (0:No, 1:Yes) */ 2887 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2888 /* Clock control functionality present ('0': no, '1': yes) */ 2889 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2890 /* Slave present (0:No, 1:Yes) */ 2891 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2892 /* Slave present (0:No, 1:Yes) */ 2893 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2894 /* Slave present (0:No, 1:Yes) */ 2895 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2896 /* Slave present (0:No, 1:Yes) */ 2897 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2898 /* Slave present (0:No, 1:Yes) */ 2899 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2900 /* Slave present (0:No, 1:Yes) */ 2901 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2902 /* Slave present (0:No, 1:Yes) */ 2903 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2904 /* Slave present (0:No, 1:Yes) */ 2905 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2906 /* Slave present (0:No, 1:Yes) */ 2907 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2908 /* Slave present (0:No, 1:Yes) */ 2909 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2910 /* Slave present (0:No, 1:Yes) */ 2911 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2912 /* Slave present (0:No, 1:Yes) */ 2913 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2914 /* Slave present (0:No, 1:Yes) */ 2915 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2916 /* Slave present (0:No, 1:Yes) */ 2917 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2918 /* Slave present (0:No, 1:Yes) */ 2919 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2920 /* Slave present (0:No, 1:Yes) */ 2921 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2922 /* Clock control functionality present ('0': no, '1': yes) */ 2923 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2924 /* Slave present (0:No, 1:Yes) */ 2925 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2926 /* Slave present (0:No, 1:Yes) */ 2927 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2928 /* Slave present (0:No, 1:Yes) */ 2929 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2930 /* Slave present (0:No, 1:Yes) */ 2931 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2932 /* Slave present (0:No, 1:Yes) */ 2933 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2934 /* Slave present (0:No, 1:Yes) */ 2935 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2936 /* Slave present (0:No, 1:Yes) */ 2937 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2938 /* Slave present (0:No, 1:Yes) */ 2939 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2940 /* Slave present (0:No, 1:Yes) */ 2941 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2942 /* Slave present (0:No, 1:Yes) */ 2943 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2944 /* Slave present (0:No, 1:Yes) */ 2945 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2946 /* Slave present (0:No, 1:Yes) */ 2947 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2948 /* Slave present (0:No, 1:Yes) */ 2949 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2950 /* Slave present (0:No, 1:Yes) */ 2951 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2952 /* Slave present (0:No, 1:Yes) */ 2953 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2954 /* Slave present (0:No, 1:Yes) */ 2955 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2956 /* Clock control functionality present ('0': no, '1': yes) */ 2957 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u 2958 /* Slave present (0:No, 1:Yes) */ 2959 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u 2960 /* Slave present (0:No, 1:Yes) */ 2961 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u 2962 /* Slave present (0:No, 1:Yes) */ 2963 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u 2964 /* Slave present (0:No, 1:Yes) */ 2965 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u 2966 /* Slave present (0:No, 1:Yes) */ 2967 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u 2968 /* Slave present (0:No, 1:Yes) */ 2969 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u 2970 /* Slave present (0:No, 1:Yes) */ 2971 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u 2972 /* Slave present (0:No, 1:Yes) */ 2973 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u 2974 /* Slave present (0:No, 1:Yes) */ 2975 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u 2976 /* Slave present (0:No, 1:Yes) */ 2977 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u 2978 /* Slave present (0:No, 1:Yes) */ 2979 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u 2980 /* Slave present (0:No, 1:Yes) */ 2981 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u 2982 /* Slave present (0:No, 1:Yes) */ 2983 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u 2984 /* Slave present (0:No, 1:Yes) */ 2985 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u 2986 /* Slave present (0:No, 1:Yes) */ 2987 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u 2988 /* Slave present (0:No, 1:Yes) */ 2989 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u 2990 /* Number of programmable clocks (outputs) */ 2991 #define PERI_CLOCK_NR 54u 2992 /* Number of 8.0 dividers */ 2993 #define PERI_DIV_8_NR 8u 2994 /* Number of 16.0 dividers */ 2995 #define PERI_DIV_16_NR 16u 2996 /* Number of 16.5 (fractional) dividers */ 2997 #define PERI_DIV_16_5_NR 4u 2998 /* Number of 24.5 (fractional) dividers */ 2999 #define PERI_DIV_24_5_NR 1u 3000 /* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ 3001 #define PERI_DIV_ADDR_WIDTH 4u 3002 /* Timeout functionality present ('0': no, '1': yes) */ 3003 #define PERI_TIMEOUT_PRESENT 1u 3004 /* Trigger module present (0=No, 1=Yes) */ 3005 #define PERI_TR 1u 3006 /* Number of trigger groups */ 3007 #define PERI_TR_GROUP_NR 10u 3008 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3009 #define PERI_TR_GROUP_NR0_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3010 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3011 #define PERI_TR_GROUP_NR1_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3012 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3013 #define PERI_TR_GROUP_NR2_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3014 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3015 #define PERI_TR_GROUP_NR3_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3016 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3017 #define PERI_TR_GROUP_NR4_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3018 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3019 #define PERI_TR_GROUP_NR5_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3020 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3021 #define PERI_TR_GROUP_NR6_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3022 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3023 #define PERI_TR_GROUP_NR7_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3024 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3025 #define PERI_TR_GROUP_NR8_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3026 /* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ 3027 #define PERI_TR_GROUP_NR9_TR_GROUP_TR_MANIPULATION_PRESENT 1u 3028 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3029 #define PERI_TR_1TO1_GROUP_NR0_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3030 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3031 #define PERI_TR_1TO1_GROUP_NR1_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3032 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3033 #define PERI_TR_1TO1_GROUP_NR2_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3034 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3035 #define PERI_TR_1TO1_GROUP_NR3_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3036 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3037 #define PERI_TR_1TO1_GROUP_NR4_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3038 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3039 #define PERI_TR_1TO1_GROUP_NR5_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3040 /* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ 3041 #define PERI_TR_1TO1_GROUP_NR6_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u 3042 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3043 #define PERI_MASTER_WIDTH 8u 3044 /* Number of profiling counters. Legal range [1, 32] */ 3045 #define PROFILE_PRFL_CNT_NR 8u 3046 /* Number of monitor event signals. Legal range [1, 128] */ 3047 #define PROFILE_PRFL_MONITOR_NR 128u 3048 /* DeepSleep support ('0':no, '1': yes) */ 3049 #define SCB0_DEEPSLEEP 0u 3050 /* Externally clocked support? ('0': no, '1': yes) */ 3051 #define SCB0_EC 0u 3052 /* I2C master support? ('0': no, '1': yes) */ 3053 #define SCB0_I2C_M 1u 3054 /* I2C slave support? ('0': no, '1': yes) */ 3055 #define SCB0_I2C_S 1u 3056 /* I2C support? (I2C_M | I2C_S) */ 3057 #define SCB0_I2C 1u 3058 /* I2C glitch filters present? ('0': no, '1': yes) */ 3059 #define SCB0_I2C_GLITCH 1u 3060 /* I2C externally clocked support? ('0': no, '1': yes) */ 3061 #define SCB0_I2C_EC 0u 3062 /* I2C master and slave support? (I2C_M & I2C_S) */ 3063 #define SCB0_I2C_M_S 1u 3064 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3065 #define SCB0_I2C_S_EC 0u 3066 /* SPI master support? ('0': no, '1': yes) */ 3067 #define SCB0_SPI_M 1u 3068 /* SPI slave support? ('0': no, '1': yes) */ 3069 #define SCB0_SPI_S 1u 3070 /* SPI support? (SPI_M | SPI_S) */ 3071 #define SCB0_SPI 1u 3072 /* SPI externally clocked support? ('0': no, '1': yes) */ 3073 #define SCB0_SPI_EC 0u 3074 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3075 #define SCB0_SPI_S_EC 0u 3076 /* UART support? ('0': no, '1': yes) */ 3077 #define SCB0_UART 1u 3078 /* SPI or UART (SPI | UART) */ 3079 #define SCB0_SPI_UART 1u 3080 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3081 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3082 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3083 #define SCB0_EZ_DATA_NR 256u 3084 /* Command/response mode support? ('0': no, '1': yes) */ 3085 #define SCB0_CMD_RESP 0u 3086 /* EZ mode support? ('0': no, '1': yes) */ 3087 #define SCB0_EZ 0u 3088 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3089 #define SCB0_EZ_CMD_RESP 0u 3090 /* I2C slave with EZ mode (I2C_S & EZ) */ 3091 #define SCB0_I2C_S_EZ 0u 3092 /* SPI slave with EZ mode (SPI_S & EZ) */ 3093 #define SCB0_SPI_S_EZ 0u 3094 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3095 #define SCB0_I2C_FAST_PLUS 1u 3096 /* Number of used spi_select signals (max 4) */ 3097 #define SCB0_CHIP_TOP_SPI_SEL_NR 3u 3098 /* DeepSleep support ('0':no, '1': yes) */ 3099 #define SCB1_DEEPSLEEP 0u 3100 /* Externally clocked support? ('0': no, '1': yes) */ 3101 #define SCB1_EC 0u 3102 /* I2C master support? ('0': no, '1': yes) */ 3103 #define SCB1_I2C_M 1u 3104 /* I2C slave support? ('0': no, '1': yes) */ 3105 #define SCB1_I2C_S 1u 3106 /* I2C support? (I2C_M | I2C_S) */ 3107 #define SCB1_I2C 1u 3108 /* I2C glitch filters present? ('0': no, '1': yes) */ 3109 #define SCB1_I2C_GLITCH 1u 3110 /* I2C externally clocked support? ('0': no, '1': yes) */ 3111 #define SCB1_I2C_EC 0u 3112 /* I2C master and slave support? (I2C_M & I2C_S) */ 3113 #define SCB1_I2C_M_S 1u 3114 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3115 #define SCB1_I2C_S_EC 0u 3116 /* SPI master support? ('0': no, '1': yes) */ 3117 #define SCB1_SPI_M 1u 3118 /* SPI slave support? ('0': no, '1': yes) */ 3119 #define SCB1_SPI_S 1u 3120 /* SPI support? (SPI_M | SPI_S) */ 3121 #define SCB1_SPI 1u 3122 /* SPI externally clocked support? ('0': no, '1': yes) */ 3123 #define SCB1_SPI_EC 0u 3124 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3125 #define SCB1_SPI_S_EC 0u 3126 /* UART support? ('0': no, '1': yes) */ 3127 #define SCB1_UART 1u 3128 /* SPI or UART (SPI | UART) */ 3129 #define SCB1_SPI_UART 1u 3130 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3131 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3132 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3133 #define SCB1_EZ_DATA_NR 256u 3134 /* Command/response mode support? ('0': no, '1': yes) */ 3135 #define SCB1_CMD_RESP 0u 3136 /* EZ mode support? ('0': no, '1': yes) */ 3137 #define SCB1_EZ 0u 3138 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3139 #define SCB1_EZ_CMD_RESP 0u 3140 /* I2C slave with EZ mode (I2C_S & EZ) */ 3141 #define SCB1_I2C_S_EZ 0u 3142 /* SPI slave with EZ mode (SPI_S & EZ) */ 3143 #define SCB1_SPI_S_EZ 0u 3144 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3145 #define SCB1_I2C_FAST_PLUS 1u 3146 /* Number of used spi_select signals (max 4) */ 3147 #define SCB1_CHIP_TOP_SPI_SEL_NR 4u 3148 /* DeepSleep support ('0':no, '1': yes) */ 3149 #define SCB2_DEEPSLEEP 0u 3150 /* Externally clocked support? ('0': no, '1': yes) */ 3151 #define SCB2_EC 0u 3152 /* I2C master support? ('0': no, '1': yes) */ 3153 #define SCB2_I2C_M 1u 3154 /* I2C slave support? ('0': no, '1': yes) */ 3155 #define SCB2_I2C_S 1u 3156 /* I2C support? (I2C_M | I2C_S) */ 3157 #define SCB2_I2C 1u 3158 /* I2C glitch filters present? ('0': no, '1': yes) */ 3159 #define SCB2_I2C_GLITCH 1u 3160 /* I2C externally clocked support? ('0': no, '1': yes) */ 3161 #define SCB2_I2C_EC 0u 3162 /* I2C master and slave support? (I2C_M & I2C_S) */ 3163 #define SCB2_I2C_M_S 1u 3164 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3165 #define SCB2_I2C_S_EC 0u 3166 /* SPI master support? ('0': no, '1': yes) */ 3167 #define SCB2_SPI_M 1u 3168 /* SPI slave support? ('0': no, '1': yes) */ 3169 #define SCB2_SPI_S 1u 3170 /* SPI support? (SPI_M | SPI_S) */ 3171 #define SCB2_SPI 1u 3172 /* SPI externally clocked support? ('0': no, '1': yes) */ 3173 #define SCB2_SPI_EC 0u 3174 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3175 #define SCB2_SPI_S_EC 0u 3176 /* UART support? ('0': no, '1': yes) */ 3177 #define SCB2_UART 1u 3178 /* SPI or UART (SPI | UART) */ 3179 #define SCB2_SPI_UART 1u 3180 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3181 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3182 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3183 #define SCB2_EZ_DATA_NR 256u 3184 /* Command/response mode support? ('0': no, '1': yes) */ 3185 #define SCB2_CMD_RESP 0u 3186 /* EZ mode support? ('0': no, '1': yes) */ 3187 #define SCB2_EZ 0u 3188 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3189 #define SCB2_EZ_CMD_RESP 0u 3190 /* I2C slave with EZ mode (I2C_S & EZ) */ 3191 #define SCB2_I2C_S_EZ 0u 3192 /* SPI slave with EZ mode (SPI_S & EZ) */ 3193 #define SCB2_SPI_S_EZ 0u 3194 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3195 #define SCB2_I2C_FAST_PLUS 1u 3196 /* Number of used spi_select signals (max 4) */ 3197 #define SCB2_CHIP_TOP_SPI_SEL_NR 4u 3198 /* DeepSleep support ('0':no, '1': yes) */ 3199 #define SCB3_DEEPSLEEP 0u 3200 /* Externally clocked support? ('0': no, '1': yes) */ 3201 #define SCB3_EC 0u 3202 /* I2C master support? ('0': no, '1': yes) */ 3203 #define SCB3_I2C_M 1u 3204 /* I2C slave support? ('0': no, '1': yes) */ 3205 #define SCB3_I2C_S 1u 3206 /* I2C support? (I2C_M | I2C_S) */ 3207 #define SCB3_I2C 1u 3208 /* I2C glitch filters present? ('0': no, '1': yes) */ 3209 #define SCB3_I2C_GLITCH 1u 3210 /* I2C externally clocked support? ('0': no, '1': yes) */ 3211 #define SCB3_I2C_EC 0u 3212 /* I2C master and slave support? (I2C_M & I2C_S) */ 3213 #define SCB3_I2C_M_S 1u 3214 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3215 #define SCB3_I2C_S_EC 0u 3216 /* SPI master support? ('0': no, '1': yes) */ 3217 #define SCB3_SPI_M 1u 3218 /* SPI slave support? ('0': no, '1': yes) */ 3219 #define SCB3_SPI_S 1u 3220 /* SPI support? (SPI_M | SPI_S) */ 3221 #define SCB3_SPI 1u 3222 /* SPI externally clocked support? ('0': no, '1': yes) */ 3223 #define SCB3_SPI_EC 0u 3224 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3225 #define SCB3_SPI_S_EC 0u 3226 /* UART support? ('0': no, '1': yes) */ 3227 #define SCB3_UART 1u 3228 /* SPI or UART (SPI | UART) */ 3229 #define SCB3_SPI_UART 1u 3230 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3231 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3232 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3233 #define SCB3_EZ_DATA_NR 256u 3234 /* Command/response mode support? ('0': no, '1': yes) */ 3235 #define SCB3_CMD_RESP 0u 3236 /* EZ mode support? ('0': no, '1': yes) */ 3237 #define SCB3_EZ 0u 3238 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3239 #define SCB3_EZ_CMD_RESP 0u 3240 /* I2C slave with EZ mode (I2C_S & EZ) */ 3241 #define SCB3_I2C_S_EZ 0u 3242 /* SPI slave with EZ mode (SPI_S & EZ) */ 3243 #define SCB3_SPI_S_EZ 0u 3244 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3245 #define SCB3_I2C_FAST_PLUS 1u 3246 /* Number of used spi_select signals (max 4) */ 3247 #define SCB3_CHIP_TOP_SPI_SEL_NR 4u 3248 /* DeepSleep support ('0':no, '1': yes) */ 3249 #define SCB4_DEEPSLEEP 0u 3250 /* Externally clocked support? ('0': no, '1': yes) */ 3251 #define SCB4_EC 0u 3252 /* I2C master support? ('0': no, '1': yes) */ 3253 #define SCB4_I2C_M 1u 3254 /* I2C slave support? ('0': no, '1': yes) */ 3255 #define SCB4_I2C_S 1u 3256 /* I2C support? (I2C_M | I2C_S) */ 3257 #define SCB4_I2C 1u 3258 /* I2C glitch filters present? ('0': no, '1': yes) */ 3259 #define SCB4_I2C_GLITCH 1u 3260 /* I2C externally clocked support? ('0': no, '1': yes) */ 3261 #define SCB4_I2C_EC 0u 3262 /* I2C master and slave support? (I2C_M & I2C_S) */ 3263 #define SCB4_I2C_M_S 1u 3264 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3265 #define SCB4_I2C_S_EC 0u 3266 /* SPI master support? ('0': no, '1': yes) */ 3267 #define SCB4_SPI_M 1u 3268 /* SPI slave support? ('0': no, '1': yes) */ 3269 #define SCB4_SPI_S 1u 3270 /* SPI support? (SPI_M | SPI_S) */ 3271 #define SCB4_SPI 1u 3272 /* SPI externally clocked support? ('0': no, '1': yes) */ 3273 #define SCB4_SPI_EC 0u 3274 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3275 #define SCB4_SPI_S_EC 0u 3276 /* UART support? ('0': no, '1': yes) */ 3277 #define SCB4_UART 1u 3278 /* SPI or UART (SPI | UART) */ 3279 #define SCB4_SPI_UART 1u 3280 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3281 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3282 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3283 #define SCB4_EZ_DATA_NR 256u 3284 /* Command/response mode support? ('0': no, '1': yes) */ 3285 #define SCB4_CMD_RESP 0u 3286 /* EZ mode support? ('0': no, '1': yes) */ 3287 #define SCB4_EZ 0u 3288 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3289 #define SCB4_EZ_CMD_RESP 0u 3290 /* I2C slave with EZ mode (I2C_S & EZ) */ 3291 #define SCB4_I2C_S_EZ 0u 3292 /* SPI slave with EZ mode (SPI_S & EZ) */ 3293 #define SCB4_SPI_S_EZ 0u 3294 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3295 #define SCB4_I2C_FAST_PLUS 1u 3296 /* Number of used spi_select signals (max 4) */ 3297 #define SCB4_CHIP_TOP_SPI_SEL_NR 4u 3298 /* DeepSleep support ('0':no, '1': yes) */ 3299 #define SCB5_DEEPSLEEP 0u 3300 /* Externally clocked support? ('0': no, '1': yes) */ 3301 #define SCB5_EC 0u 3302 /* I2C master support? ('0': no, '1': yes) */ 3303 #define SCB5_I2C_M 1u 3304 /* I2C slave support? ('0': no, '1': yes) */ 3305 #define SCB5_I2C_S 1u 3306 /* I2C support? (I2C_M | I2C_S) */ 3307 #define SCB5_I2C 1u 3308 /* I2C glitch filters present? ('0': no, '1': yes) */ 3309 #define SCB5_I2C_GLITCH 1u 3310 /* I2C externally clocked support? ('0': no, '1': yes) */ 3311 #define SCB5_I2C_EC 0u 3312 /* I2C master and slave support? (I2C_M & I2C_S) */ 3313 #define SCB5_I2C_M_S 1u 3314 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3315 #define SCB5_I2C_S_EC 0u 3316 /* SPI master support? ('0': no, '1': yes) */ 3317 #define SCB5_SPI_M 1u 3318 /* SPI slave support? ('0': no, '1': yes) */ 3319 #define SCB5_SPI_S 1u 3320 /* SPI support? (SPI_M | SPI_S) */ 3321 #define SCB5_SPI 1u 3322 /* SPI externally clocked support? ('0': no, '1': yes) */ 3323 #define SCB5_SPI_EC 0u 3324 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3325 #define SCB5_SPI_S_EC 0u 3326 /* UART support? ('0': no, '1': yes) */ 3327 #define SCB5_UART 1u 3328 /* SPI or UART (SPI | UART) */ 3329 #define SCB5_SPI_UART 1u 3330 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3331 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3332 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3333 #define SCB5_EZ_DATA_NR 256u 3334 /* Command/response mode support? ('0': no, '1': yes) */ 3335 #define SCB5_CMD_RESP 0u 3336 /* EZ mode support? ('0': no, '1': yes) */ 3337 #define SCB5_EZ 0u 3338 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3339 #define SCB5_EZ_CMD_RESP 0u 3340 /* I2C slave with EZ mode (I2C_S & EZ) */ 3341 #define SCB5_I2C_S_EZ 0u 3342 /* SPI slave with EZ mode (SPI_S & EZ) */ 3343 #define SCB5_SPI_S_EZ 0u 3344 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3345 #define SCB5_I2C_FAST_PLUS 1u 3346 /* Number of used spi_select signals (max 4) */ 3347 #define SCB5_CHIP_TOP_SPI_SEL_NR 4u 3348 /* DeepSleep support ('0':no, '1': yes) */ 3349 #define SCB6_DEEPSLEEP 0u 3350 /* Externally clocked support? ('0': no, '1': yes) */ 3351 #define SCB6_EC 0u 3352 /* I2C master support? ('0': no, '1': yes) */ 3353 #define SCB6_I2C_M 1u 3354 /* I2C slave support? ('0': no, '1': yes) */ 3355 #define SCB6_I2C_S 1u 3356 /* I2C support? (I2C_M | I2C_S) */ 3357 #define SCB6_I2C 1u 3358 /* I2C glitch filters present? ('0': no, '1': yes) */ 3359 #define SCB6_I2C_GLITCH 1u 3360 /* I2C externally clocked support? ('0': no, '1': yes) */ 3361 #define SCB6_I2C_EC 0u 3362 /* I2C master and slave support? (I2C_M & I2C_S) */ 3363 #define SCB6_I2C_M_S 1u 3364 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3365 #define SCB6_I2C_S_EC 0u 3366 /* SPI master support? ('0': no, '1': yes) */ 3367 #define SCB6_SPI_M 1u 3368 /* SPI slave support? ('0': no, '1': yes) */ 3369 #define SCB6_SPI_S 1u 3370 /* SPI support? (SPI_M | SPI_S) */ 3371 #define SCB6_SPI 1u 3372 /* SPI externally clocked support? ('0': no, '1': yes) */ 3373 #define SCB6_SPI_EC 0u 3374 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3375 #define SCB6_SPI_S_EC 0u 3376 /* UART support? ('0': no, '1': yes) */ 3377 #define SCB6_UART 1u 3378 /* SPI or UART (SPI | UART) */ 3379 #define SCB6_SPI_UART 1u 3380 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3381 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3382 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3383 #define SCB6_EZ_DATA_NR 256u 3384 /* Command/response mode support? ('0': no, '1': yes) */ 3385 #define SCB6_CMD_RESP 0u 3386 /* EZ mode support? ('0': no, '1': yes) */ 3387 #define SCB6_EZ 0u 3388 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3389 #define SCB6_EZ_CMD_RESP 0u 3390 /* I2C slave with EZ mode (I2C_S & EZ) */ 3391 #define SCB6_I2C_S_EZ 0u 3392 /* SPI slave with EZ mode (SPI_S & EZ) */ 3393 #define SCB6_SPI_S_EZ 0u 3394 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3395 #define SCB6_I2C_FAST_PLUS 1u 3396 /* Number of used spi_select signals (max 4) */ 3397 #define SCB6_CHIP_TOP_SPI_SEL_NR 4u 3398 /* DeepSleep support ('0':no, '1': yes) */ 3399 #define SCB7_DEEPSLEEP 0u 3400 /* Externally clocked support? ('0': no, '1': yes) */ 3401 #define SCB7_EC 0u 3402 /* I2C master support? ('0': no, '1': yes) */ 3403 #define SCB7_I2C_M 1u 3404 /* I2C slave support? ('0': no, '1': yes) */ 3405 #define SCB7_I2C_S 1u 3406 /* I2C support? (I2C_M | I2C_S) */ 3407 #define SCB7_I2C 1u 3408 /* I2C glitch filters present? ('0': no, '1': yes) */ 3409 #define SCB7_I2C_GLITCH 1u 3410 /* I2C externally clocked support? ('0': no, '1': yes) */ 3411 #define SCB7_I2C_EC 0u 3412 /* I2C master and slave support? (I2C_M & I2C_S) */ 3413 #define SCB7_I2C_M_S 1u 3414 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3415 #define SCB7_I2C_S_EC 0u 3416 /* SPI master support? ('0': no, '1': yes) */ 3417 #define SCB7_SPI_M 1u 3418 /* SPI slave support? ('0': no, '1': yes) */ 3419 #define SCB7_SPI_S 1u 3420 /* SPI support? (SPI_M | SPI_S) */ 3421 #define SCB7_SPI 1u 3422 /* SPI externally clocked support? ('0': no, '1': yes) */ 3423 #define SCB7_SPI_EC 0u 3424 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3425 #define SCB7_SPI_S_EC 0u 3426 /* UART support? ('0': no, '1': yes) */ 3427 #define SCB7_UART 1u 3428 /* SPI or UART (SPI | UART) */ 3429 #define SCB7_SPI_UART 1u 3430 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3431 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3432 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3433 #define SCB7_EZ_DATA_NR 256u 3434 /* Command/response mode support? ('0': no, '1': yes) */ 3435 #define SCB7_CMD_RESP 0u 3436 /* EZ mode support? ('0': no, '1': yes) */ 3437 #define SCB7_EZ 0u 3438 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3439 #define SCB7_EZ_CMD_RESP 0u 3440 /* I2C slave with EZ mode (I2C_S & EZ) */ 3441 #define SCB7_I2C_S_EZ 0u 3442 /* SPI slave with EZ mode (SPI_S & EZ) */ 3443 #define SCB7_SPI_S_EZ 0u 3444 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3445 #define SCB7_I2C_FAST_PLUS 1u 3446 /* Number of used spi_select signals (max 4) */ 3447 #define SCB7_CHIP_TOP_SPI_SEL_NR 3u 3448 /* DeepSleep support ('0':no, '1': yes) */ 3449 #define SCB8_DEEPSLEEP 1u 3450 /* Externally clocked support? ('0': no, '1': yes) */ 3451 #define SCB8_EC 1u 3452 /* I2C master support? ('0': no, '1': yes) */ 3453 #define SCB8_I2C_M 1u 3454 /* I2C slave support? ('0': no, '1': yes) */ 3455 #define SCB8_I2C_S 1u 3456 /* I2C support? (I2C_M | I2C_S) */ 3457 #define SCB8_I2C 1u 3458 /* I2C glitch filters present? ('0': no, '1': yes) */ 3459 #define SCB8_I2C_GLITCH 1u 3460 /* I2C externally clocked support? ('0': no, '1': yes) */ 3461 #define SCB8_I2C_EC 1u 3462 /* I2C master and slave support? (I2C_M & I2C_S) */ 3463 #define SCB8_I2C_M_S 1u 3464 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3465 #define SCB8_I2C_S_EC 1u 3466 /* SPI master support? ('0': no, '1': yes) */ 3467 #define SCB8_SPI_M 0u 3468 /* SPI slave support? ('0': no, '1': yes) */ 3469 #define SCB8_SPI_S 1u 3470 /* SPI support? (SPI_M | SPI_S) */ 3471 #define SCB8_SPI 1u 3472 /* SPI externally clocked support? ('0': no, '1': yes) */ 3473 #define SCB8_SPI_EC 1u 3474 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3475 #define SCB8_SPI_S_EC 1u 3476 /* UART support? ('0': no, '1': yes) */ 3477 #define SCB8_UART 0u 3478 /* SPI or UART (SPI | UART) */ 3479 #define SCB8_SPI_UART 1u 3480 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3481 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3482 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3483 #define SCB8_EZ_DATA_NR 256u 3484 /* Command/response mode support? ('0': no, '1': yes) */ 3485 #define SCB8_CMD_RESP 1u 3486 /* EZ mode support? ('0': no, '1': yes) */ 3487 #define SCB8_EZ 1u 3488 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3489 #define SCB8_EZ_CMD_RESP 1u 3490 /* I2C slave with EZ mode (I2C_S & EZ) */ 3491 #define SCB8_I2C_S_EZ 1u 3492 /* SPI slave with EZ mode (SPI_S & EZ) */ 3493 #define SCB8_SPI_S_EZ 1u 3494 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3495 #define SCB8_I2C_FAST_PLUS 1u 3496 /* Number of used spi_select signals (max 4) */ 3497 #define SCB8_CHIP_TOP_SPI_SEL_NR 1u 3498 /* DeepSleep support ('0':no, '1': yes) */ 3499 #define SCB9_DEEPSLEEP 0u 3500 /* Externally clocked support? ('0': no, '1': yes) */ 3501 #define SCB9_EC 0u 3502 /* I2C master support? ('0': no, '1': yes) */ 3503 #define SCB9_I2C_M 1u 3504 /* I2C slave support? ('0': no, '1': yes) */ 3505 #define SCB9_I2C_S 1u 3506 /* I2C support? (I2C_M | I2C_S) */ 3507 #define SCB9_I2C 1u 3508 /* I2C glitch filters present? ('0': no, '1': yes) */ 3509 #define SCB9_I2C_GLITCH 1u 3510 /* I2C externally clocked support? ('0': no, '1': yes) */ 3511 #define SCB9_I2C_EC 0u 3512 /* I2C master and slave support? (I2C_M & I2C_S) */ 3513 #define SCB9_I2C_M_S 1u 3514 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3515 #define SCB9_I2C_S_EC 0u 3516 /* SPI master support? ('0': no, '1': yes) */ 3517 #define SCB9_SPI_M 0u 3518 /* SPI slave support? ('0': no, '1': yes) */ 3519 #define SCB9_SPI_S 0u 3520 /* SPI support? (SPI_M | SPI_S) */ 3521 #define SCB9_SPI 0u 3522 /* SPI externally clocked support? ('0': no, '1': yes) */ 3523 #define SCB9_SPI_EC 0u 3524 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3525 #define SCB9_SPI_S_EC 0u 3526 /* UART support? ('0': no, '1': yes) */ 3527 #define SCB9_UART 1u 3528 /* SPI or UART (SPI | UART) */ 3529 #define SCB9_SPI_UART 1u 3530 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3531 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3532 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3533 #define SCB9_EZ_DATA_NR 256u 3534 /* Command/response mode support? ('0': no, '1': yes) */ 3535 #define SCB9_CMD_RESP 0u 3536 /* EZ mode support? ('0': no, '1': yes) */ 3537 #define SCB9_EZ 0u 3538 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3539 #define SCB9_EZ_CMD_RESP 0u 3540 /* I2C slave with EZ mode (I2C_S & EZ) */ 3541 #define SCB9_I2C_S_EZ 0u 3542 /* SPI slave with EZ mode (SPI_S & EZ) */ 3543 #define SCB9_SPI_S_EZ 0u 3544 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3545 #define SCB9_I2C_FAST_PLUS 1u 3546 /* Number of used spi_select signals (max 4) */ 3547 #define SCB9_CHIP_TOP_SPI_SEL_NR 0u 3548 /* DeepSleep support ('0':no, '1': yes) */ 3549 #define SCB10_DEEPSLEEP 0u 3550 /* Externally clocked support? ('0': no, '1': yes) */ 3551 #define SCB10_EC 0u 3552 /* I2C master support? ('0': no, '1': yes) */ 3553 #define SCB10_I2C_M 1u 3554 /* I2C slave support? ('0': no, '1': yes) */ 3555 #define SCB10_I2C_S 1u 3556 /* I2C support? (I2C_M | I2C_S) */ 3557 #define SCB10_I2C 1u 3558 /* I2C glitch filters present? ('0': no, '1': yes) */ 3559 #define SCB10_I2C_GLITCH 1u 3560 /* I2C externally clocked support? ('0': no, '1': yes) */ 3561 #define SCB10_I2C_EC 0u 3562 /* I2C master and slave support? (I2C_M & I2C_S) */ 3563 #define SCB10_I2C_M_S 1u 3564 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3565 #define SCB10_I2C_S_EC 0u 3566 /* SPI master support? ('0': no, '1': yes) */ 3567 #define SCB10_SPI_M 0u 3568 /* SPI slave support? ('0': no, '1': yes) */ 3569 #define SCB10_SPI_S 0u 3570 /* SPI support? (SPI_M | SPI_S) */ 3571 #define SCB10_SPI 0u 3572 /* SPI externally clocked support? ('0': no, '1': yes) */ 3573 #define SCB10_SPI_EC 0u 3574 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3575 #define SCB10_SPI_S_EC 0u 3576 /* UART support? ('0': no, '1': yes) */ 3577 #define SCB10_UART 1u 3578 /* SPI or UART (SPI | UART) */ 3579 #define SCB10_SPI_UART 1u 3580 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3581 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3582 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3583 #define SCB10_EZ_DATA_NR 256u 3584 /* Command/response mode support? ('0': no, '1': yes) */ 3585 #define SCB10_CMD_RESP 0u 3586 /* EZ mode support? ('0': no, '1': yes) */ 3587 #define SCB10_EZ 0u 3588 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3589 #define SCB10_EZ_CMD_RESP 0u 3590 /* I2C slave with EZ mode (I2C_S & EZ) */ 3591 #define SCB10_I2C_S_EZ 0u 3592 /* SPI slave with EZ mode (SPI_S & EZ) */ 3593 #define SCB10_SPI_S_EZ 0u 3594 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3595 #define SCB10_I2C_FAST_PLUS 1u 3596 /* Number of used spi_select signals (max 4) */ 3597 #define SCB10_CHIP_TOP_SPI_SEL_NR 0u 3598 /* DeepSleep support ('0':no, '1': yes) */ 3599 #define SCB11_DEEPSLEEP 0u 3600 /* Externally clocked support? ('0': no, '1': yes) */ 3601 #define SCB11_EC 0u 3602 /* I2C master support? ('0': no, '1': yes) */ 3603 #define SCB11_I2C_M 1u 3604 /* I2C slave support? ('0': no, '1': yes) */ 3605 #define SCB11_I2C_S 1u 3606 /* I2C support? (I2C_M | I2C_S) */ 3607 #define SCB11_I2C 1u 3608 /* I2C glitch filters present? ('0': no, '1': yes) */ 3609 #define SCB11_I2C_GLITCH 1u 3610 /* I2C externally clocked support? ('0': no, '1': yes) */ 3611 #define SCB11_I2C_EC 0u 3612 /* I2C master and slave support? (I2C_M & I2C_S) */ 3613 #define SCB11_I2C_M_S 1u 3614 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3615 #define SCB11_I2C_S_EC 0u 3616 /* SPI master support? ('0': no, '1': yes) */ 3617 #define SCB11_SPI_M 0u 3618 /* SPI slave support? ('0': no, '1': yes) */ 3619 #define SCB11_SPI_S 0u 3620 /* SPI support? (SPI_M | SPI_S) */ 3621 #define SCB11_SPI 0u 3622 /* SPI externally clocked support? ('0': no, '1': yes) */ 3623 #define SCB11_SPI_EC 0u 3624 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3625 #define SCB11_SPI_S_EC 0u 3626 /* UART support? ('0': no, '1': yes) */ 3627 #define SCB11_UART 1u 3628 /* SPI or UART (SPI | UART) */ 3629 #define SCB11_SPI_UART 1u 3630 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3631 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3632 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3633 #define SCB11_EZ_DATA_NR 256u 3634 /* Command/response mode support? ('0': no, '1': yes) */ 3635 #define SCB11_CMD_RESP 0u 3636 /* EZ mode support? ('0': no, '1': yes) */ 3637 #define SCB11_EZ 0u 3638 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3639 #define SCB11_EZ_CMD_RESP 0u 3640 /* I2C slave with EZ mode (I2C_S & EZ) */ 3641 #define SCB11_I2C_S_EZ 0u 3642 /* SPI slave with EZ mode (SPI_S & EZ) */ 3643 #define SCB11_SPI_S_EZ 0u 3644 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3645 #define SCB11_I2C_FAST_PLUS 1u 3646 /* Number of used spi_select signals (max 4) */ 3647 #define SCB11_CHIP_TOP_SPI_SEL_NR 0u 3648 /* DeepSleep support ('0':no, '1': yes) */ 3649 #define SCB12_DEEPSLEEP 0u 3650 /* Externally clocked support? ('0': no, '1': yes) */ 3651 #define SCB12_EC 0u 3652 /* I2C master support? ('0': no, '1': yes) */ 3653 #define SCB12_I2C_M 1u 3654 /* I2C slave support? ('0': no, '1': yes) */ 3655 #define SCB12_I2C_S 1u 3656 /* I2C support? (I2C_M | I2C_S) */ 3657 #define SCB12_I2C 1u 3658 /* I2C glitch filters present? ('0': no, '1': yes) */ 3659 #define SCB12_I2C_GLITCH 1u 3660 /* I2C externally clocked support? ('0': no, '1': yes) */ 3661 #define SCB12_I2C_EC 0u 3662 /* I2C master and slave support? (I2C_M & I2C_S) */ 3663 #define SCB12_I2C_M_S 1u 3664 /* I2C slave with EC? (I2C_S & I2C_EC) */ 3665 #define SCB12_I2C_S_EC 0u 3666 /* SPI master support? ('0': no, '1': yes) */ 3667 #define SCB12_SPI_M 0u 3668 /* SPI slave support? ('0': no, '1': yes) */ 3669 #define SCB12_SPI_S 0u 3670 /* SPI support? (SPI_M | SPI_S) */ 3671 #define SCB12_SPI 0u 3672 /* SPI externally clocked support? ('0': no, '1': yes) */ 3673 #define SCB12_SPI_EC 0u 3674 /* SPI slave with EC? (SPI_S & SPI_EC) */ 3675 #define SCB12_SPI_S_EC 0u 3676 /* UART support? ('0': no, '1': yes) */ 3677 #define SCB12_UART 1u 3678 /* SPI or UART (SPI | UART) */ 3679 #define SCB12_SPI_UART 1u 3680 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, 3681 CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only 3682 256 B are used. This is because the EZ mode uses 8-bit addresses. */ 3683 #define SCB12_EZ_DATA_NR 256u 3684 /* Command/response mode support? ('0': no, '1': yes) */ 3685 #define SCB12_CMD_RESP 0u 3686 /* EZ mode support? ('0': no, '1': yes) */ 3687 #define SCB12_EZ 0u 3688 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ 3689 #define SCB12_EZ_CMD_RESP 0u 3690 /* I2C slave with EZ mode (I2C_S & EZ) */ 3691 #define SCB12_I2C_S_EZ 0u 3692 /* SPI slave with EZ mode (SPI_S & EZ) */ 3693 #define SCB12_SPI_S_EZ 0u 3694 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ 3695 #define SCB12_I2C_FAST_PLUS 1u 3696 /* Number of used spi_select signals (max 4) */ 3697 #define SCB12_CHIP_TOP_SPI_SEL_NR 0u 3698 /* Basically the max packet size, which gets double buffered in RAM 0: 512B 3699 (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for 3700 data) */ 3701 #define SDHC0_MAX_BLK_SIZE 0u 3702 /* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this 3703 adds 288 bytes of space to the RAM for this purpose. */ 3704 #define SDHC0_CQE_PRESENT 0u 3705 /* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have 3706 the Retention flag (Note, CTL.ENABLE is always retained irrespective of this 3707 parameter) */ 3708 #define SDHC0_RETENTION_PRESENT 1u 3709 /* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data 3710 pins) */ 3711 #define SDHC0_CHIP_TOP_DATA8_PRESENT 0u 3712 /* Chip top connect card_detect */ 3713 #define SDHC0_CHIP_TOP_CARD_DETECT_PRESENT 1u 3714 /* Chip top connect card_mech_write_prot_in */ 3715 #define SDHC0_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u 3716 /* Chip top connect led_ctrl_out and led_ctrl_out_en */ 3717 #define SDHC0_CHIP_TOP_LED_CTRL_PRESENT 0u 3718 /* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ 3719 #define SDHC0_CHIP_TOP_IO_VOLT_SEL_PRESENT 1u 3720 /* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ 3721 #define SDHC0_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u 3722 /* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ 3723 #define SDHC0_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u 3724 /* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ 3725 #define SDHC0_CHIP_TOP_CARD_EMMC_RESET_PRESENT 0u 3726 /* Chip top connect interrupt_wakeup (not used for eMMC) */ 3727 #define SDHC0_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u 3728 /* Basically the max packet size, which gets double buffered in RAM 0: 512B 3729 (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for 3730 data) */ 3731 #define SDHC0_CORE_MAX_BLK_SIZE 0u 3732 /* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this 3733 adds 288 bytes of space to the RAM for this purpose. */ 3734 #define SDHC0_CORE_CQE_PRESENT 0u 3735 /* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have 3736 the Retention flag (Note, CTL.ENABLE is always retained irrespective of this 3737 parameter) */ 3738 #define SDHC0_CORE_RETENTION_PRESENT 1u 3739 /* Basically the max packet size, which gets double buffered in RAM 0: 512B 3740 (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for 3741 data) */ 3742 #define SDHC1_MAX_BLK_SIZE 0u 3743 /* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this 3744 adds 288 bytes of space to the RAM for this purpose. */ 3745 #define SDHC1_CQE_PRESENT 0u 3746 /* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have 3747 the Retention flag (Note, CTL.ENABLE is always retained irrespective of this 3748 parameter) */ 3749 #define SDHC1_RETENTION_PRESENT 1u 3750 /* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data 3751 pins) */ 3752 #define SDHC1_CHIP_TOP_DATA8_PRESENT 1u 3753 /* Chip top connect card_detect */ 3754 #define SDHC1_CHIP_TOP_CARD_DETECT_PRESENT 1u 3755 /* Chip top connect card_mech_write_prot_in */ 3756 #define SDHC1_CHIP_TOP_CARD_WRITE_PROT_PRESENT 1u 3757 /* Chip top connect led_ctrl_out and led_ctrl_out_en */ 3758 #define SDHC1_CHIP_TOP_LED_CTRL_PRESENT 1u 3759 /* Chip top connect io_volt_sel_out and io_volt_sel_out_en */ 3760 #define SDHC1_CHIP_TOP_IO_VOLT_SEL_PRESENT 1u 3761 /* Chip top connect io_drive_strength_out and io_drive_strength_out_en */ 3762 #define SDHC1_CHIP_TOP_IO_DRIVE_STRENGTH_PRESENT 0u 3763 /* Chip top connect card_if_pwr_en_out and card_if_pwr_en_out_en */ 3764 #define SDHC1_CHIP_TOP_CARD_IF_PWR_EN_PRESENT 1u 3765 /* Chip top connect card_emmc_reset_n_out and card_emmc_reset_n_out_en */ 3766 #define SDHC1_CHIP_TOP_CARD_EMMC_RESET_PRESENT 1u 3767 /* Chip top connect interrupt_wakeup (not used for eMMC) */ 3768 #define SDHC1_CHIP_TOP_INTERRUPT_WAKEUP_PRESENT 1u 3769 /* Basically the max packet size, which gets double buffered in RAM 0: 512B 3770 (implies 1KB of RAM space for data) 1: 1KB (implies 2KB of RAM space for 3771 data) */ 3772 #define SDHC1_CORE_MAX_BLK_SIZE 0u 3773 /* 0: No Command Queuing Engine present 1: Command Queuing Engine present; this 3774 adds 288 bytes of space to the RAM for this purpose. */ 3775 #define SDHC1_CORE_CQE_PRESENT 0u 3776 /* 0: no retention of any SDHC_CORE regs 1: retention of SDHC_CORE regs that have 3777 the Retention flag (Note, CTL.ENABLE is always retained irrespective of this 3778 parameter) */ 3779 #define SDHC1_CORE_RETENTION_PRESENT 1u 3780 /* SONOS Flash is used or not ('0': no, '1': yes) */ 3781 #define SFLASH_FLASHC_IS_SONOS 1u 3782 /* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ 3783 #define SFLASH_CPUSS_WOUNDING_PRESENT 0u 3784 /* Base address of the SMIF XIP memory region. This address must be a multiple of 3785 the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This 3786 address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP 3787 memory region should NOT overlap with other memory regions. */ 3788 #define SMIF_SMIF_XIP_ADDR 0x18000000u 3789 /* Capacity of the SMIF XIP memory region. The more significant bits of this 3790 parameter must be '1' and the lesser significant bits of this paramter must 3791 be '0'. E.g., 0xfff0:0000 specifies a 1 MB memory region. Legal values are 3792 {0xffff:0000, 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000, 3793 0xffe0:0000, ..., 0xe000:0000}. */ 3794 #define SMIF_SMIF_XIP_MASK 0xF8000000u 3795 /* Cryptography (AES) support ('0' = no support, '1' = support) */ 3796 #define SMIF_CRYPTO 1u 3797 /* Number of external devices supported ([1,4]) */ 3798 #define SMIF_DEVICE_NR 4u 3799 /* External device write support. This is a 4-bit field. Each external device has 3800 a dedicated bit. E.g., if bit 2 is '1', external device 2 has write support. */ 3801 #define SMIF_DEVICE_WR_EN 15u 3802 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ 3803 #define SMIF_MASTER_WIDTH 8u 3804 /* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data 3805 pins) */ 3806 #define SMIF_CHIP_TOP_DATA8_PRESENT 1u 3807 /* Number of used spi_select signals (max 4) */ 3808 #define SMIF_CHIP_TOP_SPI_SEL_NR 4u 3809 /* Number of regulator modules instantiated within SRSS, start with estimate, 3810 update after CMR feedback */ 3811 #define SRSS_NUM_ACTREG_PWRMOD 2u 3812 /* Number of shorting switches between vccd and vccact (target dynamic voltage 3813 drop < 10mV) */ 3814 #define SRSS_NUM_ACTIVE_SWITCH 3u 3815 /* ULP linear regulator system is present */ 3816 #define SRSS_ULPLINREG_PRESENT 1u 3817 /* HT linear regulator system is present */ 3818 #define SRSS_HTLINREG_PRESENT 0u 3819 /* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT 3820 or SIMOBUCK_PRESENT. */ 3821 #define SRSS_BUCKCTL_PRESENT 1u 3822 /* Low-current SISO buck core regulator is present. Only compatible with ULP 3823 linear regulator system (ULPLINREG_PRESENT==1). */ 3824 #define SRSS_S40S_SISOBUCKLC_PRESENT 1u 3825 /* SIMO buck core regulator is present. Only compatible with ULP linear regulator 3826 system (ULPLINREG_PRESENT==1). */ 3827 #define SRSS_SIMOBUCK_PRESENT 0u 3828 /* Precision ILO (PILO) is present */ 3829 #define SRSS_PILO_PRESENT 0u 3830 /* External Crystal Oscillator is present (high frequency) */ 3831 #define SRSS_ECO_PRESENT 1u 3832 /* System Buck-Boost is present */ 3833 #define SRSS_SYSBB_PRESENT 0u 3834 /* Number of clock paths. Must be > 0 */ 3835 #define SRSS_NUM_CLKPATH 6u 3836 /* Number of PLLs present. Must be <= NUM_CLKPATH */ 3837 #define SRSS_NUM_PLL 2u 3838 /* Number of HFCLK roots present. Must be > 0 */ 3839 #define SRSS_NUM_HFROOT 6u 3840 /* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ 3841 #define SRSS_NUM_HIBDATA 1u 3842 /* Backup domain is present (includes RTC and WCO) */ 3843 #define SRSS_BACKUP_PRESENT 1u 3844 /* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of 3845 mask indicates presence of a CSV. */ 3846 #define SRSS_MASK_HFCSV 0u 3847 /* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ 3848 #define SRSS_WCOCSV_PRESENT 0u 3849 /* Number of software watchdog timers. */ 3850 #define SRSS_NUM_MCWDT 2u 3851 /* Number of DSI inputs into clock muxes. This is used for logic optimization. */ 3852 #define SRSS_NUM_DSI 0u 3853 /* Alternate high-frequency clock is present. This is used for logic optimization. */ 3854 #define SRSS_ALTHF_PRESENT 0u 3855 /* Alternate low-frequency clock is present. This is used for logic optimization. */ 3856 #define SRSS_ALTLF_PRESENT 0u 3857 /* Use the hardened clkactfllmux block */ 3858 #define SRSS_USE_HARD_CLKACTFLLMUX 1u 3859 /* Number of clock paths, including direct paths in hardened clkactfllmux block 3860 (Must be >= NUM_CLKPATH) */ 3861 #define SRSS_HARD_CLKPATH 6u 3862 /* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= 3863 NUM_PLL+1) */ 3864 #define SRSS_HARD_CLKPATHMUX 6u 3865 /* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ 3866 #define SRSS_HARD_HFROOT 6u 3867 /* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ 3868 #define SRSS_HARD_ECOMUX_PRESENT 1u 3869 /* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ 3870 #define SRSS_HARD_ALTHFMUX_PRESENT 1u 3871 /* Backup memory is present (only used when BACKUP_PRESENT==1) */ 3872 #define SRSS_BACKUP_BMEM_PRESENT 0u 3873 /* Number of Backup registers to include (each is 32b). Only used when 3874 BACKUP_PRESENT==1. */ 3875 #define SRSS_BACKUP_NUM_BREG 16u 3876 /* Number of counters per IP (1..32) */ 3877 #define TCPWM0_CNT_NR 8u 3878 /* Counter width (in number of bits) */ 3879 #define TCPWM0_CNT_CNT_WIDTH 32u 3880 /* Number of counters per IP (1..32) */ 3881 #define TCPWM1_CNT_NR 24u 3882 /* Counter width (in number of bits) */ 3883 #define TCPWM1_CNT_CNT_WIDTH 16u 3884 3885 /* MMIO Targets Defines */ 3886 /* MMIO1.CRYPTO */ 3887 #define CY_MMIO_CRYPTO_GROUP_NR 1u 3888 #define CY_MMIO_CRYPTO_SLAVE_NR 0u 3889 /* MMIO2.CPUSS */ 3890 #define CY_MMIO_CPUSS_GROUP_NR 2u 3891 #define CY_MMIO_CPUSS_SLAVE_NR 0u 3892 /* MMIO2.FAULT */ 3893 #define CY_MMIO_FAULT_GROUP_NR 2u 3894 #define CY_MMIO_FAULT_SLAVE_NR 1u 3895 /* MMIO2.IPC */ 3896 #define CY_MMIO_IPC_GROUP_NR 2u 3897 #define CY_MMIO_IPC_SLAVE_NR 2u 3898 /* MMIO2.PROT */ 3899 #define CY_MMIO_PROT_GROUP_NR 2u 3900 #define CY_MMIO_PROT_SLAVE_NR 3u 3901 /* MMIO2.FLASHC */ 3902 #define CY_MMIO_FLASHC_GROUP_NR 2u 3903 #define CY_MMIO_FLASHC_SLAVE_NR 4u 3904 /* MMIO2.SRSS */ 3905 #define CY_MMIO_SRSS_GROUP_NR 2u 3906 #define CY_MMIO_SRSS_SLAVE_NR 6u 3907 /* MMIO2.BACKUP */ 3908 #define CY_MMIO_BACKUP_GROUP_NR 2u 3909 #define CY_MMIO_BACKUP_SLAVE_NR 7u 3910 /* MMIO2.DW */ 3911 #define CY_MMIO_DW_GROUP_NR 2u 3912 #define CY_MMIO_DW_SLAVE_NR 8u 3913 /* MMIO2.DMAC */ 3914 #define CY_MMIO_DMAC_GROUP_NR 2u 3915 #define CY_MMIO_DMAC_SLAVE_NR 10u 3916 /* MMIO2.EFUSE */ 3917 #define CY_MMIO_EFUSE_GROUP_NR 2u 3918 #define CY_MMIO_EFUSE_SLAVE_NR 12u 3919 /* MMIO2.PROFILE */ 3920 #define CY_MMIO_PROFILE_GROUP_NR 2u 3921 #define CY_MMIO_PROFILE_SLAVE_NR 13u 3922 /* MMIO3.HSIOM */ 3923 #define CY_MMIO_HSIOM_GROUP_NR 3u 3924 #define CY_MMIO_HSIOM_SLAVE_NR 0u 3925 /* MMIO3.GPIO */ 3926 #define CY_MMIO_GPIO_GROUP_NR 3u 3927 #define CY_MMIO_GPIO_SLAVE_NR 1u 3928 /* MMIO3.SMARTIO */ 3929 #define CY_MMIO_SMARTIO_GROUP_NR 3u 3930 #define CY_MMIO_SMARTIO_SLAVE_NR 2u 3931 /* MMIO3.LPCOMP */ 3932 #define CY_MMIO_LPCOMP_GROUP_NR 3u 3933 #define CY_MMIO_LPCOMP_SLAVE_NR 5u 3934 /* MMIO3.CSD0 */ 3935 #define CY_MMIO_CSD0_GROUP_NR 3u 3936 #define CY_MMIO_CSD0_SLAVE_NR 6u 3937 /* MMIO3.TCPWM0 */ 3938 #define CY_MMIO_TCPWM0_GROUP_NR 3u 3939 #define CY_MMIO_TCPWM0_SLAVE_NR 8u 3940 /* MMIO3.TCPWM1 */ 3941 #define CY_MMIO_TCPWM1_GROUP_NR 3u 3942 #define CY_MMIO_TCPWM1_SLAVE_NR 9u 3943 /* MMIO3.LCD0 */ 3944 #define CY_MMIO_LCD0_GROUP_NR 3u 3945 #define CY_MMIO_LCD0_SLAVE_NR 11u 3946 /* MMIO3.USBFS0 */ 3947 #define CY_MMIO_USBFS0_GROUP_NR 3u 3948 #define CY_MMIO_USBFS0_SLAVE_NR 15u 3949 /* MMIO4.SMIF0 */ 3950 #define CY_MMIO_SMIF0_GROUP_NR 4u 3951 #define CY_MMIO_SMIF0_SLAVE_NR 2u 3952 /* MMIO4.SDHC0 */ 3953 #define CY_MMIO_SDHC0_GROUP_NR 4u 3954 #define CY_MMIO_SDHC0_SLAVE_NR 6u 3955 /* MMIO4.SDHC1 */ 3956 #define CY_MMIO_SDHC1_GROUP_NR 4u 3957 #define CY_MMIO_SDHC1_SLAVE_NR 7u 3958 /* MMIO6.SCB0 */ 3959 #define CY_MMIO_SCB0_GROUP_NR 6u 3960 #define CY_MMIO_SCB0_SLAVE_NR 0u 3961 /* MMIO6.SCB1 */ 3962 #define CY_MMIO_SCB1_GROUP_NR 6u 3963 #define CY_MMIO_SCB1_SLAVE_NR 1u 3964 /* MMIO6.SCB2 */ 3965 #define CY_MMIO_SCB2_GROUP_NR 6u 3966 #define CY_MMIO_SCB2_SLAVE_NR 2u 3967 /* MMIO6.SCB3 */ 3968 #define CY_MMIO_SCB3_GROUP_NR 6u 3969 #define CY_MMIO_SCB3_SLAVE_NR 3u 3970 /* MMIO6.SCB4 */ 3971 #define CY_MMIO_SCB4_GROUP_NR 6u 3972 #define CY_MMIO_SCB4_SLAVE_NR 4u 3973 /* MMIO6.SCB5 */ 3974 #define CY_MMIO_SCB5_GROUP_NR 6u 3975 #define CY_MMIO_SCB5_SLAVE_NR 5u 3976 /* MMIO6.SCB6 */ 3977 #define CY_MMIO_SCB6_GROUP_NR 6u 3978 #define CY_MMIO_SCB6_SLAVE_NR 6u 3979 /* MMIO6.SCB7 */ 3980 #define CY_MMIO_SCB7_GROUP_NR 6u 3981 #define CY_MMIO_SCB7_SLAVE_NR 7u 3982 /* MMIO6.SCB8 */ 3983 #define CY_MMIO_SCB8_GROUP_NR 6u 3984 #define CY_MMIO_SCB8_SLAVE_NR 8u 3985 /* MMIO6.SCB9 */ 3986 #define CY_MMIO_SCB9_GROUP_NR 6u 3987 #define CY_MMIO_SCB9_SLAVE_NR 9u 3988 /* MMIO6.SCB10 */ 3989 #define CY_MMIO_SCB10_GROUP_NR 6u 3990 #define CY_MMIO_SCB10_SLAVE_NR 10u 3991 /* MMIO6.SCB11 */ 3992 #define CY_MMIO_SCB11_GROUP_NR 6u 3993 #define CY_MMIO_SCB11_SLAVE_NR 11u 3994 /* MMIO6.SCB12 */ 3995 #define CY_MMIO_SCB12_GROUP_NR 6u 3996 #define CY_MMIO_SCB12_SLAVE_NR 12u 3997 /* MMIO9.PASS */ 3998 #define CY_MMIO_PASS_GROUP_NR 9u 3999 #define CY_MMIO_PASS_SLAVE_NR 0u 4000 /* MMIO10.PDM0 */ 4001 #define CY_MMIO_PDM0_GROUP_NR 10u 4002 #define CY_MMIO_PDM0_SLAVE_NR 1u 4003 /* MMIO10.I2S0 */ 4004 #define CY_MMIO_I2S0_GROUP_NR 10u 4005 #define CY_MMIO_I2S0_SLAVE_NR 2u 4006 /* MMIO10.I2S1 */ 4007 #define CY_MMIO_I2S1_GROUP_NR 10u 4008 #define CY_MMIO_I2S1_SLAVE_NR 3u 4009 4010 /* Backward compatibility definitions */ 4011 #define CPUSS_IRQ_NR CPUSS_SYSTEM_INT_NR 4012 #define CPUSS_DPSLP_IRQ_NR CPUSS_SYSTEM_DPSLP_INT_NR 4013 4014 /* Protection regions */ 4015 typedef enum 4016 { 4017 PROT_PERI_MAIN = 0, /* Address 0x40000000, size 0x00002000 */ 4018 PROT_PERI_GR0_GROUP = 1, /* Address 0x40004010, size 0x00000004 */ 4019 PROT_PERI_GR1_GROUP = 2, /* Address 0x40004030, size 0x00000004 */ 4020 PROT_PERI_GR2_GROUP = 3, /* Address 0x40004050, size 0x00000004 */ 4021 PROT_PERI_GR3_GROUP = 4, /* Address 0x40004060, size 0x00000020 */ 4022 PROT_PERI_GR4_GROUP = 5, /* Address 0x40004080, size 0x00000020 */ 4023 PROT_PERI_GR6_GROUP = 6, /* Address 0x400040c0, size 0x00000020 */ 4024 PROT_PERI_GR9_GROUP = 7, /* Address 0x40004120, size 0x00000020 */ 4025 PROT_PERI_GR10_GROUP = 8, /* Address 0x40004140, size 0x00000020 */ 4026 PROT_PERI_TR = 9, /* Address 0x40008000, size 0x00008000 */ 4027 PROT_CRYPTO_MAIN = 10, /* Address 0x40100000, size 0x00000400 */ 4028 PROT_CRYPTO_CRYPTO = 11, /* Address 0x40101000, size 0x00000800 */ 4029 PROT_CRYPTO_BOOT = 12, /* Address 0x40102000, size 0x00000100 */ 4030 PROT_CRYPTO_KEY0 = 13, /* Address 0x40102100, size 0x00000004 */ 4031 PROT_CRYPTO_KEY1 = 14, /* Address 0x40102120, size 0x00000004 */ 4032 PROT_CRYPTO_BUF = 15, /* Address 0x40108000, size 0x00001000 */ 4033 PROT_CPUSS_CM4 = 16, /* Address 0x40200000, size 0x00000400 */ 4034 PROT_CPUSS_CM0 = 17, /* Address 0x40201000, size 0x00001000 */ 4035 PROT_CPUSS_BOOT = 18, /* Address 0x40202000, size 0x00000200 */ 4036 PROT_CPUSS_CM0_INT = 19, /* Address 0x40208000, size 0x00000400 */ 4037 PROT_CPUSS_CM4_INT = 20, /* Address 0x4020a000, size 0x00000400 */ 4038 PROT_FAULT_STRUCT0_MAIN = 21, /* Address 0x40210000, size 0x00000100 */ 4039 PROT_FAULT_STRUCT1_MAIN = 22, /* Address 0x40210100, size 0x00000100 */ 4040 PROT_IPC_STRUCT0_IPC = 23, /* Address 0x40220000, size 0x00000020 */ 4041 PROT_IPC_STRUCT1_IPC = 24, /* Address 0x40220020, size 0x00000020 */ 4042 PROT_IPC_STRUCT2_IPC = 25, /* Address 0x40220040, size 0x00000020 */ 4043 PROT_IPC_STRUCT3_IPC = 26, /* Address 0x40220060, size 0x00000020 */ 4044 PROT_IPC_STRUCT4_IPC = 27, /* Address 0x40220080, size 0x00000020 */ 4045 PROT_IPC_STRUCT5_IPC = 28, /* Address 0x402200a0, size 0x00000020 */ 4046 PROT_IPC_STRUCT6_IPC = 29, /* Address 0x402200c0, size 0x00000020 */ 4047 PROT_IPC_STRUCT7_IPC = 30, /* Address 0x402200e0, size 0x00000020 */ 4048 PROT_IPC_STRUCT8_IPC = 31, /* Address 0x40220100, size 0x00000020 */ 4049 PROT_IPC_STRUCT9_IPC = 32, /* Address 0x40220120, size 0x00000020 */ 4050 PROT_IPC_STRUCT10_IPC = 33, /* Address 0x40220140, size 0x00000020 */ 4051 PROT_IPC_STRUCT11_IPC = 34, /* Address 0x40220160, size 0x00000020 */ 4052 PROT_IPC_STRUCT12_IPC = 35, /* Address 0x40220180, size 0x00000020 */ 4053 PROT_IPC_STRUCT13_IPC = 36, /* Address 0x402201a0, size 0x00000020 */ 4054 PROT_IPC_STRUCT14_IPC = 37, /* Address 0x402201c0, size 0x00000020 */ 4055 PROT_IPC_STRUCT15_IPC = 38, /* Address 0x402201e0, size 0x00000020 */ 4056 PROT_IPC_INTR_STRUCT0_INTR = 39, /* Address 0x40221000, size 0x00000010 */ 4057 PROT_IPC_INTR_STRUCT1_INTR = 40, /* Address 0x40221020, size 0x00000010 */ 4058 PROT_IPC_INTR_STRUCT2_INTR = 41, /* Address 0x40221040, size 0x00000010 */ 4059 PROT_IPC_INTR_STRUCT3_INTR = 42, /* Address 0x40221060, size 0x00000010 */ 4060 PROT_IPC_INTR_STRUCT4_INTR = 43, /* Address 0x40221080, size 0x00000010 */ 4061 PROT_IPC_INTR_STRUCT5_INTR = 44, /* Address 0x402210a0, size 0x00000010 */ 4062 PROT_IPC_INTR_STRUCT6_INTR = 45, /* Address 0x402210c0, size 0x00000010 */ 4063 PROT_IPC_INTR_STRUCT7_INTR = 46, /* Address 0x402210e0, size 0x00000010 */ 4064 PROT_IPC_INTR_STRUCT8_INTR = 47, /* Address 0x40221100, size 0x00000010 */ 4065 PROT_IPC_INTR_STRUCT9_INTR = 48, /* Address 0x40221120, size 0x00000010 */ 4066 PROT_IPC_INTR_STRUCT10_INTR = 49, /* Address 0x40221140, size 0x00000010 */ 4067 PROT_IPC_INTR_STRUCT11_INTR = 50, /* Address 0x40221160, size 0x00000010 */ 4068 PROT_IPC_INTR_STRUCT12_INTR = 51, /* Address 0x40221180, size 0x00000010 */ 4069 PROT_IPC_INTR_STRUCT13_INTR = 52, /* Address 0x402211a0, size 0x00000010 */ 4070 PROT_IPC_INTR_STRUCT14_INTR = 53, /* Address 0x402211c0, size 0x00000010 */ 4071 PROT_IPC_INTR_STRUCT15_INTR = 54, /* Address 0x402211e0, size 0x00000010 */ 4072 PROT_PROT_SMPU_MAIN = 55, /* Address 0x40230000, size 0x00000040 */ 4073 PROT_PROT_MPU0_MAIN = 56, /* Address 0x40234000, size 0x00000004 */ 4074 PROT_PROT_MPU5_MAIN = 57, /* Address 0x40235400, size 0x00000400 */ 4075 PROT_PROT_MPU6_MAIN = 58, /* Address 0x40235800, size 0x00000400 */ 4076 PROT_PROT_MPU14_MAIN = 59, /* Address 0x40237800, size 0x00000004 */ 4077 PROT_PROT_MPU15_MAIN = 60, /* Address 0x40237c00, size 0x00000400 */ 4078 PROT_FLASHC_MAIN = 61, /* Address 0x40240000, size 0x00000008 */ 4079 PROT_FLASHC_CMD = 62, /* Address 0x40240008, size 0x00000004 */ 4080 PROT_FLASHC_DFT = 63, /* Address 0x40240200, size 0x00000100 */ 4081 PROT_FLASHC_CM0 = 64, /* Address 0x40240400, size 0x00000080 */ 4082 PROT_FLASHC_CM4 = 65, /* Address 0x40240480, size 0x00000080 */ 4083 PROT_FLASHC_CRYPTO = 66, /* Address 0x40240500, size 0x00000004 */ 4084 PROT_FLASHC_DW0 = 67, /* Address 0x40240580, size 0x00000004 */ 4085 PROT_FLASHC_DW1 = 68, /* Address 0x40240600, size 0x00000004 */ 4086 PROT_FLASHC_DMAC = 69, /* Address 0x40240680, size 0x00000004 */ 4087 PROT_FLASHC_EXT_MS0 = 70, /* Address 0x40240700, size 0x00000004 */ 4088 PROT_FLASHC_EXT_MS1 = 71, /* Address 0x40240780, size 0x00000004 */ 4089 PROT_FLASHC_FM = 72, /* Address 0x4024f000, size 0x00001000 */ 4090 PROT_SRSS_MAIN1 = 73, /* Address 0x40260000, size 0x00000100 */ 4091 PROT_SRSS_MAIN2 = 74, /* Address 0x40260100, size 0x00000010 */ 4092 PROT_WDT = 75, /* Address 0x40260180, size 0x00000010 */ 4093 PROT_MAIN = 76, /* Address 0x40260200, size 0x00000080 */ 4094 PROT_SRSS_MAIN3 = 77, /* Address 0x40260300, size 0x00000100 */ 4095 PROT_SRSS_MAIN4 = 78, /* Address 0x40260400, size 0x00000400 */ 4096 PROT_SRSS_MAIN5 = 79, /* Address 0x40260800, size 0x00000008 */ 4097 PROT_SRSS_MAIN6 = 80, /* Address 0x40267000, size 0x00001000 */ 4098 PROT_SRSS_MAIN7 = 81, /* Address 0x4026ff00, size 0x00000080 */ 4099 PROT_BACKUP_BACKUP = 82, /* Address 0x40270000, size 0x00010000 */ 4100 PROT_DW0_DW = 83, /* Address 0x40280000, size 0x00000080 */ 4101 PROT_DW1_DW = 84, /* Address 0x40290000, size 0x00000080 */ 4102 PROT_DW0_DW_CRC = 85, /* Address 0x40280100, size 0x00000080 */ 4103 PROT_DW1_DW_CRC = 86, /* Address 0x40290100, size 0x00000080 */ 4104 PROT_DW0_CH_STRUCT0_CH = 87, /* Address 0x40288000, size 0x00000040 */ 4105 PROT_DW0_CH_STRUCT1_CH = 88, /* Address 0x40288040, size 0x00000040 */ 4106 PROT_DW0_CH_STRUCT2_CH = 89, /* Address 0x40288080, size 0x00000040 */ 4107 PROT_DW0_CH_STRUCT3_CH = 90, /* Address 0x402880c0, size 0x00000040 */ 4108 PROT_DW0_CH_STRUCT4_CH = 91, /* Address 0x40288100, size 0x00000040 */ 4109 PROT_DW0_CH_STRUCT5_CH = 92, /* Address 0x40288140, size 0x00000040 */ 4110 PROT_DW0_CH_STRUCT6_CH = 93, /* Address 0x40288180, size 0x00000040 */ 4111 PROT_DW0_CH_STRUCT7_CH = 94, /* Address 0x402881c0, size 0x00000040 */ 4112 PROT_DW0_CH_STRUCT8_CH = 95, /* Address 0x40288200, size 0x00000040 */ 4113 PROT_DW0_CH_STRUCT9_CH = 96, /* Address 0x40288240, size 0x00000040 */ 4114 PROT_DW0_CH_STRUCT10_CH = 97, /* Address 0x40288280, size 0x00000040 */ 4115 PROT_DW0_CH_STRUCT11_CH = 98, /* Address 0x402882c0, size 0x00000040 */ 4116 PROT_DW0_CH_STRUCT12_CH = 99, /* Address 0x40288300, size 0x00000040 */ 4117 PROT_DW0_CH_STRUCT13_CH = 100, /* Address 0x40288340, size 0x00000040 */ 4118 PROT_DW0_CH_STRUCT14_CH = 101, /* Address 0x40288380, size 0x00000040 */ 4119 PROT_DW0_CH_STRUCT15_CH = 102, /* Address 0x402883c0, size 0x00000040 */ 4120 PROT_DW0_CH_STRUCT16_CH = 103, /* Address 0x40288400, size 0x00000040 */ 4121 PROT_DW0_CH_STRUCT17_CH = 104, /* Address 0x40288440, size 0x00000040 */ 4122 PROT_DW0_CH_STRUCT18_CH = 105, /* Address 0x40288480, size 0x00000040 */ 4123 PROT_DW0_CH_STRUCT19_CH = 106, /* Address 0x402884c0, size 0x00000040 */ 4124 PROT_DW0_CH_STRUCT20_CH = 107, /* Address 0x40288500, size 0x00000040 */ 4125 PROT_DW0_CH_STRUCT21_CH = 108, /* Address 0x40288540, size 0x00000040 */ 4126 PROT_DW0_CH_STRUCT22_CH = 109, /* Address 0x40288580, size 0x00000040 */ 4127 PROT_DW0_CH_STRUCT23_CH = 110, /* Address 0x402885c0, size 0x00000040 */ 4128 PROT_DW0_CH_STRUCT24_CH = 111, /* Address 0x40288600, size 0x00000040 */ 4129 PROT_DW0_CH_STRUCT25_CH = 112, /* Address 0x40288640, size 0x00000040 */ 4130 PROT_DW0_CH_STRUCT26_CH = 113, /* Address 0x40288680, size 0x00000040 */ 4131 PROT_DW0_CH_STRUCT27_CH = 114, /* Address 0x402886c0, size 0x00000040 */ 4132 PROT_DW0_CH_STRUCT28_CH = 115, /* Address 0x40288700, size 0x00000040 */ 4133 PROT_DW1_CH_STRUCT0_CH = 116, /* Address 0x40298000, size 0x00000040 */ 4134 PROT_DW1_CH_STRUCT1_CH = 117, /* Address 0x40298040, size 0x00000040 */ 4135 PROT_DW1_CH_STRUCT2_CH = 118, /* Address 0x40298080, size 0x00000040 */ 4136 PROT_DW1_CH_STRUCT3_CH = 119, /* Address 0x402980c0, size 0x00000040 */ 4137 PROT_DW1_CH_STRUCT4_CH = 120, /* Address 0x40298100, size 0x00000040 */ 4138 PROT_DW1_CH_STRUCT5_CH = 121, /* Address 0x40298140, size 0x00000040 */ 4139 PROT_DW1_CH_STRUCT6_CH = 122, /* Address 0x40298180, size 0x00000040 */ 4140 PROT_DW1_CH_STRUCT7_CH = 123, /* Address 0x402981c0, size 0x00000040 */ 4141 PROT_DW1_CH_STRUCT8_CH = 124, /* Address 0x40298200, size 0x00000040 */ 4142 PROT_DW1_CH_STRUCT9_CH = 125, /* Address 0x40298240, size 0x00000040 */ 4143 PROT_DW1_CH_STRUCT10_CH = 126, /* Address 0x40298280, size 0x00000040 */ 4144 PROT_DW1_CH_STRUCT11_CH = 127, /* Address 0x402982c0, size 0x00000040 */ 4145 PROT_DW1_CH_STRUCT12_CH = 128, /* Address 0x40298300, size 0x00000040 */ 4146 PROT_DW1_CH_STRUCT13_CH = 129, /* Address 0x40298340, size 0x00000040 */ 4147 PROT_DW1_CH_STRUCT14_CH = 130, /* Address 0x40298380, size 0x00000040 */ 4148 PROT_DW1_CH_STRUCT15_CH = 131, /* Address 0x402983c0, size 0x00000040 */ 4149 PROT_DW1_CH_STRUCT16_CH = 132, /* Address 0x40298400, size 0x00000040 */ 4150 PROT_DW1_CH_STRUCT17_CH = 133, /* Address 0x40298440, size 0x00000040 */ 4151 PROT_DW1_CH_STRUCT18_CH = 134, /* Address 0x40298480, size 0x00000040 */ 4152 PROT_DW1_CH_STRUCT19_CH = 135, /* Address 0x402984c0, size 0x00000040 */ 4153 PROT_DW1_CH_STRUCT20_CH = 136, /* Address 0x40298500, size 0x00000040 */ 4154 PROT_DW1_CH_STRUCT21_CH = 137, /* Address 0x40298540, size 0x00000040 */ 4155 PROT_DW1_CH_STRUCT22_CH = 138, /* Address 0x40298580, size 0x00000040 */ 4156 PROT_DW1_CH_STRUCT23_CH = 139, /* Address 0x402985c0, size 0x00000040 */ 4157 PROT_DW1_CH_STRUCT24_CH = 140, /* Address 0x40298600, size 0x00000040 */ 4158 PROT_DW1_CH_STRUCT25_CH = 141, /* Address 0x40298640, size 0x00000040 */ 4159 PROT_DW1_CH_STRUCT26_CH = 142, /* Address 0x40298680, size 0x00000040 */ 4160 PROT_DW1_CH_STRUCT27_CH = 143, /* Address 0x402986c0, size 0x00000040 */ 4161 PROT_DW1_CH_STRUCT28_CH = 144, /* Address 0x40298700, size 0x00000040 */ 4162 PROT_DMAC_TOP = 145, /* Address 0x402a0000, size 0x00000010 */ 4163 PROT_DMAC_CH0_CH = 146, /* Address 0x402a1000, size 0x00000100 */ 4164 PROT_DMAC_CH1_CH = 147, /* Address 0x402a1100, size 0x00000100 */ 4165 PROT_DMAC_CH2_CH = 148, /* Address 0x402a1200, size 0x00000100 */ 4166 PROT_DMAC_CH3_CH = 149, /* Address 0x402a1300, size 0x00000100 */ 4167 PROT_EFUSE_CTL = 150, /* Address 0x402c0000, size 0x00000080 */ 4168 PROT_EFUSE_DATA = 151, /* Address 0x402c0800, size 0x00000200 */ 4169 PROT_PROFILE = 152, /* Address 0x402d0000, size 0x00010000 */ 4170 PROT_HSIOM_PRT0_PRT = 153, /* Address 0x40300000, size 0x00000008 */ 4171 PROT_HSIOM_PRT1_PRT = 154, /* Address 0x40300010, size 0x00000008 */ 4172 PROT_HSIOM_PRT2_PRT = 155, /* Address 0x40300020, size 0x00000008 */ 4173 PROT_HSIOM_PRT3_PRT = 156, /* Address 0x40300030, size 0x00000008 */ 4174 PROT_HSIOM_PRT4_PRT = 157, /* Address 0x40300040, size 0x00000008 */ 4175 PROT_HSIOM_PRT5_PRT = 158, /* Address 0x40300050, size 0x00000008 */ 4176 PROT_HSIOM_PRT6_PRT = 159, /* Address 0x40300060, size 0x00000008 */ 4177 PROT_HSIOM_PRT7_PRT = 160, /* Address 0x40300070, size 0x00000008 */ 4178 PROT_HSIOM_PRT8_PRT = 161, /* Address 0x40300080, size 0x00000008 */ 4179 PROT_HSIOM_PRT9_PRT = 162, /* Address 0x40300090, size 0x00000008 */ 4180 PROT_HSIOM_PRT10_PRT = 163, /* Address 0x403000a0, size 0x00000008 */ 4181 PROT_HSIOM_PRT11_PRT = 164, /* Address 0x403000b0, size 0x00000008 */ 4182 PROT_HSIOM_PRT12_PRT = 165, /* Address 0x403000c0, size 0x00000008 */ 4183 PROT_HSIOM_PRT13_PRT = 166, /* Address 0x403000d0, size 0x00000008 */ 4184 PROT_HSIOM_PRT14_PRT = 167, /* Address 0x403000e0, size 0x00000008 */ 4185 PROT_HSIOM_AMUX = 168, /* Address 0x40302000, size 0x00000020 */ 4186 PROT_HSIOM_MON = 169, /* Address 0x40302200, size 0x00000010 */ 4187 PROT_GPIO_PRT0_PRT = 170, /* Address 0x40310000, size 0x00000040 */ 4188 PROT_GPIO_PRT1_PRT = 171, /* Address 0x40310080, size 0x00000040 */ 4189 PROT_GPIO_PRT2_PRT = 172, /* Address 0x40310100, size 0x00000040 */ 4190 PROT_GPIO_PRT3_PRT = 173, /* Address 0x40310180, size 0x00000040 */ 4191 PROT_GPIO_PRT4_PRT = 174, /* Address 0x40310200, size 0x00000040 */ 4192 PROT_GPIO_PRT5_PRT = 175, /* Address 0x40310280, size 0x00000040 */ 4193 PROT_GPIO_PRT6_PRT = 176, /* Address 0x40310300, size 0x00000040 */ 4194 PROT_GPIO_PRT7_PRT = 177, /* Address 0x40310380, size 0x00000040 */ 4195 PROT_GPIO_PRT8_PRT = 178, /* Address 0x40310400, size 0x00000040 */ 4196 PROT_GPIO_PRT9_PRT = 179, /* Address 0x40310480, size 0x00000040 */ 4197 PROT_GPIO_PRT10_PRT = 180, /* Address 0x40310500, size 0x00000040 */ 4198 PROT_GPIO_PRT11_PRT = 181, /* Address 0x40310580, size 0x00000040 */ 4199 PROT_GPIO_PRT12_PRT = 182, /* Address 0x40310600, size 0x00000040 */ 4200 PROT_GPIO_PRT13_PRT = 183, /* Address 0x40310680, size 0x00000040 */ 4201 PROT_GPIO_PRT14_PRT = 184, /* Address 0x40310700, size 0x00000040 */ 4202 PROT_GPIO_PRT0_CFG = 185, /* Address 0x40310040, size 0x00000010 */ 4203 PROT_GPIO_PRT1_CFG = 186, /* Address 0x403100c0, size 0x00000010 */ 4204 PROT_GPIO_PRT2_CFG = 187, /* Address 0x40310140, size 0x00000010 */ 4205 PROT_GPIO_PRT3_CFG = 188, /* Address 0x403101c0, size 0x00000010 */ 4206 PROT_GPIO_PRT4_CFG = 189, /* Address 0x40310240, size 0x00000010 */ 4207 PROT_GPIO_PRT5_CFG = 190, /* Address 0x403102c0, size 0x00000010 */ 4208 PROT_GPIO_PRT6_CFG = 191, /* Address 0x40310340, size 0x00000010 */ 4209 PROT_GPIO_PRT7_CFG = 192, /* Address 0x403103c0, size 0x00000010 */ 4210 PROT_GPIO_PRT8_CFG = 193, /* Address 0x40310440, size 0x00000010 */ 4211 PROT_GPIO_PRT9_CFG = 194, /* Address 0x403104c0, size 0x00000010 */ 4212 PROT_GPIO_PRT10_CFG = 195, /* Address 0x40310540, size 0x00000010 */ 4213 PROT_GPIO_PRT11_CFG = 196, /* Address 0x403105c0, size 0x00000010 */ 4214 PROT_GPIO_PRT12_CFG = 197, /* Address 0x40310640, size 0x00000010 */ 4215 PROT_GPIO_PRT13_CFG = 198, /* Address 0x403106c0, size 0x00000010 */ 4216 PROT_GPIO_PRT14_CFG = 199, /* Address 0x40310740, size 0x00000008 */ 4217 PROT_GPIO_GPIO = 200, /* Address 0x40314000, size 0x00000040 */ 4218 PROT_GPIO_TEST = 201, /* Address 0x40315000, size 0x00000008 */ 4219 PROT_SMARTIO_PRT8_PRT = 202, /* Address 0x40320800, size 0x00000100 */ 4220 PROT_SMARTIO_PRT9_PRT = 203, /* Address 0x40320900, size 0x00000100 */ 4221 PROT_LPCOMP = 204, /* Address 0x40350000, size 0x00010000 */ 4222 PROT_CSD0 = 205, /* Address 0x40360000, size 0x00001000 */ 4223 PROT_TCPWM0 = 206, /* Address 0x40380000, size 0x00010000 */ 4224 PROT_TCPWM1 = 207, /* Address 0x40390000, size 0x00010000 */ 4225 PROT_LCD0 = 208, /* Address 0x403b0000, size 0x00010000 */ 4226 PROT_USBFS0 = 209, /* Address 0x403f0000, size 0x00010000 */ 4227 PROT_SMIF0 = 210, /* Address 0x40420000, size 0x00010000 */ 4228 PROT_SDHC0 = 211, /* Address 0x40460000, size 0x00010000 */ 4229 PROT_SDHC1 = 212, /* Address 0x40470000, size 0x00010000 */ 4230 PROT_SCB0 = 213, /* Address 0x40600000, size 0x00010000 */ 4231 PROT_SCB1 = 214, /* Address 0x40610000, size 0x00010000 */ 4232 PROT_SCB2 = 215, /* Address 0x40620000, size 0x00010000 */ 4233 PROT_SCB3 = 216, /* Address 0x40630000, size 0x00010000 */ 4234 PROT_SCB4 = 217, /* Address 0x40640000, size 0x00010000 */ 4235 PROT_SCB5 = 218, /* Address 0x40650000, size 0x00010000 */ 4236 PROT_SCB6 = 219, /* Address 0x40660000, size 0x00010000 */ 4237 PROT_SCB7 = 220, /* Address 0x40670000, size 0x00010000 */ 4238 PROT_SCB8 = 221, /* Address 0x40680000, size 0x00010000 */ 4239 PROT_SCB9 = 222, /* Address 0x40690000, size 0x00010000 */ 4240 PROT_SCB10 = 223, /* Address 0x406a0000, size 0x00010000 */ 4241 PROT_SCB11 = 224, /* Address 0x406b0000, size 0x00010000 */ 4242 PROT_SCB12 = 225, /* Address 0x406c0000, size 0x00010000 */ 4243 PROT_PASS = 226, /* Address 0x40900000, size 0x00100000 */ 4244 PROT_PDM0 = 227, /* Address 0x40a00000, size 0x00001000 */ 4245 PROT_I2S0 = 228, /* Address 0x40a10000, size 0x00001000 */ 4246 PROT_I2S1 = 229 /* Address 0x40a11000, size 0x00001000 */ 4247 } cy_en_prot_region_t; 4248 4249 #endif /* _PSOC6_02_CONFIG_H_ */ 4250 4251 4252 /* [] END OF FILE */ 4253
