1 /***************************************************************************//** 2 * \file cyip_tcpwm.h 3 * 4 * \brief 5 * TCPWM IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_TCPWM_H_ 28 #define _CYIP_TCPWM_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * TCPWM 34 *******************************************************************************/ 35 36 #define TCPWM_CNT_SECTION_SIZE 0x00000040UL 37 #define TCPWM_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief Timer/Counter/PWM Counter Module (TCPWM_CNT) 41 */ 42 typedef struct { 43 __IOM uint32_t CTRL; /*!< 0x00000000 Counter control register */ 44 __IM uint32_t STATUS; /*!< 0x00000004 Counter status register */ 45 __IOM uint32_t COUNTER; /*!< 0x00000008 Counter count register */ 46 __IOM uint32_t CC; /*!< 0x0000000C Counter compare/capture register */ 47 __IOM uint32_t CC_BUFF; /*!< 0x00000010 Counter buffered compare/capture register */ 48 __IOM uint32_t PERIOD; /*!< 0x00000014 Counter period register */ 49 __IOM uint32_t PERIOD_BUFF; /*!< 0x00000018 Counter buffered period register */ 50 __IM uint32_t RESERVED; 51 __IOM uint32_t TR_CTRL0; /*!< 0x00000020 Counter trigger control register 0 */ 52 __IOM uint32_t TR_CTRL1; /*!< 0x00000024 Counter trigger control register 1 */ 53 __IOM uint32_t TR_CTRL2; /*!< 0x00000028 Counter trigger control register 2 */ 54 __IM uint32_t RESERVED1; 55 __IOM uint32_t INTR; /*!< 0x00000030 Interrupt request register */ 56 __IOM uint32_t INTR_SET; /*!< 0x00000034 Interrupt set request register */ 57 __IOM uint32_t INTR_MASK; /*!< 0x00000038 Interrupt mask register */ 58 __IM uint32_t INTR_MASKED; /*!< 0x0000003C Interrupt masked request register */ 59 } TCPWM_CNT_V1_Type; /*!< Size = 64 (0x40) */ 60 61 /** 62 * \brief Timer/Counter/PWM (TCPWM) 63 */ 64 typedef struct { 65 __IOM uint32_t CTRL; /*!< 0x00000000 TCPWM control register */ 66 __IOM uint32_t CTRL_CLR; /*!< 0x00000004 TCPWM control clear register */ 67 __IOM uint32_t CTRL_SET; /*!< 0x00000008 TCPWM control set register */ 68 __IOM uint32_t CMD_CAPTURE; /*!< 0x0000000C TCPWM capture command register */ 69 __IOM uint32_t CMD_RELOAD; /*!< 0x00000010 TCPWM reload command register */ 70 __IOM uint32_t CMD_STOP; /*!< 0x00000014 TCPWM stop command register */ 71 __IOM uint32_t CMD_START; /*!< 0x00000018 TCPWM start command register */ 72 __IM uint32_t INTR_CAUSE; /*!< 0x0000001C TCPWM Counter interrupt cause register */ 73 __IM uint32_t RESERVED[56]; 74 TCPWM_CNT_V1_Type CNT[32]; /*!< 0x00000100 Timer/Counter/PWM Counter Module */ 75 } TCPWM_V1_Type; /*!< Size = 2304 (0x900) */ 76 77 78 /* TCPWM_CNT.CTRL */ 79 #define TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Pos 0UL 80 #define TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk 0x1UL 81 #define TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Pos 1UL 82 #define TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk 0x2UL 83 #define TCPWM_CNT_CTRL_PWM_SYNC_KILL_Pos 2UL 84 #define TCPWM_CNT_CTRL_PWM_SYNC_KILL_Msk 0x4UL 85 #define TCPWM_CNT_CTRL_PWM_STOP_ON_KILL_Pos 3UL 86 #define TCPWM_CNT_CTRL_PWM_STOP_ON_KILL_Msk 0x8UL 87 #define TCPWM_CNT_CTRL_GENERIC_Pos 8UL 88 #define TCPWM_CNT_CTRL_GENERIC_Msk 0xFF00UL 89 #define TCPWM_CNT_CTRL_UP_DOWN_MODE_Pos 16UL 90 #define TCPWM_CNT_CTRL_UP_DOWN_MODE_Msk 0x30000UL 91 #define TCPWM_CNT_CTRL_ONE_SHOT_Pos 18UL 92 #define TCPWM_CNT_CTRL_ONE_SHOT_Msk 0x40000UL 93 #define TCPWM_CNT_CTRL_QUADRATURE_MODE_Pos 20UL 94 #define TCPWM_CNT_CTRL_QUADRATURE_MODE_Msk 0x300000UL 95 #define TCPWM_CNT_CTRL_MODE_Pos 24UL 96 #define TCPWM_CNT_CTRL_MODE_Msk 0x7000000UL 97 /* TCPWM_CNT.STATUS */ 98 #define TCPWM_CNT_STATUS_DOWN_Pos 0UL 99 #define TCPWM_CNT_STATUS_DOWN_Msk 0x1UL 100 #define TCPWM_CNT_STATUS_GENERIC_Pos 8UL 101 #define TCPWM_CNT_STATUS_GENERIC_Msk 0xFF00UL 102 #define TCPWM_CNT_STATUS_RUNNING_Pos 31UL 103 #define TCPWM_CNT_STATUS_RUNNING_Msk 0x80000000UL 104 /* TCPWM_CNT.COUNTER */ 105 #define TCPWM_CNT_COUNTER_COUNTER_Pos 0UL 106 #define TCPWM_CNT_COUNTER_COUNTER_Msk 0xFFFFFFFFUL 107 /* TCPWM_CNT.CC */ 108 #define TCPWM_CNT_CC_CC_Pos 0UL 109 #define TCPWM_CNT_CC_CC_Msk 0xFFFFFFFFUL 110 /* TCPWM_CNT.CC_BUFF */ 111 #define TCPWM_CNT_CC_BUFF_CC_Pos 0UL 112 #define TCPWM_CNT_CC_BUFF_CC_Msk 0xFFFFFFFFUL 113 /* TCPWM_CNT.PERIOD */ 114 #define TCPWM_CNT_PERIOD_PERIOD_Pos 0UL 115 #define TCPWM_CNT_PERIOD_PERIOD_Msk 0xFFFFFFFFUL 116 /* TCPWM_CNT.PERIOD_BUFF */ 117 #define TCPWM_CNT_PERIOD_BUFF_PERIOD_Pos 0UL 118 #define TCPWM_CNT_PERIOD_BUFF_PERIOD_Msk 0xFFFFFFFFUL 119 /* TCPWM_CNT.TR_CTRL0 */ 120 #define TCPWM_CNT_TR_CTRL0_CAPTURE_SEL_Pos 0UL 121 #define TCPWM_CNT_TR_CTRL0_CAPTURE_SEL_Msk 0xFUL 122 #define TCPWM_CNT_TR_CTRL0_COUNT_SEL_Pos 4UL 123 #define TCPWM_CNT_TR_CTRL0_COUNT_SEL_Msk 0xF0UL 124 #define TCPWM_CNT_TR_CTRL0_RELOAD_SEL_Pos 8UL 125 #define TCPWM_CNT_TR_CTRL0_RELOAD_SEL_Msk 0xF00UL 126 #define TCPWM_CNT_TR_CTRL0_STOP_SEL_Pos 12UL 127 #define TCPWM_CNT_TR_CTRL0_STOP_SEL_Msk 0xF000UL 128 #define TCPWM_CNT_TR_CTRL0_START_SEL_Pos 16UL 129 #define TCPWM_CNT_TR_CTRL0_START_SEL_Msk 0xF0000UL 130 /* TCPWM_CNT.TR_CTRL1 */ 131 #define TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE_Pos 0UL 132 #define TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE_Msk 0x3UL 133 #define TCPWM_CNT_TR_CTRL1_COUNT_EDGE_Pos 2UL 134 #define TCPWM_CNT_TR_CTRL1_COUNT_EDGE_Msk 0xCUL 135 #define TCPWM_CNT_TR_CTRL1_RELOAD_EDGE_Pos 4UL 136 #define TCPWM_CNT_TR_CTRL1_RELOAD_EDGE_Msk 0x30UL 137 #define TCPWM_CNT_TR_CTRL1_STOP_EDGE_Pos 6UL 138 #define TCPWM_CNT_TR_CTRL1_STOP_EDGE_Msk 0xC0UL 139 #define TCPWM_CNT_TR_CTRL1_START_EDGE_Pos 8UL 140 #define TCPWM_CNT_TR_CTRL1_START_EDGE_Msk 0x300UL 141 /* TCPWM_CNT.TR_CTRL2 */ 142 #define TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE_Pos 0UL 143 #define TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE_Msk 0x3UL 144 #define TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE_Pos 2UL 145 #define TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE_Msk 0xCUL 146 #define TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE_Pos 4UL 147 #define TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE_Msk 0x30UL 148 /* TCPWM_CNT.INTR */ 149 #define TCPWM_CNT_INTR_TC_Pos 0UL 150 #define TCPWM_CNT_INTR_TC_Msk 0x1UL 151 #define TCPWM_CNT_INTR_CC_MATCH_Pos 1UL 152 #define TCPWM_CNT_INTR_CC_MATCH_Msk 0x2UL 153 /* TCPWM_CNT.INTR_SET */ 154 #define TCPWM_CNT_INTR_SET_TC_Pos 0UL 155 #define TCPWM_CNT_INTR_SET_TC_Msk 0x1UL 156 #define TCPWM_CNT_INTR_SET_CC_MATCH_Pos 1UL 157 #define TCPWM_CNT_INTR_SET_CC_MATCH_Msk 0x2UL 158 /* TCPWM_CNT.INTR_MASK */ 159 #define TCPWM_CNT_INTR_MASK_TC_Pos 0UL 160 #define TCPWM_CNT_INTR_MASK_TC_Msk 0x1UL 161 #define TCPWM_CNT_INTR_MASK_CC_MATCH_Pos 1UL 162 #define TCPWM_CNT_INTR_MASK_CC_MATCH_Msk 0x2UL 163 /* TCPWM_CNT.INTR_MASKED */ 164 #define TCPWM_CNT_INTR_MASKED_TC_Pos 0UL 165 #define TCPWM_CNT_INTR_MASKED_TC_Msk 0x1UL 166 #define TCPWM_CNT_INTR_MASKED_CC_MATCH_Pos 1UL 167 #define TCPWM_CNT_INTR_MASKED_CC_MATCH_Msk 0x2UL 168 169 170 /* TCPWM.CTRL */ 171 #define TCPWM_CTRL_COUNTER_ENABLED_Pos 0UL 172 #define TCPWM_CTRL_COUNTER_ENABLED_Msk 0xFFFFFFFFUL 173 /* TCPWM.CTRL_CLR */ 174 #define TCPWM_CTRL_CLR_COUNTER_ENABLED_Pos 0UL 175 #define TCPWM_CTRL_CLR_COUNTER_ENABLED_Msk 0xFFFFFFFFUL 176 /* TCPWM.CTRL_SET */ 177 #define TCPWM_CTRL_SET_COUNTER_ENABLED_Pos 0UL 178 #define TCPWM_CTRL_SET_COUNTER_ENABLED_Msk 0xFFFFFFFFUL 179 /* TCPWM.CMD_CAPTURE */ 180 #define TCPWM_CMD_CAPTURE_COUNTER_CAPTURE_Pos 0UL 181 #define TCPWM_CMD_CAPTURE_COUNTER_CAPTURE_Msk 0xFFFFFFFFUL 182 /* TCPWM.CMD_RELOAD */ 183 #define TCPWM_CMD_RELOAD_COUNTER_RELOAD_Pos 0UL 184 #define TCPWM_CMD_RELOAD_COUNTER_RELOAD_Msk 0xFFFFFFFFUL 185 /* TCPWM.CMD_STOP */ 186 #define TCPWM_CMD_STOP_COUNTER_STOP_Pos 0UL 187 #define TCPWM_CMD_STOP_COUNTER_STOP_Msk 0xFFFFFFFFUL 188 /* TCPWM.CMD_START */ 189 #define TCPWM_CMD_START_COUNTER_START_Pos 0UL 190 #define TCPWM_CMD_START_COUNTER_START_Msk 0xFFFFFFFFUL 191 /* TCPWM.INTR_CAUSE */ 192 #define TCPWM_INTR_CAUSE_COUNTER_INT_Pos 0UL 193 #define TCPWM_INTR_CAUSE_COUNTER_INT_Msk 0xFFFFFFFFUL 194 195 196 #endif /* _CYIP_TCPWM_H_ */ 197 198 199 /* [] END OF FILE */ 200
