1 /***************************************************************************//** 2 * \file cyip_srss.h 3 * 4 * \brief 5 * SRSS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_SRSS_H_ 28 #define _CYIP_SRSS_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * SRSS 34 *******************************************************************************/ 35 36 #define MCWDT_STRUCT_SECTION_SIZE 0x00000040UL 37 #define SRSS_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief Multi-Counter Watchdog Timer (MCWDT_STRUCT) 41 */ 42 typedef struct { 43 __IM uint32_t RESERVED; 44 __IOM uint32_t MCWDT_CNTLOW; /*!< 0x00000004 Multi-Counter Watchdog Sub-counters 0/1 */ 45 __IOM uint32_t MCWDT_CNTHIGH; /*!< 0x00000008 Multi-Counter Watchdog Sub-counter 2 */ 46 __IOM uint32_t MCWDT_MATCH; /*!< 0x0000000C Multi-Counter Watchdog Counter Match Register */ 47 __IOM uint32_t MCWDT_CONFIG; /*!< 0x00000010 Multi-Counter Watchdog Counter Configuration */ 48 __IOM uint32_t MCWDT_CTL; /*!< 0x00000014 Multi-Counter Watchdog Counter Control */ 49 __IOM uint32_t MCWDT_INTR; /*!< 0x00000018 Multi-Counter Watchdog Counter Interrupt Register */ 50 __IOM uint32_t MCWDT_INTR_SET; /*!< 0x0000001C Multi-Counter Watchdog Counter Interrupt Set Register */ 51 __IOM uint32_t MCWDT_INTR_MASK; /*!< 0x00000020 Multi-Counter Watchdog Counter Interrupt Mask Register */ 52 __IM uint32_t MCWDT_INTR_MASKED; /*!< 0x00000024 Multi-Counter Watchdog Counter Interrupt Masked Register */ 53 __IOM uint32_t MCWDT_LOCK; /*!< 0x00000028 Multi-Counter Watchdog Counter Lock Register */ 54 __IM uint32_t RESERVED1[5]; 55 } MCWDT_STRUCT_V1_Type; /*!< Size = 64 (0x40) */ 56 57 /** 58 * \brief SRSS Core Registers (SRSS) 59 */ 60 typedef struct { 61 __IOM uint32_t PWR_CTL; /*!< 0x00000000 Power Mode Control */ 62 __IOM uint32_t PWR_HIBERNATE; /*!< 0x00000004 HIBERNATE Mode Register */ 63 __IOM uint32_t PWR_LVD_CTL; /*!< 0x00000008 Low Voltage Detector (LVD) Configuration Register */ 64 __IM uint32_t RESERVED[2]; 65 __IOM uint32_t PWR_BUCK_CTL; /*!< 0x00000014 Buck Control Register */ 66 __IOM uint32_t PWR_BUCK_CTL2; /*!< 0x00000018 Buck Control Register 2 */ 67 __IM uint32_t PWR_LVD_STATUS; /*!< 0x0000001C Low Voltage Detector (LVD) Status Register */ 68 __IM uint32_t RESERVED1[24]; 69 __IOM uint32_t PWR_HIB_DATA[16]; /*!< 0x00000080 HIBERNATE Data Register */ 70 __IM uint32_t RESERVED2[48]; 71 __IOM uint32_t WDT_CTL; /*!< 0x00000180 Watchdog Counter Control Register */ 72 __IOM uint32_t WDT_CNT; /*!< 0x00000184 Watchdog Counter Count Register */ 73 __IOM uint32_t WDT_MATCH; /*!< 0x00000188 Watchdog Counter Match Register */ 74 __IM uint32_t RESERVED3[29]; 75 MCWDT_STRUCT_V1_Type MCWDT_STRUCT[4]; /*!< 0x00000200 Multi-Counter Watchdog Timer */ 76 __IOM uint32_t CLK_DSI_SELECT[16]; /*!< 0x00000300 Clock DSI Select Register */ 77 __IOM uint32_t CLK_PATH_SELECT[16]; /*!< 0x00000340 Clock Path Select Register */ 78 __IOM uint32_t CLK_ROOT_SELECT[16]; /*!< 0x00000380 Clock Root Select Register */ 79 __IM uint32_t RESERVED4[80]; 80 __IOM uint32_t CLK_SELECT; /*!< 0x00000500 Clock selection register */ 81 __IOM uint32_t CLK_TIMER_CTL; /*!< 0x00000504 Timer Clock Control Register */ 82 __IM uint32_t RESERVED5; 83 __IOM uint32_t CLK_ILO_CONFIG; /*!< 0x0000050C ILO Configuration */ 84 __IOM uint32_t CLK_IMO_CONFIG; /*!< 0x00000510 IMO Configuration */ 85 __IOM uint32_t CLK_OUTPUT_FAST; /*!< 0x00000514 Fast Clock Output Select Register */ 86 __IOM uint32_t CLK_OUTPUT_SLOW; /*!< 0x00000518 Slow Clock Output Select Register */ 87 __IOM uint32_t CLK_CAL_CNT1; /*!< 0x0000051C Clock Calibration Counter 1 */ 88 __IM uint32_t CLK_CAL_CNT2; /*!< 0x00000520 Clock Calibration Counter 2 */ 89 __IM uint32_t RESERVED6[2]; 90 __IOM uint32_t CLK_ECO_CONFIG; /*!< 0x0000052C ECO Configuration Register */ 91 __IM uint32_t CLK_ECO_STATUS; /*!< 0x00000530 ECO Status Register */ 92 __IM uint32_t RESERVED7[2]; 93 __IOM uint32_t CLK_PILO_CONFIG; /*!< 0x0000053C Precision ILO Configuration Register */ 94 __IM uint32_t RESERVED8; 95 __IOM uint32_t CLK_MF_SELECT; /*!< 0x00000544 Medium Frequency Clock Select Register */ 96 __IOM uint32_t CLK_MFO_CONFIG; /*!< 0x00000548 MFO Configuration Register */ 97 __IM uint32_t RESERVED9[13]; 98 __IOM uint32_t CLK_FLL_CONFIG; /*!< 0x00000580 FLL Configuration Register */ 99 __IOM uint32_t CLK_FLL_CONFIG2; /*!< 0x00000584 FLL Configuration Register 2 */ 100 __IOM uint32_t CLK_FLL_CONFIG3; /*!< 0x00000588 FLL Configuration Register 3 */ 101 __IOM uint32_t CLK_FLL_CONFIG4; /*!< 0x0000058C FLL Configuration Register 4 */ 102 __IOM uint32_t CLK_FLL_STATUS; /*!< 0x00000590 FLL Status Register */ 103 __IM uint32_t RESERVED10[27]; 104 __IOM uint32_t CLK_PLL_CONFIG[15]; /*!< 0x00000600 PLL Configuration Register */ 105 __IM uint32_t RESERVED11; 106 __IOM uint32_t CLK_PLL_STATUS[15]; /*!< 0x00000640 PLL Status Register */ 107 __IM uint32_t RESERVED12[33]; 108 __IOM uint32_t SRSS_INTR; /*!< 0x00000700 SRSS Interrupt Register */ 109 __IOM uint32_t SRSS_INTR_SET; /*!< 0x00000704 SRSS Interrupt Set Register */ 110 __IOM uint32_t SRSS_INTR_MASK; /*!< 0x00000708 SRSS Interrupt Mask Register */ 111 __IM uint32_t SRSS_INTR_MASKED; /*!< 0x0000070C SRSS Interrupt Masked Register */ 112 __IOM uint32_t SRSS_INTR_CFG; /*!< 0x00000710 SRSS Interrupt Configuration Register */ 113 __IM uint32_t RESERVED13[59]; 114 __IOM uint32_t RES_CAUSE; /*!< 0x00000800 Reset Cause Observation Register */ 115 __IOM uint32_t RES_CAUSE2; /*!< 0x00000804 Reset Cause Observation Register 2 */ 116 __IM uint32_t RESERVED14[7614]; 117 __IOM uint32_t PWR_TRIM_REF_CTL; /*!< 0x00007F00 Reference Trim Register */ 118 __IOM uint32_t PWR_TRIM_BODOVP_CTL; /*!< 0x00007F04 BOD/OVP Trim Register */ 119 __IOM uint32_t CLK_TRIM_CCO_CTL; /*!< 0x00007F08 CCO Trim Register */ 120 __IOM uint32_t CLK_TRIM_CCO_CTL2; /*!< 0x00007F0C CCO Trim Register 2 */ 121 __IM uint32_t RESERVED15[8]; 122 __IOM uint32_t PWR_TRIM_WAKE_CTL; /*!< 0x00007F30 Wakeup Trim Register */ 123 __IM uint32_t RESERVED16[8183]; 124 __IOM uint32_t PWR_TRIM_LVD_CTL; /*!< 0x0000FF10 LVD Trim Register */ 125 __IM uint32_t RESERVED17; 126 __IOM uint32_t CLK_TRIM_ILO_CTL; /*!< 0x0000FF18 ILO Trim Register */ 127 __IOM uint32_t PWR_TRIM_PWRSYS_CTL; /*!< 0x0000FF1C Power System Trim Register */ 128 __IOM uint32_t CLK_TRIM_ECO_CTL; /*!< 0x0000FF20 ECO Trim Register */ 129 __IOM uint32_t CLK_TRIM_PILO_CTL; /*!< 0x0000FF24 PILO Trim Register */ 130 __IOM uint32_t CLK_TRIM_PILO_CTL2; /*!< 0x0000FF28 PILO Trim Register 2 */ 131 __IOM uint32_t CLK_TRIM_PILO_CTL3; /*!< 0x0000FF2C PILO Trim Register 3 */ 132 } SRSS_V1_Type; /*!< Size = 65328 (0xFF30) */ 133 134 135 /* MCWDT_STRUCT.MCWDT_CNTLOW */ 136 #define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Pos 0UL 137 #define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk 0xFFFFUL 138 #define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Pos 16UL 139 #define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Msk 0xFFFF0000UL 140 /* MCWDT_STRUCT.MCWDT_CNTHIGH */ 141 #define MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2_Pos 0UL 142 #define MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2_Msk 0xFFFFFFFFUL 143 /* MCWDT_STRUCT.MCWDT_MATCH */ 144 #define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Pos 0UL 145 #define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk 0xFFFFUL 146 #define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1_Pos 16UL 147 #define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1_Msk 0xFFFF0000UL 148 /* MCWDT_STRUCT.MCWDT_CONFIG */ 149 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0_Pos 0UL 150 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0_Msk 0x3UL 151 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Pos 2UL 152 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk 0x4UL 153 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Pos 3UL 154 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Msk 0x8UL 155 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1_Pos 8UL 156 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1_Msk 0x300UL 157 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Pos 10UL 158 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Msk 0x400UL 159 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Pos 11UL 160 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Msk 0x800UL 161 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2_Pos 16UL 162 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2_Msk 0x10000UL 163 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2_Pos 24UL 164 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2_Msk 0x1F000000UL 165 /* MCWDT_STRUCT.MCWDT_CTL */ 166 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Pos 0UL 167 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk 0x1UL 168 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0_Pos 1UL 169 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0_Msk 0x2UL 170 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Pos 3UL 171 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Msk 0x8UL 172 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Pos 8UL 173 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk 0x100UL 174 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1_Pos 9UL 175 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1_Msk 0x200UL 176 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Pos 11UL 177 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Msk 0x800UL 178 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Pos 16UL 179 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk 0x10000UL 180 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2_Pos 17UL 181 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2_Msk 0x20000UL 182 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Pos 19UL 183 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Msk 0x80000UL 184 /* MCWDT_STRUCT.MCWDT_INTR */ 185 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT0_Pos 0UL 186 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT0_Msk 0x1UL 187 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT1_Pos 1UL 188 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT1_Msk 0x2UL 189 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT2_Pos 2UL 190 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT2_Msk 0x4UL 191 /* MCWDT_STRUCT.MCWDT_INTR_SET */ 192 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT0_Pos 0UL 193 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT0_Msk 0x1UL 194 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT1_Pos 1UL 195 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT1_Msk 0x2UL 196 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT2_Pos 2UL 197 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT2_Msk 0x4UL 198 /* MCWDT_STRUCT.MCWDT_INTR_MASK */ 199 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT0_Pos 0UL 200 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT0_Msk 0x1UL 201 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT1_Pos 1UL 202 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT1_Msk 0x2UL 203 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT2_Pos 2UL 204 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT2_Msk 0x4UL 205 /* MCWDT_STRUCT.MCWDT_INTR_MASKED */ 206 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT0_Pos 0UL 207 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT0_Msk 0x1UL 208 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT1_Pos 1UL 209 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT1_Msk 0x2UL 210 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT2_Pos 2UL 211 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT2_Msk 0x4UL 212 /* MCWDT_STRUCT.MCWDT_LOCK */ 213 #define MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Pos 30UL 214 #define MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Msk 0xC0000000UL 215 216 217 /* SRSS.PWR_CTL */ 218 #define SRSS_PWR_CTL_POWER_MODE_Pos 0UL 219 #define SRSS_PWR_CTL_POWER_MODE_Msk 0x3UL 220 #define SRSS_PWR_CTL_DEBUG_SESSION_Pos 4UL 221 #define SRSS_PWR_CTL_DEBUG_SESSION_Msk 0x10UL 222 #define SRSS_PWR_CTL_LPM_READY_Pos 5UL 223 #define SRSS_PWR_CTL_LPM_READY_Msk 0x20UL 224 #define SRSS_PWR_CTL_IREF_LPMODE_Pos 18UL 225 #define SRSS_PWR_CTL_IREF_LPMODE_Msk 0x40000UL 226 #define SRSS_PWR_CTL_VREFBUF_OK_Pos 19UL 227 #define SRSS_PWR_CTL_VREFBUF_OK_Msk 0x80000UL 228 #define SRSS_PWR_CTL_DPSLP_REG_DIS_Pos 20UL 229 #define SRSS_PWR_CTL_DPSLP_REG_DIS_Msk 0x100000UL 230 #define SRSS_PWR_CTL_RET_REG_DIS_Pos 21UL 231 #define SRSS_PWR_CTL_RET_REG_DIS_Msk 0x200000UL 232 #define SRSS_PWR_CTL_NWELL_REG_DIS_Pos 22UL 233 #define SRSS_PWR_CTL_NWELL_REG_DIS_Msk 0x400000UL 234 #define SRSS_PWR_CTL_LINREG_DIS_Pos 23UL 235 #define SRSS_PWR_CTL_LINREG_DIS_Msk 0x800000UL 236 #define SRSS_PWR_CTL_LINREG_LPMODE_Pos 24UL 237 #define SRSS_PWR_CTL_LINREG_LPMODE_Msk 0x1000000UL 238 #define SRSS_PWR_CTL_PORBOD_LPMODE_Pos 25UL 239 #define SRSS_PWR_CTL_PORBOD_LPMODE_Msk 0x2000000UL 240 #define SRSS_PWR_CTL_BGREF_LPMODE_Pos 26UL 241 #define SRSS_PWR_CTL_BGREF_LPMODE_Msk 0x4000000UL 242 #define SRSS_PWR_CTL_PLL_LS_BYPASS_Pos 27UL 243 #define SRSS_PWR_CTL_PLL_LS_BYPASS_Msk 0x8000000UL 244 #define SRSS_PWR_CTL_VREFBUF_LPMODE_Pos 28UL 245 #define SRSS_PWR_CTL_VREFBUF_LPMODE_Msk 0x10000000UL 246 #define SRSS_PWR_CTL_VREFBUF_DIS_Pos 29UL 247 #define SRSS_PWR_CTL_VREFBUF_DIS_Msk 0x20000000UL 248 #define SRSS_PWR_CTL_ACT_REF_DIS_Pos 30UL 249 #define SRSS_PWR_CTL_ACT_REF_DIS_Msk 0x40000000UL 250 #define SRSS_PWR_CTL_ACT_REF_OK_Pos 31UL 251 #define SRSS_PWR_CTL_ACT_REF_OK_Msk 0x80000000UL 252 /* SRSS.PWR_HIBERNATE */ 253 #define SRSS_PWR_HIBERNATE_TOKEN_Pos 0UL 254 #define SRSS_PWR_HIBERNATE_TOKEN_Msk 0xFFUL 255 #define SRSS_PWR_HIBERNATE_UNLOCK_Pos 8UL 256 #define SRSS_PWR_HIBERNATE_UNLOCK_Msk 0xFF00UL 257 #define SRSS_PWR_HIBERNATE_FREEZE_Pos 17UL 258 #define SRSS_PWR_HIBERNATE_FREEZE_Msk 0x20000UL 259 #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Pos 18UL 260 #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk 0x40000UL 261 #define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Pos 19UL 262 #define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk 0x80000UL 263 #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos 20UL 264 #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk 0xF00000UL 265 #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos 24UL 266 #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk 0xF000000UL 267 #define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Pos 30UL 268 #define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Msk 0x40000000UL 269 #define SRSS_PWR_HIBERNATE_HIBERNATE_Pos 31UL 270 #define SRSS_PWR_HIBERNATE_HIBERNATE_Msk 0x80000000UL 271 /* SRSS.PWR_LVD_CTL */ 272 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Pos 0UL 273 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Msk 0xFUL 274 #define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Pos 4UL 275 #define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Msk 0x70UL 276 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_Pos 7UL 277 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_Msk 0x80UL 278 /* SRSS.PWR_BUCK_CTL */ 279 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Pos 0UL 280 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Msk 0x7UL 281 #define SRSS_PWR_BUCK_CTL_BUCK_EN_Pos 30UL 282 #define SRSS_PWR_BUCK_CTL_BUCK_EN_Msk 0x40000000UL 283 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Pos 31UL 284 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Msk 0x80000000UL 285 /* SRSS.PWR_BUCK_CTL2 */ 286 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Pos 0UL 287 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Msk 0x7UL 288 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Pos 30UL 289 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Msk 0x40000000UL 290 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Pos 31UL 291 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Msk 0x80000000UL 292 /* SRSS.PWR_LVD_STATUS */ 293 #define SRSS_PWR_LVD_STATUS_HVLVD1_OK_Pos 0UL 294 #define SRSS_PWR_LVD_STATUS_HVLVD1_OK_Msk 0x1UL 295 /* SRSS.PWR_HIB_DATA */ 296 #define SRSS_PWR_HIB_DATA_HIB_DATA_Pos 0UL 297 #define SRSS_PWR_HIB_DATA_HIB_DATA_Msk 0xFFFFFFFFUL 298 /* SRSS.WDT_CTL */ 299 #define SRSS_WDT_CTL_WDT_EN_Pos 0UL 300 #define SRSS_WDT_CTL_WDT_EN_Msk 0x1UL 301 #define SRSS_WDT_CTL_WDT_LOCK_Pos 30UL 302 #define SRSS_WDT_CTL_WDT_LOCK_Msk 0xC0000000UL 303 /* SRSS.WDT_CNT */ 304 #define SRSS_WDT_CNT_COUNTER_Pos 0UL 305 #define SRSS_WDT_CNT_COUNTER_Msk 0xFFFFUL 306 /* SRSS.WDT_MATCH */ 307 #define SRSS_WDT_MATCH_MATCH_Pos 0UL 308 #define SRSS_WDT_MATCH_MATCH_Msk 0xFFFFUL 309 #define SRSS_WDT_MATCH_IGNORE_BITS_Pos 16UL 310 #define SRSS_WDT_MATCH_IGNORE_BITS_Msk 0xF0000UL 311 /* SRSS.CLK_DSI_SELECT */ 312 #define SRSS_CLK_DSI_SELECT_DSI_MUX_Pos 0UL 313 #define SRSS_CLK_DSI_SELECT_DSI_MUX_Msk 0x1FUL 314 /* SRSS.CLK_PATH_SELECT */ 315 #define SRSS_CLK_PATH_SELECT_PATH_MUX_Pos 0UL 316 #define SRSS_CLK_PATH_SELECT_PATH_MUX_Msk 0x7UL 317 /* SRSS.CLK_ROOT_SELECT */ 318 #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Pos 0UL 319 #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Msk 0xFUL 320 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Pos 4UL 321 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk 0x30UL 322 #define SRSS_CLK_ROOT_SELECT_ENABLE_Pos 31UL 323 #define SRSS_CLK_ROOT_SELECT_ENABLE_Msk 0x80000000UL 324 /* SRSS.CLK_SELECT */ 325 #define SRSS_CLK_SELECT_LFCLK_SEL_Pos 0UL 326 #define SRSS_CLK_SELECT_LFCLK_SEL_Msk 0x3UL 327 #define SRSS_CLK_SELECT_PUMP_SEL_Pos 8UL 328 #define SRSS_CLK_SELECT_PUMP_SEL_Msk 0xF00UL 329 #define SRSS_CLK_SELECT_PUMP_DIV_Pos 12UL 330 #define SRSS_CLK_SELECT_PUMP_DIV_Msk 0x7000UL 331 #define SRSS_CLK_SELECT_PUMP_ENABLE_Pos 15UL 332 #define SRSS_CLK_SELECT_PUMP_ENABLE_Msk 0x8000UL 333 /* SRSS.CLK_TIMER_CTL */ 334 #define SRSS_CLK_TIMER_CTL_TIMER_SEL_Pos 0UL 335 #define SRSS_CLK_TIMER_CTL_TIMER_SEL_Msk 0x1UL 336 #define SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Pos 8UL 337 #define SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk 0x300UL 338 #define SRSS_CLK_TIMER_CTL_TIMER_DIV_Pos 16UL 339 #define SRSS_CLK_TIMER_CTL_TIMER_DIV_Msk 0xFF0000UL 340 #define SRSS_CLK_TIMER_CTL_ENABLE_Pos 31UL 341 #define SRSS_CLK_TIMER_CTL_ENABLE_Msk 0x80000000UL 342 /* SRSS.CLK_ILO_CONFIG */ 343 #define SRSS_CLK_ILO_CONFIG_ILO_BACKUP_Pos 0UL 344 #define SRSS_CLK_ILO_CONFIG_ILO_BACKUP_Msk 0x1UL 345 #define SRSS_CLK_ILO_CONFIG_ENABLE_Pos 31UL 346 #define SRSS_CLK_ILO_CONFIG_ENABLE_Msk 0x80000000UL 347 /* SRSS.CLK_IMO_CONFIG */ 348 #define SRSS_CLK_IMO_CONFIG_ENABLE_Pos 31UL 349 #define SRSS_CLK_IMO_CONFIG_ENABLE_Msk 0x80000000UL 350 /* SRSS.CLK_OUTPUT_FAST */ 351 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Pos 0UL 352 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk 0xFUL 353 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Pos 4UL 354 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk 0xF0UL 355 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos 8UL 356 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk 0xF00UL 357 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Pos 16UL 358 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk 0xF0000UL 359 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Pos 20UL 360 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk 0xF00000UL 361 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos 24UL 362 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk 0xF000000UL 363 /* SRSS.CLK_OUTPUT_SLOW */ 364 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos 0UL 365 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk 0xFUL 366 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos 4UL 367 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk 0xF0UL 368 /* SRSS.CLK_CAL_CNT1 */ 369 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Pos 0UL 370 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Msk 0xFFFFFFUL 371 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos 31UL 372 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk 0x80000000UL 373 /* SRSS.CLK_CAL_CNT2 */ 374 #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Pos 0UL 375 #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Msk 0xFFFFFFUL 376 /* SRSS.CLK_ECO_CONFIG */ 377 #define SRSS_CLK_ECO_CONFIG_AGC_EN_Pos 1UL 378 #define SRSS_CLK_ECO_CONFIG_AGC_EN_Msk 0x2UL 379 #define SRSS_CLK_ECO_CONFIG_ECO_EN_Pos 31UL 380 #define SRSS_CLK_ECO_CONFIG_ECO_EN_Msk 0x80000000UL 381 /* SRSS.CLK_ECO_STATUS */ 382 #define SRSS_CLK_ECO_STATUS_ECO_OK_Pos 0UL 383 #define SRSS_CLK_ECO_STATUS_ECO_OK_Msk 0x1UL 384 #define SRSS_CLK_ECO_STATUS_ECO_READY_Pos 1UL 385 #define SRSS_CLK_ECO_STATUS_ECO_READY_Msk 0x2UL 386 /* SRSS.CLK_PILO_CONFIG */ 387 #define SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Pos 0UL 388 #define SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Msk 0x3FFUL 389 #define SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Pos 29UL 390 #define SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Msk 0x20000000UL 391 #define SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Pos 30UL 392 #define SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk 0x40000000UL 393 #define SRSS_CLK_PILO_CONFIG_PILO_EN_Pos 31UL 394 #define SRSS_CLK_PILO_CONFIG_PILO_EN_Msk 0x80000000UL 395 /* SRSS.CLK_MF_SELECT */ 396 #define SRSS_CLK_MF_SELECT_MFCLK_SEL_Pos 0UL 397 #define SRSS_CLK_MF_SELECT_MFCLK_SEL_Msk 0x7UL 398 #define SRSS_CLK_MF_SELECT_MFCLK_DIV_Pos 8UL 399 #define SRSS_CLK_MF_SELECT_MFCLK_DIV_Msk 0xFF00UL 400 #define SRSS_CLK_MF_SELECT_ENABLE_Pos 31UL 401 #define SRSS_CLK_MF_SELECT_ENABLE_Msk 0x80000000UL 402 /* SRSS.CLK_MFO_CONFIG */ 403 #define SRSS_CLK_MFO_CONFIG_DPSLP_ENABLE_Pos 30UL 404 #define SRSS_CLK_MFO_CONFIG_DPSLP_ENABLE_Msk 0x40000000UL 405 #define SRSS_CLK_MFO_CONFIG_ENABLE_Pos 31UL 406 #define SRSS_CLK_MFO_CONFIG_ENABLE_Msk 0x80000000UL 407 /* SRSS.CLK_FLL_CONFIG */ 408 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos 0UL 409 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk 0x3FFFFUL 410 #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos 24UL 411 #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk 0x1000000UL 412 #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Pos 31UL 413 #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk 0x80000000UL 414 /* SRSS.CLK_FLL_CONFIG2 */ 415 #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos 0UL 416 #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk 0x1FFFUL 417 #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Pos 16UL 418 #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk 0x1FF0000UL 419 /* SRSS.CLK_FLL_CONFIG3 */ 420 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos 0UL 421 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk 0xFUL 422 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos 4UL 423 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk 0xF0UL 424 #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos 8UL 425 #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk 0x1FFF00UL 426 #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Pos 28UL 427 #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Msk 0x30000000UL 428 /* SRSS.CLK_FLL_CONFIG4 */ 429 #define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Pos 0UL 430 #define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Msk 0xFFUL 431 #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Pos 8UL 432 #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Msk 0x700UL 433 #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos 16UL 434 #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk 0x1FF0000UL 435 #define SRSS_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Pos 30UL 436 #define SRSS_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Msk 0x40000000UL 437 #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Pos 31UL 438 #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk 0x80000000UL 439 /* SRSS.CLK_FLL_STATUS */ 440 #define SRSS_CLK_FLL_STATUS_LOCKED_Pos 0UL 441 #define SRSS_CLK_FLL_STATUS_LOCKED_Msk 0x1UL 442 #define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Pos 1UL 443 #define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 444 #define SRSS_CLK_FLL_STATUS_CCO_READY_Pos 2UL 445 #define SRSS_CLK_FLL_STATUS_CCO_READY_Msk 0x4UL 446 /* SRSS.CLK_PLL_CONFIG */ 447 #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos 0UL 448 #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk 0x7FUL 449 #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Pos 8UL 450 #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Msk 0x1F00UL 451 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos 16UL 452 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Msk 0x1F0000UL 453 #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Pos 27UL 454 #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Msk 0x8000000UL 455 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos 28UL 456 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk 0x30000000UL 457 #define SRSS_CLK_PLL_CONFIG_ENABLE_Pos 31UL 458 #define SRSS_CLK_PLL_CONFIG_ENABLE_Msk 0x80000000UL 459 /* SRSS.CLK_PLL_STATUS */ 460 #define SRSS_CLK_PLL_STATUS_LOCKED_Pos 0UL 461 #define SRSS_CLK_PLL_STATUS_LOCKED_Msk 0x1UL 462 #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos 1UL 463 #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 464 /* SRSS.SRSS_INTR */ 465 #define SRSS_SRSS_INTR_WDT_MATCH_Pos 0UL 466 #define SRSS_SRSS_INTR_WDT_MATCH_Msk 0x1UL 467 #define SRSS_SRSS_INTR_HVLVD1_Pos 1UL 468 #define SRSS_SRSS_INTR_HVLVD1_Msk 0x2UL 469 #define SRSS_SRSS_INTR_CLK_CAL_Pos 5UL 470 #define SRSS_SRSS_INTR_CLK_CAL_Msk 0x20UL 471 /* SRSS.SRSS_INTR_SET */ 472 #define SRSS_SRSS_INTR_SET_WDT_MATCH_Pos 0UL 473 #define SRSS_SRSS_INTR_SET_WDT_MATCH_Msk 0x1UL 474 #define SRSS_SRSS_INTR_SET_HVLVD1_Pos 1UL 475 #define SRSS_SRSS_INTR_SET_HVLVD1_Msk 0x2UL 476 #define SRSS_SRSS_INTR_SET_CLK_CAL_Pos 5UL 477 #define SRSS_SRSS_INTR_SET_CLK_CAL_Msk 0x20UL 478 /* SRSS.SRSS_INTR_MASK */ 479 #define SRSS_SRSS_INTR_MASK_WDT_MATCH_Pos 0UL 480 #define SRSS_SRSS_INTR_MASK_WDT_MATCH_Msk 0x1UL 481 #define SRSS_SRSS_INTR_MASK_HVLVD1_Pos 1UL 482 #define SRSS_SRSS_INTR_MASK_HVLVD1_Msk 0x2UL 483 #define SRSS_SRSS_INTR_MASK_CLK_CAL_Pos 5UL 484 #define SRSS_SRSS_INTR_MASK_CLK_CAL_Msk 0x20UL 485 /* SRSS.SRSS_INTR_MASKED */ 486 #define SRSS_SRSS_INTR_MASKED_WDT_MATCH_Pos 0UL 487 #define SRSS_SRSS_INTR_MASKED_WDT_MATCH_Msk 0x1UL 488 #define SRSS_SRSS_INTR_MASKED_HVLVD1_Pos 1UL 489 #define SRSS_SRSS_INTR_MASKED_HVLVD1_Msk 0x2UL 490 #define SRSS_SRSS_INTR_MASKED_CLK_CAL_Pos 5UL 491 #define SRSS_SRSS_INTR_MASKED_CLK_CAL_Msk 0x20UL 492 /* SRSS.SRSS_INTR_CFG */ 493 #define SRSS_SRSS_INTR_CFG_HVLVD1_EDGE_SEL_Pos 0UL 494 #define SRSS_SRSS_INTR_CFG_HVLVD1_EDGE_SEL_Msk 0x3UL 495 /* SRSS.RES_CAUSE */ 496 #define SRSS_RES_CAUSE_RESET_WDT_Pos 0UL 497 #define SRSS_RES_CAUSE_RESET_WDT_Msk 0x1UL 498 #define SRSS_RES_CAUSE_RESET_ACT_FAULT_Pos 1UL 499 #define SRSS_RES_CAUSE_RESET_ACT_FAULT_Msk 0x2UL 500 #define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Pos 2UL 501 #define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Msk 0x4UL 502 #define SRSS_RES_CAUSE_RESET_CSV_WCO_LOSS_Pos 3UL 503 #define SRSS_RES_CAUSE_RESET_CSV_WCO_LOSS_Msk 0x8UL 504 #define SRSS_RES_CAUSE_RESET_SOFT_Pos 4UL 505 #define SRSS_RES_CAUSE_RESET_SOFT_Msk 0x10UL 506 #define SRSS_RES_CAUSE_RESET_MCWDT0_Pos 5UL 507 #define SRSS_RES_CAUSE_RESET_MCWDT0_Msk 0x20UL 508 #define SRSS_RES_CAUSE_RESET_MCWDT1_Pos 6UL 509 #define SRSS_RES_CAUSE_RESET_MCWDT1_Msk 0x40UL 510 #define SRSS_RES_CAUSE_RESET_MCWDT2_Pos 7UL 511 #define SRSS_RES_CAUSE_RESET_MCWDT2_Msk 0x80UL 512 #define SRSS_RES_CAUSE_RESET_MCWDT3_Pos 8UL 513 #define SRSS_RES_CAUSE_RESET_MCWDT3_Msk 0x100UL 514 /* SRSS.RES_CAUSE2 */ 515 #define SRSS_RES_CAUSE2_RESET_CSV_HF_LOSS_Pos 0UL 516 #define SRSS_RES_CAUSE2_RESET_CSV_HF_LOSS_Msk 0xFFFFUL 517 #define SRSS_RES_CAUSE2_RESET_CSV_HF_FREQ_Pos 16UL 518 #define SRSS_RES_CAUSE2_RESET_CSV_HF_FREQ_Msk 0xFFFF0000UL 519 /* SRSS.PWR_TRIM_REF_CTL */ 520 #define SRSS_PWR_TRIM_REF_CTL_ACT_REF_TCTRIM_Pos 0UL 521 #define SRSS_PWR_TRIM_REF_CTL_ACT_REF_TCTRIM_Msk 0xFUL 522 #define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ITRIM_Pos 4UL 523 #define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ITRIM_Msk 0xF0UL 524 #define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ABSTRIM_Pos 8UL 525 #define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ABSTRIM_Msk 0x1F00UL 526 #define SRSS_PWR_TRIM_REF_CTL_ACT_REF_IBOOST_Pos 14UL 527 #define SRSS_PWR_TRIM_REF_CTL_ACT_REF_IBOOST_Msk 0x4000UL 528 #define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_TCTRIM_Pos 16UL 529 #define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_TCTRIM_Msk 0xF0000UL 530 #define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ABSTRIM_Pos 20UL 531 #define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ABSTRIM_Msk 0x1F00000UL 532 #define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ITRIM_Pos 28UL 533 #define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ITRIM_Msk 0xF0000000UL 534 /* SRSS.PWR_TRIM_BODOVP_CTL */ 535 #define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_TRIPSEL_Pos 0UL 536 #define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_TRIPSEL_Msk 0x7UL 537 #define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_OFSTRIM_Pos 4UL 538 #define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_OFSTRIM_Msk 0x70UL 539 #define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_ITRIM_Pos 7UL 540 #define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_ITRIM_Msk 0x380UL 541 #define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_TRIPSEL_Pos 10UL 542 #define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_TRIPSEL_Msk 0x1C00UL 543 #define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_OFSTRIM_Pos 14UL 544 #define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_OFSTRIM_Msk 0x1C000UL 545 #define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_ITRIM_Pos 17UL 546 #define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_ITRIM_Msk 0xE0000UL 547 /* SRSS.CLK_TRIM_CCO_CTL */ 548 #define SRSS_CLK_TRIM_CCO_CTL_CCO_RCSTRIM_Pos 0UL 549 #define SRSS_CLK_TRIM_CCO_CTL_CCO_RCSTRIM_Msk 0x3FUL 550 #define SRSS_CLK_TRIM_CCO_CTL_CCO_STABLE_CNT_Pos 24UL 551 #define SRSS_CLK_TRIM_CCO_CTL_CCO_STABLE_CNT_Msk 0x3F000000UL 552 #define SRSS_CLK_TRIM_CCO_CTL_ENABLE_CNT_Pos 31UL 553 #define SRSS_CLK_TRIM_CCO_CTL_ENABLE_CNT_Msk 0x80000000UL 554 /* SRSS.CLK_TRIM_CCO_CTL2 */ 555 #define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM1_Pos 0UL 556 #define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM1_Msk 0x1FUL 557 #define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM2_Pos 5UL 558 #define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM2_Msk 0x3E0UL 559 #define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM3_Pos 10UL 560 #define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM3_Msk 0x7C00UL 561 #define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM4_Pos 15UL 562 #define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM4_Msk 0xF8000UL 563 #define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM5_Pos 20UL 564 #define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM5_Msk 0x1F00000UL 565 /* SRSS.PWR_TRIM_WAKE_CTL */ 566 #define SRSS_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Pos 0UL 567 #define SRSS_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Msk 0xFFUL 568 /* SRSS.PWR_TRIM_LVD_CTL */ 569 #define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_OFSTRIM_Pos 0UL 570 #define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_OFSTRIM_Msk 0x7UL 571 #define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_ITRIM_Pos 4UL 572 #define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_ITRIM_Msk 0x70UL 573 /* SRSS.CLK_TRIM_ILO_CTL */ 574 #define SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM_Pos 0UL 575 #define SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM_Msk 0x3FUL 576 /* SRSS.PWR_TRIM_PWRSYS_CTL */ 577 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Pos 0UL 578 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Msk 0x1FUL 579 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Pos 30UL 580 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Msk 0xC0000000UL 581 /* SRSS.CLK_TRIM_ECO_CTL */ 582 #define SRSS_CLK_TRIM_ECO_CTL_WDTRIM_Pos 0UL 583 #define SRSS_CLK_TRIM_ECO_CTL_WDTRIM_Msk 0x7UL 584 #define SRSS_CLK_TRIM_ECO_CTL_ATRIM_Pos 4UL 585 #define SRSS_CLK_TRIM_ECO_CTL_ATRIM_Msk 0xF0UL 586 #define SRSS_CLK_TRIM_ECO_CTL_FTRIM_Pos 8UL 587 #define SRSS_CLK_TRIM_ECO_CTL_FTRIM_Msk 0x300UL 588 #define SRSS_CLK_TRIM_ECO_CTL_RTRIM_Pos 10UL 589 #define SRSS_CLK_TRIM_ECO_CTL_RTRIM_Msk 0xC00UL 590 #define SRSS_CLK_TRIM_ECO_CTL_GTRIM_Pos 12UL 591 #define SRSS_CLK_TRIM_ECO_CTL_GTRIM_Msk 0x3000UL 592 #define SRSS_CLK_TRIM_ECO_CTL_ITRIM_Pos 16UL 593 #define SRSS_CLK_TRIM_ECO_CTL_ITRIM_Msk 0x3F0000UL 594 /* SRSS.CLK_TRIM_PILO_CTL */ 595 #define SRSS_CLK_TRIM_PILO_CTL_PILO_CFREQ_Pos 0UL 596 #define SRSS_CLK_TRIM_PILO_CTL_PILO_CFREQ_Msk 0x3FUL 597 #define SRSS_CLK_TRIM_PILO_CTL_PILO_OSC_TRIM_Pos 12UL 598 #define SRSS_CLK_TRIM_PILO_CTL_PILO_OSC_TRIM_Msk 0x7000UL 599 #define SRSS_CLK_TRIM_PILO_CTL_PILO_COMP_TRIM_Pos 16UL 600 #define SRSS_CLK_TRIM_PILO_CTL_PILO_COMP_TRIM_Msk 0x30000UL 601 #define SRSS_CLK_TRIM_PILO_CTL_PILO_NBIAS_TRIM_Pos 18UL 602 #define SRSS_CLK_TRIM_PILO_CTL_PILO_NBIAS_TRIM_Msk 0xC0000UL 603 #define SRSS_CLK_TRIM_PILO_CTL_PILO_RES_TRIM_Pos 20UL 604 #define SRSS_CLK_TRIM_PILO_CTL_PILO_RES_TRIM_Msk 0x1F00000UL 605 #define SRSS_CLK_TRIM_PILO_CTL_PILO_ISLOPE_TRIM_Pos 26UL 606 #define SRSS_CLK_TRIM_PILO_CTL_PILO_ISLOPE_TRIM_Msk 0xC000000UL 607 #define SRSS_CLK_TRIM_PILO_CTL_PILO_VTDIFF_TRIM_Pos 28UL 608 #define SRSS_CLK_TRIM_PILO_CTL_PILO_VTDIFF_TRIM_Msk 0x70000000UL 609 /* SRSS.CLK_TRIM_PILO_CTL2 */ 610 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_VREF_TRIM_Pos 0UL 611 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_VREF_TRIM_Msk 0xFFUL 612 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREFBM_TRIM_Pos 8UL 613 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREFBM_TRIM_Msk 0x1F00UL 614 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREF_TRIM_Pos 16UL 615 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREF_TRIM_Msk 0xFF0000UL 616 /* SRSS.CLK_TRIM_PILO_CTL3 */ 617 #define SRSS_CLK_TRIM_PILO_CTL3_PILO_ENGOPT_Pos 0UL 618 #define SRSS_CLK_TRIM_PILO_CTL3_PILO_ENGOPT_Msk 0xFFFFUL 619 620 621 #endif /* _CYIP_SRSS_H_ */ 622 623 624 /* [] END OF FILE */ 625
