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Searched refs:SMIF_DEVICE_ADDR_CTL_DIV2_Msk (Results 1 – 4 of 4) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_smif.h144 #define SMIF_DEVICE_ADDR_CTL_DIV2_Msk 0x100UL macro
/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/include/
Dcy_smif_memslot.h1363 … ((0UL != memCfg->dualQuadSlots)? SMIF_DEVICE_ADDR_CTL_DIV2_Msk: 0UL); in XipRegInit()
1478 … ((0UL != memCfg->dualQuadSlots)? SMIF_DEVICE_ADDR_CTL_DIV2_Msk: 0UL); in XipRegInit()
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_smif_v2.h175 #define SMIF_DEVICE_ADDR_CTL_DIV2_Msk 0x100UL macro
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/ip/
Dcyip_smif_v3.h278 #define SMIF_DEVICE_ADDR_CTL_DIV2_Msk 0x100UL macro