1 /* 2 * Copyright 2023, Cypress Semiconductor Corporation (an Infineon company) 3 * SPDX-License-Identifier: Apache-2.0 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 #ifndef INCLUDED_WHD_SDIO_H_ 19 #define INCLUDED_WHD_SDIO_H_ 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 /****************************************************** 26 * SDIO Constants 27 ******************************************************/ 28 /* CurrentSdiodProgGuide r23 */ 29 30 /* Base registers */ 31 #define SDIO_CORE(wd) ( (uint32_t)(GET_C_VAR(wd, SDIOD_CORE_BASE_ADDRESS) + 0x00) ) 32 #define SDIO_INT_STATUS(wd) ( (uint32_t)(GET_C_VAR(wd, SDIOD_CORE_BASE_ADDRESS) + 0x20) ) 33 #define SDIO_TO_SB_MAILBOX(wd) ( (uint32_t)(GET_C_VAR(wd, SDIOD_CORE_BASE_ADDRESS) + 0x40) ) 34 #define SDIO_TO_SB_MAILBOX_DATA(wd) ( (uint32_t)(GET_C_VAR(wd, SDIOD_CORE_BASE_ADDRESS) + 0x48) ) 35 #define SDIO_TO_HOST_MAILBOX_DATA(wd) ( (uint32_t)(GET_C_VAR(wd, SDIOD_CORE_BASE_ADDRESS) + 0x4C) ) 36 #define SDIO_INT_HOST_MASK(wd) ( (uint32_t)(GET_C_VAR(wd, SDIOD_CORE_BASE_ADDRESS) + 0x24) ) 37 #define SDIO_FUNCTION_INT_MASK(wd) ( (uint32_t)(GET_C_VAR(wd, SDIOD_CORE_BASE_ADDRESS) + 0x34) ) 38 39 /* SDIO Function 0 (SDIO Bus) register addresses */ 40 41 /* SDIO Device CCCR (Card Common Control Register) offsets */ 42 /* CCCR accesses do not require backpane clock */ 43 #define SDIOD_CCCR_REV ( (uint32_t)0x00 ) /* CCCR/SDIO Revision */ 44 #define SDIOD_CCCR_SDREV ( (uint32_t)0x01 ) /* SD Revision */ 45 #define SDIOD_CCCR_IOEN ( (uint32_t)0x02 ) /* I/O Enable */ 46 #define SDIOD_CCCR_IORDY ( (uint32_t)0x03 ) /* I/O Ready */ 47 #define SDIOD_CCCR_INTEN ( (uint32_t)0x04 ) /* Interrupt Enable */ 48 #define SDIOD_CCCR_INTPEND ( (uint32_t)0x05 ) /* Interrupt Pending */ 49 #define SDIOD_CCCR_IOABORT ( (uint32_t)0x06 ) /* I/O Abort */ 50 #define SDIOD_CCCR_BICTRL ( (uint32_t)0x07 ) /* Bus Interface control */ 51 #define SDIOD_CCCR_CAPABLITIES ( (uint32_t)0x08 ) /* Card Capabilities */ 52 #define SDIOD_CCCR_CISPTR_0 ( (uint32_t)0x09 ) /* Common CIS Base Address Pointer Register 0 (LSB) */ 53 #define SDIOD_CCCR_CISPTR_1 ( (uint32_t)0x0A ) /* Common CIS Base Address Pointer Register 1 */ 54 #define SDIOD_CCCR_CISPTR_2 ( (uint32_t)0x0B ) /* Common CIS Base Address Pointer Register 2 (MSB - only bit 1 valid)*/ 55 #define SDIOD_CCCR_BUSSUSP ( (uint32_t)0x0C ) /* Bus Suspend. Valid only if SBS is set */ 56 #define SDIOD_CCCR_FUNCSEL ( (uint32_t)0x0D ) /* Function Select. Valid only if SBS is set */ 57 #define SDIOD_CCCR_EXECFLAGS ( (uint32_t)0x0E ) /* Exec Flags. Valid only if SBS is set */ 58 #define SDIOD_CCCR_RDYFLAGS ( (uint32_t)0x0F ) /* Ready Flags. Valid only if SBS is set */ 59 #define SDIOD_CCCR_BLKSIZE_0 ( (uint32_t)0x10 ) /* Function 0 (Bus) SDIO Block Size Register 0 (LSB) */ 60 #define SDIOD_CCCR_BLKSIZE_1 ( (uint32_t)0x11 ) /* Function 0 (Bus) SDIO Block Size Register 1 (MSB) */ 61 #define SDIOD_CCCR_POWER_CONTROL ( (uint32_t)0x12 ) /* Power Control */ 62 #define SDIOD_CCCR_SPEED_CONTROL ( (uint32_t)0x13 ) /* Bus Speed Select (control device entry into high-speed clocking mode) */ 63 #define SDIOD_CCCR_UHS_I ( (uint32_t)0x14 ) /* UHS-I Support */ 64 #define SDIOD_CCCR_DRIVE ( (uint32_t)0x15 ) /* Drive Strength */ 65 #define SDIOD_CCCR_INTEXT ( (uint32_t)0x16 ) /* Interrupt Extension */ 66 #define SDIOD_CCCR_BRCM_CARDCAP ( (uint32_t)0xF0 ) /* Brcm Card Capability */ 67 #define SDIOD_SEP_INT_CTL ( (uint32_t)0xF2 ) /* Separate Interrupt Control*/ 68 #define SDIOD_CCCR_F1INFO ( (uint32_t)0x100 ) /* Function 1 (Backplane) Info */ 69 #define SDIOD_CCCR_F1HP ( (uint32_t)0x102 ) /* Function 1 (Backplane) High Power */ 70 #define SDIOD_CCCR_F1CISPTR_0 ( (uint32_t)0x109 ) /* Function 1 (Backplane) CIS Base Address Pointer Register 0 (LSB) */ 71 #define SDIOD_CCCR_F1CISPTR_1 ( (uint32_t)0x10A ) /* Function 1 (Backplane) CIS Base Address Pointer Register 1 */ 72 #define SDIOD_CCCR_F1CISPTR_2 ( (uint32_t)0x10B ) /* Function 1 (Backplane) CIS Base Address Pointer Register 2 (MSB - only bit 1 valid) */ 73 #define SDIOD_CCCR_F1BLKSIZE_0 ( (uint32_t)0x110 ) /* Function 1 (Backplane) SDIO Block Size Register 0 (LSB) */ 74 #define SDIOD_CCCR_F1BLKSIZE_1 ( (uint32_t)0x111 ) /* Function 1 (Backplane) SDIO Block Size Register 1 (MSB) */ 75 #define SDIOD_CCCR_F2INFO ( (uint32_t)0x200 ) /* Function 2 (WLAN Data FIFO) Info */ 76 #define SDIOD_CCCR_F2HP ( (uint32_t)0x202 ) /* Function 2 (WLAN Data FIFO) High Power */ 77 #define SDIOD_CCCR_F2CISPTR_0 ( (uint32_t)0x209 ) /* Function 2 (WLAN Data FIFO) CIS Base Address Pointer Register 0 (LSB) */ 78 #define SDIOD_CCCR_F2CISPTR_1 ( (uint32_t)0x20A ) /* Function 2 (WLAN Data FIFO) CIS Base Address Pointer Register 1 */ 79 #define SDIOD_CCCR_F2CISPTR_2 ( (uint32_t)0x20B ) /* Function 2 (WLAN Data FIFO) CIS Base Address Pointer Register 2 (MSB - only bit 1 valid) */ 80 #define SDIOD_CCCR_F2BLKSIZE_0 ( (uint32_t)0x210 ) /* Function 2 (WLAN Data FIFO) SDIO Block Size Register 0 (LSB) */ 81 #define SDIOD_CCCR_F2BLKSIZE_1 ( (uint32_t)0x211 ) /* Function 2 (WLAN Data FIFO) SDIO Block Size Register 1 (MSB) */ 82 #define SDIOD_CCCR_F3INFO ( (uint32_t)0x300 ) /* Function 3 (Bluetooth Data FIFO) Info */ 83 #define SDIOD_CCCR_F3HP ( (uint32_t)0x302 ) /* Function 3 (Bluetooth Data FIFO) High Power */ 84 #define SDIOD_CCCR_F3CISPTR_0 ( (uint32_t)0x309 ) /* Function 3 (Bluetooth Data FIFO) CIS Base Address Pointer Register 0 (LSB) */ 85 #define SDIOD_CCCR_F3CISPTR_1 ( (uint32_t)0x30A ) /* Function 3 (Bluetooth Data FIFO) CIS Base Address Pointer Register 1 */ 86 #define SDIOD_CCCR_F3CISPTR_2 ( (uint32_t)0x30B ) /* Function 3 (Bluetooth Data FIFO) CIS Base Address Pointer Register 2 (MSB - only bit 1 valid) */ 87 #define SDIOD_CCCR_F3BLKSIZE_0 ( (uint32_t)0x310 ) /* Function 3 (Bluetooth Data FIFO) SDIO Block Size Register 0 (LSB) */ 88 #define SDIOD_CCCR_F3BLKSIZE_1 ( (uint32_t)0x311 ) /* Function 3 (Bluetooth Data FIFO) SDIO Block Size Register 1 (MSB) */ 89 90 91 /* SDIO Function 1 (Backplane) register addresses */ 92 /* Addresses 0x00000000 - 0x0000FFFF are directly access the backplane 93 * throught the backplane window. Addresses above 0x0000FFFF are 94 * registers relating to backplane access, and do not require a backpane 95 * clock to access them 96 */ 97 #define SDIO_GPIO_SELECT ( (uint32_t)0x10005 ) 98 #define SDIO_GPIO_OUTPUT ( (uint32_t)0x10006 ) 99 #define SDIO_GPIO_ENABLE ( (uint32_t)0x10007 ) 100 #define SDIO_FUNCTION2_WATERMARK ( (uint32_t)0x10008 ) 101 #define SDIO_DEVICE_CONTROL ( (uint32_t)0x10009 ) 102 #define SDIO_BACKPLANE_ADDRESS_LOW ( (uint32_t)0x1000A ) 103 #define SDIO_BACKPLANE_ADDRESS_MID ( (uint32_t)0x1000B ) 104 #define SDIO_BACKPLANE_ADDRESS_HIGH ( (uint32_t)0x1000C ) 105 #define SDIO_FRAME_CONTROL ( (uint32_t)0x1000D ) 106 #define SDIO_CHIP_CLOCK_CSR ( (uint32_t)0x1000E ) 107 #define SDIO_PULL_UP ( (uint32_t)0x1000F ) 108 #define SDIO_READ_FRAME_BC_LOW ( (uint32_t)0x1001B ) 109 #define SDIO_READ_FRAME_BC_HIGH ( (uint32_t)0x1001C ) 110 #define SDIO_WAKEUP_CTRL ( (uint32_t)0x1001E ) 111 #define SDIO_SLEEP_CSR ( (uint32_t)0x1001F ) 112 #define I_HMB_SW_MASK ( (uint32_t)0x000000F0 ) 113 #define I_HMB_FRAME_IND (1 << 6) 114 #define I_HMB_HOST_INT (1 << 7) 115 #define I_HMB_FC_CHANGE (1 << 5) 116 #define FRAME_AVAILABLE_MASK I_HMB_SW_MASK 117 118 /****************************************************** 119 * Bit Masks 120 ******************************************************/ 121 122 /* SDIOD_CCCR_REV Bits */ 123 #define SDIO_REV_SDIOID_MASK ( (uint32_t)0xF0 ) /* SDIO spec revision number */ 124 #define SDIO_REV_CCCRID_MASK ( (uint32_t)0x0F ) /* CCCR format version number */ 125 126 /* SDIOD_CCCR_SDREV Bits */ 127 #define SD_REV_PHY_MASK ( (uint32_t)0x0F ) /* SD format version number */ 128 129 /* SDIOD_CCCR_IOEN Bits */ 130 #define SDIO_FUNC_ENABLE_1 ( (uint32_t)0x02 ) /* function 1 I/O enable */ 131 #define SDIO_FUNC_ENABLE_2 ( (uint32_t)0x04 ) /* function 2 I/O enable */ 132 #define SDIO_FUNC_ENABLE_3 ( (uint32_t)0x08 ) /* function 3 I/O enable */ 133 134 /* SDIOD_CCCR_IORDY Bits */ 135 #define SDIO_FUNC_READY_1 ( (uint32_t)0x02 ) /* function 1 I/O ready */ 136 #define SDIO_FUNC_READY_2 ( (uint32_t)0x04 ) /* function 2 I/O ready */ 137 #define SDIO_FUNC_READY_3 ( (uint32_t)0x08 ) /* function 3 I/O ready */ 138 139 /* SDIOD_CCCR_INTEN Bits */ 140 #define INTR_CTL_MASTER_EN ( (uint32_t)0x01 ) /* interrupt enable master */ 141 #define INTR_CTL_FUNC1_EN ( (uint32_t)0x02 ) /* interrupt enable for function 1 */ 142 #define INTR_CTL_FUNC2_EN ( (uint32_t)0x04 ) /* interrupt enable for function 2 */ 143 144 /* SDIOD_SEP_INT_CTL Bits */ 145 #define SEP_INTR_CTL_MASK ( (uint32_t)0x01 ) /* out-of-band interrupt mask */ 146 #define SEP_INTR_CTL_EN ( (uint32_t)0x02 ) /* out-of-band interrupt output enable */ 147 #define SEP_INTR_CTL_POL ( (uint32_t)0x04 ) /* out-of-band interrupt polarity */ 148 149 /* SDIOD_CCCR_INTPEND Bits */ 150 #define INTR_STATUS_FUNC1 ( (uint32_t)0x02 ) /* interrupt pending for function 1 */ 151 #define INTR_STATUS_FUNC2 ( (uint32_t)0x04 ) /* interrupt pending for function 2 */ 152 #define INTR_STATUS_FUNC3 ( (uint32_t)0x08 ) /* interrupt pending for function 3 */ 153 154 /* SDIOD_CCCR_IOABORT Bits */ 155 #define IO_ABORT_RESET_ALL ( (uint32_t)0x08 ) /* I/O card reset */ 156 #define IO_ABORT_FUNC_MASK ( (uint32_t)0x07 ) /* abort selction: function x */ 157 158 /* SDIOD_CCCR_BICTRL Bits */ 159 #define BUS_CARD_DETECT_DIS ( (uint32_t)0x80 ) /* Card Detect disable */ 160 #define BUS_SPI_CONT_INTR_CAP ( (uint32_t)0x40 ) /* support continuous SPI interrupt */ 161 #define BUS_SPI_CONT_INTR_EN ( (uint32_t)0x20 ) /* continuous SPI interrupt enable */ 162 #define BUS_SD_DATA_WIDTH_MASK ( (uint32_t)0x03 ) /* bus width mask */ 163 #define BUS_SD_DATA_WIDTH_4BIT ( (uint32_t)0x02 ) /* bus width 4-bit mode */ 164 #define BUS_SD_DATA_WIDTH_1BIT ( (uint32_t)0x00 ) /* bus width 1-bit mode */ 165 166 /* SDIOD_CCCR_CAPABLITIES Bits */ 167 #define SDIO_CAP_4BLS ( (uint32_t)0x80 ) /* 4-bit support for low speed card */ 168 #define SDIO_CAP_LSC ( (uint32_t)0x40 ) /* low speed card */ 169 #define SDIO_CAP_E4MI ( (uint32_t)0x20 ) /* enable interrupt between block of data in 4-bit mode */ 170 #define SDIO_CAP_S4MI ( (uint32_t)0x10 ) /* support interrupt between block of data in 4-bit mode */ 171 #define SDIO_CAP_SBS ( (uint32_t)0x08 ) /* support suspend/resume */ 172 #define SDIO_CAP_SRW ( (uint32_t)0x04 ) /* support read wait */ 173 #define SDIO_CAP_SMB ( (uint32_t)0x02 ) /* support multi-block transfer */ 174 #define SDIO_CAP_SDC ( (uint32_t)0x01 ) /* Support Direct commands during multi-byte transfer */ 175 176 /* SDIOD_CCCR_POWER_CONTROL Bits */ 177 #define SDIO_POWER_SMPC ( (uint32_t)0x01 ) /* supports master power control (RO) */ 178 #define SDIO_POWER_EMPC ( (uint32_t)0x02 ) /* enable master power control (allow > 200mA) (RW) */ 179 180 /* SDIOD_CCCR_SPEED_CONTROL Bits */ 181 #define SDIO_SPEED_SHS ( (uint32_t)0x01 ) /* supports high-speed [clocking] mode (RO) */ 182 #define SDIO_SPEED_EHS ( (uint32_t)0x02 ) /* enable high-speed [clocking] mode (RW) */ 183 184 /* SDIOD_CCCR_BRCM_CARDCAP Bits */ 185 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_SUPPORT ( (uint32_t)0x02 ) /* Supports CMD14 */ 186 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_EXT ( (uint32_t)0x04 ) /* CMD14 is allowed in FSM command state */ 187 #define SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC ( (uint32_t)0x08 ) /* sdiod_aos does not decode any command */ 188 189 /* SDIO_FUNCTION_INT_MASK Bits*/ 190 #define SDIO_FUNC_MASK_F1 ( (uint32_t)0x01 ) /* interrupt mask enable for function 1 */ 191 #define SDIO_FUNC_MASK_F2 ( (uint32_t)0x02 ) /* interrupt mask enable for function 2 */ 192 193 /* SDIO_DEVICE_CONTROL Bits */ 194 #define SDIO_DATA_PAD_ISO ( (uint32_t)0x08 ) /* isolate internal SDIO data bus signals */ 195 196 /* SDIO_CHIP_CLOCK_CSR Bits */ 197 #define SBSDIO_FORCE_ALP ( (uint32_t)0x01 ) /* Force ALP request to backplane */ 198 #define SBSDIO_FORCE_HT ( (uint32_t)0x02 ) /* Force HT request to backplane */ 199 #define SBSDIO_FORCE_ILP ( (uint32_t)0x04 ) /* Force ILP request to backplane */ 200 #define SBSDIO_ALP_AVAIL_REQ ( (uint32_t)0x08 ) /* Make ALP ready (power up xtal) */ 201 #define SBSDIO_HT_AVAIL_REQ ( (uint32_t)0x10 ) /* Make HT ready (power up PLL) */ 202 #define SBSDIO_FORCE_HW_CLKREQ_OFF ( (uint32_t)0x20 ) /* Squelch clock requests from HW */ 203 #define SBSDIO_ALP_AVAIL ( (uint32_t)0x40 ) /* Status: ALP is ready */ 204 #define SBSDIO_HT_AVAIL ( (uint32_t)0x80 ) /* Status: HT is ready */ 205 #define SBSDIO_Rev8_HT_AVAIL ( (uint32_t)0x40 ) 206 #define SBSDIO_Rev8_ALP_AVAIL ( (uint32_t)0x80 ) 207 208 /* SDIO_FRAME_CONTROL Bits */ 209 #define SFC_RF_TERM ( (uint32_t)(1 << 0) ) /* Read Frame Terminate */ 210 #define SFC_WF_TERM ( (uint32_t)(1 << 1) ) /* Write Frame Terminate */ 211 #define SFC_CRC4WOOS ( (uint32_t)(1 << 2) ) /* HW reports CRC error for write out of sync */ 212 #define SFC_ABORTALL ( (uint32_t)(1 << 3) ) /* Abort cancels all in-progress frames */ 213 214 /* SDIO_TO_SB_MAILBOX bits corresponding to intstatus bits */ 215 #define SMB_NAK ( (uint32_t)(1 << 0) ) /* To SB Mailbox Frame NAK */ 216 #define SMB_INT_ACK ( (uint32_t)(1 << 1) ) /* To SB Mailbox Host Interrupt ACK */ 217 #define SMB_USE_OOB ( (uint32_t)(1 << 2) ) /* To SB Mailbox Use OOB Wakeup */ 218 #define SMB_DEV_INT ( (uint32_t)(1 << 3) ) /* To SB Mailbox Miscellaneous Interrupt */ 219 220 /* SDIO_WAKEUP_CTRL bits */ 221 #define SBSDIO_WCTRL_WAKE_TILL_ALP_AVAIL ( (uint32_t)(1 << 0) ) /* WakeTillAlpAvail bit */ 222 #define SBSDIO_WCTRL_WAKE_TILL_HT_AVAIL ( (uint32_t)(1 << 1) ) /* WakeTillHTAvail bit */ 223 224 /* SDIO_SLEEP_CSR bits */ 225 #define SBSDIO_SLPCSR_KEEP_SDIO_ON ( (uint32_t)(1 << 0) ) /* KeepSdioOn bit */ 226 #define SBSDIO_SLPCSR_DEVICE_ON ( (uint32_t)(1 << 1) ) /* DeviceOn bit */ 227 228 /* To hostmail box data */ 229 #define I_HMB_DATA_NAKHANDLED 0x0001 /* retransmit NAK'd frame */ 230 #define I_HMB_DATA_DEVREADY 0x0002 /* talk to host after enable */ 231 #define I_HMB_DATA_FC 0x0004 /* per prio flowcontrol update flag */ 232 #define I_HMB_DATA_FWREADY 0x0008 /* fw ready for protocol activity */ 233 #define I_HMB_DATA_FWHALT 0x0010 /* firmware halted */ 234 235 #ifdef __cplusplus 236 } /* extern "C" */ 237 #endif 238 239 #endif /* ifndef INCLUDED_WHD_SDIO_H_ */ 240 241
