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Searched refs:REG_I2S_CTL (Results 1 – 4 of 4) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/source/
Dcy_i2s.c67 REG_I2S_CTL(base) = 0UL; /* Disable TX/RX sub-blocks before clock changing */ in Cy_I2S_Init()
166 REG_I2S_CTL(base) |= I2S_CTL_TX_ENABLED_Msk; in Cy_I2S_Init()
171 REG_I2S_CTL(base) |= I2S_CTL_RX_ENABLED_Msk; in Cy_I2S_Init()
215 REG_I2S_CTL(base) = 0UL; in Cy_I2S_DeInit()
/hal_infineon-3.7.0/mtb-hal-cat1/source/
Dcyhal_audio_common.c51 #define REG_I2S_CTL(base) I2S_CTL(base) macro
1102 ? (0u != (REG_I2S_CTL(obj->base) & I2S_CTL_TX_ENABLED_Msk)) in _cyhal_audioss_is_direction_enabled()
1103 : (0u != (REG_I2S_CTL(obj->base) & I2S_CTL_RX_ENABLED_Msk)); in _cyhal_audioss_is_direction_enabled()
1581 pdl_config->txEnabled = _FLD2BOOL(I2S_CTL_TX_ENABLED, REG_I2S_CTL(base)); in _cyhal_audioss_reconstruct_pdl_config()
1582 pdl_config->rxEnabled = _FLD2BOOL(I2S_CTL_RX_ENABLED, REG_I2S_CTL(base)); in _cyhal_audioss_reconstruct_pdl_config()
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h931 #define REG_I2S_CTL(base) (((I2S_V1_Type*)(base))->CTL) macro
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h1606 #define REG_I2S_CTL(base) (((I2S_Type*)(base))->CTL) macro