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Searched refs:PCLK_TCPWM1_CLOCKS0 (Results 1 – 5 of 5) sorted by relevance

/hal_infineon-3.7.0/mtb-hal-cat1/include_pvt/
Dcyhal_peri_common.h39 #define _CYHAL_TCPWM1_PCLK_CLOCK0 PCLK_TCPWM1_CLOCKS0
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dpsoc6_01_config.h60 PCLK_TCPWM1_CLOCKS0 = 0x001Bu, /* tcpwm[1].clocks[0] */ enumerator
Dpsoc6_03_config.h46 PCLK_TCPWM1_CLOCKS0 = 0x000Du, /* tcpwm[1].clocks[0] */ enumerator
Dpsoc6_02_config.h56 PCLK_TCPWM1_CLOCKS0 = 0x0017u, /* tcpwm[1].clocks[0] */ enumerator
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dxmc7200_config.h93 PCLK_TCPWM1_CLOCKS0 = 0x012Du, /* tcpwm[1].clocks[0] */ enumerator