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Searched refs:PCLK_TCPWM0_CLOCKS1 (Results 1 – 6 of 6) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dpsoc6_01_config.h53 PCLK_TCPWM0_CLOCKS1 = 0x0014u, /* tcpwm[0].clocks[1] */ enumerator
Dpsoc6_03_config.h43 PCLK_TCPWM0_CLOCKS1 = 0x000Au, /* tcpwm[0].clocks[1] */ enumerator
Dpsoc6_04_config.h41 PCLK_TCPWM0_CLOCKS1 = 0x0008u, /* tcpwm[0].clocks[1] */ enumerator
Dpsoc6_02_config.h49 PCLK_TCPWM0_CLOCKS1 = 0x0010u, /* tcpwm[0].clocks[1] */ enumerator
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dxmc7100_config.h78 PCLK_TCPWM0_CLOCKS1 = 0x0127u, /* tcpwm[0].clocks[1] */ enumerator
Dxmc7200_config.h40 PCLK_TCPWM0_CLOCKS1 = 0x0007u, /* tcpwm[0].clocks[1] */ enumerator