1  /**********************************************************************
2  * Copyright (C) 2016 Cadence Design Systems, Inc.- http://www.cadence.com
3  * SPDX-License-Identifier: Apache-2.0
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  *     http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  ***********************************************************************/
17 
18 
19 #ifndef __REG_EMAC_REGS_MACRO_H__
20 #define __REG_EMAC_REGS_MACRO_H__
21 
22 
23 /* macros for BlueprintGlobalNameSpace::emac_regs::network_control */
24 #ifndef __EMAC_REGS__NETWORK_CONTROL_MACRO__
25 #define __EMAC_REGS__NETWORK_CONTROL_MACRO__
26 
27 /* macros for field loopback */
28 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__SHIFT                           0
29 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__WIDTH                           1
30 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__MASK                  0x00000001U
31 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__RESET                           0
32 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__READ(src) \
33                     ((uint32_t)(src)\
34                     & 0x00000001U)
35 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__WRITE(src) \
36                     ((uint32_t)(src)\
37                     & 0x00000001U)
38 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__MODIFY(dst, src) \
39                     (dst) = ((dst) &\
40                     ~0x00000001U) | ((uint32_t)(src) &\
41                     0x00000001U)
42 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__VERIFY(src) \
43                     (!(((uint32_t)(src)\
44                     & ~0x00000001U)))
45 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__SET(dst) \
46                     (dst) = ((dst) &\
47                     ~0x00000001U) | (uint32_t)(1)
48 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK__CLR(dst) \
49                     (dst) = ((dst) &\
50                     ~0x00000001U) | (uint32_t)(0)
51 
52 /* macros for field loopback_local */
53 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__SHIFT                     1
54 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__WIDTH                     1
55 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__MASK            0x00000002U
56 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__RESET                     0
57 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__READ(src) \
58                     (((uint32_t)(src)\
59                     & 0x00000002U) >> 1)
60 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__WRITE(src) \
61                     (((uint32_t)(src)\
62                     << 1) & 0x00000002U)
63 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__MODIFY(dst, src) \
64                     (dst) = ((dst) &\
65                     ~0x00000002U) | (((uint32_t)(src) <<\
66                     1) & 0x00000002U)
67 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__VERIFY(src) \
68                     (!((((uint32_t)(src)\
69                     << 1) & ~0x00000002U)))
70 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__SET(dst) \
71                     (dst) = ((dst) &\
72                     ~0x00000002U) | ((uint32_t)(1) << 1)
73 #define EMAC_REGS__NETWORK_CONTROL__LOOPBACK_LOCAL__CLR(dst) \
74                     (dst) = ((dst) &\
75                     ~0x00000002U) | ((uint32_t)(0) << 1)
76 
77 /* macros for field enable_receive */
78 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__SHIFT                     2
79 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__WIDTH                     1
80 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__MASK            0x00000004U
81 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__RESET                     0
82 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__READ(src) \
83                     (((uint32_t)(src)\
84                     & 0x00000004U) >> 2)
85 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__WRITE(src) \
86                     (((uint32_t)(src)\
87                     << 2) & 0x00000004U)
88 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__MODIFY(dst, src) \
89                     (dst) = ((dst) &\
90                     ~0x00000004U) | (((uint32_t)(src) <<\
91                     2) & 0x00000004U)
92 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__VERIFY(src) \
93                     (!((((uint32_t)(src)\
94                     << 2) & ~0x00000004U)))
95 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__SET(dst) \
96                     (dst) = ((dst) &\
97                     ~0x00000004U) | ((uint32_t)(1) << 2)
98 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_RECEIVE__CLR(dst) \
99                     (dst) = ((dst) &\
100                     ~0x00000004U) | ((uint32_t)(0) << 2)
101 
102 /* macros for field enable_transmit */
103 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__SHIFT                    3
104 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__WIDTH                    1
105 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__MASK           0x00000008U
106 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__RESET                    0
107 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__READ(src) \
108                     (((uint32_t)(src)\
109                     & 0x00000008U) >> 3)
110 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__WRITE(src) \
111                     (((uint32_t)(src)\
112                     << 3) & 0x00000008U)
113 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__MODIFY(dst, src) \
114                     (dst) = ((dst) &\
115                     ~0x00000008U) | (((uint32_t)(src) <<\
116                     3) & 0x00000008U)
117 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__VERIFY(src) \
118                     (!((((uint32_t)(src)\
119                     << 3) & ~0x00000008U)))
120 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__SET(dst) \
121                     (dst) = ((dst) &\
122                     ~0x00000008U) | ((uint32_t)(1) << 3)
123 #define EMAC_REGS__NETWORK_CONTROL__ENABLE_TRANSMIT__CLR(dst) \
124                     (dst) = ((dst) &\
125                     ~0x00000008U) | ((uint32_t)(0) << 3)
126 
127 /* macros for field man_port_en */
128 #define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__SHIFT                        4
129 #define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__WIDTH                        1
130 #define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__MASK               0x00000010U
131 #define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__RESET                        0
132 #define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__READ(src) \
133                     (((uint32_t)(src)\
134                     & 0x00000010U) >> 4)
135 #define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__WRITE(src) \
136                     (((uint32_t)(src)\
137                     << 4) & 0x00000010U)
138 #define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__MODIFY(dst, src) \
139                     (dst) = ((dst) &\
140                     ~0x00000010U) | (((uint32_t)(src) <<\
141                     4) & 0x00000010U)
142 #define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__VERIFY(src) \
143                     (!((((uint32_t)(src)\
144                     << 4) & ~0x00000010U)))
145 #define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__SET(dst) \
146                     (dst) = ((dst) &\
147                     ~0x00000010U) | ((uint32_t)(1) << 4)
148 #define EMAC_REGS__NETWORK_CONTROL__MAN_PORT_EN__CLR(dst) \
149                     (dst) = ((dst) &\
150                     ~0x00000010U) | ((uint32_t)(0) << 4)
151 
152 /* macros for field clear_all_stats_regs */
153 #define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__SHIFT               5
154 #define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__WIDTH               1
155 #define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__MASK      0x00000020U
156 #define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__RESET               0
157 #define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__WRITE(src) \
158                     (((uint32_t)(src)\
159                     << 5) & 0x00000020U)
160 #define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__MODIFY(dst, src) \
161                     (dst) = ((dst) &\
162                     ~0x00000020U) | (((uint32_t)(src) <<\
163                     5) & 0x00000020U)
164 #define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__VERIFY(src) \
165                     (!((((uint32_t)(src)\
166                     << 5) & ~0x00000020U)))
167 #define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__SET(dst) \
168                     (dst) = ((dst) &\
169                     ~0x00000020U) | ((uint32_t)(1) << 5)
170 #define EMAC_REGS__NETWORK_CONTROL__CLEAR_ALL_STATS_REGS__CLR(dst) \
171                     (dst) = ((dst) &\
172                     ~0x00000020U) | ((uint32_t)(0) << 5)
173 
174 /* macros for field inc_all_stats_regs */
175 #define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__SHIFT                 6
176 #define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__WIDTH                 1
177 #define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__MASK        0x00000040U
178 #define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__RESET                 0
179 #define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__WRITE(src) \
180                     (((uint32_t)(src)\
181                     << 6) & 0x00000040U)
182 #define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__MODIFY(dst, src) \
183                     (dst) = ((dst) &\
184                     ~0x00000040U) | (((uint32_t)(src) <<\
185                     6) & 0x00000040U)
186 #define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__VERIFY(src) \
187                     (!((((uint32_t)(src)\
188                     << 6) & ~0x00000040U)))
189 #define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__SET(dst) \
190                     (dst) = ((dst) &\
191                     ~0x00000040U) | ((uint32_t)(1) << 6)
192 #define EMAC_REGS__NETWORK_CONTROL__INC_ALL_STATS_REGS__CLR(dst) \
193                     (dst) = ((dst) &\
194                     ~0x00000040U) | ((uint32_t)(0) << 6)
195 
196 /* macros for field stats_write_en */
197 #define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__SHIFT                     7
198 #define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__WIDTH                     1
199 #define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__MASK            0x00000080U
200 #define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__RESET                     0
201 #define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__READ(src) \
202                     (((uint32_t)(src)\
203                     & 0x00000080U) >> 7)
204 #define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__WRITE(src) \
205                     (((uint32_t)(src)\
206                     << 7) & 0x00000080U)
207 #define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__MODIFY(dst, src) \
208                     (dst) = ((dst) &\
209                     ~0x00000080U) | (((uint32_t)(src) <<\
210                     7) & 0x00000080U)
211 #define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__VERIFY(src) \
212                     (!((((uint32_t)(src)\
213                     << 7) & ~0x00000080U)))
214 #define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__SET(dst) \
215                     (dst) = ((dst) &\
216                     ~0x00000080U) | ((uint32_t)(1) << 7)
217 #define EMAC_REGS__NETWORK_CONTROL__STATS_WRITE_EN__CLR(dst) \
218                     (dst) = ((dst) &\
219                     ~0x00000080U) | ((uint32_t)(0) << 7)
220 
221 /* macros for field back_pressure */
222 #define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__SHIFT                      8
223 #define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__WIDTH                      1
224 #define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__MASK             0x00000100U
225 #define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__RESET                      0
226 #define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__READ(src) \
227                     (((uint32_t)(src)\
228                     & 0x00000100U) >> 8)
229 #define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__WRITE(src) \
230                     (((uint32_t)(src)\
231                     << 8) & 0x00000100U)
232 #define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__MODIFY(dst, src) \
233                     (dst) = ((dst) &\
234                     ~0x00000100U) | (((uint32_t)(src) <<\
235                     8) & 0x00000100U)
236 #define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__VERIFY(src) \
237                     (!((((uint32_t)(src)\
238                     << 8) & ~0x00000100U)))
239 #define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__SET(dst) \
240                     (dst) = ((dst) &\
241                     ~0x00000100U) | ((uint32_t)(1) << 8)
242 #define EMAC_REGS__NETWORK_CONTROL__BACK_PRESSURE__CLR(dst) \
243                     (dst) = ((dst) &\
244                     ~0x00000100U) | ((uint32_t)(0) << 8)
245 
246 /* macros for field tx_start_pclk */
247 #define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__SHIFT                      9
248 #define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__WIDTH                      1
249 #define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__MASK             0x00000200U
250 #define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__RESET                      0
251 #define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__WRITE(src) \
252                     (((uint32_t)(src)\
253                     << 9) & 0x00000200U)
254 #define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__MODIFY(dst, src) \
255                     (dst) = ((dst) &\
256                     ~0x00000200U) | (((uint32_t)(src) <<\
257                     9) & 0x00000200U)
258 #define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__VERIFY(src) \
259                     (!((((uint32_t)(src)\
260                     << 9) & ~0x00000200U)))
261 #define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__SET(dst) \
262                     (dst) = ((dst) &\
263                     ~0x00000200U) | ((uint32_t)(1) << 9)
264 #define EMAC_REGS__NETWORK_CONTROL__TX_START_PCLK__CLR(dst) \
265                     (dst) = ((dst) &\
266                     ~0x00000200U) | ((uint32_t)(0) << 9)
267 
268 /* macros for field tx_halt_pclk */
269 #define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__SHIFT                      10
270 #define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__WIDTH                       1
271 #define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__MASK              0x00000400U
272 #define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__RESET                       0
273 #define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__WRITE(src) \
274                     (((uint32_t)(src)\
275                     << 10) & 0x00000400U)
276 #define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__MODIFY(dst, src) \
277                     (dst) = ((dst) &\
278                     ~0x00000400U) | (((uint32_t)(src) <<\
279                     10) & 0x00000400U)
280 #define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__VERIFY(src) \
281                     (!((((uint32_t)(src)\
282                     << 10) & ~0x00000400U)))
283 #define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__SET(dst) \
284                     (dst) = ((dst) &\
285                     ~0x00000400U) | ((uint32_t)(1) << 10)
286 #define EMAC_REGS__NETWORK_CONTROL__TX_HALT_PCLK__CLR(dst) \
287                     (dst) = ((dst) &\
288                     ~0x00000400U) | ((uint32_t)(0) << 10)
289 
290 /* macros for field tx_pause_frame_req */
291 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__SHIFT                11
292 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__WIDTH                 1
293 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__MASK        0x00000800U
294 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__RESET                 0
295 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__WRITE(src) \
296                     (((uint32_t)(src)\
297                     << 11) & 0x00000800U)
298 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__MODIFY(dst, src) \
299                     (dst) = ((dst) &\
300                     ~0x00000800U) | (((uint32_t)(src) <<\
301                     11) & 0x00000800U)
302 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__VERIFY(src) \
303                     (!((((uint32_t)(src)\
304                     << 11) & ~0x00000800U)))
305 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__SET(dst) \
306                     (dst) = ((dst) &\
307                     ~0x00000800U) | ((uint32_t)(1) << 11)
308 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_REQ__CLR(dst) \
309                     (dst) = ((dst) &\
310                     ~0x00000800U) | ((uint32_t)(0) << 11)
311 
312 /* macros for field tx_pause_frame_zero */
313 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__SHIFT               12
314 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__WIDTH                1
315 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__MASK       0x00001000U
316 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__RESET                0
317 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__WRITE(src) \
318                     (((uint32_t)(src)\
319                     << 12) & 0x00001000U)
320 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__MODIFY(dst, src) \
321                     (dst) = ((dst) &\
322                     ~0x00001000U) | (((uint32_t)(src) <<\
323                     12) & 0x00001000U)
324 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__VERIFY(src) \
325                     (!((((uint32_t)(src)\
326                     << 12) & ~0x00001000U)))
327 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__SET(dst) \
328                     (dst) = ((dst) &\
329                     ~0x00001000U) | ((uint32_t)(1) << 12)
330 #define EMAC_REGS__NETWORK_CONTROL__TX_PAUSE_FRAME_ZERO__CLR(dst) \
331                     (dst) = ((dst) &\
332                     ~0x00001000U) | ((uint32_t)(0) << 12)
333 
334 /* macros for field stats_take_snap */
335 #define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__SHIFT                   13
336 #define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__WIDTH                    1
337 #define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__MASK           0x00002000U
338 #define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__RESET                    0
339 #define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__WRITE(src) \
340                     (((uint32_t)(src)\
341                     << 13) & 0x00002000U)
342 #define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__MODIFY(dst, src) \
343                     (dst) = ((dst) &\
344                     ~0x00002000U) | (((uint32_t)(src) <<\
345                     13) & 0x00002000U)
346 #define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__VERIFY(src) \
347                     (!((((uint32_t)(src)\
348                     << 13) & ~0x00002000U)))
349 #define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__SET(dst) \
350                     (dst) = ((dst) &\
351                     ~0x00002000U) | ((uint32_t)(1) << 13)
352 #define EMAC_REGS__NETWORK_CONTROL__STATS_TAKE_SNAP__CLR(dst) \
353                     (dst) = ((dst) &\
354                     ~0x00002000U) | ((uint32_t)(0) << 13)
355 
356 /* macros for field stats_read_snap */
357 #define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__SHIFT                   14
358 #define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__WIDTH                    1
359 #define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__MASK           0x00004000U
360 #define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__RESET                    0
361 #define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__READ(src) \
362                     (((uint32_t)(src)\
363                     & 0x00004000U) >> 14)
364 #define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__WRITE(src) \
365                     (((uint32_t)(src)\
366                     << 14) & 0x00004000U)
367 #define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__MODIFY(dst, src) \
368                     (dst) = ((dst) &\
369                     ~0x00004000U) | (((uint32_t)(src) <<\
370                     14) & 0x00004000U)
371 #define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__VERIFY(src) \
372                     (!((((uint32_t)(src)\
373                     << 14) & ~0x00004000U)))
374 #define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__SET(dst) \
375                     (dst) = ((dst) &\
376                     ~0x00004000U) | ((uint32_t)(1) << 14)
377 #define EMAC_REGS__NETWORK_CONTROL__STATS_READ_SNAP__CLR(dst) \
378                     (dst) = ((dst) &\
379                     ~0x00004000U) | ((uint32_t)(0) << 14)
380 
381 /* macros for field store_rx_ts */
382 #define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__SHIFT                       15
383 #define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__WIDTH                        1
384 #define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__MASK               0x00008000U
385 #define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__RESET                        0
386 #define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__READ(src) \
387                     (((uint32_t)(src)\
388                     & 0x00008000U) >> 15)
389 #define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__WRITE(src) \
390                     (((uint32_t)(src)\
391                     << 15) & 0x00008000U)
392 #define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__MODIFY(dst, src) \
393                     (dst) = ((dst) &\
394                     ~0x00008000U) | (((uint32_t)(src) <<\
395                     15) & 0x00008000U)
396 #define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__VERIFY(src) \
397                     (!((((uint32_t)(src)\
398                     << 15) & ~0x00008000U)))
399 #define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__SET(dst) \
400                     (dst) = ((dst) &\
401                     ~0x00008000U) | ((uint32_t)(1) << 15)
402 #define EMAC_REGS__NETWORK_CONTROL__STORE_RX_TS__CLR(dst) \
403                     (dst) = ((dst) &\
404                     ~0x00008000U) | ((uint32_t)(0) << 15)
405 
406 /* macros for field pfc_enable */
407 #define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__SHIFT                        16
408 #define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__WIDTH                         1
409 #define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__MASK                0x00010000U
410 #define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__RESET                         0
411 #define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__READ(src) \
412                     (((uint32_t)(src)\
413                     & 0x00010000U) >> 16)
414 #define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__WRITE(src) \
415                     (((uint32_t)(src)\
416                     << 16) & 0x00010000U)
417 #define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__MODIFY(dst, src) \
418                     (dst) = ((dst) &\
419                     ~0x00010000U) | (((uint32_t)(src) <<\
420                     16) & 0x00010000U)
421 #define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__VERIFY(src) \
422                     (!((((uint32_t)(src)\
423                     << 16) & ~0x00010000U)))
424 #define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__SET(dst) \
425                     (dst) = ((dst) &\
426                     ~0x00010000U) | ((uint32_t)(1) << 16)
427 #define EMAC_REGS__NETWORK_CONTROL__PFC_ENABLE__CLR(dst) \
428                     (dst) = ((dst) &\
429                     ~0x00010000U) | ((uint32_t)(0) << 16)
430 
431 /* macros for field transmit_pfc_priority_based_pause_frame */
432 #define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__SHIFT \
433                     17
434 #define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__WIDTH \
435                     1
436 #define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__MASK \
437                     0x00020000U
438 #define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__RESET \
439                     0
440 #define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__WRITE(src) \
441                     (((uint32_t)(src)\
442                     << 17) & 0x00020000U)
443 #define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__MODIFY(dst, src) \
444                     (dst) = ((dst) &\
445                     ~0x00020000U) | (((uint32_t)(src) <<\
446                     17) & 0x00020000U)
447 #define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__VERIFY(src) \
448                     (!((((uint32_t)(src)\
449                     << 17) & ~0x00020000U)))
450 #define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__SET(dst) \
451                     (dst) = ((dst) &\
452                     ~0x00020000U) | ((uint32_t)(1) << 17)
453 #define EMAC_REGS__NETWORK_CONTROL__TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME__CLR(dst) \
454                     (dst) = ((dst) &\
455                     ~0x00020000U) | ((uint32_t)(0) << 17)
456 
457 /* macros for field flush_rx_pkt_pclk */
458 #define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__SHIFT                 18
459 #define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__WIDTH                  1
460 #define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__MASK         0x00040000U
461 #define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__RESET                  0
462 #define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__WRITE(src) \
463                     (((uint32_t)(src)\
464                     << 18) & 0x00040000U)
465 #define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__MODIFY(dst, src) \
466                     (dst) = ((dst) &\
467                     ~0x00040000U) | (((uint32_t)(src) <<\
468                     18) & 0x00040000U)
469 #define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__VERIFY(src) \
470                     (!((((uint32_t)(src)\
471                     << 18) & ~0x00040000U)))
472 #define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__SET(dst) \
473                     (dst) = ((dst) &\
474                     ~0x00040000U) | ((uint32_t)(1) << 18)
475 #define EMAC_REGS__NETWORK_CONTROL__FLUSH_RX_PKT_PCLK__CLR(dst) \
476                     (dst) = ((dst) &\
477                     ~0x00040000U) | ((uint32_t)(0) << 18)
478 
479 /* macros for field tx_lpi_en */
480 #define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__SHIFT                         19
481 #define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__WIDTH                          1
482 #define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__MASK                 0x00080000U
483 #define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__RESET                          0
484 #define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__READ(src) \
485                     (((uint32_t)(src)\
486                     & 0x00080000U) >> 19)
487 #define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__WRITE(src) \
488                     (((uint32_t)(src)\
489                     << 19) & 0x00080000U)
490 #define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__MODIFY(dst, src) \
491                     (dst) = ((dst) &\
492                     ~0x00080000U) | (((uint32_t)(src) <<\
493                     19) & 0x00080000U)
494 #define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__VERIFY(src) \
495                     (!((((uint32_t)(src)\
496                     << 19) & ~0x00080000U)))
497 #define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__SET(dst) \
498                     (dst) = ((dst) &\
499                     ~0x00080000U) | ((uint32_t)(1) << 19)
500 #define EMAC_REGS__NETWORK_CONTROL__TX_LPI_EN__CLR(dst) \
501                     (dst) = ((dst) &\
502                     ~0x00080000U) | ((uint32_t)(0) << 19)
503 
504 /* macros for field ptp_unicast_ena */
505 #define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__SHIFT                   20
506 #define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__WIDTH                    1
507 #define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__MASK           0x00100000U
508 #define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__RESET                    0
509 #define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__READ(src) \
510                     (((uint32_t)(src)\
511                     & 0x00100000U) >> 20)
512 #define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__WRITE(src) \
513                     (((uint32_t)(src)\
514                     << 20) & 0x00100000U)
515 #define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__MODIFY(dst, src) \
516                     (dst) = ((dst) &\
517                     ~0x00100000U) | (((uint32_t)(src) <<\
518                     20) & 0x00100000U)
519 #define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__VERIFY(src) \
520                     (!((((uint32_t)(src)\
521                     << 20) & ~0x00100000U)))
522 #define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__SET(dst) \
523                     (dst) = ((dst) &\
524                     ~0x00100000U) | ((uint32_t)(1) << 20)
525 #define EMAC_REGS__NETWORK_CONTROL__PTP_UNICAST_ENA__CLR(dst) \
526                     (dst) = ((dst) &\
527                     ~0x00100000U) | ((uint32_t)(0) << 20)
528 
529 /* macros for field alt_sgmii_mode */
530 #define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__SHIFT                    21
531 #define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__WIDTH                     1
532 #define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__MASK            0x00200000U
533 #define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__RESET                     0
534 #define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__READ(src) \
535                     (((uint32_t)(src)\
536                     & 0x00200000U) >> 21)
537 #define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__WRITE(src) \
538                     (((uint32_t)(src)\
539                     << 21) & 0x00200000U)
540 #define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__MODIFY(dst, src) \
541                     (dst) = ((dst) &\
542                     ~0x00200000U) | (((uint32_t)(src) <<\
543                     21) & 0x00200000U)
544 #define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__VERIFY(src) \
545                     (!((((uint32_t)(src)\
546                     << 21) & ~0x00200000U)))
547 #define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__SET(dst) \
548                     (dst) = ((dst) &\
549                     ~0x00200000U) | ((uint32_t)(1) << 21)
550 #define EMAC_REGS__NETWORK_CONTROL__ALT_SGMII_MODE__CLR(dst) \
551                     (dst) = ((dst) &\
552                     ~0x00200000U) | ((uint32_t)(0) << 21)
553 
554 /* macros for field store_udp_offset */
555 #define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__SHIFT                  22
556 #define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__WIDTH                   1
557 #define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__MASK          0x00400000U
558 #define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__RESET                   0
559 #define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__READ(src) \
560                     (((uint32_t)(src)\
561                     & 0x00400000U) >> 22)
562 #define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__WRITE(src) \
563                     (((uint32_t)(src)\
564                     << 22) & 0x00400000U)
565 #define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__MODIFY(dst, src) \
566                     (dst) = ((dst) &\
567                     ~0x00400000U) | (((uint32_t)(src) <<\
568                     22) & 0x00400000U)
569 #define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__VERIFY(src) \
570                     (!((((uint32_t)(src)\
571                     << 22) & ~0x00400000U)))
572 #define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__SET(dst) \
573                     (dst) = ((dst) &\
574                     ~0x00400000U) | ((uint32_t)(1) << 22)
575 #define EMAC_REGS__NETWORK_CONTROL__STORE_UDP_OFFSET__CLR(dst) \
576                     (dst) = ((dst) &\
577                     ~0x00400000U) | ((uint32_t)(0) << 22)
578 
579 /* macros for field ext_tsu_port_enable */
580 #define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__SHIFT               23
581 #define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__WIDTH                1
582 #define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__MASK       0x00800000U
583 #define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__RESET                0
584 #define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__READ(src) \
585                     (((uint32_t)(src)\
586                     & 0x00800000U) >> 23)
587 #define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__WRITE(src) \
588                     (((uint32_t)(src)\
589                     << 23) & 0x00800000U)
590 #define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__MODIFY(dst, src) \
591                     (dst) = ((dst) &\
592                     ~0x00800000U) | (((uint32_t)(src) <<\
593                     23) & 0x00800000U)
594 #define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__VERIFY(src) \
595                     (!((((uint32_t)(src)\
596                     << 23) & ~0x00800000U)))
597 #define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__SET(dst) \
598                     (dst) = ((dst) &\
599                     ~0x00800000U) | ((uint32_t)(1) << 23)
600 #define EMAC_REGS__NETWORK_CONTROL__EXT_TSU_PORT_ENABLE__CLR(dst) \
601                     (dst) = ((dst) &\
602                     ~0x00800000U) | ((uint32_t)(0) << 23)
603 
604 /* macros for field one_step_sync_mode */
605 #define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__SHIFT                24
606 #define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__WIDTH                 1
607 #define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__MASK        0x01000000U
608 #define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__RESET                 0
609 #define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__READ(src) \
610                     (((uint32_t)(src)\
611                     & 0x01000000U) >> 24)
612 #define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__WRITE(src) \
613                     (((uint32_t)(src)\
614                     << 24) & 0x01000000U)
615 #define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__MODIFY(dst, src) \
616                     (dst) = ((dst) &\
617                     ~0x01000000U) | (((uint32_t)(src) <<\
618                     24) & 0x01000000U)
619 #define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__VERIFY(src) \
620                     (!((((uint32_t)(src)\
621                     << 24) & ~0x01000000U)))
622 #define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__SET(dst) \
623                     (dst) = ((dst) &\
624                     ~0x01000000U) | ((uint32_t)(1) << 24)
625 #define EMAC_REGS__NETWORK_CONTROL__ONE_STEP_SYNC_MODE__CLR(dst) \
626                     (dst) = ((dst) &\
627                     ~0x01000000U) | ((uint32_t)(0) << 24)
628 
629 /* macros for field pfc_ctrl */
630 #define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__SHIFT                          25
631 #define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__WIDTH                           1
632 #define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__MASK                  0x02000000U
633 #define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__RESET                           0
634 #define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__READ(src) \
635                     (((uint32_t)(src)\
636                     & 0x02000000U) >> 25)
637 #define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__WRITE(src) \
638                     (((uint32_t)(src)\
639                     << 25) & 0x02000000U)
640 #define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__MODIFY(dst, src) \
641                     (dst) = ((dst) &\
642                     ~0x02000000U) | (((uint32_t)(src) <<\
643                     25) & 0x02000000U)
644 #define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__VERIFY(src) \
645                     (!((((uint32_t)(src)\
646                     << 25) & ~0x02000000U)))
647 #define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__SET(dst) \
648                     (dst) = ((dst) &\
649                     ~0x02000000U) | ((uint32_t)(1) << 25)
650 #define EMAC_REGS__NETWORK_CONTROL__PFC_CTRL__CLR(dst) \
651                     (dst) = ((dst) &\
652                     ~0x02000000U) | ((uint32_t)(0) << 25)
653 
654 /* macros for field ext_rxq_sel_en */
655 #define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__SHIFT                    26
656 #define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__WIDTH                     1
657 #define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__MASK            0x04000000U
658 #define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__RESET                     0
659 #define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__READ(src) \
660                     (((uint32_t)(src)\
661                     & 0x04000000U) >> 26)
662 #define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__WRITE(src) \
663                     (((uint32_t)(src)\
664                     << 26) & 0x04000000U)
665 #define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__MODIFY(dst, src) \
666                     (dst) = ((dst) &\
667                     ~0x04000000U) | (((uint32_t)(src) <<\
668                     26) & 0x04000000U)
669 #define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__VERIFY(src) \
670                     (!((((uint32_t)(src)\
671                     << 26) & ~0x04000000U)))
672 #define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__SET(dst) \
673                     (dst) = ((dst) &\
674                     ~0x04000000U) | ((uint32_t)(1) << 26)
675 #define EMAC_REGS__NETWORK_CONTROL__EXT_RXQ_SEL_EN__CLR(dst) \
676                     (dst) = ((dst) &\
677                     ~0x04000000U) | ((uint32_t)(0) << 26)
678 
679 /* macros for field oss_correction_field */
680 #define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__SHIFT              27
681 #define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__WIDTH               1
682 #define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__MASK      0x08000000U
683 #define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__RESET               0
684 #define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__READ(src) \
685                     (((uint32_t)(src)\
686                     & 0x08000000U) >> 27)
687 #define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__WRITE(src) \
688                     (((uint32_t)(src)\
689                     << 27) & 0x08000000U)
690 #define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__MODIFY(dst, src) \
691                     (dst) = ((dst) &\
692                     ~0x08000000U) | (((uint32_t)(src) <<\
693                     27) & 0x08000000U)
694 #define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__VERIFY(src) \
695                     (!((((uint32_t)(src)\
696                     << 27) & ~0x08000000U)))
697 #define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__SET(dst) \
698                     (dst) = ((dst) &\
699                     ~0x08000000U) | ((uint32_t)(1) << 27)
700 #define EMAC_REGS__NETWORK_CONTROL__OSS_CORRECTION_FIELD__CLR(dst) \
701                     (dst) = ((dst) &\
702                     ~0x08000000U) | ((uint32_t)(0) << 27)
703 
704 /* macros for field sel_mii_on_rgmii */
705 #define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__SHIFT                  28
706 #define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__WIDTH                   1
707 #define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__MASK          0x10000000U
708 #define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__RESET                   0
709 #define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__READ(src) \
710                     (((uint32_t)(src)\
711                     & 0x10000000U) >> 28)
712 #define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__WRITE(src) \
713                     (((uint32_t)(src)\
714                     << 28) & 0x10000000U)
715 #define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__MODIFY(dst, src) \
716                     (dst) = ((dst) &\
717                     ~0x10000000U) | (((uint32_t)(src) <<\
718                     28) & 0x10000000U)
719 #define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__VERIFY(src) \
720                     (!((((uint32_t)(src)\
721                     << 28) & ~0x10000000U)))
722 #define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__SET(dst) \
723                     (dst) = ((dst) &\
724                     ~0x10000000U) | ((uint32_t)(1) << 28)
725 #define EMAC_REGS__NETWORK_CONTROL__SEL_MII_ON_RGMII__CLR(dst) \
726                     (dst) = ((dst) &\
727                     ~0x10000000U) | ((uint32_t)(0) << 28)
728 
729 /* macros for field two_pt_five_gig */
730 #define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__SHIFT                   29
731 #define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__WIDTH                    1
732 #define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__MASK           0x20000000U
733 #define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__RESET                    0
734 #define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__READ(src) \
735                     (((uint32_t)(src)\
736                     & 0x20000000U) >> 29)
737 #define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__WRITE(src) \
738                     (((uint32_t)(src)\
739                     << 29) & 0x20000000U)
740 #define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__MODIFY(dst, src) \
741                     (dst) = ((dst) &\
742                     ~0x20000000U) | (((uint32_t)(src) <<\
743                     29) & 0x20000000U)
744 #define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__VERIFY(src) \
745                     (!((((uint32_t)(src)\
746                     << 29) & ~0x20000000U)))
747 #define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__SET(dst) \
748                     (dst) = ((dst) &\
749                     ~0x20000000U) | ((uint32_t)(1) << 29)
750 #define EMAC_REGS__NETWORK_CONTROL__TWO_PT_FIVE_GIG__CLR(dst) \
751                     (dst) = ((dst) &\
752                     ~0x20000000U) | ((uint32_t)(0) << 29)
753 
754 /* macros for field ifg_eats_qav_credit */
755 #define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__SHIFT               30
756 #define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__WIDTH                1
757 #define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__MASK       0x40000000U
758 #define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__RESET                0
759 #define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__READ(src) \
760                     (((uint32_t)(src)\
761                     & 0x40000000U) >> 30)
762 #define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__WRITE(src) \
763                     (((uint32_t)(src)\
764                     << 30) & 0x40000000U)
765 #define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__MODIFY(dst, src) \
766                     (dst) = ((dst) &\
767                     ~0x40000000U) | (((uint32_t)(src) <<\
768                     30) & 0x40000000U)
769 #define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__VERIFY(src) \
770                     (!((((uint32_t)(src)\
771                     << 30) & ~0x40000000U)))
772 #define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__SET(dst) \
773                     (dst) = ((dst) &\
774                     ~0x40000000U) | ((uint32_t)(1) << 30)
775 #define EMAC_REGS__NETWORK_CONTROL__IFG_EATS_QAV_CREDIT__CLR(dst) \
776                     (dst) = ((dst) &\
777                     ~0x40000000U) | ((uint32_t)(0) << 30)
778 
779 /* macros for field reserved_31 */
780 #define EMAC_REGS__NETWORK_CONTROL__RESERVED_31__SHIFT                       31
781 #define EMAC_REGS__NETWORK_CONTROL__RESERVED_31__WIDTH                        1
782 #define EMAC_REGS__NETWORK_CONTROL__RESERVED_31__MASK               0x80000000U
783 #define EMAC_REGS__NETWORK_CONTROL__RESERVED_31__RESET                        0
784 #define EMAC_REGS__NETWORK_CONTROL__RESERVED_31__READ(src) \
785                     (((uint32_t)(src)\
786                     & 0x80000000U) >> 31)
787 #define EMAC_REGS__NETWORK_CONTROL__RESERVED_31__SET(dst) \
788                     (dst) = ((dst) &\
789                     ~0x80000000U) | ((uint32_t)(1) << 31)
790 #define EMAC_REGS__NETWORK_CONTROL__RESERVED_31__CLR(dst) \
791                     (dst) = ((dst) &\
792                     ~0x80000000U) | ((uint32_t)(0) << 31)
793 #define EMAC_REGS__NETWORK_CONTROL__TYPE                               uint32_t
794 #define EMAC_REGS__NETWORK_CONTROL__READ                            0xfff9c19fU
795 #define EMAC_REGS__NETWORK_CONTROL__WRITE                           0xfff9c19fU
796 
797 #endif /* __EMAC_REGS__NETWORK_CONTROL_MACRO__ */
798 
799 
800 /* macros for network_control */
801 #define INST_NETWORK_CONTROL__NUM                                             1
802 
803 /* macros for BlueprintGlobalNameSpace::emac_regs::network_config */
804 #ifndef __EMAC_REGS__NETWORK_CONFIG_MACRO__
805 #define __EMAC_REGS__NETWORK_CONFIG_MACRO__
806 
807 /* macros for field speed */
808 #define EMAC_REGS__NETWORK_CONFIG__SPEED__SHIFT                               0
809 #define EMAC_REGS__NETWORK_CONFIG__SPEED__WIDTH                               1
810 #define EMAC_REGS__NETWORK_CONFIG__SPEED__MASK                      0x00000001U
811 #define EMAC_REGS__NETWORK_CONFIG__SPEED__RESET                               0
812 #define EMAC_REGS__NETWORK_CONFIG__SPEED__READ(src) \
813                     ((uint32_t)(src)\
814                     & 0x00000001U)
815 #define EMAC_REGS__NETWORK_CONFIG__SPEED__WRITE(src) \
816                     ((uint32_t)(src)\
817                     & 0x00000001U)
818 #define EMAC_REGS__NETWORK_CONFIG__SPEED__MODIFY(dst, src) \
819                     (dst) = ((dst) &\
820                     ~0x00000001U) | ((uint32_t)(src) &\
821                     0x00000001U)
822 #define EMAC_REGS__NETWORK_CONFIG__SPEED__VERIFY(src) \
823                     (!(((uint32_t)(src)\
824                     & ~0x00000001U)))
825 #define EMAC_REGS__NETWORK_CONFIG__SPEED__SET(dst) \
826                     (dst) = ((dst) &\
827                     ~0x00000001U) | (uint32_t)(1)
828 #define EMAC_REGS__NETWORK_CONFIG__SPEED__CLR(dst) \
829                     (dst) = ((dst) &\
830                     ~0x00000001U) | (uint32_t)(0)
831 
832 /* macros for field full_duplex */
833 #define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__SHIFT                         1
834 #define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__WIDTH                         1
835 #define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__MASK                0x00000002U
836 #define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__RESET                         0
837 #define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__READ(src) \
838                     (((uint32_t)(src)\
839                     & 0x00000002U) >> 1)
840 #define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__WRITE(src) \
841                     (((uint32_t)(src)\
842                     << 1) & 0x00000002U)
843 #define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__MODIFY(dst, src) \
844                     (dst) = ((dst) &\
845                     ~0x00000002U) | (((uint32_t)(src) <<\
846                     1) & 0x00000002U)
847 #define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__VERIFY(src) \
848                     (!((((uint32_t)(src)\
849                     << 1) & ~0x00000002U)))
850 #define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__SET(dst) \
851                     (dst) = ((dst) &\
852                     ~0x00000002U) | ((uint32_t)(1) << 1)
853 #define EMAC_REGS__NETWORK_CONFIG__FULL_DUPLEX__CLR(dst) \
854                     (dst) = ((dst) &\
855                     ~0x00000002U) | ((uint32_t)(0) << 1)
856 
857 /* macros for field discard_non_vlan_frames */
858 #define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__SHIFT             2
859 #define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__WIDTH             1
860 #define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__MASK    0x00000004U
861 #define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__RESET             0
862 #define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__READ(src) \
863                     (((uint32_t)(src)\
864                     & 0x00000004U) >> 2)
865 #define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__WRITE(src) \
866                     (((uint32_t)(src)\
867                     << 2) & 0x00000004U)
868 #define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__MODIFY(dst, src) \
869                     (dst) = ((dst) &\
870                     ~0x00000004U) | (((uint32_t)(src) <<\
871                     2) & 0x00000004U)
872 #define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__VERIFY(src) \
873                     (!((((uint32_t)(src)\
874                     << 2) & ~0x00000004U)))
875 #define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__SET(dst) \
876                     (dst) = ((dst) &\
877                     ~0x00000004U) | ((uint32_t)(1) << 2)
878 #define EMAC_REGS__NETWORK_CONFIG__DISCARD_NON_VLAN_FRAMES__CLR(dst) \
879                     (dst) = ((dst) &\
880                     ~0x00000004U) | ((uint32_t)(0) << 2)
881 
882 /* macros for field jumbo_frames */
883 #define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__SHIFT                        3
884 #define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__WIDTH                        1
885 #define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__MASK               0x00000008U
886 #define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__RESET                        0
887 #define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__READ(src) \
888                     (((uint32_t)(src)\
889                     & 0x00000008U) >> 3)
890 #define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__WRITE(src) \
891                     (((uint32_t)(src)\
892                     << 3) & 0x00000008U)
893 #define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__MODIFY(dst, src) \
894                     (dst) = ((dst) &\
895                     ~0x00000008U) | (((uint32_t)(src) <<\
896                     3) & 0x00000008U)
897 #define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__VERIFY(src) \
898                     (!((((uint32_t)(src)\
899                     << 3) & ~0x00000008U)))
900 #define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__SET(dst) \
901                     (dst) = ((dst) &\
902                     ~0x00000008U) | ((uint32_t)(1) << 3)
903 #define EMAC_REGS__NETWORK_CONFIG__JUMBO_FRAMES__CLR(dst) \
904                     (dst) = ((dst) &\
905                     ~0x00000008U) | ((uint32_t)(0) << 3)
906 
907 /* macros for field copy_all_frames */
908 #define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__SHIFT                     4
909 #define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__WIDTH                     1
910 #define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__MASK            0x00000010U
911 #define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__RESET                     0
912 #define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__READ(src) \
913                     (((uint32_t)(src)\
914                     & 0x00000010U) >> 4)
915 #define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__WRITE(src) \
916                     (((uint32_t)(src)\
917                     << 4) & 0x00000010U)
918 #define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__MODIFY(dst, src) \
919                     (dst) = ((dst) &\
920                     ~0x00000010U) | (((uint32_t)(src) <<\
921                     4) & 0x00000010U)
922 #define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__VERIFY(src) \
923                     (!((((uint32_t)(src)\
924                     << 4) & ~0x00000010U)))
925 #define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__SET(dst) \
926                     (dst) = ((dst) &\
927                     ~0x00000010U) | ((uint32_t)(1) << 4)
928 #define EMAC_REGS__NETWORK_CONFIG__COPY_ALL_FRAMES__CLR(dst) \
929                     (dst) = ((dst) &\
930                     ~0x00000010U) | ((uint32_t)(0) << 4)
931 
932 /* macros for field no_broadcast */
933 #define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__SHIFT                        5
934 #define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__WIDTH                        1
935 #define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__MASK               0x00000020U
936 #define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__RESET                        0
937 #define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__READ(src) \
938                     (((uint32_t)(src)\
939                     & 0x00000020U) >> 5)
940 #define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__WRITE(src) \
941                     (((uint32_t)(src)\
942                     << 5) & 0x00000020U)
943 #define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__MODIFY(dst, src) \
944                     (dst) = ((dst) &\
945                     ~0x00000020U) | (((uint32_t)(src) <<\
946                     5) & 0x00000020U)
947 #define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__VERIFY(src) \
948                     (!((((uint32_t)(src)\
949                     << 5) & ~0x00000020U)))
950 #define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__SET(dst) \
951                     (dst) = ((dst) &\
952                     ~0x00000020U) | ((uint32_t)(1) << 5)
953 #define EMAC_REGS__NETWORK_CONFIG__NO_BROADCAST__CLR(dst) \
954                     (dst) = ((dst) &\
955                     ~0x00000020U) | ((uint32_t)(0) << 5)
956 
957 /* macros for field multicast_hash_enable */
958 #define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__SHIFT               6
959 #define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__WIDTH               1
960 #define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__MASK      0x00000040U
961 #define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__RESET               0
962 #define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__READ(src) \
963                     (((uint32_t)(src)\
964                     & 0x00000040U) >> 6)
965 #define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__WRITE(src) \
966                     (((uint32_t)(src)\
967                     << 6) & 0x00000040U)
968 #define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__MODIFY(dst, src) \
969                     (dst) = ((dst) &\
970                     ~0x00000040U) | (((uint32_t)(src) <<\
971                     6) & 0x00000040U)
972 #define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__VERIFY(src) \
973                     (!((((uint32_t)(src)\
974                     << 6) & ~0x00000040U)))
975 #define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__SET(dst) \
976                     (dst) = ((dst) &\
977                     ~0x00000040U) | ((uint32_t)(1) << 6)
978 #define EMAC_REGS__NETWORK_CONFIG__MULTICAST_HASH_ENABLE__CLR(dst) \
979                     (dst) = ((dst) &\
980                     ~0x00000040U) | ((uint32_t)(0) << 6)
981 
982 /* macros for field unicast_hash_enable */
983 #define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__SHIFT                 7
984 #define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__WIDTH                 1
985 #define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__MASK        0x00000080U
986 #define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__RESET                 0
987 #define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__READ(src) \
988                     (((uint32_t)(src)\
989                     & 0x00000080U) >> 7)
990 #define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__WRITE(src) \
991                     (((uint32_t)(src)\
992                     << 7) & 0x00000080U)
993 #define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__MODIFY(dst, src) \
994                     (dst) = ((dst) &\
995                     ~0x00000080U) | (((uint32_t)(src) <<\
996                     7) & 0x00000080U)
997 #define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__VERIFY(src) \
998                     (!((((uint32_t)(src)\
999                     << 7) & ~0x00000080U)))
1000 #define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__SET(dst) \
1001                     (dst) = ((dst) &\
1002                     ~0x00000080U) | ((uint32_t)(1) << 7)
1003 #define EMAC_REGS__NETWORK_CONFIG__UNICAST_HASH_ENABLE__CLR(dst) \
1004                     (dst) = ((dst) &\
1005                     ~0x00000080U) | ((uint32_t)(0) << 7)
1006 
1007 /* macros for field receive_1536_byte_frames */
1008 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__SHIFT            8
1009 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__WIDTH            1
1010 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__MASK   0x00000100U
1011 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__RESET            0
1012 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__READ(src) \
1013                     (((uint32_t)(src)\
1014                     & 0x00000100U) >> 8)
1015 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__WRITE(src) \
1016                     (((uint32_t)(src)\
1017                     << 8) & 0x00000100U)
1018 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__MODIFY(dst, src) \
1019                     (dst) = ((dst) &\
1020                     ~0x00000100U) | (((uint32_t)(src) <<\
1021                     8) & 0x00000100U)
1022 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__VERIFY(src) \
1023                     (!((((uint32_t)(src)\
1024                     << 8) & ~0x00000100U)))
1025 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__SET(dst) \
1026                     (dst) = ((dst) &\
1027                     ~0x00000100U) | ((uint32_t)(1) << 8)
1028 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_1536_BYTE_FRAMES__CLR(dst) \
1029                     (dst) = ((dst) &\
1030                     ~0x00000100U) | ((uint32_t)(0) << 8)
1031 
1032 /* macros for field external_address_match_enable */
1033 #define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__SHIFT       9
1034 #define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__WIDTH       1
1035 #define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__MASK \
1036                     0x00000200U
1037 #define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__RESET       0
1038 #define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__READ(src) \
1039                     (((uint32_t)(src)\
1040                     & 0x00000200U) >> 9)
1041 #define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__WRITE(src) \
1042                     (((uint32_t)(src)\
1043                     << 9) & 0x00000200U)
1044 #define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__MODIFY(dst, src) \
1045                     (dst) = ((dst) &\
1046                     ~0x00000200U) | (((uint32_t)(src) <<\
1047                     9) & 0x00000200U)
1048 #define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__VERIFY(src) \
1049                     (!((((uint32_t)(src)\
1050                     << 9) & ~0x00000200U)))
1051 #define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__SET(dst) \
1052                     (dst) = ((dst) &\
1053                     ~0x00000200U) | ((uint32_t)(1) << 9)
1054 #define EMAC_REGS__NETWORK_CONFIG__EXTERNAL_ADDRESS_MATCH_ENABLE__CLR(dst) \
1055                     (dst) = ((dst) &\
1056                     ~0x00000200U) | ((uint32_t)(0) << 9)
1057 
1058 /* macros for field gigabit_mode_enable */
1059 #define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__SHIFT                10
1060 #define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__WIDTH                 1
1061 #define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__MASK        0x00000400U
1062 #define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__RESET                 0
1063 #define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__READ(src) \
1064                     (((uint32_t)(src)\
1065                     & 0x00000400U) >> 10)
1066 #define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__WRITE(src) \
1067                     (((uint32_t)(src)\
1068                     << 10) & 0x00000400U)
1069 #define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__MODIFY(dst, src) \
1070                     (dst) = ((dst) &\
1071                     ~0x00000400U) | (((uint32_t)(src) <<\
1072                     10) & 0x00000400U)
1073 #define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__VERIFY(src) \
1074                     (!((((uint32_t)(src)\
1075                     << 10) & ~0x00000400U)))
1076 #define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__SET(dst) \
1077                     (dst) = ((dst) &\
1078                     ~0x00000400U) | ((uint32_t)(1) << 10)
1079 #define EMAC_REGS__NETWORK_CONFIG__GIGABIT_MODE_ENABLE__CLR(dst) \
1080                     (dst) = ((dst) &\
1081                     ~0x00000400U) | ((uint32_t)(0) << 10)
1082 
1083 /* macros for field pcs_select */
1084 #define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__SHIFT                         11
1085 #define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__WIDTH                          1
1086 #define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__MASK                 0x00000800U
1087 #define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__RESET                          0
1088 #define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__READ(src) \
1089                     (((uint32_t)(src)\
1090                     & 0x00000800U) >> 11)
1091 #define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__WRITE(src) \
1092                     (((uint32_t)(src)\
1093                     << 11) & 0x00000800U)
1094 #define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__MODIFY(dst, src) \
1095                     (dst) = ((dst) &\
1096                     ~0x00000800U) | (((uint32_t)(src) <<\
1097                     11) & 0x00000800U)
1098 #define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__VERIFY(src) \
1099                     (!((((uint32_t)(src)\
1100                     << 11) & ~0x00000800U)))
1101 #define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__SET(dst) \
1102                     (dst) = ((dst) &\
1103                     ~0x00000800U) | ((uint32_t)(1) << 11)
1104 #define EMAC_REGS__NETWORK_CONFIG__PCS_SELECT__CLR(dst) \
1105                     (dst) = ((dst) &\
1106                     ~0x00000800U) | ((uint32_t)(0) << 11)
1107 
1108 /* macros for field retry_test */
1109 #define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__SHIFT                         12
1110 #define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__WIDTH                          1
1111 #define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__MASK                 0x00001000U
1112 #define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__RESET                          0
1113 #define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__READ(src) \
1114                     (((uint32_t)(src)\
1115                     & 0x00001000U) >> 12)
1116 #define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__WRITE(src) \
1117                     (((uint32_t)(src)\
1118                     << 12) & 0x00001000U)
1119 #define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__MODIFY(dst, src) \
1120                     (dst) = ((dst) &\
1121                     ~0x00001000U) | (((uint32_t)(src) <<\
1122                     12) & 0x00001000U)
1123 #define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__VERIFY(src) \
1124                     (!((((uint32_t)(src)\
1125                     << 12) & ~0x00001000U)))
1126 #define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__SET(dst) \
1127                     (dst) = ((dst) &\
1128                     ~0x00001000U) | ((uint32_t)(1) << 12)
1129 #define EMAC_REGS__NETWORK_CONFIG__RETRY_TEST__CLR(dst) \
1130                     (dst) = ((dst) &\
1131                     ~0x00001000U) | ((uint32_t)(0) << 12)
1132 
1133 /* macros for field pause_enable */
1134 #define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__SHIFT                       13
1135 #define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__WIDTH                        1
1136 #define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__MASK               0x00002000U
1137 #define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__RESET                        0
1138 #define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__READ(src) \
1139                     (((uint32_t)(src)\
1140                     & 0x00002000U) >> 13)
1141 #define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__WRITE(src) \
1142                     (((uint32_t)(src)\
1143                     << 13) & 0x00002000U)
1144 #define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__MODIFY(dst, src) \
1145                     (dst) = ((dst) &\
1146                     ~0x00002000U) | (((uint32_t)(src) <<\
1147                     13) & 0x00002000U)
1148 #define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__VERIFY(src) \
1149                     (!((((uint32_t)(src)\
1150                     << 13) & ~0x00002000U)))
1151 #define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__SET(dst) \
1152                     (dst) = ((dst) &\
1153                     ~0x00002000U) | ((uint32_t)(1) << 13)
1154 #define EMAC_REGS__NETWORK_CONFIG__PAUSE_ENABLE__CLR(dst) \
1155                     (dst) = ((dst) &\
1156                     ~0x00002000U) | ((uint32_t)(0) << 13)
1157 
1158 /* macros for field receive_buffer_offset */
1159 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__SHIFT              14
1160 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__WIDTH               2
1161 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__MASK      0x0000c000U
1162 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__RESET               0
1163 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__READ(src) \
1164                     (((uint32_t)(src)\
1165                     & 0x0000c000U) >> 14)
1166 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__WRITE(src) \
1167                     (((uint32_t)(src)\
1168                     << 14) & 0x0000c000U)
1169 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__MODIFY(dst, src) \
1170                     (dst) = ((dst) &\
1171                     ~0x0000c000U) | (((uint32_t)(src) <<\
1172                     14) & 0x0000c000U)
1173 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_BUFFER_OFFSET__VERIFY(src) \
1174                     (!((((uint32_t)(src)\
1175                     << 14) & ~0x0000c000U)))
1176 
1177 /* macros for field length_field_error_frame_discard */
1178 #define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__SHIFT   16
1179 #define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__WIDTH    1
1180 #define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__MASK \
1181                     0x00010000U
1182 #define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__RESET    0
1183 #define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__READ(src) \
1184                     (((uint32_t)(src)\
1185                     & 0x00010000U) >> 16)
1186 #define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__WRITE(src) \
1187                     (((uint32_t)(src)\
1188                     << 16) & 0x00010000U)
1189 #define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__MODIFY(dst, src) \
1190                     (dst) = ((dst) &\
1191                     ~0x00010000U) | (((uint32_t)(src) <<\
1192                     16) & 0x00010000U)
1193 #define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__VERIFY(src) \
1194                     (!((((uint32_t)(src)\
1195                     << 16) & ~0x00010000U)))
1196 #define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__SET(dst) \
1197                     (dst) = ((dst) &\
1198                     ~0x00010000U) | ((uint32_t)(1) << 16)
1199 #define EMAC_REGS__NETWORK_CONFIG__LENGTH_FIELD_ERROR_FRAME_DISCARD__CLR(dst) \
1200                     (dst) = ((dst) &\
1201                     ~0x00010000U) | ((uint32_t)(0) << 16)
1202 
1203 /* macros for field fcs_remove */
1204 #define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__SHIFT                         17
1205 #define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__WIDTH                          1
1206 #define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__MASK                 0x00020000U
1207 #define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__RESET                          0
1208 #define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__READ(src) \
1209                     (((uint32_t)(src)\
1210                     & 0x00020000U) >> 17)
1211 #define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__WRITE(src) \
1212                     (((uint32_t)(src)\
1213                     << 17) & 0x00020000U)
1214 #define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__MODIFY(dst, src) \
1215                     (dst) = ((dst) &\
1216                     ~0x00020000U) | (((uint32_t)(src) <<\
1217                     17) & 0x00020000U)
1218 #define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__VERIFY(src) \
1219                     (!((((uint32_t)(src)\
1220                     << 17) & ~0x00020000U)))
1221 #define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__SET(dst) \
1222                     (dst) = ((dst) &\
1223                     ~0x00020000U) | ((uint32_t)(1) << 17)
1224 #define EMAC_REGS__NETWORK_CONFIG__FCS_REMOVE__CLR(dst) \
1225                     (dst) = ((dst) &\
1226                     ~0x00020000U) | ((uint32_t)(0) << 17)
1227 
1228 /* macros for field mdc_clock_division */
1229 #define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__SHIFT                 18
1230 #define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__WIDTH                  3
1231 #define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__MASK         0x001c0000U
1232 #define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__RESET                  2
1233 #define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__READ(src) \
1234                     (((uint32_t)(src)\
1235                     & 0x001c0000U) >> 18)
1236 #define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__WRITE(src) \
1237                     (((uint32_t)(src)\
1238                     << 18) & 0x001c0000U)
1239 #define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__MODIFY(dst, src) \
1240                     (dst) = ((dst) &\
1241                     ~0x001c0000U) | (((uint32_t)(src) <<\
1242                     18) & 0x001c0000U)
1243 #define EMAC_REGS__NETWORK_CONFIG__MDC_CLOCK_DIVISION__VERIFY(src) \
1244                     (!((((uint32_t)(src)\
1245                     << 18) & ~0x001c0000U)))
1246 
1247 /* macros for field data_bus_width */
1248 #define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__SHIFT                     21
1249 #define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__WIDTH                      2
1250 #define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__MASK             0x00600000U
1251 #define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__RESET                      0
1252 #define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__READ(src) \
1253                     (((uint32_t)(src)\
1254                     & 0x00600000U) >> 21)
1255 #define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__WRITE(src) \
1256                     (((uint32_t)(src)\
1257                     << 21) & 0x00600000U)
1258 #define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__MODIFY(dst, src) \
1259                     (dst) = ((dst) &\
1260                     ~0x00600000U) | (((uint32_t)(src) <<\
1261                     21) & 0x00600000U)
1262 #define EMAC_REGS__NETWORK_CONFIG__DATA_BUS_WIDTH__VERIFY(src) \
1263                     (!((((uint32_t)(src)\
1264                     << 21) & ~0x00600000U)))
1265 
1266 /* macros for field disable_copy_of_pause_frames */
1267 #define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__SHIFT       23
1268 #define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__WIDTH        1
1269 #define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__MASK \
1270                     0x00800000U
1271 #define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__RESET        0
1272 #define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__READ(src) \
1273                     (((uint32_t)(src)\
1274                     & 0x00800000U) >> 23)
1275 #define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__WRITE(src) \
1276                     (((uint32_t)(src)\
1277                     << 23) & 0x00800000U)
1278 #define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__MODIFY(dst, src) \
1279                     (dst) = ((dst) &\
1280                     ~0x00800000U) | (((uint32_t)(src) <<\
1281                     23) & 0x00800000U)
1282 #define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__VERIFY(src) \
1283                     (!((((uint32_t)(src)\
1284                     << 23) & ~0x00800000U)))
1285 #define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__SET(dst) \
1286                     (dst) = ((dst) &\
1287                     ~0x00800000U) | ((uint32_t)(1) << 23)
1288 #define EMAC_REGS__NETWORK_CONFIG__DISABLE_COPY_OF_PAUSE_FRAMES__CLR(dst) \
1289                     (dst) = ((dst) &\
1290                     ~0x00800000U) | ((uint32_t)(0) << 23)
1291 
1292 /* macros for field receive_checksum_offload_enable */
1293 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__SHIFT    24
1294 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__WIDTH     1
1295 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__MASK \
1296                     0x01000000U
1297 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__RESET     0
1298 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__READ(src) \
1299                     (((uint32_t)(src)\
1300                     & 0x01000000U) >> 24)
1301 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__WRITE(src) \
1302                     (((uint32_t)(src)\
1303                     << 24) & 0x01000000U)
1304 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__MODIFY(dst, src) \
1305                     (dst) = ((dst) &\
1306                     ~0x01000000U) | (((uint32_t)(src) <<\
1307                     24) & 0x01000000U)
1308 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__VERIFY(src) \
1309                     (!((((uint32_t)(src)\
1310                     << 24) & ~0x01000000U)))
1311 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__SET(dst) \
1312                     (dst) = ((dst) &\
1313                     ~0x01000000U) | ((uint32_t)(1) << 24)
1314 #define EMAC_REGS__NETWORK_CONFIG__RECEIVE_CHECKSUM_OFFLOAD_ENABLE__CLR(dst) \
1315                     (dst) = ((dst) &\
1316                     ~0x01000000U) | ((uint32_t)(0) << 24)
1317 
1318 /* macros for field en_half_duplex_rx */
1319 #define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__SHIFT                  25
1320 #define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__WIDTH                   1
1321 #define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__MASK          0x02000000U
1322 #define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__RESET                   0
1323 #define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__READ(src) \
1324                     (((uint32_t)(src)\
1325                     & 0x02000000U) >> 25)
1326 #define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__WRITE(src) \
1327                     (((uint32_t)(src)\
1328                     << 25) & 0x02000000U)
1329 #define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__MODIFY(dst, src) \
1330                     (dst) = ((dst) &\
1331                     ~0x02000000U) | (((uint32_t)(src) <<\
1332                     25) & 0x02000000U)
1333 #define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__VERIFY(src) \
1334                     (!((((uint32_t)(src)\
1335                     << 25) & ~0x02000000U)))
1336 #define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__SET(dst) \
1337                     (dst) = ((dst) &\
1338                     ~0x02000000U) | ((uint32_t)(1) << 25)
1339 #define EMAC_REGS__NETWORK_CONFIG__EN_HALF_DUPLEX_RX__CLR(dst) \
1340                     (dst) = ((dst) &\
1341                     ~0x02000000U) | ((uint32_t)(0) << 25)
1342 
1343 /* macros for field ignore_rx_fcs */
1344 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__SHIFT                      26
1345 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__WIDTH                       1
1346 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__MASK              0x04000000U
1347 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__RESET                       0
1348 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__READ(src) \
1349                     (((uint32_t)(src)\
1350                     & 0x04000000U) >> 26)
1351 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__WRITE(src) \
1352                     (((uint32_t)(src)\
1353                     << 26) & 0x04000000U)
1354 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__MODIFY(dst, src) \
1355                     (dst) = ((dst) &\
1356                     ~0x04000000U) | (((uint32_t)(src) <<\
1357                     26) & 0x04000000U)
1358 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__VERIFY(src) \
1359                     (!((((uint32_t)(src)\
1360                     << 26) & ~0x04000000U)))
1361 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__SET(dst) \
1362                     (dst) = ((dst) &\
1363                     ~0x04000000U) | ((uint32_t)(1) << 26)
1364 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_RX_FCS__CLR(dst) \
1365                     (dst) = ((dst) &\
1366                     ~0x04000000U) | ((uint32_t)(0) << 26)
1367 
1368 /* macros for field sgmii_mode_enable */
1369 #define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__SHIFT                  27
1370 #define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__WIDTH                   1
1371 #define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__MASK          0x08000000U
1372 #define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__RESET                   0
1373 #define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__READ(src) \
1374                     (((uint32_t)(src)\
1375                     & 0x08000000U) >> 27)
1376 #define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__WRITE(src) \
1377                     (((uint32_t)(src)\
1378                     << 27) & 0x08000000U)
1379 #define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__MODIFY(dst, src) \
1380                     (dst) = ((dst) &\
1381                     ~0x08000000U) | (((uint32_t)(src) <<\
1382                     27) & 0x08000000U)
1383 #define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__VERIFY(src) \
1384                     (!((((uint32_t)(src)\
1385                     << 27) & ~0x08000000U)))
1386 #define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__SET(dst) \
1387                     (dst) = ((dst) &\
1388                     ~0x08000000U) | ((uint32_t)(1) << 27)
1389 #define EMAC_REGS__NETWORK_CONFIG__SGMII_MODE_ENABLE__CLR(dst) \
1390                     (dst) = ((dst) &\
1391                     ~0x08000000U) | ((uint32_t)(0) << 27)
1392 
1393 /* macros for field ipg_stretch_enable */
1394 #define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__SHIFT                 28
1395 #define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__WIDTH                  1
1396 #define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__MASK         0x10000000U
1397 #define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__RESET                  0
1398 #define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__READ(src) \
1399                     (((uint32_t)(src)\
1400                     & 0x10000000U) >> 28)
1401 #define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__WRITE(src) \
1402                     (((uint32_t)(src)\
1403                     << 28) & 0x10000000U)
1404 #define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__MODIFY(dst, src) \
1405                     (dst) = ((dst) &\
1406                     ~0x10000000U) | (((uint32_t)(src) <<\
1407                     28) & 0x10000000U)
1408 #define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__VERIFY(src) \
1409                     (!((((uint32_t)(src)\
1410                     << 28) & ~0x10000000U)))
1411 #define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__SET(dst) \
1412                     (dst) = ((dst) &\
1413                     ~0x10000000U) | ((uint32_t)(1) << 28)
1414 #define EMAC_REGS__NETWORK_CONFIG__IPG_STRETCH_ENABLE__CLR(dst) \
1415                     (dst) = ((dst) &\
1416                     ~0x10000000U) | ((uint32_t)(0) << 28)
1417 
1418 /* macros for field nsp_change */
1419 #define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__SHIFT                         29
1420 #define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__WIDTH                          1
1421 #define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__MASK                 0x20000000U
1422 #define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__RESET                          0
1423 #define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__READ(src) \
1424                     (((uint32_t)(src)\
1425                     & 0x20000000U) >> 29)
1426 #define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__WRITE(src) \
1427                     (((uint32_t)(src)\
1428                     << 29) & 0x20000000U)
1429 #define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__MODIFY(dst, src) \
1430                     (dst) = ((dst) &\
1431                     ~0x20000000U) | (((uint32_t)(src) <<\
1432                     29) & 0x20000000U)
1433 #define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__VERIFY(src) \
1434                     (!((((uint32_t)(src)\
1435                     << 29) & ~0x20000000U)))
1436 #define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__SET(dst) \
1437                     (dst) = ((dst) &\
1438                     ~0x20000000U) | ((uint32_t)(1) << 29)
1439 #define EMAC_REGS__NETWORK_CONFIG__NSP_CHANGE__CLR(dst) \
1440                     (dst) = ((dst) &\
1441                     ~0x20000000U) | ((uint32_t)(0) << 29)
1442 
1443 /* macros for field ignore_ipg_rx_er */
1444 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__SHIFT                   30
1445 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__WIDTH                    1
1446 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__MASK           0x40000000U
1447 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__RESET                    0
1448 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__READ(src) \
1449                     (((uint32_t)(src)\
1450                     & 0x40000000U) >> 30)
1451 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__WRITE(src) \
1452                     (((uint32_t)(src)\
1453                     << 30) & 0x40000000U)
1454 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__MODIFY(dst, src) \
1455                     (dst) = ((dst) &\
1456                     ~0x40000000U) | (((uint32_t)(src) <<\
1457                     30) & 0x40000000U)
1458 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__VERIFY(src) \
1459                     (!((((uint32_t)(src)\
1460                     << 30) & ~0x40000000U)))
1461 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__SET(dst) \
1462                     (dst) = ((dst) &\
1463                     ~0x40000000U) | ((uint32_t)(1) << 30)
1464 #define EMAC_REGS__NETWORK_CONFIG__IGNORE_IPG_RX_ER__CLR(dst) \
1465                     (dst) = ((dst) &\
1466                     ~0x40000000U) | ((uint32_t)(0) << 30)
1467 
1468 /* macros for field uni_direction_enable */
1469 #define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__SHIFT               31
1470 #define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__WIDTH                1
1471 #define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__MASK       0x80000000U
1472 #define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__RESET                0
1473 #define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__READ(src) \
1474                     (((uint32_t)(src)\
1475                     & 0x80000000U) >> 31)
1476 #define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__WRITE(src) \
1477                     (((uint32_t)(src)\
1478                     << 31) & 0x80000000U)
1479 #define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__MODIFY(dst, src) \
1480                     (dst) = ((dst) &\
1481                     ~0x80000000U) | (((uint32_t)(src) <<\
1482                     31) & 0x80000000U)
1483 #define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__VERIFY(src) \
1484                     (!((((uint32_t)(src)\
1485                     << 31) & ~0x80000000U)))
1486 #define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__SET(dst) \
1487                     (dst) = ((dst) &\
1488                     ~0x80000000U) | ((uint32_t)(1) << 31)
1489 #define EMAC_REGS__NETWORK_CONFIG__UNI_DIRECTION_ENABLE__CLR(dst) \
1490                     (dst) = ((dst) &\
1491                     ~0x80000000U) | ((uint32_t)(0) << 31)
1492 #define EMAC_REGS__NETWORK_CONFIG__TYPE                                uint32_t
1493 #define EMAC_REGS__NETWORK_CONFIG__READ                             0xffffffffU
1494 #define EMAC_REGS__NETWORK_CONFIG__WRITE                            0xffffffffU
1495 
1496 #endif /* __EMAC_REGS__NETWORK_CONFIG_MACRO__ */
1497 
1498 
1499 /* macros for network_config */
1500 #define INST_NETWORK_CONFIG__NUM                                              1
1501 
1502 /* macros for BlueprintGlobalNameSpace::emac_regs::network_status */
1503 #ifndef __EMAC_REGS__NETWORK_STATUS_MACRO__
1504 #define __EMAC_REGS__NETWORK_STATUS_MACRO__
1505 
1506 /* macros for field pcs_link_state */
1507 #define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__SHIFT                      0
1508 #define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__WIDTH                      1
1509 #define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__MASK             0x00000001U
1510 #define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__RESET                      0
1511 #define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__READ(src) \
1512                     ((uint32_t)(src)\
1513                     & 0x00000001U)
1514 #define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__SET(dst) \
1515                     (dst) = ((dst) &\
1516                     ~0x00000001U) | (uint32_t)(1)
1517 #define EMAC_REGS__NETWORK_STATUS__PCS_LINK_STATE__CLR(dst) \
1518                     (dst) = ((dst) &\
1519                     ~0x00000001U) | (uint32_t)(0)
1520 
1521 /* macros for field mdio_in */
1522 #define EMAC_REGS__NETWORK_STATUS__MDIO_IN__SHIFT                             1
1523 #define EMAC_REGS__NETWORK_STATUS__MDIO_IN__WIDTH                             1
1524 #define EMAC_REGS__NETWORK_STATUS__MDIO_IN__MASK                    0x00000002U
1525 #define EMAC_REGS__NETWORK_STATUS__MDIO_IN__RESET                             0
1526 #define EMAC_REGS__NETWORK_STATUS__MDIO_IN__READ(src) \
1527                     (((uint32_t)(src)\
1528                     & 0x00000002U) >> 1)
1529 #define EMAC_REGS__NETWORK_STATUS__MDIO_IN__SET(dst) \
1530                     (dst) = ((dst) &\
1531                     ~0x00000002U) | ((uint32_t)(1) << 1)
1532 #define EMAC_REGS__NETWORK_STATUS__MDIO_IN__CLR(dst) \
1533                     (dst) = ((dst) &\
1534                     ~0x00000002U) | ((uint32_t)(0) << 1)
1535 
1536 /* macros for field man_done */
1537 #define EMAC_REGS__NETWORK_STATUS__MAN_DONE__SHIFT                            2
1538 #define EMAC_REGS__NETWORK_STATUS__MAN_DONE__WIDTH                            1
1539 #define EMAC_REGS__NETWORK_STATUS__MAN_DONE__MASK                   0x00000004U
1540 #define EMAC_REGS__NETWORK_STATUS__MAN_DONE__RESET                            1
1541 #define EMAC_REGS__NETWORK_STATUS__MAN_DONE__READ(src) \
1542                     (((uint32_t)(src)\
1543                     & 0x00000004U) >> 2)
1544 #define EMAC_REGS__NETWORK_STATUS__MAN_DONE__SET(dst) \
1545                     (dst) = ((dst) &\
1546                     ~0x00000004U) | ((uint32_t)(1) << 2)
1547 #define EMAC_REGS__NETWORK_STATUS__MAN_DONE__CLR(dst) \
1548                     (dst) = ((dst) &\
1549                     ~0x00000004U) | ((uint32_t)(0) << 2)
1550 
1551 /* macros for field mac_full_duplex */
1552 #define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__SHIFT                     3
1553 #define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__WIDTH                     1
1554 #define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__MASK            0x00000008U
1555 #define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__RESET                     0
1556 #define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__READ(src) \
1557                     (((uint32_t)(src)\
1558                     & 0x00000008U) >> 3)
1559 #define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__SET(dst) \
1560                     (dst) = ((dst) &\
1561                     ~0x00000008U) | ((uint32_t)(1) << 3)
1562 #define EMAC_REGS__NETWORK_STATUS__MAC_FULL_DUPLEX__CLR(dst) \
1563                     (dst) = ((dst) &\
1564                     ~0x00000008U) | ((uint32_t)(0) << 3)
1565 
1566 /* macros for field mac_pause_rx_en */
1567 #define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__SHIFT                     4
1568 #define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__WIDTH                     1
1569 #define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__MASK            0x00000010U
1570 #define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__RESET                     0
1571 #define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__READ(src) \
1572                     (((uint32_t)(src)\
1573                     & 0x00000010U) >> 4)
1574 #define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__SET(dst) \
1575                     (dst) = ((dst) &\
1576                     ~0x00000010U) | ((uint32_t)(1) << 4)
1577 #define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_RX_EN__CLR(dst) \
1578                     (dst) = ((dst) &\
1579                     ~0x00000010U) | ((uint32_t)(0) << 4)
1580 
1581 /* macros for field mac_pause_tx_en */
1582 #define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__SHIFT                     5
1583 #define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__WIDTH                     1
1584 #define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__MASK            0x00000020U
1585 #define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__RESET                     0
1586 #define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__READ(src) \
1587                     (((uint32_t)(src)\
1588                     & 0x00000020U) >> 5)
1589 #define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__SET(dst) \
1590                     (dst) = ((dst) &\
1591                     ~0x00000020U) | ((uint32_t)(1) << 5)
1592 #define EMAC_REGS__NETWORK_STATUS__MAC_PAUSE_TX_EN__CLR(dst) \
1593                     (dst) = ((dst) &\
1594                     ~0x00000020U) | ((uint32_t)(0) << 5)
1595 
1596 /* macros for field pfc_negotiate_pclk */
1597 #define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__SHIFT                  6
1598 #define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__WIDTH                  1
1599 #define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__MASK         0x00000040U
1600 #define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__RESET                  0
1601 #define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__READ(src) \
1602                     (((uint32_t)(src)\
1603                     & 0x00000040U) >> 6)
1604 #define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__SET(dst) \
1605                     (dst) = ((dst) &\
1606                     ~0x00000040U) | ((uint32_t)(1) << 6)
1607 #define EMAC_REGS__NETWORK_STATUS__PFC_NEGOTIATE_PCLK__CLR(dst) \
1608                     (dst) = ((dst) &\
1609                     ~0x00000040U) | ((uint32_t)(0) << 6)
1610 
1611 /* macros for field lpi_indicate_pclk */
1612 #define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__SHIFT                   7
1613 #define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__WIDTH                   1
1614 #define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__MASK          0x00000080U
1615 #define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__RESET                   0
1616 #define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__READ(src) \
1617                     (((uint32_t)(src)\
1618                     & 0x00000080U) >> 7)
1619 #define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__SET(dst) \
1620                     (dst) = ((dst) &\
1621                     ~0x00000080U) | ((uint32_t)(1) << 7)
1622 #define EMAC_REGS__NETWORK_STATUS__LPI_INDICATE_PCLK__CLR(dst) \
1623                     (dst) = ((dst) &\
1624                     ~0x00000080U) | ((uint32_t)(0) << 7)
1625 
1626 /* macros for field reserved_31_8 */
1627 #define EMAC_REGS__NETWORK_STATUS__RESERVED_31_8__SHIFT                       8
1628 #define EMAC_REGS__NETWORK_STATUS__RESERVED_31_8__WIDTH                      24
1629 #define EMAC_REGS__NETWORK_STATUS__RESERVED_31_8__MASK              0xffffff00U
1630 #define EMAC_REGS__NETWORK_STATUS__RESERVED_31_8__RESET                       0
1631 #define EMAC_REGS__NETWORK_STATUS__RESERVED_31_8__READ(src) \
1632                     (((uint32_t)(src)\
1633                     & 0xffffff00U) >> 8)
1634 #define EMAC_REGS__NETWORK_STATUS__TYPE                                uint32_t
1635 #define EMAC_REGS__NETWORK_STATUS__READ                             0xffffffffU
1636 
1637 #endif /* __EMAC_REGS__NETWORK_STATUS_MACRO__ */
1638 
1639 
1640 /* macros for network_status */
1641 #define INST_NETWORK_STATUS__NUM                                              1
1642 
1643 /* macros for BlueprintGlobalNameSpace::emac_regs::user_io_register */
1644 #ifndef __EMAC_REGS__USER_IO_REGISTER_MACRO__
1645 #define __EMAC_REGS__USER_IO_REGISTER_MACRO__
1646 
1647 /* macros for field user_programmable_outputs */
1648 #define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__SHIFT         0
1649 #define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__WIDTH        16
1650 #define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__MASK \
1651                     0x0000ffffU
1652 #define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__RESET         0
1653 #define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__READ(src) \
1654                     ((uint32_t)(src)\
1655                     & 0x0000ffffU)
1656 #define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__WRITE(src) \
1657                     ((uint32_t)(src)\
1658                     & 0x0000ffffU)
1659 #define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__MODIFY(dst, src) \
1660                     (dst) = ((dst) &\
1661                     ~0x0000ffffU) | ((uint32_t)(src) &\
1662                     0x0000ffffU)
1663 #define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_OUTPUTS__VERIFY(src) \
1664                     (!(((uint32_t)(src)\
1665                     & ~0x0000ffffU)))
1666 
1667 /* macros for field user_programmable_inputs */
1668 #define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_INPUTS__SHIFT         16
1669 #define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_INPUTS__WIDTH         16
1670 #define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_INPUTS__MASK 0xffff0000U
1671 #define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_INPUTS__RESET          0
1672 #define EMAC_REGS__USER_IO_REGISTER__USER_PROGRAMMABLE_INPUTS__READ(src) \
1673                     (((uint32_t)(src)\
1674                     & 0xffff0000U) >> 16)
1675 #define EMAC_REGS__USER_IO_REGISTER__TYPE                              uint32_t
1676 #define EMAC_REGS__USER_IO_REGISTER__READ                           0xffffffffU
1677 #define EMAC_REGS__USER_IO_REGISTER__WRITE                          0xffffffffU
1678 
1679 #endif /* __EMAC_REGS__USER_IO_REGISTER_MACRO__ */
1680 
1681 
1682 /* macros for user_io_register */
1683 #define INST_USER_IO_REGISTER__NUM                                            1
1684 
1685 /* macros for BlueprintGlobalNameSpace::emac_regs::dma_config */
1686 #ifndef __EMAC_REGS__DMA_CONFIG_MACRO__
1687 #define __EMAC_REGS__DMA_CONFIG_MACRO__
1688 
1689 /* macros for field amba_burst_length */
1690 #define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__SHIFT                       0
1691 #define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__WIDTH                       5
1692 #define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__MASK              0x0000001fU
1693 #define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__RESET                       4
1694 #define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__READ(src) \
1695                     ((uint32_t)(src)\
1696                     & 0x0000001fU)
1697 #define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__WRITE(src) \
1698                     ((uint32_t)(src)\
1699                     & 0x0000001fU)
1700 #define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__MODIFY(dst, src) \
1701                     (dst) = ((dst) &\
1702                     ~0x0000001fU) | ((uint32_t)(src) &\
1703                     0x0000001fU)
1704 #define EMAC_REGS__DMA_CONFIG__AMBA_BURST_LENGTH__VERIFY(src) \
1705                     (!(((uint32_t)(src)\
1706                     & ~0x0000001fU)))
1707 
1708 /* macros for field hdr_data_splitting_en */
1709 #define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__SHIFT                   5
1710 #define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__WIDTH                   1
1711 #define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__MASK          0x00000020U
1712 #define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__RESET                 0b0
1713 #define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__READ(src) \
1714                     (((uint32_t)(src)\
1715                     & 0x00000020U) >> 5)
1716 #define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__WRITE(src) \
1717                     (((uint32_t)(src)\
1718                     << 5) & 0x00000020U)
1719 #define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__MODIFY(dst, src) \
1720                     (dst) = ((dst) &\
1721                     ~0x00000020U) | (((uint32_t)(src) <<\
1722                     5) & 0x00000020U)
1723 #define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__VERIFY(src) \
1724                     (!((((uint32_t)(src)\
1725                     << 5) & ~0x00000020U)))
1726 #define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__SET(dst) \
1727                     (dst) = ((dst) &\
1728                     ~0x00000020U) | ((uint32_t)(1) << 5)
1729 #define EMAC_REGS__DMA_CONFIG__HDR_DATA_SPLITTING_EN__CLR(dst) \
1730                     (dst) = ((dst) &\
1731                     ~0x00000020U) | ((uint32_t)(0) << 5)
1732 
1733 /* macros for field endian_swap_management */
1734 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__SHIFT                  6
1735 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__WIDTH                  1
1736 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__MASK         0x00000040U
1737 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__RESET                  1
1738 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__READ(src) \
1739                     (((uint32_t)(src)\
1740                     & 0x00000040U) >> 6)
1741 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__WRITE(src) \
1742                     (((uint32_t)(src)\
1743                     << 6) & 0x00000040U)
1744 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__MODIFY(dst, src) \
1745                     (dst) = ((dst) &\
1746                     ~0x00000040U) | (((uint32_t)(src) <<\
1747                     6) & 0x00000040U)
1748 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__VERIFY(src) \
1749                     (!((((uint32_t)(src)\
1750                     << 6) & ~0x00000040U)))
1751 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__SET(dst) \
1752                     (dst) = ((dst) &\
1753                     ~0x00000040U) | ((uint32_t)(1) << 6)
1754 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_MANAGEMENT__CLR(dst) \
1755                     (dst) = ((dst) &\
1756                     ~0x00000040U) | ((uint32_t)(0) << 6)
1757 
1758 /* macros for field endian_swap_packet */
1759 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__SHIFT                      7
1760 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__WIDTH                      1
1761 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__MASK             0x00000080U
1762 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__RESET                      1
1763 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__READ(src) \
1764                     (((uint32_t)(src)\
1765                     & 0x00000080U) >> 7)
1766 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__WRITE(src) \
1767                     (((uint32_t)(src)\
1768                     << 7) & 0x00000080U)
1769 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__MODIFY(dst, src) \
1770                     (dst) = ((dst) &\
1771                     ~0x00000080U) | (((uint32_t)(src) <<\
1772                     7) & 0x00000080U)
1773 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__VERIFY(src) \
1774                     (!((((uint32_t)(src)\
1775                     << 7) & ~0x00000080U)))
1776 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__SET(dst) \
1777                     (dst) = ((dst) &\
1778                     ~0x00000080U) | ((uint32_t)(1) << 7)
1779 #define EMAC_REGS__DMA_CONFIG__ENDIAN_SWAP_PACKET__CLR(dst) \
1780                     (dst) = ((dst) &\
1781                     ~0x00000080U) | ((uint32_t)(0) << 7)
1782 
1783 /* macros for field rx_pbuf_size */
1784 #define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__SHIFT                            8
1785 #define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__WIDTH                            2
1786 #define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__MASK                   0x00000300U
1787 #define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__RESET                            3
1788 #define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__READ(src) \
1789                     (((uint32_t)(src)\
1790                     & 0x00000300U) >> 8)
1791 #define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__WRITE(src) \
1792                     (((uint32_t)(src)\
1793                     << 8) & 0x00000300U)
1794 #define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__MODIFY(dst, src) \
1795                     (dst) = ((dst) &\
1796                     ~0x00000300U) | (((uint32_t)(src) <<\
1797                     8) & 0x00000300U)
1798 #define EMAC_REGS__DMA_CONFIG__RX_PBUF_SIZE__VERIFY(src) \
1799                     (!((((uint32_t)(src)\
1800                     << 8) & ~0x00000300U)))
1801 
1802 /* macros for field tx_pbuf_size */
1803 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__SHIFT                           10
1804 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__WIDTH                            1
1805 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__MASK                   0x00000400U
1806 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__RESET                            1
1807 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__READ(src) \
1808                     (((uint32_t)(src)\
1809                     & 0x00000400U) >> 10)
1810 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__WRITE(src) \
1811                     (((uint32_t)(src)\
1812                     << 10) & 0x00000400U)
1813 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__MODIFY(dst, src) \
1814                     (dst) = ((dst) &\
1815                     ~0x00000400U) | (((uint32_t)(src) <<\
1816                     10) & 0x00000400U)
1817 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__VERIFY(src) \
1818                     (!((((uint32_t)(src)\
1819                     << 10) & ~0x00000400U)))
1820 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__SET(dst) \
1821                     (dst) = ((dst) &\
1822                     ~0x00000400U) | ((uint32_t)(1) << 10)
1823 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_SIZE__CLR(dst) \
1824                     (dst) = ((dst) &\
1825                     ~0x00000400U) | ((uint32_t)(0) << 10)
1826 
1827 /* macros for field tx_pbuf_tcp_en */
1828 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__SHIFT                         11
1829 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__WIDTH                          1
1830 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__MASK                 0x00000800U
1831 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__RESET                          0
1832 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__READ(src) \
1833                     (((uint32_t)(src)\
1834                     & 0x00000800U) >> 11)
1835 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__WRITE(src) \
1836                     (((uint32_t)(src)\
1837                     << 11) & 0x00000800U)
1838 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__MODIFY(dst, src) \
1839                     (dst) = ((dst) &\
1840                     ~0x00000800U) | (((uint32_t)(src) <<\
1841                     11) & 0x00000800U)
1842 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__VERIFY(src) \
1843                     (!((((uint32_t)(src)\
1844                     << 11) & ~0x00000800U)))
1845 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__SET(dst) \
1846                     (dst) = ((dst) &\
1847                     ~0x00000800U) | ((uint32_t)(1) << 11)
1848 #define EMAC_REGS__DMA_CONFIG__TX_PBUF_TCP_EN__CLR(dst) \
1849                     (dst) = ((dst) &\
1850                     ~0x00000800U) | ((uint32_t)(0) << 11)
1851 
1852 /* macros for field infinite_last_dbuf_size_en */
1853 #define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__SHIFT             12
1854 #define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__WIDTH              1
1855 #define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__MASK     0x00001000U
1856 #define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__RESET              0
1857 #define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__READ(src) \
1858                     (((uint32_t)(src)\
1859                     & 0x00001000U) >> 12)
1860 #define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__WRITE(src) \
1861                     (((uint32_t)(src)\
1862                     << 12) & 0x00001000U)
1863 #define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__MODIFY(dst, src) \
1864                     (dst) = ((dst) &\
1865                     ~0x00001000U) | (((uint32_t)(src) <<\
1866                     12) & 0x00001000U)
1867 #define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__VERIFY(src) \
1868                     (!((((uint32_t)(src)\
1869                     << 12) & ~0x00001000U)))
1870 #define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__SET(dst) \
1871                     (dst) = ((dst) &\
1872                     ~0x00001000U) | ((uint32_t)(1) << 12)
1873 #define EMAC_REGS__DMA_CONFIG__INFINITE_LAST_DBUF_SIZE_EN__CLR(dst) \
1874                     (dst) = ((dst) &\
1875                     ~0x00001000U) | ((uint32_t)(0) << 12)
1876 
1877 /* macros for field crc_error_report */
1878 #define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__SHIFT                       13
1879 #define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__WIDTH                        1
1880 #define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__MASK               0x00002000U
1881 #define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__RESET                        0
1882 #define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__READ(src) \
1883                     (((uint32_t)(src)\
1884                     & 0x00002000U) >> 13)
1885 #define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__WRITE(src) \
1886                     (((uint32_t)(src)\
1887                     << 13) & 0x00002000U)
1888 #define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__MODIFY(dst, src) \
1889                     (dst) = ((dst) &\
1890                     ~0x00002000U) | (((uint32_t)(src) <<\
1891                     13) & 0x00002000U)
1892 #define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__VERIFY(src) \
1893                     (!((((uint32_t)(src)\
1894                     << 13) & ~0x00002000U)))
1895 #define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__SET(dst) \
1896                     (dst) = ((dst) &\
1897                     ~0x00002000U) | ((uint32_t)(1) << 13)
1898 #define EMAC_REGS__DMA_CONFIG__CRC_ERROR_REPORT__CLR(dst) \
1899                     (dst) = ((dst) &\
1900                     ~0x00002000U) | ((uint32_t)(0) << 13)
1901 
1902 /* macros for field reserved_15_14 */
1903 #define EMAC_REGS__DMA_CONFIG__RESERVED_15_14__SHIFT                         14
1904 #define EMAC_REGS__DMA_CONFIG__RESERVED_15_14__WIDTH                          2
1905 #define EMAC_REGS__DMA_CONFIG__RESERVED_15_14__MASK                 0x0000c000U
1906 #define EMAC_REGS__DMA_CONFIG__RESERVED_15_14__RESET                          0
1907 #define EMAC_REGS__DMA_CONFIG__RESERVED_15_14__READ(src) \
1908                     (((uint32_t)(src)\
1909                     & 0x0000c000U) >> 14)
1910 
1911 /* macros for field rx_buf_size */
1912 #define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__SHIFT                            16
1913 #define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__WIDTH                             8
1914 #define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__MASK                    0x00ff0000U
1915 #define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__RESET                             2
1916 #define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__READ(src) \
1917                     (((uint32_t)(src)\
1918                     & 0x00ff0000U) >> 16)
1919 #define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__WRITE(src) \
1920                     (((uint32_t)(src)\
1921                     << 16) & 0x00ff0000U)
1922 #define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__MODIFY(dst, src) \
1923                     (dst) = ((dst) &\
1924                     ~0x00ff0000U) | (((uint32_t)(src) <<\
1925                     16) & 0x00ff0000U)
1926 #define EMAC_REGS__DMA_CONFIG__RX_BUF_SIZE__VERIFY(src) \
1927                     (!((((uint32_t)(src)\
1928                     << 16) & ~0x00ff0000U)))
1929 
1930 /* macros for field force_discard_on_err */
1931 #define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__SHIFT                   24
1932 #define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__WIDTH                    1
1933 #define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__MASK           0x01000000U
1934 #define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__RESET                    0
1935 #define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__READ(src) \
1936                     (((uint32_t)(src)\
1937                     & 0x01000000U) >> 24)
1938 #define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__WRITE(src) \
1939                     (((uint32_t)(src)\
1940                     << 24) & 0x01000000U)
1941 #define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__MODIFY(dst, src) \
1942                     (dst) = ((dst) &\
1943                     ~0x01000000U) | (((uint32_t)(src) <<\
1944                     24) & 0x01000000U)
1945 #define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__VERIFY(src) \
1946                     (!((((uint32_t)(src)\
1947                     << 24) & ~0x01000000U)))
1948 #define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__SET(dst) \
1949                     (dst) = ((dst) &\
1950                     ~0x01000000U) | ((uint32_t)(1) << 24)
1951 #define EMAC_REGS__DMA_CONFIG__FORCE_DISCARD_ON_ERR__CLR(dst) \
1952                     (dst) = ((dst) &\
1953                     ~0x01000000U) | ((uint32_t)(0) << 24)
1954 
1955 /* macros for field force_max_amba_burst_rx */
1956 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__SHIFT                25
1957 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__WIDTH                 1
1958 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__MASK        0x02000000U
1959 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__RESET                 0
1960 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__READ(src) \
1961                     (((uint32_t)(src)\
1962                     & 0x02000000U) >> 25)
1963 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__WRITE(src) \
1964                     (((uint32_t)(src)\
1965                     << 25) & 0x02000000U)
1966 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__MODIFY(dst, src) \
1967                     (dst) = ((dst) &\
1968                     ~0x02000000U) | (((uint32_t)(src) <<\
1969                     25) & 0x02000000U)
1970 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__VERIFY(src) \
1971                     (!((((uint32_t)(src)\
1972                     << 25) & ~0x02000000U)))
1973 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__SET(dst) \
1974                     (dst) = ((dst) &\
1975                     ~0x02000000U) | ((uint32_t)(1) << 25)
1976 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_RX__CLR(dst) \
1977                     (dst) = ((dst) &\
1978                     ~0x02000000U) | ((uint32_t)(0) << 25)
1979 
1980 /* macros for field force_max_amba_burst_tx */
1981 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__SHIFT                26
1982 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__WIDTH                 1
1983 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__MASK        0x04000000U
1984 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__RESET                 0
1985 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__READ(src) \
1986                     (((uint32_t)(src)\
1987                     & 0x04000000U) >> 26)
1988 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__WRITE(src) \
1989                     (((uint32_t)(src)\
1990                     << 26) & 0x04000000U)
1991 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__MODIFY(dst, src) \
1992                     (dst) = ((dst) &\
1993                     ~0x04000000U) | (((uint32_t)(src) <<\
1994                     26) & 0x04000000U)
1995 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__VERIFY(src) \
1996                     (!((((uint32_t)(src)\
1997                     << 26) & ~0x04000000U)))
1998 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__SET(dst) \
1999                     (dst) = ((dst) &\
2000                     ~0x04000000U) | ((uint32_t)(1) << 26)
2001 #define EMAC_REGS__DMA_CONFIG__FORCE_MAX_AMBA_BURST_TX__CLR(dst) \
2002                     (dst) = ((dst) &\
2003                     ~0x04000000U) | ((uint32_t)(0) << 26)
2004 
2005 /* macros for field reserved_27 */
2006 #define EMAC_REGS__DMA_CONFIG__RESERVED_27__SHIFT                            27
2007 #define EMAC_REGS__DMA_CONFIG__RESERVED_27__WIDTH                             1
2008 #define EMAC_REGS__DMA_CONFIG__RESERVED_27__MASK                    0x08000000U
2009 #define EMAC_REGS__DMA_CONFIG__RESERVED_27__RESET                             0
2010 #define EMAC_REGS__DMA_CONFIG__RESERVED_27__READ(src) \
2011                     (((uint32_t)(src)\
2012                     & 0x08000000U) >> 27)
2013 #define EMAC_REGS__DMA_CONFIG__RESERVED_27__SET(dst) \
2014                     (dst) = ((dst) &\
2015                     ~0x08000000U) | ((uint32_t)(1) << 27)
2016 #define EMAC_REGS__DMA_CONFIG__RESERVED_27__CLR(dst) \
2017                     (dst) = ((dst) &\
2018                     ~0x08000000U) | ((uint32_t)(0) << 27)
2019 
2020 /* macros for field rx_bd_extended_mode_en */
2021 #define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__SHIFT                 28
2022 #define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__WIDTH                  1
2023 #define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__MASK         0x10000000U
2024 #define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__RESET                  0
2025 #define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__READ(src) \
2026                     (((uint32_t)(src)\
2027                     & 0x10000000U) >> 28)
2028 #define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__WRITE(src) \
2029                     (((uint32_t)(src)\
2030                     << 28) & 0x10000000U)
2031 #define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__MODIFY(dst, src) \
2032                     (dst) = ((dst) &\
2033                     ~0x10000000U) | (((uint32_t)(src) <<\
2034                     28) & 0x10000000U)
2035 #define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__VERIFY(src) \
2036                     (!((((uint32_t)(src)\
2037                     << 28) & ~0x10000000U)))
2038 #define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__SET(dst) \
2039                     (dst) = ((dst) &\
2040                     ~0x10000000U) | ((uint32_t)(1) << 28)
2041 #define EMAC_REGS__DMA_CONFIG__RX_BD_EXTENDED_MODE_EN__CLR(dst) \
2042                     (dst) = ((dst) &\
2043                     ~0x10000000U) | ((uint32_t)(0) << 28)
2044 
2045 /* macros for field tx_bd_extended_mode_en */
2046 #define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__SHIFT                 29
2047 #define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__WIDTH                  1
2048 #define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__MASK         0x20000000U
2049 #define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__RESET                  0
2050 #define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__READ(src) \
2051                     (((uint32_t)(src)\
2052                     & 0x20000000U) >> 29)
2053 #define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__WRITE(src) \
2054                     (((uint32_t)(src)\
2055                     << 29) & 0x20000000U)
2056 #define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__MODIFY(dst, src) \
2057                     (dst) = ((dst) &\
2058                     ~0x20000000U) | (((uint32_t)(src) <<\
2059                     29) & 0x20000000U)
2060 #define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__VERIFY(src) \
2061                     (!((((uint32_t)(src)\
2062                     << 29) & ~0x20000000U)))
2063 #define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__SET(dst) \
2064                     (dst) = ((dst) &\
2065                     ~0x20000000U) | ((uint32_t)(1) << 29)
2066 #define EMAC_REGS__DMA_CONFIG__TX_BD_EXTENDED_MODE_EN__CLR(dst) \
2067                     (dst) = ((dst) &\
2068                     ~0x20000000U) | ((uint32_t)(0) << 29)
2069 
2070 /* macros for field dma_addr_bus_width_1 */
2071 #define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__SHIFT                   30
2072 #define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__WIDTH                    1
2073 #define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__MASK           0x40000000U
2074 #define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__RESET                    0
2075 #define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__READ(src) \
2076                     (((uint32_t)(src)\
2077                     & 0x40000000U) >> 30)
2078 #define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__WRITE(src) \
2079                     (((uint32_t)(src)\
2080                     << 30) & 0x40000000U)
2081 #define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__MODIFY(dst, src) \
2082                     (dst) = ((dst) &\
2083                     ~0x40000000U) | (((uint32_t)(src) <<\
2084                     30) & 0x40000000U)
2085 #define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__VERIFY(src) \
2086                     (!((((uint32_t)(src)\
2087                     << 30) & ~0x40000000U)))
2088 #define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__SET(dst) \
2089                     (dst) = ((dst) &\
2090                     ~0x40000000U) | ((uint32_t)(1) << 30)
2091 #define EMAC_REGS__DMA_CONFIG__DMA_ADDR_BUS_WIDTH_1__CLR(dst) \
2092                     (dst) = ((dst) &\
2093                     ~0x40000000U) | ((uint32_t)(0) << 30)
2094 
2095 /* macros for field reserved_31 */
2096 #define EMAC_REGS__DMA_CONFIG__RESERVED_31__SHIFT                            31
2097 #define EMAC_REGS__DMA_CONFIG__RESERVED_31__WIDTH                             1
2098 #define EMAC_REGS__DMA_CONFIG__RESERVED_31__MASK                    0x80000000U
2099 #define EMAC_REGS__DMA_CONFIG__RESERVED_31__RESET                             0
2100 #define EMAC_REGS__DMA_CONFIG__RESERVED_31__READ(src) \
2101                     (((uint32_t)(src)\
2102                     & 0x80000000U) >> 31)
2103 #define EMAC_REGS__DMA_CONFIG__RESERVED_31__SET(dst) \
2104                     (dst) = ((dst) &\
2105                     ~0x80000000U) | ((uint32_t)(1) << 31)
2106 #define EMAC_REGS__DMA_CONFIG__RESERVED_31__CLR(dst) \
2107                     (dst) = ((dst) &\
2108                     ~0x80000000U) | ((uint32_t)(0) << 31)
2109 #define EMAC_REGS__DMA_CONFIG__TYPE                                    uint32_t
2110 #define EMAC_REGS__DMA_CONFIG__READ                                 0xffffffffU
2111 #define EMAC_REGS__DMA_CONFIG__WRITE                                0xffffffffU
2112 
2113 #endif /* __EMAC_REGS__DMA_CONFIG_MACRO__ */
2114 
2115 
2116 /* macros for dma_config */
2117 #define INST_DMA_CONFIG__NUM                                                  1
2118 
2119 /* macros for BlueprintGlobalNameSpace::emac_regs::transmit_status */
2120 #ifndef __EMAC_REGS__TRANSMIT_STATUS_MACRO__
2121 #define __EMAC_REGS__TRANSMIT_STATUS_MACRO__
2122 
2123 /* macros for field used_bit_read */
2124 #define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__SHIFT                      0
2125 #define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__WIDTH                      1
2126 #define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__MASK             0x00000001U
2127 #define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__RESET                      0
2128 #define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__READ(src) \
2129                     ((uint32_t)(src)\
2130                     & 0x00000001U)
2131 #define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__WRITE(src) \
2132                     ((uint32_t)(src)\
2133                     & 0x00000001U)
2134 #define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__MODIFY(dst, src) \
2135                     (dst) = ((dst) &\
2136                     ~0x00000001U) | ((uint32_t)(src) &\
2137                     0x00000001U)
2138 #define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__VERIFY(src) \
2139                     (!(((uint32_t)(src)\
2140                     & ~0x00000001U)))
2141 #define EMAC_REGS__TRANSMIT_STATUS__USED_BIT_READ__CLR(dst) \
2142                     (dst) = ((dst) &\
2143                     ~0x00000001U) | (uint32_t)(1)
2144 
2145 /* macros for field collision_occurred */
2146 #define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__SHIFT                 1
2147 #define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__WIDTH                 1
2148 #define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__MASK        0x00000002U
2149 #define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__RESET                 0
2150 #define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__READ(src) \
2151                     (((uint32_t)(src)\
2152                     & 0x00000002U) >> 1)
2153 #define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__WRITE(src) \
2154                     (((uint32_t)(src)\
2155                     << 1) & 0x00000002U)
2156 #define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__MODIFY(dst, src) \
2157                     (dst) = ((dst) &\
2158                     ~0x00000002U) | (((uint32_t)(src) <<\
2159                     1) & 0x00000002U)
2160 #define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__VERIFY(src) \
2161                     (!((((uint32_t)(src)\
2162                     << 1) & ~0x00000002U)))
2163 #define EMAC_REGS__TRANSMIT_STATUS__COLLISION_OCCURRED__CLR(dst) \
2164                     (dst) = ((dst) &\
2165                     ~0x00000002U) | ((uint32_t)(1) << 1)
2166 
2167 /* macros for field retry_limit_exceeded */
2168 #define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__SHIFT               2
2169 #define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__WIDTH               1
2170 #define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__MASK      0x00000004U
2171 #define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__RESET               0
2172 #define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__READ(src) \
2173                     (((uint32_t)(src)\
2174                     & 0x00000004U) >> 2)
2175 #define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__WRITE(src) \
2176                     (((uint32_t)(src)\
2177                     << 2) & 0x00000004U)
2178 #define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__MODIFY(dst, src) \
2179                     (dst) = ((dst) &\
2180                     ~0x00000004U) | (((uint32_t)(src) <<\
2181                     2) & 0x00000004U)
2182 #define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__VERIFY(src) \
2183                     (!((((uint32_t)(src)\
2184                     << 2) & ~0x00000004U)))
2185 #define EMAC_REGS__TRANSMIT_STATUS__RETRY_LIMIT_EXCEEDED__CLR(dst) \
2186                     (dst) = ((dst) &\
2187                     ~0x00000004U) | ((uint32_t)(1) << 2)
2188 
2189 /* macros for field transmit_go */
2190 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__SHIFT                        3
2191 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__WIDTH                        1
2192 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__MASK               0x00000008U
2193 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__RESET                        0
2194 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__READ(src) \
2195                     (((uint32_t)(src)\
2196                     & 0x00000008U) >> 3)
2197 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__SET(dst) \
2198                     (dst) = ((dst) &\
2199                     ~0x00000008U) | ((uint32_t)(1) << 3)
2200 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_GO__CLR(dst) \
2201                     (dst) = ((dst) &\
2202                     ~0x00000008U) | ((uint32_t)(0) << 3)
2203 
2204 /* macros for field amba_error */
2205 #define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__SHIFT                         4
2206 #define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__WIDTH                         1
2207 #define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__MASK                0x00000010U
2208 #define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__RESET                         0
2209 #define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__READ(src) \
2210                     (((uint32_t)(src)\
2211                     & 0x00000010U) >> 4)
2212 #define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__WRITE(src) \
2213                     (((uint32_t)(src)\
2214                     << 4) & 0x00000010U)
2215 #define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__MODIFY(dst, src) \
2216                     (dst) = ((dst) &\
2217                     ~0x00000010U) | (((uint32_t)(src) <<\
2218                     4) & 0x00000010U)
2219 #define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__VERIFY(src) \
2220                     (!((((uint32_t)(src)\
2221                     << 4) & ~0x00000010U)))
2222 #define EMAC_REGS__TRANSMIT_STATUS__AMBA_ERROR__CLR(dst) \
2223                     (dst) = ((dst) &\
2224                     ~0x00000010U) | ((uint32_t)(1) << 4)
2225 
2226 /* macros for field transmit_complete */
2227 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__SHIFT                  5
2228 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__WIDTH                  1
2229 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__MASK         0x00000020U
2230 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__RESET                  0
2231 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__READ(src) \
2232                     (((uint32_t)(src)\
2233                     & 0x00000020U) >> 5)
2234 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__WRITE(src) \
2235                     (((uint32_t)(src)\
2236                     << 5) & 0x00000020U)
2237 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__MODIFY(dst, src) \
2238                     (dst) = ((dst) &\
2239                     ~0x00000020U) | (((uint32_t)(src) <<\
2240                     5) & 0x00000020U)
2241 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__VERIFY(src) \
2242                     (!((((uint32_t)(src)\
2243                     << 5) & ~0x00000020U)))
2244 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_COMPLETE__CLR(dst) \
2245                     (dst) = ((dst) &\
2246                     ~0x00000020U) | ((uint32_t)(1) << 5)
2247 
2248 /* macros for field transmit_under_run */
2249 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__SHIFT                 6
2250 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__WIDTH                 1
2251 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__MASK        0x00000040U
2252 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__RESET                 0
2253 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__READ(src) \
2254                     (((uint32_t)(src)\
2255                     & 0x00000040U) >> 6)
2256 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__WRITE(src) \
2257                     (((uint32_t)(src)\
2258                     << 6) & 0x00000040U)
2259 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__MODIFY(dst, src) \
2260                     (dst) = ((dst) &\
2261                     ~0x00000040U) | (((uint32_t)(src) <<\
2262                     6) & 0x00000040U)
2263 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__VERIFY(src) \
2264                     (!((((uint32_t)(src)\
2265                     << 6) & ~0x00000040U)))
2266 #define EMAC_REGS__TRANSMIT_STATUS__TRANSMIT_UNDER_RUN__CLR(dst) \
2267                     (dst) = ((dst) &\
2268                     ~0x00000040U) | ((uint32_t)(1) << 6)
2269 
2270 /* macros for field late_collision_occurred */
2271 #define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__SHIFT            7
2272 #define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__WIDTH            1
2273 #define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__MASK   0x00000080U
2274 #define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__RESET            0
2275 #define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__READ(src) \
2276                     (((uint32_t)(src)\
2277                     & 0x00000080U) >> 7)
2278 #define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__WRITE(src) \
2279                     (((uint32_t)(src)\
2280                     << 7) & 0x00000080U)
2281 #define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__MODIFY(dst, src) \
2282                     (dst) = ((dst) &\
2283                     ~0x00000080U) | (((uint32_t)(src) <<\
2284                     7) & 0x00000080U)
2285 #define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__VERIFY(src) \
2286                     (!((((uint32_t)(src)\
2287                     << 7) & ~0x00000080U)))
2288 #define EMAC_REGS__TRANSMIT_STATUS__LATE_COLLISION_OCCURRED__CLR(dst) \
2289                     (dst) = ((dst) &\
2290                     ~0x00000080U) | ((uint32_t)(1) << 7)
2291 
2292 /* macros for field resp_not_ok */
2293 #define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__SHIFT                        8
2294 #define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__WIDTH                        1
2295 #define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__MASK               0x00000100U
2296 #define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__RESET                        0
2297 #define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__READ(src) \
2298                     (((uint32_t)(src)\
2299                     & 0x00000100U) >> 8)
2300 #define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__WRITE(src) \
2301                     (((uint32_t)(src)\
2302                     << 8) & 0x00000100U)
2303 #define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__MODIFY(dst, src) \
2304                     (dst) = ((dst) &\
2305                     ~0x00000100U) | (((uint32_t)(src) <<\
2306                     8) & 0x00000100U)
2307 #define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__VERIFY(src) \
2308                     (!((((uint32_t)(src)\
2309                     << 8) & ~0x00000100U)))
2310 #define EMAC_REGS__TRANSMIT_STATUS__RESP_NOT_OK__CLR(dst) \
2311                     (dst) = ((dst) &\
2312                     ~0x00000100U) | ((uint32_t)(1) << 8)
2313 
2314 /* macros for field reserved_31_9 */
2315 #define EMAC_REGS__TRANSMIT_STATUS__RESERVED_31_9__SHIFT                      9
2316 #define EMAC_REGS__TRANSMIT_STATUS__RESERVED_31_9__WIDTH                     23
2317 #define EMAC_REGS__TRANSMIT_STATUS__RESERVED_31_9__MASK             0xfffffe00U
2318 #define EMAC_REGS__TRANSMIT_STATUS__RESERVED_31_9__RESET                      0
2319 #define EMAC_REGS__TRANSMIT_STATUS__RESERVED_31_9__READ(src) \
2320                     (((uint32_t)(src)\
2321                     & 0xfffffe00U) >> 9)
2322 #define EMAC_REGS__TRANSMIT_STATUS__TYPE                               uint32_t
2323 #define EMAC_REGS__TRANSMIT_STATUS__READ                            0xffffffffU
2324 #define EMAC_REGS__TRANSMIT_STATUS__WRITE                           0xffffffffU
2325 #define EMAC_REGS__TRANSMIT_STATUS__WOCLR                           0x000001f7U
2326 
2327 #endif /* __EMAC_REGS__TRANSMIT_STATUS_MACRO__ */
2328 
2329 
2330 /* macros for transmit_status */
2331 #define INST_TRANSMIT_STATUS__NUM                                             1
2332 
2333 /* macros for BlueprintGlobalNameSpace::emac_regs::receive_q_ptr */
2334 #ifndef __EMAC_REGS__RECEIVE_Q_PTR_MACRO__
2335 #define __EMAC_REGS__RECEIVE_Q_PTR_MACRO__
2336 
2337 /* macros for field dma_rx_dis_q */
2338 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__SHIFT                         0
2339 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__WIDTH                         1
2340 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__MASK                0x00000001U
2341 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__RESET                       0b0
2342 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__READ(src) \
2343                     ((uint32_t)(src)\
2344                     & 0x00000001U)
2345 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__WRITE(src) \
2346                     ((uint32_t)(src)\
2347                     & 0x00000001U)
2348 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__MODIFY(dst, src) \
2349                     (dst) = ((dst) &\
2350                     ~0x00000001U) | ((uint32_t)(src) &\
2351                     0x00000001U)
2352 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__VERIFY(src) \
2353                     (!(((uint32_t)(src)\
2354                     & ~0x00000001U)))
2355 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__SET(dst) \
2356                     (dst) = ((dst) &\
2357                     ~0x00000001U) | (uint32_t)(1)
2358 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_DIS_Q__CLR(dst) \
2359                     (dst) = ((dst) &\
2360                     ~0x00000001U) | (uint32_t)(0)
2361 
2362 /* macros for field reserved_1_1 */
2363 #define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1_1__SHIFT                         1
2364 #define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1_1__WIDTH                         1
2365 #define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1_1__MASK                0x00000002U
2366 #define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1_1__RESET                       0b0
2367 #define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1_1__READ(src) \
2368                     (((uint32_t)(src)\
2369                     & 0x00000002U) >> 1)
2370 #define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1_1__SET(dst) \
2371                     (dst) = ((dst) &\
2372                     ~0x00000002U) | ((uint32_t)(1) << 1)
2373 #define EMAC_REGS__RECEIVE_Q_PTR__RESERVED_1_1__CLR(dst) \
2374                     (dst) = ((dst) &\
2375                     ~0x00000002U) | ((uint32_t)(0) << 1)
2376 
2377 /* macros for field dma_rx_q_ptr */
2378 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__SHIFT                         2
2379 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__WIDTH                        30
2380 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__MASK                0xfffffffcU
2381 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__RESET                         0
2382 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__READ(src) \
2383                     (((uint32_t)(src)\
2384                     & 0xfffffffcU) >> 2)
2385 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__WRITE(src) \
2386                     (((uint32_t)(src)\
2387                     << 2) & 0xfffffffcU)
2388 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__MODIFY(dst, src) \
2389                     (dst) = ((dst) &\
2390                     ~0xfffffffcU) | (((uint32_t)(src) <<\
2391                     2) & 0xfffffffcU)
2392 #define EMAC_REGS__RECEIVE_Q_PTR__DMA_RX_Q_PTR__VERIFY(src) \
2393                     (!((((uint32_t)(src)\
2394                     << 2) & ~0xfffffffcU)))
2395 #define EMAC_REGS__RECEIVE_Q_PTR__TYPE                                 uint32_t
2396 #define EMAC_REGS__RECEIVE_Q_PTR__READ                              0xffffffffU
2397 #define EMAC_REGS__RECEIVE_Q_PTR__WRITE                             0xffffffffU
2398 
2399 #endif /* __EMAC_REGS__RECEIVE_Q_PTR_MACRO__ */
2400 
2401 
2402 /* macros for receive_q_ptr */
2403 #define INST_RECEIVE_Q_PTR__NUM                                               1
2404 
2405 /* macros for BlueprintGlobalNameSpace::emac_regs::transmit_q_ptr */
2406 #ifndef __EMAC_REGS__TRANSMIT_Q_PTR_MACRO__
2407 #define __EMAC_REGS__TRANSMIT_Q_PTR_MACRO__
2408 
2409 /* macros for field dma_tx_dis_q */
2410 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__SHIFT                        0
2411 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__WIDTH                        1
2412 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__MASK               0x00000001U
2413 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__RESET                      0b0
2414 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__READ(src) \
2415                     ((uint32_t)(src)\
2416                     & 0x00000001U)
2417 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__WRITE(src) \
2418                     ((uint32_t)(src)\
2419                     & 0x00000001U)
2420 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__MODIFY(dst, src) \
2421                     (dst) = ((dst) &\
2422                     ~0x00000001U) | ((uint32_t)(src) &\
2423                     0x00000001U)
2424 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__VERIFY(src) \
2425                     (!(((uint32_t)(src)\
2426                     & ~0x00000001U)))
2427 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__SET(dst) \
2428                     (dst) = ((dst) &\
2429                     ~0x00000001U) | (uint32_t)(1)
2430 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_DIS_Q__CLR(dst) \
2431                     (dst) = ((dst) &\
2432                     ~0x00000001U) | (uint32_t)(0)
2433 
2434 /* macros for field reserved_1_1 */
2435 #define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1_1__SHIFT                        1
2436 #define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1_1__WIDTH                        1
2437 #define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1_1__MASK               0x00000002U
2438 #define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1_1__RESET                      0b0
2439 #define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1_1__READ(src) \
2440                     (((uint32_t)(src)\
2441                     & 0x00000002U) >> 1)
2442 #define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1_1__SET(dst) \
2443                     (dst) = ((dst) &\
2444                     ~0x00000002U) | ((uint32_t)(1) << 1)
2445 #define EMAC_REGS__TRANSMIT_Q_PTR__RESERVED_1_1__CLR(dst) \
2446                     (dst) = ((dst) &\
2447                     ~0x00000002U) | ((uint32_t)(0) << 1)
2448 
2449 /* macros for field dma_tx_q_ptr */
2450 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__SHIFT                        2
2451 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__WIDTH                       30
2452 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__MASK               0xfffffffcU
2453 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__RESET                        0
2454 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__READ(src) \
2455                     (((uint32_t)(src)\
2456                     & 0xfffffffcU) >> 2)
2457 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__WRITE(src) \
2458                     (((uint32_t)(src)\
2459                     << 2) & 0xfffffffcU)
2460 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__MODIFY(dst, src) \
2461                     (dst) = ((dst) &\
2462                     ~0xfffffffcU) | (((uint32_t)(src) <<\
2463                     2) & 0xfffffffcU)
2464 #define EMAC_REGS__TRANSMIT_Q_PTR__DMA_TX_Q_PTR__VERIFY(src) \
2465                     (!((((uint32_t)(src)\
2466                     << 2) & ~0xfffffffcU)))
2467 #define EMAC_REGS__TRANSMIT_Q_PTR__TYPE                                uint32_t
2468 #define EMAC_REGS__TRANSMIT_Q_PTR__READ                             0xffffffffU
2469 #define EMAC_REGS__TRANSMIT_Q_PTR__WRITE                            0xffffffffU
2470 
2471 #endif /* __EMAC_REGS__TRANSMIT_Q_PTR_MACRO__ */
2472 
2473 
2474 /* macros for transmit_q_ptr */
2475 #define INST_TRANSMIT_Q_PTR__NUM                                              1
2476 
2477 /* macros for BlueprintGlobalNameSpace::emac_regs::receive_status */
2478 #ifndef __EMAC_REGS__RECEIVE_STATUS_MACRO__
2479 #define __EMAC_REGS__RECEIVE_STATUS_MACRO__
2480 
2481 /* macros for field buffer_not_available */
2482 #define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__SHIFT                0
2483 #define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__WIDTH                1
2484 #define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__MASK       0x00000001U
2485 #define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__RESET                0
2486 #define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__READ(src) \
2487                     ((uint32_t)(src)\
2488                     & 0x00000001U)
2489 #define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__WRITE(src) \
2490                     ((uint32_t)(src)\
2491                     & 0x00000001U)
2492 #define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__MODIFY(dst, src) \
2493                     (dst) = ((dst) &\
2494                     ~0x00000001U) | ((uint32_t)(src) &\
2495                     0x00000001U)
2496 #define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__VERIFY(src) \
2497                     (!(((uint32_t)(src)\
2498                     & ~0x00000001U)))
2499 #define EMAC_REGS__RECEIVE_STATUS__BUFFER_NOT_AVAILABLE__CLR(dst) \
2500                     (dst) = ((dst) &\
2501                     ~0x00000001U) | (uint32_t)(1)
2502 
2503 /* macros for field frame_received */
2504 #define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__SHIFT                      1
2505 #define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__WIDTH                      1
2506 #define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__MASK             0x00000002U
2507 #define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__RESET                      0
2508 #define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__READ(src) \
2509                     (((uint32_t)(src)\
2510                     & 0x00000002U) >> 1)
2511 #define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__WRITE(src) \
2512                     (((uint32_t)(src)\
2513                     << 1) & 0x00000002U)
2514 #define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__MODIFY(dst, src) \
2515                     (dst) = ((dst) &\
2516                     ~0x00000002U) | (((uint32_t)(src) <<\
2517                     1) & 0x00000002U)
2518 #define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__VERIFY(src) \
2519                     (!((((uint32_t)(src)\
2520                     << 1) & ~0x00000002U)))
2521 #define EMAC_REGS__RECEIVE_STATUS__FRAME_RECEIVED__CLR(dst) \
2522                     (dst) = ((dst) &\
2523                     ~0x00000002U) | ((uint32_t)(1) << 1)
2524 
2525 /* macros for field receive_overrun */
2526 #define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__SHIFT                     2
2527 #define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__WIDTH                     1
2528 #define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__MASK            0x00000004U
2529 #define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__RESET                     0
2530 #define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__READ(src) \
2531                     (((uint32_t)(src)\
2532                     & 0x00000004U) >> 2)
2533 #define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__WRITE(src) \
2534                     (((uint32_t)(src)\
2535                     << 2) & 0x00000004U)
2536 #define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__MODIFY(dst, src) \
2537                     (dst) = ((dst) &\
2538                     ~0x00000004U) | (((uint32_t)(src) <<\
2539                     2) & 0x00000004U)
2540 #define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__VERIFY(src) \
2541                     (!((((uint32_t)(src)\
2542                     << 2) & ~0x00000004U)))
2543 #define EMAC_REGS__RECEIVE_STATUS__RECEIVE_OVERRUN__CLR(dst) \
2544                     (dst) = ((dst) &\
2545                     ~0x00000004U) | ((uint32_t)(1) << 2)
2546 
2547 /* macros for field resp_not_ok */
2548 #define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__SHIFT                         3
2549 #define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__WIDTH                         1
2550 #define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__MASK                0x00000008U
2551 #define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__RESET                         0
2552 #define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__READ(src) \
2553                     (((uint32_t)(src)\
2554                     & 0x00000008U) >> 3)
2555 #define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__WRITE(src) \
2556                     (((uint32_t)(src)\
2557                     << 3) & 0x00000008U)
2558 #define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__MODIFY(dst, src) \
2559                     (dst) = ((dst) &\
2560                     ~0x00000008U) | (((uint32_t)(src) <<\
2561                     3) & 0x00000008U)
2562 #define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__VERIFY(src) \
2563                     (!((((uint32_t)(src)\
2564                     << 3) & ~0x00000008U)))
2565 #define EMAC_REGS__RECEIVE_STATUS__RESP_NOT_OK__CLR(dst) \
2566                     (dst) = ((dst) &\
2567                     ~0x00000008U) | ((uint32_t)(1) << 3)
2568 
2569 /* macros for field reserved_31_4 */
2570 #define EMAC_REGS__RECEIVE_STATUS__RESERVED_31_4__SHIFT                       4
2571 #define EMAC_REGS__RECEIVE_STATUS__RESERVED_31_4__WIDTH                      28
2572 #define EMAC_REGS__RECEIVE_STATUS__RESERVED_31_4__MASK              0xfffffff0U
2573 #define EMAC_REGS__RECEIVE_STATUS__RESERVED_31_4__RESET                       0
2574 #define EMAC_REGS__RECEIVE_STATUS__RESERVED_31_4__READ(src) \
2575                     (((uint32_t)(src)\
2576                     & 0xfffffff0U) >> 4)
2577 #define EMAC_REGS__RECEIVE_STATUS__TYPE                                uint32_t
2578 #define EMAC_REGS__RECEIVE_STATUS__READ                             0xffffffffU
2579 #define EMAC_REGS__RECEIVE_STATUS__WRITE                            0xffffffffU
2580 #define EMAC_REGS__RECEIVE_STATUS__WOCLR                            0x0000000fU
2581 
2582 #endif /* __EMAC_REGS__RECEIVE_STATUS_MACRO__ */
2583 
2584 
2585 /* macros for receive_status */
2586 #define INST_RECEIVE_STATUS__NUM                                              1
2587 
2588 /* macros for BlueprintGlobalNameSpace::emac_regs::int_status */
2589 #ifndef __EMAC_REGS__INT_STATUS_MACRO__
2590 #define __EMAC_REGS__INT_STATUS_MACRO__
2591 
2592 /* macros for field management_frame_sent */
2593 #define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__SHIFT                   0
2594 #define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__WIDTH                   1
2595 #define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__MASK          0x00000001U
2596 #define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__RESET                 0b0
2597 #define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__READ(src) \
2598                     ((uint32_t)(src)\
2599                     & 0x00000001U)
2600 #define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__WRITE(src) \
2601                     ((uint32_t)(src)\
2602                     & 0x00000001U)
2603 #define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__MODIFY(dst, src) \
2604                     (dst) = ((dst) &\
2605                     ~0x00000001U) | ((uint32_t)(src) &\
2606                     0x00000001U)
2607 #define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__VERIFY(src) \
2608                     (!(((uint32_t)(src)\
2609                     & ~0x00000001U)))
2610 #define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__SET(dst) \
2611                     (dst) = ((dst) &\
2612                     ~0x00000001U) | (uint32_t)(1)
2613 #define EMAC_REGS__INT_STATUS__MANAGEMENT_FRAME_SENT__CLR(dst) \
2614                     (dst) = ((dst) &\
2615                     ~0x00000001U) | (uint32_t)(0)
2616 
2617 /* macros for field receive_complete */
2618 #define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__SHIFT                        1
2619 #define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__WIDTH                        1
2620 #define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__MASK               0x00000002U
2621 #define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__RESET                      0b0
2622 #define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__READ(src) \
2623                     (((uint32_t)(src)\
2624                     & 0x00000002U) >> 1)
2625 #define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__WRITE(src) \
2626                     (((uint32_t)(src)\
2627                     << 1) & 0x00000002U)
2628 #define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__MODIFY(dst, src) \
2629                     (dst) = ((dst) &\
2630                     ~0x00000002U) | (((uint32_t)(src) <<\
2631                     1) & 0x00000002U)
2632 #define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__VERIFY(src) \
2633                     (!((((uint32_t)(src)\
2634                     << 1) & ~0x00000002U)))
2635 #define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__SET(dst) \
2636                     (dst) = ((dst) &\
2637                     ~0x00000002U) | ((uint32_t)(1) << 1)
2638 #define EMAC_REGS__INT_STATUS__RECEIVE_COMPLETE__CLR(dst) \
2639                     (dst) = ((dst) &\
2640                     ~0x00000002U) | ((uint32_t)(0) << 1)
2641 
2642 /* macros for field rx_used_bit_read */
2643 #define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__SHIFT                        2
2644 #define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__WIDTH                        1
2645 #define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__MASK               0x00000004U
2646 #define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__RESET                      0b0
2647 #define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__READ(src) \
2648                     (((uint32_t)(src)\
2649                     & 0x00000004U) >> 2)
2650 #define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__WRITE(src) \
2651                     (((uint32_t)(src)\
2652                     << 2) & 0x00000004U)
2653 #define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__MODIFY(dst, src) \
2654                     (dst) = ((dst) &\
2655                     ~0x00000004U) | (((uint32_t)(src) <<\
2656                     2) & 0x00000004U)
2657 #define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__VERIFY(src) \
2658                     (!((((uint32_t)(src)\
2659                     << 2) & ~0x00000004U)))
2660 #define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__SET(dst) \
2661                     (dst) = ((dst) &\
2662                     ~0x00000004U) | ((uint32_t)(1) << 2)
2663 #define EMAC_REGS__INT_STATUS__RX_USED_BIT_READ__CLR(dst) \
2664                     (dst) = ((dst) &\
2665                     ~0x00000004U) | ((uint32_t)(0) << 2)
2666 
2667 /* macros for field tx_used_bit_read */
2668 #define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__SHIFT                        3
2669 #define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__WIDTH                        1
2670 #define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__MASK               0x00000008U
2671 #define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__RESET                      0b0
2672 #define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__READ(src) \
2673                     (((uint32_t)(src)\
2674                     & 0x00000008U) >> 3)
2675 #define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__WRITE(src) \
2676                     (((uint32_t)(src)\
2677                     << 3) & 0x00000008U)
2678 #define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__MODIFY(dst, src) \
2679                     (dst) = ((dst) &\
2680                     ~0x00000008U) | (((uint32_t)(src) <<\
2681                     3) & 0x00000008U)
2682 #define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__VERIFY(src) \
2683                     (!((((uint32_t)(src)\
2684                     << 3) & ~0x00000008U)))
2685 #define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__SET(dst) \
2686                     (dst) = ((dst) &\
2687                     ~0x00000008U) | ((uint32_t)(1) << 3)
2688 #define EMAC_REGS__INT_STATUS__TX_USED_BIT_READ__CLR(dst) \
2689                     (dst) = ((dst) &\
2690                     ~0x00000008U) | ((uint32_t)(0) << 3)
2691 
2692 /* macros for field transmit_under_run */
2693 #define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__SHIFT                      4
2694 #define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__WIDTH                      1
2695 #define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__MASK             0x00000010U
2696 #define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__RESET                    0b0
2697 #define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__READ(src) \
2698                     (((uint32_t)(src)\
2699                     & 0x00000010U) >> 4)
2700 #define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__WRITE(src) \
2701                     (((uint32_t)(src)\
2702                     << 4) & 0x00000010U)
2703 #define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__MODIFY(dst, src) \
2704                     (dst) = ((dst) &\
2705                     ~0x00000010U) | (((uint32_t)(src) <<\
2706                     4) & 0x00000010U)
2707 #define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__VERIFY(src) \
2708                     (!((((uint32_t)(src)\
2709                     << 4) & ~0x00000010U)))
2710 #define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__SET(dst) \
2711                     (dst) = ((dst) &\
2712                     ~0x00000010U) | ((uint32_t)(1) << 4)
2713 #define EMAC_REGS__INT_STATUS__TRANSMIT_UNDER_RUN__CLR(dst) \
2714                     (dst) = ((dst) &\
2715                     ~0x00000010U) | ((uint32_t)(0) << 4)
2716 
2717 /* macros for field retry_limit_exceeded_or_late_collision */
2718 #define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT  5
2719 #define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH  1
2720 #define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK \
2721                     0x00000020U
2722 #define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET \
2723                     0b0
2724 #define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
2725                     (((uint32_t)(src)\
2726                     & 0x00000020U) >> 5)
2727 #define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WRITE(src) \
2728                     (((uint32_t)(src)\
2729                     << 5) & 0x00000020U)
2730 #define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MODIFY(dst, src) \
2731                     (dst) = ((dst) &\
2732                     ~0x00000020U) | (((uint32_t)(src) <<\
2733                     5) & 0x00000020U)
2734 #define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__VERIFY(src) \
2735                     (!((((uint32_t)(src)\
2736                     << 5) & ~0x00000020U)))
2737 #define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
2738                     (dst) = ((dst) &\
2739                     ~0x00000020U) | ((uint32_t)(1) << 5)
2740 #define EMAC_REGS__INT_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
2741                     (dst) = ((dst) &\
2742                     ~0x00000020U) | ((uint32_t)(0) << 5)
2743 
2744 /* macros for field amba_error */
2745 #define EMAC_REGS__INT_STATUS__AMBA_ERROR__SHIFT                              6
2746 #define EMAC_REGS__INT_STATUS__AMBA_ERROR__WIDTH                              1
2747 #define EMAC_REGS__INT_STATUS__AMBA_ERROR__MASK                     0x00000040U
2748 #define EMAC_REGS__INT_STATUS__AMBA_ERROR__RESET                            0b0
2749 #define EMAC_REGS__INT_STATUS__AMBA_ERROR__READ(src) \
2750                     (((uint32_t)(src)\
2751                     & 0x00000040U) >> 6)
2752 #define EMAC_REGS__INT_STATUS__AMBA_ERROR__WRITE(src) \
2753                     (((uint32_t)(src)\
2754                     << 6) & 0x00000040U)
2755 #define EMAC_REGS__INT_STATUS__AMBA_ERROR__MODIFY(dst, src) \
2756                     (dst) = ((dst) &\
2757                     ~0x00000040U) | (((uint32_t)(src) <<\
2758                     6) & 0x00000040U)
2759 #define EMAC_REGS__INT_STATUS__AMBA_ERROR__VERIFY(src) \
2760                     (!((((uint32_t)(src)\
2761                     << 6) & ~0x00000040U)))
2762 #define EMAC_REGS__INT_STATUS__AMBA_ERROR__SET(dst) \
2763                     (dst) = ((dst) &\
2764                     ~0x00000040U) | ((uint32_t)(1) << 6)
2765 #define EMAC_REGS__INT_STATUS__AMBA_ERROR__CLR(dst) \
2766                     (dst) = ((dst) &\
2767                     ~0x00000040U) | ((uint32_t)(0) << 6)
2768 
2769 /* macros for field transmit_complete */
2770 #define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__SHIFT                       7
2771 #define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__WIDTH                       1
2772 #define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__MASK              0x00000080U
2773 #define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__RESET                     0b0
2774 #define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__READ(src) \
2775                     (((uint32_t)(src)\
2776                     & 0x00000080U) >> 7)
2777 #define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__WRITE(src) \
2778                     (((uint32_t)(src)\
2779                     << 7) & 0x00000080U)
2780 #define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__MODIFY(dst, src) \
2781                     (dst) = ((dst) &\
2782                     ~0x00000080U) | (((uint32_t)(src) <<\
2783                     7) & 0x00000080U)
2784 #define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__VERIFY(src) \
2785                     (!((((uint32_t)(src)\
2786                     << 7) & ~0x00000080U)))
2787 #define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__SET(dst) \
2788                     (dst) = ((dst) &\
2789                     ~0x00000080U) | ((uint32_t)(1) << 7)
2790 #define EMAC_REGS__INT_STATUS__TRANSMIT_COMPLETE__CLR(dst) \
2791                     (dst) = ((dst) &\
2792                     ~0x00000080U) | ((uint32_t)(0) << 7)
2793 
2794 /* macros for field reserved_8 */
2795 #define EMAC_REGS__INT_STATUS__RESERVED_8__SHIFT                              8
2796 #define EMAC_REGS__INT_STATUS__RESERVED_8__WIDTH                              1
2797 #define EMAC_REGS__INT_STATUS__RESERVED_8__MASK                     0x00000100U
2798 #define EMAC_REGS__INT_STATUS__RESERVED_8__RESET                              0
2799 #define EMAC_REGS__INT_STATUS__RESERVED_8__READ(src) \
2800                     (((uint32_t)(src)\
2801                     & 0x00000100U) >> 8)
2802 #define EMAC_REGS__INT_STATUS__RESERVED_8__SET(dst) \
2803                     (dst) = ((dst) &\
2804                     ~0x00000100U) | ((uint32_t)(1) << 8)
2805 #define EMAC_REGS__INT_STATUS__RESERVED_8__CLR(dst) \
2806                     (dst) = ((dst) &\
2807                     ~0x00000100U) | ((uint32_t)(0) << 8)
2808 
2809 /* macros for field link_change */
2810 #define EMAC_REGS__INT_STATUS__LINK_CHANGE__SHIFT                             9
2811 #define EMAC_REGS__INT_STATUS__LINK_CHANGE__WIDTH                             1
2812 #define EMAC_REGS__INT_STATUS__LINK_CHANGE__MASK                    0x00000200U
2813 #define EMAC_REGS__INT_STATUS__LINK_CHANGE__RESET                           0b0
2814 #define EMAC_REGS__INT_STATUS__LINK_CHANGE__READ(src) \
2815                     (((uint32_t)(src)\
2816                     & 0x00000200U) >> 9)
2817 #define EMAC_REGS__INT_STATUS__LINK_CHANGE__WRITE(src) \
2818                     (((uint32_t)(src)\
2819                     << 9) & 0x00000200U)
2820 #define EMAC_REGS__INT_STATUS__LINK_CHANGE__MODIFY(dst, src) \
2821                     (dst) = ((dst) &\
2822                     ~0x00000200U) | (((uint32_t)(src) <<\
2823                     9) & 0x00000200U)
2824 #define EMAC_REGS__INT_STATUS__LINK_CHANGE__VERIFY(src) \
2825                     (!((((uint32_t)(src)\
2826                     << 9) & ~0x00000200U)))
2827 #define EMAC_REGS__INT_STATUS__LINK_CHANGE__SET(dst) \
2828                     (dst) = ((dst) &\
2829                     ~0x00000200U) | ((uint32_t)(1) << 9)
2830 #define EMAC_REGS__INT_STATUS__LINK_CHANGE__CLR(dst) \
2831                     (dst) = ((dst) &\
2832                     ~0x00000200U) | ((uint32_t)(0) << 9)
2833 
2834 /* macros for field receive_overrun */
2835 #define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__SHIFT                        10
2836 #define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__WIDTH                         1
2837 #define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__MASK                0x00000400U
2838 #define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__RESET                       0b0
2839 #define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__READ(src) \
2840                     (((uint32_t)(src)\
2841                     & 0x00000400U) >> 10)
2842 #define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__WRITE(src) \
2843                     (((uint32_t)(src)\
2844                     << 10) & 0x00000400U)
2845 #define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__MODIFY(dst, src) \
2846                     (dst) = ((dst) &\
2847                     ~0x00000400U) | (((uint32_t)(src) <<\
2848                     10) & 0x00000400U)
2849 #define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__VERIFY(src) \
2850                     (!((((uint32_t)(src)\
2851                     << 10) & ~0x00000400U)))
2852 #define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__SET(dst) \
2853                     (dst) = ((dst) &\
2854                     ~0x00000400U) | ((uint32_t)(1) << 10)
2855 #define EMAC_REGS__INT_STATUS__RECEIVE_OVERRUN__CLR(dst) \
2856                     (dst) = ((dst) &\
2857                     ~0x00000400U) | ((uint32_t)(0) << 10)
2858 
2859 /* macros for field resp_not_ok */
2860 #define EMAC_REGS__INT_STATUS__RESP_NOT_OK__SHIFT                            11
2861 #define EMAC_REGS__INT_STATUS__RESP_NOT_OK__WIDTH                             1
2862 #define EMAC_REGS__INT_STATUS__RESP_NOT_OK__MASK                    0x00000800U
2863 #define EMAC_REGS__INT_STATUS__RESP_NOT_OK__RESET                           0b0
2864 #define EMAC_REGS__INT_STATUS__RESP_NOT_OK__READ(src) \
2865                     (((uint32_t)(src)\
2866                     & 0x00000800U) >> 11)
2867 #define EMAC_REGS__INT_STATUS__RESP_NOT_OK__WRITE(src) \
2868                     (((uint32_t)(src)\
2869                     << 11) & 0x00000800U)
2870 #define EMAC_REGS__INT_STATUS__RESP_NOT_OK__MODIFY(dst, src) \
2871                     (dst) = ((dst) &\
2872                     ~0x00000800U) | (((uint32_t)(src) <<\
2873                     11) & 0x00000800U)
2874 #define EMAC_REGS__INT_STATUS__RESP_NOT_OK__VERIFY(src) \
2875                     (!((((uint32_t)(src)\
2876                     << 11) & ~0x00000800U)))
2877 #define EMAC_REGS__INT_STATUS__RESP_NOT_OK__SET(dst) \
2878                     (dst) = ((dst) &\
2879                     ~0x00000800U) | ((uint32_t)(1) << 11)
2880 #define EMAC_REGS__INT_STATUS__RESP_NOT_OK__CLR(dst) \
2881                     (dst) = ((dst) &\
2882                     ~0x00000800U) | ((uint32_t)(0) << 11)
2883 
2884 /* macros for field pause_frame_with_non_zero_pause_quantum_received */
2885 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__SHIFT \
2886                     12
2887 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__WIDTH \
2888                     1
2889 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__MASK \
2890                     0x00001000U
2891 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__RESET \
2892                     0b0
2893 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__READ(src) \
2894                     (((uint32_t)(src)\
2895                     & 0x00001000U) >> 12)
2896 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__WRITE(src) \
2897                     (((uint32_t)(src)\
2898                     << 12) & 0x00001000U)
2899 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__MODIFY(dst, src) \
2900                     (dst) = ((dst) &\
2901                     ~0x00001000U) | (((uint32_t)(src) <<\
2902                     12) & 0x00001000U)
2903 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__VERIFY(src) \
2904                     (!((((uint32_t)(src)\
2905                     << 12) & ~0x00001000U)))
2906 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__SET(dst) \
2907                     (dst) = ((dst) &\
2908                     ~0x00001000U) | ((uint32_t)(1) << 12)
2909 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED__CLR(dst) \
2910                     (dst) = ((dst) &\
2911                     ~0x00001000U) | ((uint32_t)(0) << 12)
2912 
2913 /* macros for field pause_time_elapsed */
2914 #define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__SHIFT                     13
2915 #define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__WIDTH                      1
2916 #define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__MASK             0x00002000U
2917 #define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__RESET                    0b0
2918 #define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__READ(src) \
2919                     (((uint32_t)(src)\
2920                     & 0x00002000U) >> 13)
2921 #define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__WRITE(src) \
2922                     (((uint32_t)(src)\
2923                     << 13) & 0x00002000U)
2924 #define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__MODIFY(dst, src) \
2925                     (dst) = ((dst) &\
2926                     ~0x00002000U) | (((uint32_t)(src) <<\
2927                     13) & 0x00002000U)
2928 #define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__VERIFY(src) \
2929                     (!((((uint32_t)(src)\
2930                     << 13) & ~0x00002000U)))
2931 #define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__SET(dst) \
2932                     (dst) = ((dst) &\
2933                     ~0x00002000U) | ((uint32_t)(1) << 13)
2934 #define EMAC_REGS__INT_STATUS__PAUSE_TIME_ELAPSED__CLR(dst) \
2935                     (dst) = ((dst) &\
2936                     ~0x00002000U) | ((uint32_t)(0) << 13)
2937 
2938 /* macros for field pause_frame_transmitted */
2939 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__SHIFT                14
2940 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__WIDTH                 1
2941 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__MASK        0x00004000U
2942 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__RESET               0b0
2943 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__READ(src) \
2944                     (((uint32_t)(src)\
2945                     & 0x00004000U) >> 14)
2946 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__WRITE(src) \
2947                     (((uint32_t)(src)\
2948                     << 14) & 0x00004000U)
2949 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__MODIFY(dst, src) \
2950                     (dst) = ((dst) &\
2951                     ~0x00004000U) | (((uint32_t)(src) <<\
2952                     14) & 0x00004000U)
2953 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__VERIFY(src) \
2954                     (!((((uint32_t)(src)\
2955                     << 14) & ~0x00004000U)))
2956 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__SET(dst) \
2957                     (dst) = ((dst) &\
2958                     ~0x00004000U) | ((uint32_t)(1) << 14)
2959 #define EMAC_REGS__INT_STATUS__PAUSE_FRAME_TRANSMITTED__CLR(dst) \
2960                     (dst) = ((dst) &\
2961                     ~0x00004000U) | ((uint32_t)(0) << 14)
2962 
2963 /* macros for field external_interrupt */
2964 #define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__SHIFT                     15
2965 #define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__WIDTH                      1
2966 #define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__MASK             0x00008000U
2967 #define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__RESET                    0b0
2968 #define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__READ(src) \
2969                     (((uint32_t)(src)\
2970                     & 0x00008000U) >> 15)
2971 #define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__WRITE(src) \
2972                     (((uint32_t)(src)\
2973                     << 15) & 0x00008000U)
2974 #define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__MODIFY(dst, src) \
2975                     (dst) = ((dst) &\
2976                     ~0x00008000U) | (((uint32_t)(src) <<\
2977                     15) & 0x00008000U)
2978 #define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__VERIFY(src) \
2979                     (!((((uint32_t)(src)\
2980                     << 15) & ~0x00008000U)))
2981 #define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__SET(dst) \
2982                     (dst) = ((dst) &\
2983                     ~0x00008000U) | ((uint32_t)(1) << 15)
2984 #define EMAC_REGS__INT_STATUS__EXTERNAL_INTERRUPT__CLR(dst) \
2985                     (dst) = ((dst) &\
2986                     ~0x00008000U) | ((uint32_t)(0) << 15)
2987 
2988 /* macros for field pcs_auto_negotiation_complete */
2989 #define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__SHIFT          16
2990 #define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__WIDTH           1
2991 #define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__MASK  0x00010000U
2992 #define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__RESET         0b0
2993 #define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__READ(src) \
2994                     (((uint32_t)(src)\
2995                     & 0x00010000U) >> 16)
2996 #define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__WRITE(src) \
2997                     (((uint32_t)(src)\
2998                     << 16) & 0x00010000U)
2999 #define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__MODIFY(dst, src) \
3000                     (dst) = ((dst) &\
3001                     ~0x00010000U) | (((uint32_t)(src) <<\
3002                     16) & 0x00010000U)
3003 #define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__VERIFY(src) \
3004                     (!((((uint32_t)(src)\
3005                     << 16) & ~0x00010000U)))
3006 #define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__SET(dst) \
3007                     (dst) = ((dst) &\
3008                     ~0x00010000U) | ((uint32_t)(1) << 16)
3009 #define EMAC_REGS__INT_STATUS__PCS_AUTO_NEGOTIATION_COMPLETE__CLR(dst) \
3010                     (dst) = ((dst) &\
3011                     ~0x00010000U) | ((uint32_t)(0) << 16)
3012 
3013 /* macros for field pcs_link_partner_page_received */
3014 #define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__SHIFT         17
3015 #define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__WIDTH          1
3016 #define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__MASK 0x00020000U
3017 #define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__RESET        0b0
3018 #define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__READ(src) \
3019                     (((uint32_t)(src)\
3020                     & 0x00020000U) >> 17)
3021 #define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__WRITE(src) \
3022                     (((uint32_t)(src)\
3023                     << 17) & 0x00020000U)
3024 #define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__MODIFY(dst, src) \
3025                     (dst) = ((dst) &\
3026                     ~0x00020000U) | (((uint32_t)(src) <<\
3027                     17) & 0x00020000U)
3028 #define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__VERIFY(src) \
3029                     (!((((uint32_t)(src)\
3030                     << 17) & ~0x00020000U)))
3031 #define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__SET(dst) \
3032                     (dst) = ((dst) &\
3033                     ~0x00020000U) | ((uint32_t)(1) << 17)
3034 #define EMAC_REGS__INT_STATUS__PCS_LINK_PARTNER_PAGE_RECEIVED__CLR(dst) \
3035                     (dst) = ((dst) &\
3036                     ~0x00020000U) | ((uint32_t)(0) << 17)
3037 
3038 /* macros for field ptp_delay_req_frame_received */
3039 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__SHIFT           18
3040 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__WIDTH            1
3041 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__MASK   0x00040000U
3042 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__RESET          0b0
3043 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__READ(src) \
3044                     (((uint32_t)(src)\
3045                     & 0x00040000U) >> 18)
3046 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__WRITE(src) \
3047                     (((uint32_t)(src)\
3048                     << 18) & 0x00040000U)
3049 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \
3050                     (dst) = ((dst) &\
3051                     ~0x00040000U) | (((uint32_t)(src) <<\
3052                     18) & 0x00040000U)
3053 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__VERIFY(src) \
3054                     (!((((uint32_t)(src)\
3055                     << 18) & ~0x00040000U)))
3056 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__SET(dst) \
3057                     (dst) = ((dst) &\
3058                     ~0x00040000U) | ((uint32_t)(1) << 18)
3059 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_RECEIVED__CLR(dst) \
3060                     (dst) = ((dst) &\
3061                     ~0x00040000U) | ((uint32_t)(0) << 18)
3062 
3063 /* macros for field ptp_sync_frame_received */
3064 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__SHIFT                19
3065 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__WIDTH                 1
3066 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__MASK        0x00080000U
3067 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__RESET               0b0
3068 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__READ(src) \
3069                     (((uint32_t)(src)\
3070                     & 0x00080000U) >> 19)
3071 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__WRITE(src) \
3072                     (((uint32_t)(src)\
3073                     << 19) & 0x00080000U)
3074 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__MODIFY(dst, src) \
3075                     (dst) = ((dst) &\
3076                     ~0x00080000U) | (((uint32_t)(src) <<\
3077                     19) & 0x00080000U)
3078 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__VERIFY(src) \
3079                     (!((((uint32_t)(src)\
3080                     << 19) & ~0x00080000U)))
3081 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__SET(dst) \
3082                     (dst) = ((dst) &\
3083                     ~0x00080000U) | ((uint32_t)(1) << 19)
3084 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_RECEIVED__CLR(dst) \
3085                     (dst) = ((dst) &\
3086                     ~0x00080000U) | ((uint32_t)(0) << 19)
3087 
3088 /* macros for field ptp_delay_req_frame_transmitted */
3089 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__SHIFT        20
3090 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__WIDTH         1
3091 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__MASK \
3092                     0x00100000U
3093 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__RESET       0b0
3094 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__READ(src) \
3095                     (((uint32_t)(src)\
3096                     & 0x00100000U) >> 20)
3097 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \
3098                     (((uint32_t)(src)\
3099                     << 20) & 0x00100000U)
3100 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \
3101                     (dst) = ((dst) &\
3102                     ~0x00100000U) | (((uint32_t)(src) <<\
3103                     20) & 0x00100000U)
3104 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \
3105                     (!((((uint32_t)(src)\
3106                     << 20) & ~0x00100000U)))
3107 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__SET(dst) \
3108                     (dst) = ((dst) &\
3109                     ~0x00100000U) | ((uint32_t)(1) << 20)
3110 #define EMAC_REGS__INT_STATUS__PTP_DELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \
3111                     (dst) = ((dst) &\
3112                     ~0x00100000U) | ((uint32_t)(0) << 20)
3113 
3114 /* macros for field ptp_sync_frame_transmitted */
3115 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__SHIFT             21
3116 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__WIDTH              1
3117 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__MASK     0x00200000U
3118 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__RESET            0b0
3119 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__READ(src) \
3120                     (((uint32_t)(src)\
3121                     & 0x00200000U) >> 21)
3122 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__WRITE(src) \
3123                     (((uint32_t)(src)\
3124                     << 21) & 0x00200000U)
3125 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__MODIFY(dst, src) \
3126                     (dst) = ((dst) &\
3127                     ~0x00200000U) | (((uint32_t)(src) <<\
3128                     21) & 0x00200000U)
3129 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__VERIFY(src) \
3130                     (!((((uint32_t)(src)\
3131                     << 21) & ~0x00200000U)))
3132 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__SET(dst) \
3133                     (dst) = ((dst) &\
3134                     ~0x00200000U) | ((uint32_t)(1) << 21)
3135 #define EMAC_REGS__INT_STATUS__PTP_SYNC_FRAME_TRANSMITTED__CLR(dst) \
3136                     (dst) = ((dst) &\
3137                     ~0x00200000U) | ((uint32_t)(0) << 21)
3138 
3139 /* macros for field ptp_pdelay_req_frame_received */
3140 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__SHIFT          22
3141 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__WIDTH           1
3142 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__MASK  0x00400000U
3143 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__RESET         0b0
3144 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__READ(src) \
3145                     (((uint32_t)(src)\
3146                     & 0x00400000U) >> 22)
3147 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__WRITE(src) \
3148                     (((uint32_t)(src)\
3149                     << 22) & 0x00400000U)
3150 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \
3151                     (dst) = ((dst) &\
3152                     ~0x00400000U) | (((uint32_t)(src) <<\
3153                     22) & 0x00400000U)
3154 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__VERIFY(src) \
3155                     (!((((uint32_t)(src)\
3156                     << 22) & ~0x00400000U)))
3157 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__SET(dst) \
3158                     (dst) = ((dst) &\
3159                     ~0x00400000U) | ((uint32_t)(1) << 22)
3160 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_RECEIVED__CLR(dst) \
3161                     (dst) = ((dst) &\
3162                     ~0x00400000U) | ((uint32_t)(0) << 22)
3163 
3164 /* macros for field ptp_pdelay_resp_frame_received */
3165 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__SHIFT         23
3166 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__WIDTH          1
3167 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__MASK 0x00800000U
3168 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__RESET        0b0
3169 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__READ(src) \
3170                     (((uint32_t)(src)\
3171                     & 0x00800000U) >> 23)
3172 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__WRITE(src) \
3173                     (((uint32_t)(src)\
3174                     << 23) & 0x00800000U)
3175 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__MODIFY(dst, src) \
3176                     (dst) = ((dst) &\
3177                     ~0x00800000U) | (((uint32_t)(src) <<\
3178                     23) & 0x00800000U)
3179 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__VERIFY(src) \
3180                     (!((((uint32_t)(src)\
3181                     << 23) & ~0x00800000U)))
3182 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__SET(dst) \
3183                     (dst) = ((dst) &\
3184                     ~0x00800000U) | ((uint32_t)(1) << 23)
3185 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_RECEIVED__CLR(dst) \
3186                     (dst) = ((dst) &\
3187                     ~0x00800000U) | ((uint32_t)(0) << 23)
3188 
3189 /* macros for field ptp_pdelay_req_frame_transmitted */
3190 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__SHIFT       24
3191 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__WIDTH        1
3192 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__MASK \
3193                     0x01000000U
3194 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__RESET      0b0
3195 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__READ(src) \
3196                     (((uint32_t)(src)\
3197                     & 0x01000000U) >> 24)
3198 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \
3199                     (((uint32_t)(src)\
3200                     << 24) & 0x01000000U)
3201 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \
3202                     (dst) = ((dst) &\
3203                     ~0x01000000U) | (((uint32_t)(src) <<\
3204                     24) & 0x01000000U)
3205 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \
3206                     (!((((uint32_t)(src)\
3207                     << 24) & ~0x01000000U)))
3208 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__SET(dst) \
3209                     (dst) = ((dst) &\
3210                     ~0x01000000U) | ((uint32_t)(1) << 24)
3211 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \
3212                     (dst) = ((dst) &\
3213                     ~0x01000000U) | ((uint32_t)(0) << 24)
3214 
3215 /* macros for field ptp_pdelay_resp_frame_transmitted */
3216 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__SHIFT      25
3217 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__WIDTH       1
3218 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__MASK \
3219                     0x02000000U
3220 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__RESET     0b0
3221 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__READ(src) \
3222                     (((uint32_t)(src)\
3223                     & 0x02000000U) >> 25)
3224 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__WRITE(src) \
3225                     (((uint32_t)(src)\
3226                     << 25) & 0x02000000U)
3227 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__MODIFY(dst, src) \
3228                     (dst) = ((dst) &\
3229                     ~0x02000000U) | (((uint32_t)(src) <<\
3230                     25) & 0x02000000U)
3231 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__VERIFY(src) \
3232                     (!((((uint32_t)(src)\
3233                     << 25) & ~0x02000000U)))
3234 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__SET(dst) \
3235                     (dst) = ((dst) &\
3236                     ~0x02000000U) | ((uint32_t)(1) << 25)
3237 #define EMAC_REGS__INT_STATUS__PTP_PDELAY_RESP_FRAME_TRANSMITTED__CLR(dst) \
3238                     (dst) = ((dst) &\
3239                     ~0x02000000U) | ((uint32_t)(0) << 25)
3240 
3241 /* macros for field tsu_seconds_register_increment */
3242 #define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__SHIFT         26
3243 #define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__WIDTH          1
3244 #define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__MASK 0x04000000U
3245 #define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__RESET        0b0
3246 #define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__READ(src) \
3247                     (((uint32_t)(src)\
3248                     & 0x04000000U) >> 26)
3249 #define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__WRITE(src) \
3250                     (((uint32_t)(src)\
3251                     << 26) & 0x04000000U)
3252 #define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__MODIFY(dst, src) \
3253                     (dst) = ((dst) &\
3254                     ~0x04000000U) | (((uint32_t)(src) <<\
3255                     26) & 0x04000000U)
3256 #define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__VERIFY(src) \
3257                     (!((((uint32_t)(src)\
3258                     << 26) & ~0x04000000U)))
3259 #define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__SET(dst) \
3260                     (dst) = ((dst) &\
3261                     ~0x04000000U) | ((uint32_t)(1) << 26)
3262 #define EMAC_REGS__INT_STATUS__TSU_SECONDS_REGISTER_INCREMENT__CLR(dst) \
3263                     (dst) = ((dst) &\
3264                     ~0x04000000U) | ((uint32_t)(0) << 26)
3265 
3266 /* macros for field receive_lpi_indication_status_bit_change */
3267 #define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__SHIFT \
3268                     27
3269 #define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__WIDTH \
3270                     1
3271 #define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__MASK \
3272                     0x08000000U
3273 #define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__RESET \
3274                     0b0
3275 #define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__READ(src) \
3276                     (((uint32_t)(src)\
3277                     & 0x08000000U) >> 27)
3278 #define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__WRITE(src) \
3279                     (((uint32_t)(src)\
3280                     << 27) & 0x08000000U)
3281 #define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__MODIFY(dst, src) \
3282                     (dst) = ((dst) &\
3283                     ~0x08000000U) | (((uint32_t)(src) <<\
3284                     27) & 0x08000000U)
3285 #define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__VERIFY(src) \
3286                     (!((((uint32_t)(src)\
3287                     << 27) & ~0x08000000U)))
3288 #define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__SET(dst) \
3289                     (dst) = ((dst) &\
3290                     ~0x08000000U) | ((uint32_t)(1) << 27)
3291 #define EMAC_REGS__INT_STATUS__RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE__CLR(dst) \
3292                     (dst) = ((dst) &\
3293                     ~0x08000000U) | ((uint32_t)(0) << 27)
3294 
3295 /* macros for field wol_interrupt */
3296 #define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__SHIFT                          28
3297 #define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__WIDTH                           1
3298 #define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__MASK                  0x10000000U
3299 #define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__RESET                         0b0
3300 #define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__READ(src) \
3301                     (((uint32_t)(src)\
3302                     & 0x10000000U) >> 28)
3303 #define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__WRITE(src) \
3304                     (((uint32_t)(src)\
3305                     << 28) & 0x10000000U)
3306 #define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__MODIFY(dst, src) \
3307                     (dst) = ((dst) &\
3308                     ~0x10000000U) | (((uint32_t)(src) <<\
3309                     28) & 0x10000000U)
3310 #define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__VERIFY(src) \
3311                     (!((((uint32_t)(src)\
3312                     << 28) & ~0x10000000U)))
3313 #define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__SET(dst) \
3314                     (dst) = ((dst) &\
3315                     ~0x10000000U) | ((uint32_t)(1) << 28)
3316 #define EMAC_REGS__INT_STATUS__WOL_INTERRUPT__CLR(dst) \
3317                     (dst) = ((dst) &\
3318                     ~0x10000000U) | ((uint32_t)(0) << 28)
3319 
3320 /* macros for field tsu_timer_comparison_interrupt */
3321 #define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__SHIFT         29
3322 #define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__WIDTH          1
3323 #define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__MASK 0x20000000U
3324 #define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__RESET        0b0
3325 #define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__READ(src) \
3326                     (((uint32_t)(src)\
3327                     & 0x20000000U) >> 29)
3328 #define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__WRITE(src) \
3329                     (((uint32_t)(src)\
3330                     << 29) & 0x20000000U)
3331 #define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__MODIFY(dst, src) \
3332                     (dst) = ((dst) &\
3333                     ~0x20000000U) | (((uint32_t)(src) <<\
3334                     29) & 0x20000000U)
3335 #define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__VERIFY(src) \
3336                     (!((((uint32_t)(src)\
3337                     << 29) & ~0x20000000U)))
3338 #define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__SET(dst) \
3339                     (dst) = ((dst) &\
3340                     ~0x20000000U) | ((uint32_t)(1) << 29)
3341 #define EMAC_REGS__INT_STATUS__TSU_TIMER_COMPARISON_INTERRUPT__CLR(dst) \
3342                     (dst) = ((dst) &\
3343                     ~0x20000000U) | ((uint32_t)(0) << 29)
3344 
3345 /* macros for field reserved_30_30 */
3346 #define EMAC_REGS__INT_STATUS__RESERVED_30_30__SHIFT                         30
3347 #define EMAC_REGS__INT_STATUS__RESERVED_30_30__WIDTH                          1
3348 #define EMAC_REGS__INT_STATUS__RESERVED_30_30__MASK                 0x40000000U
3349 #define EMAC_REGS__INT_STATUS__RESERVED_30_30__RESET                          0
3350 #define EMAC_REGS__INT_STATUS__RESERVED_30_30__READ(src) \
3351                     (((uint32_t)(src)\
3352                     & 0x40000000U) >> 30)
3353 #define EMAC_REGS__INT_STATUS__RESERVED_30_30__SET(dst) \
3354                     (dst) = ((dst) &\
3355                     ~0x40000000U) | ((uint32_t)(1) << 30)
3356 #define EMAC_REGS__INT_STATUS__RESERVED_30_30__CLR(dst) \
3357                     (dst) = ((dst) &\
3358                     ~0x40000000U) | ((uint32_t)(0) << 30)
3359 
3360 /* macros for field reserved_31_31 */
3361 #define EMAC_REGS__INT_STATUS__RESERVED_31_31__SHIFT                         31
3362 #define EMAC_REGS__INT_STATUS__RESERVED_31_31__WIDTH                          1
3363 #define EMAC_REGS__INT_STATUS__RESERVED_31_31__MASK                 0x80000000U
3364 #define EMAC_REGS__INT_STATUS__RESERVED_31_31__RESET                          0
3365 #define EMAC_REGS__INT_STATUS__RESERVED_31_31__READ(src) \
3366                     (((uint32_t)(src)\
3367                     & 0x80000000U) >> 31)
3368 #define EMAC_REGS__INT_STATUS__RESERVED_31_31__SET(dst) \
3369                     (dst) = ((dst) &\
3370                     ~0x80000000U) | ((uint32_t)(1) << 31)
3371 #define EMAC_REGS__INT_STATUS__RESERVED_31_31__CLR(dst) \
3372                     (dst) = ((dst) &\
3373                     ~0x80000000U) | ((uint32_t)(0) << 31)
3374 #define EMAC_REGS__INT_STATUS__TYPE                                    uint32_t
3375 #define EMAC_REGS__INT_STATUS__READ                                 0xffffffffU
3376 #define EMAC_REGS__INT_STATUS__RCLR                                 0x3ffffeffU
3377 #define EMAC_REGS__INT_STATUS__WRITE                                0xffffffffU
3378 
3379 #endif /* __EMAC_REGS__INT_STATUS_MACRO__ */
3380 
3381 
3382 /* macros for int_status */
3383 #define INST_INT_STATUS__NUM                                                  1
3384 
3385 /* macros for BlueprintGlobalNameSpace::emac_regs::int_enable */
3386 #ifndef __EMAC_REGS__INT_ENABLE_MACRO__
3387 #define __EMAC_REGS__INT_ENABLE_MACRO__
3388 
3389 /* macros for field enable_management_done_interrupt */
3390 #define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__SHIFT        0
3391 #define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__WIDTH        1
3392 #define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__MASK \
3393                     0x00000001U
3394 #define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__RESET        0
3395 #define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__WRITE(src) \
3396                     ((uint32_t)(src)\
3397                     & 0x00000001U)
3398 #define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__MODIFY(dst, src) \
3399                     (dst) = ((dst) &\
3400                     ~0x00000001U) | ((uint32_t)(src) &\
3401                     0x00000001U)
3402 #define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__VERIFY(src) \
3403                     (!(((uint32_t)(src)\
3404                     & ~0x00000001U)))
3405 #define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__SET(dst) \
3406                     (dst) = ((dst) &\
3407                     ~0x00000001U) | (uint32_t)(1)
3408 #define EMAC_REGS__INT_ENABLE__ENABLE_MANAGEMENT_DONE_INTERRUPT__CLR(dst) \
3409                     (dst) = ((dst) &\
3410                     ~0x00000001U) | (uint32_t)(0)
3411 
3412 /* macros for field enable_receive_complete_interrupt */
3413 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__SHIFT       1
3414 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__WIDTH       1
3415 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__MASK \
3416                     0x00000002U
3417 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__RESET       0
3418 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__WRITE(src) \
3419                     (((uint32_t)(src)\
3420                     << 1) & 0x00000002U)
3421 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__MODIFY(dst, src) \
3422                     (dst) = ((dst) &\
3423                     ~0x00000002U) | (((uint32_t)(src) <<\
3424                     1) & 0x00000002U)
3425 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__VERIFY(src) \
3426                     (!((((uint32_t)(src)\
3427                     << 1) & ~0x00000002U)))
3428 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__SET(dst) \
3429                     (dst) = ((dst) &\
3430                     ~0x00000002U) | ((uint32_t)(1) << 1)
3431 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__CLR(dst) \
3432                     (dst) = ((dst) &\
3433                     ~0x00000002U) | ((uint32_t)(0) << 1)
3434 
3435 /* macros for field enable_receive_used_bit_read_interrupt */
3436 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__SHIFT  2
3437 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__WIDTH  1
3438 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__MASK \
3439                     0x00000004U
3440 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__RESET  0
3441 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__WRITE(src) \
3442                     (((uint32_t)(src)\
3443                     << 2) & 0x00000004U)
3444 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \
3445                     (dst) = ((dst) &\
3446                     ~0x00000004U) | (((uint32_t)(src) <<\
3447                     2) & 0x00000004U)
3448 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__VERIFY(src) \
3449                     (!((((uint32_t)(src)\
3450                     << 2) & ~0x00000004U)))
3451 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__SET(dst) \
3452                     (dst) = ((dst) &\
3453                     ~0x00000004U) | ((uint32_t)(1) << 2)
3454 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT__CLR(dst) \
3455                     (dst) = ((dst) &\
3456                     ~0x00000004U) | ((uint32_t)(0) << 2)
3457 
3458 /* macros for field enable_transmit_used_bit_read_interrupt */
3459 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SHIFT 3
3460 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__WIDTH 1
3461 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__MASK \
3462                     0x00000008U
3463 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__RESET 0
3464 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__WRITE(src) \
3465                     (((uint32_t)(src)\
3466                     << 3) & 0x00000008U)
3467 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \
3468                     (dst) = ((dst) &\
3469                     ~0x00000008U) | (((uint32_t)(src) <<\
3470                     3) & 0x00000008U)
3471 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__VERIFY(src) \
3472                     (!((((uint32_t)(src)\
3473                     << 3) & ~0x00000008U)))
3474 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SET(dst) \
3475                     (dst) = ((dst) &\
3476                     ~0x00000008U) | ((uint32_t)(1) << 3)
3477 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__CLR(dst) \
3478                     (dst) = ((dst) &\
3479                     ~0x00000008U) | ((uint32_t)(0) << 3)
3480 
3481 /* macros for field enable_transmit_buffer_under_run_interrupt */
3482 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__SHIFT \
3483                     4
3484 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__WIDTH \
3485                     1
3486 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__MASK \
3487                     0x00000010U
3488 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__RESET \
3489                     0
3490 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__WRITE(src) \
3491                     (((uint32_t)(src)\
3492                     << 4) & 0x00000010U)
3493 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__MODIFY(dst, src) \
3494                     (dst) = ((dst) &\
3495                     ~0x00000010U) | (((uint32_t)(src) <<\
3496                     4) & 0x00000010U)
3497 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__VERIFY(src) \
3498                     (!((((uint32_t)(src)\
3499                     << 4) & ~0x00000010U)))
3500 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__SET(dst) \
3501                     (dst) = ((dst) &\
3502                     ~0x00000010U) | ((uint32_t)(1) << 4)
3503 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__CLR(dst) \
3504                     (dst) = ((dst) &\
3505                     ~0x00000010U) | ((uint32_t)(0) << 4)
3506 
3507 /* macros for field enable_retry_limit_exceeded_or_late_collision_interrupt */
3508 #define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SHIFT \
3509                     5
3510 #define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WIDTH \
3511                     1
3512 #define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MASK \
3513                     0x00000020U
3514 #define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__RESET \
3515                     0
3516 #define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WRITE(src) \
3517                     (((uint32_t)(src)\
3518                     << 5) & 0x00000020U)
3519 #define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MODIFY(dst, src) \
3520                     (dst) = ((dst) &\
3521                     ~0x00000020U) | (((uint32_t)(src) <<\
3522                     5) & 0x00000020U)
3523 #define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__VERIFY(src) \
3524                     (!((((uint32_t)(src)\
3525                     << 5) & ~0x00000020U)))
3526 #define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SET(dst) \
3527                     (dst) = ((dst) &\
3528                     ~0x00000020U) | ((uint32_t)(1) << 5)
3529 #define EMAC_REGS__INT_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__CLR(dst) \
3530                     (dst) = ((dst) &\
3531                     ~0x00000020U) | ((uint32_t)(0) << 5)
3532 
3533 /* macros for field enable_transmit_frame_corruption_due_to_amba_error_interrupt */
3534 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SHIFT \
3535                     6
3536 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WIDTH \
3537                     1
3538 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MASK \
3539                     0x00000040U
3540 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__RESET \
3541                     0
3542 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WRITE(src) \
3543                     (((uint32_t)(src)\
3544                     << 6) & 0x00000040U)
3545 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MODIFY(dst, src) \
3546                     (dst) = ((dst) &\
3547                     ~0x00000040U) | (((uint32_t)(src) <<\
3548                     6) & 0x00000040U)
3549 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__VERIFY(src) \
3550                     (!((((uint32_t)(src)\
3551                     << 6) & ~0x00000040U)))
3552 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SET(dst) \
3553                     (dst) = ((dst) &\
3554                     ~0x00000040U) | ((uint32_t)(1) << 6)
3555 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__CLR(dst) \
3556                     (dst) = ((dst) &\
3557                     ~0x00000040U) | ((uint32_t)(0) << 6)
3558 
3559 /* macros for field enable_transmit_complete_interrupt */
3560 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__SHIFT      7
3561 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__WIDTH      1
3562 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__MASK \
3563                     0x00000080U
3564 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__RESET      0
3565 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__WRITE(src) \
3566                     (((uint32_t)(src)\
3567                     << 7) & 0x00000080U)
3568 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__MODIFY(dst, src) \
3569                     (dst) = ((dst) &\
3570                     ~0x00000080U) | (((uint32_t)(src) <<\
3571                     7) & 0x00000080U)
3572 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__VERIFY(src) \
3573                     (!((((uint32_t)(src)\
3574                     << 7) & ~0x00000080U)))
3575 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__SET(dst) \
3576                     (dst) = ((dst) &\
3577                     ~0x00000080U) | ((uint32_t)(1) << 7)
3578 #define EMAC_REGS__INT_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__CLR(dst) \
3579                     (dst) = ((dst) &\
3580                     ~0x00000080U) | ((uint32_t)(0) << 7)
3581 
3582 /* macros for field not_used */
3583 #define EMAC_REGS__INT_ENABLE__NOT_USED__SHIFT                                8
3584 #define EMAC_REGS__INT_ENABLE__NOT_USED__WIDTH                                1
3585 #define EMAC_REGS__INT_ENABLE__NOT_USED__MASK                       0x00000100U
3586 #define EMAC_REGS__INT_ENABLE__NOT_USED__RESET                                0
3587 #define EMAC_REGS__INT_ENABLE__NOT_USED__READ(src) \
3588                     (((uint32_t)(src)\
3589                     & 0x00000100U) >> 8)
3590 #define EMAC_REGS__INT_ENABLE__NOT_USED__SET(dst) \
3591                     (dst) = ((dst) &\
3592                     ~0x00000100U) | ((uint32_t)(1) << 8)
3593 #define EMAC_REGS__INT_ENABLE__NOT_USED__CLR(dst) \
3594                     (dst) = ((dst) &\
3595                     ~0x00000100U) | ((uint32_t)(0) << 8)
3596 
3597 /* macros for field enable_link_change_interrupt */
3598 #define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__SHIFT            9
3599 #define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__WIDTH            1
3600 #define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__MASK   0x00000200U
3601 #define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__RESET            0
3602 #define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__WRITE(src) \
3603                     (((uint32_t)(src)\
3604                     << 9) & 0x00000200U)
3605 #define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__MODIFY(dst, src) \
3606                     (dst) = ((dst) &\
3607                     ~0x00000200U) | (((uint32_t)(src) <<\
3608                     9) & 0x00000200U)
3609 #define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__VERIFY(src) \
3610                     (!((((uint32_t)(src)\
3611                     << 9) & ~0x00000200U)))
3612 #define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__SET(dst) \
3613                     (dst) = ((dst) &\
3614                     ~0x00000200U) | ((uint32_t)(1) << 9)
3615 #define EMAC_REGS__INT_ENABLE__ENABLE_LINK_CHANGE_INTERRUPT__CLR(dst) \
3616                     (dst) = ((dst) &\
3617                     ~0x00000200U) | ((uint32_t)(0) << 9)
3618 
3619 /* macros for field enable_receive_overrun_interrupt */
3620 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__SHIFT       10
3621 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__WIDTH        1
3622 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__MASK \
3623                     0x00000400U
3624 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__RESET        0
3625 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__WRITE(src) \
3626                     (((uint32_t)(src)\
3627                     << 10) & 0x00000400U)
3628 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__MODIFY(dst, src) \
3629                     (dst) = ((dst) &\
3630                     ~0x00000400U) | (((uint32_t)(src) <<\
3631                     10) & 0x00000400U)
3632 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__VERIFY(src) \
3633                     (!((((uint32_t)(src)\
3634                     << 10) & ~0x00000400U)))
3635 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__SET(dst) \
3636                     (dst) = ((dst) &\
3637                     ~0x00000400U) | ((uint32_t)(1) << 10)
3638 #define EMAC_REGS__INT_ENABLE__ENABLE_RECEIVE_OVERRUN_INTERRUPT__CLR(dst) \
3639                     (dst) = ((dst) &\
3640                     ~0x00000400U) | ((uint32_t)(0) << 10)
3641 
3642 /* macros for field enable_resp_not_ok_interrupt */
3643 #define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__SHIFT           11
3644 #define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__WIDTH            1
3645 #define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__MASK   0x00000800U
3646 #define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__RESET            0
3647 #define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__WRITE(src) \
3648                     (((uint32_t)(src)\
3649                     << 11) & 0x00000800U)
3650 #define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__MODIFY(dst, src) \
3651                     (dst) = ((dst) &\
3652                     ~0x00000800U) | (((uint32_t)(src) <<\
3653                     11) & 0x00000800U)
3654 #define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__VERIFY(src) \
3655                     (!((((uint32_t)(src)\
3656                     << 11) & ~0x00000800U)))
3657 #define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__SET(dst) \
3658                     (dst) = ((dst) &\
3659                     ~0x00000800U) | ((uint32_t)(1) << 11)
3660 #define EMAC_REGS__INT_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__CLR(dst) \
3661                     (dst) = ((dst) &\
3662                     ~0x00000800U) | ((uint32_t)(0) << 11)
3663 
3664 /* macros for field enable_pause_frame_with_non_zero_pause_quantum_interrupt */
3665 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__SHIFT \
3666                     12
3667 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__WIDTH \
3668                     1
3669 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__MASK \
3670                     0x00001000U
3671 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__RESET \
3672                     0
3673 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__WRITE(src) \
3674                     (((uint32_t)(src)\
3675                     << 12) & 0x00001000U)
3676 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__MODIFY(dst, src) \
3677                     (dst) = ((dst) &\
3678                     ~0x00001000U) | (((uint32_t)(src) <<\
3679                     12) & 0x00001000U)
3680 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__VERIFY(src) \
3681                     (!((((uint32_t)(src)\
3682                     << 12) & ~0x00001000U)))
3683 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__SET(dst) \
3684                     (dst) = ((dst) &\
3685                     ~0x00001000U) | ((uint32_t)(1) << 12)
3686 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__CLR(dst) \
3687                     (dst) = ((dst) &\
3688                     ~0x00001000U) | ((uint32_t)(0) << 12)
3689 
3690 /* macros for field enable_pause_time_zero_interrupt */
3691 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__SHIFT       13
3692 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__WIDTH        1
3693 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__MASK \
3694                     0x00002000U
3695 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__RESET        0
3696 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__WRITE(src) \
3697                     (((uint32_t)(src)\
3698                     << 13) & 0x00002000U)
3699 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__MODIFY(dst, src) \
3700                     (dst) = ((dst) &\
3701                     ~0x00002000U) | (((uint32_t)(src) <<\
3702                     13) & 0x00002000U)
3703 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__VERIFY(src) \
3704                     (!((((uint32_t)(src)\
3705                     << 13) & ~0x00002000U)))
3706 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__SET(dst) \
3707                     (dst) = ((dst) &\
3708                     ~0x00002000U) | ((uint32_t)(1) << 13)
3709 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_TIME_ZERO_INTERRUPT__CLR(dst) \
3710                     (dst) = ((dst) &\
3711                     ~0x00002000U) | ((uint32_t)(0) << 13)
3712 
3713 /* macros for field enable_pause_frame_transmitted_interrupt */
3714 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__SHIFT \
3715                     14
3716 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__WIDTH \
3717                     1
3718 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__MASK \
3719                     0x00004000U
3720 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__RESET \
3721                     0
3722 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__WRITE(src) \
3723                     (((uint32_t)(src)\
3724                     << 14) & 0x00004000U)
3725 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__MODIFY(dst, src) \
3726                     (dst) = ((dst) &\
3727                     ~0x00004000U) | (((uint32_t)(src) <<\
3728                     14) & 0x00004000U)
3729 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__VERIFY(src) \
3730                     (!((((uint32_t)(src)\
3731                     << 14) & ~0x00004000U)))
3732 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__SET(dst) \
3733                     (dst) = ((dst) &\
3734                     ~0x00004000U) | ((uint32_t)(1) << 14)
3735 #define EMAC_REGS__INT_ENABLE__ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__CLR(dst) \
3736                     (dst) = ((dst) &\
3737                     ~0x00004000U) | ((uint32_t)(0) << 14)
3738 
3739 /* macros for field enable_external_interrupt */
3740 #define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__SHIFT              15
3741 #define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__WIDTH               1
3742 #define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__MASK      0x00008000U
3743 #define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__RESET               0
3744 #define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__WRITE(src) \
3745                     (((uint32_t)(src)\
3746                     << 15) & 0x00008000U)
3747 #define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__MODIFY(dst, src) \
3748                     (dst) = ((dst) &\
3749                     ~0x00008000U) | (((uint32_t)(src) <<\
3750                     15) & 0x00008000U)
3751 #define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__VERIFY(src) \
3752                     (!((((uint32_t)(src)\
3753                     << 15) & ~0x00008000U)))
3754 #define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__SET(dst) \
3755                     (dst) = ((dst) &\
3756                     ~0x00008000U) | ((uint32_t)(1) << 15)
3757 #define EMAC_REGS__INT_ENABLE__ENABLE_EXTERNAL_INTERRUPT__CLR(dst) \
3758                     (dst) = ((dst) &\
3759                     ~0x00008000U) | ((uint32_t)(0) << 15)
3760 
3761 /* macros for field enable_pcs_auto_negotiation_complete_interrupt */
3762 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__SHIFT \
3763                     16
3764 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__WIDTH \
3765                     1
3766 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__MASK \
3767                     0x00010000U
3768 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__RESET \
3769                     0
3770 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__WRITE(src) \
3771                     (((uint32_t)(src)\
3772                     << 16) & 0x00010000U)
3773 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__MODIFY(dst, src) \
3774                     (dst) = ((dst) &\
3775                     ~0x00010000U) | (((uint32_t)(src) <<\
3776                     16) & 0x00010000U)
3777 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__VERIFY(src) \
3778                     (!((((uint32_t)(src)\
3779                     << 16) & ~0x00010000U)))
3780 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__SET(dst) \
3781                     (dst) = ((dst) &\
3782                     ~0x00010000U) | ((uint32_t)(1) << 16)
3783 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__CLR(dst) \
3784                     (dst) = ((dst) &\
3785                     ~0x00010000U) | ((uint32_t)(0) << 16)
3786 
3787 /* macros for field enable_pcs_link_partner_page_received */
3788 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__SHIFT  17
3789 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__WIDTH   1
3790 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__MASK \
3791                     0x00020000U
3792 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__RESET   0
3793 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__WRITE(src) \
3794                     (((uint32_t)(src)\
3795                     << 17) & 0x00020000U)
3796 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__MODIFY(dst, src) \
3797                     (dst) = ((dst) &\
3798                     ~0x00020000U) | (((uint32_t)(src) <<\
3799                     17) & 0x00020000U)
3800 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__VERIFY(src) \
3801                     (!((((uint32_t)(src)\
3802                     << 17) & ~0x00020000U)))
3803 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__SET(dst) \
3804                     (dst) = ((dst) &\
3805                     ~0x00020000U) | ((uint32_t)(1) << 17)
3806 #define EMAC_REGS__INT_ENABLE__ENABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__CLR(dst) \
3807                     (dst) = ((dst) &\
3808                     ~0x00020000U) | ((uint32_t)(0) << 17)
3809 
3810 /* macros for field enable_ptp_delay_req_frame_received */
3811 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__SHIFT    18
3812 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__WIDTH     1
3813 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__MASK \
3814                     0x00040000U
3815 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__RESET     0
3816 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__WRITE(src) \
3817                     (((uint32_t)(src)\
3818                     << 18) & 0x00040000U)
3819 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \
3820                     (dst) = ((dst) &\
3821                     ~0x00040000U) | (((uint32_t)(src) <<\
3822                     18) & 0x00040000U)
3823 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__VERIFY(src) \
3824                     (!((((uint32_t)(src)\
3825                     << 18) & ~0x00040000U)))
3826 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__SET(dst) \
3827                     (dst) = ((dst) &\
3828                     ~0x00040000U) | ((uint32_t)(1) << 18)
3829 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED__CLR(dst) \
3830                     (dst) = ((dst) &\
3831                     ~0x00040000U) | ((uint32_t)(0) << 18)
3832 
3833 /* macros for field enable_ptp_sync_frame_received */
3834 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__SHIFT         19
3835 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__WIDTH          1
3836 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__MASK 0x00080000U
3837 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__RESET          0
3838 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__WRITE(src) \
3839                     (((uint32_t)(src)\
3840                     << 19) & 0x00080000U)
3841 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__MODIFY(dst, src) \
3842                     (dst) = ((dst) &\
3843                     ~0x00080000U) | (((uint32_t)(src) <<\
3844                     19) & 0x00080000U)
3845 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__VERIFY(src) \
3846                     (!((((uint32_t)(src)\
3847                     << 19) & ~0x00080000U)))
3848 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__SET(dst) \
3849                     (dst) = ((dst) &\
3850                     ~0x00080000U) | ((uint32_t)(1) << 19)
3851 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_RECEIVED__CLR(dst) \
3852                     (dst) = ((dst) &\
3853                     ~0x00080000U) | ((uint32_t)(0) << 19)
3854 
3855 /* macros for field enable_ptp_delay_req_frame_transmitted */
3856 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__SHIFT 20
3857 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__WIDTH  1
3858 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__MASK \
3859                     0x00100000U
3860 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__RESET  0
3861 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \
3862                     (((uint32_t)(src)\
3863                     << 20) & 0x00100000U)
3864 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \
3865                     (dst) = ((dst) &\
3866                     ~0x00100000U) | (((uint32_t)(src) <<\
3867                     20) & 0x00100000U)
3868 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \
3869                     (!((((uint32_t)(src)\
3870                     << 20) & ~0x00100000U)))
3871 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__SET(dst) \
3872                     (dst) = ((dst) &\
3873                     ~0x00100000U) | ((uint32_t)(1) << 20)
3874 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \
3875                     (dst) = ((dst) &\
3876                     ~0x00100000U) | ((uint32_t)(0) << 20)
3877 
3878 /* macros for field enable_ptp_sync_frame_transmitted */
3879 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__SHIFT      21
3880 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__WIDTH       1
3881 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__MASK \
3882                     0x00200000U
3883 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__RESET       0
3884 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__WRITE(src) \
3885                     (((uint32_t)(src)\
3886                     << 21) & 0x00200000U)
3887 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__MODIFY(dst, src) \
3888                     (dst) = ((dst) &\
3889                     ~0x00200000U) | (((uint32_t)(src) <<\
3890                     21) & 0x00200000U)
3891 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__VERIFY(src) \
3892                     (!((((uint32_t)(src)\
3893                     << 21) & ~0x00200000U)))
3894 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__SET(dst) \
3895                     (dst) = ((dst) &\
3896                     ~0x00200000U) | ((uint32_t)(1) << 21)
3897 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_SYNC_FRAME_TRANSMITTED__CLR(dst) \
3898                     (dst) = ((dst) &\
3899                     ~0x00200000U) | ((uint32_t)(0) << 21)
3900 
3901 /* macros for field enable_ptp_pdelay_req_frame_received */
3902 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__SHIFT   22
3903 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__WIDTH    1
3904 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__MASK \
3905                     0x00400000U
3906 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__RESET    0
3907 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__WRITE(src) \
3908                     (((uint32_t)(src)\
3909                     << 22) & 0x00400000U)
3910 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \
3911                     (dst) = ((dst) &\
3912                     ~0x00400000U) | (((uint32_t)(src) <<\
3913                     22) & 0x00400000U)
3914 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__VERIFY(src) \
3915                     (!((((uint32_t)(src)\
3916                     << 22) & ~0x00400000U)))
3917 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__SET(dst) \
3918                     (dst) = ((dst) &\
3919                     ~0x00400000U) | ((uint32_t)(1) << 22)
3920 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__CLR(dst) \
3921                     (dst) = ((dst) &\
3922                     ~0x00400000U) | ((uint32_t)(0) << 22)
3923 
3924 /* macros for field enable_ptp_pdelay_resp_frame_received */
3925 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__SHIFT  23
3926 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__WIDTH   1
3927 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__MASK \
3928                     0x00800000U
3929 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__RESET   0
3930 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__WRITE(src) \
3931                     (((uint32_t)(src)\
3932                     << 23) & 0x00800000U)
3933 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__MODIFY(dst, src) \
3934                     (dst) = ((dst) &\
3935                     ~0x00800000U) | (((uint32_t)(src) <<\
3936                     23) & 0x00800000U)
3937 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__VERIFY(src) \
3938                     (!((((uint32_t)(src)\
3939                     << 23) & ~0x00800000U)))
3940 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__SET(dst) \
3941                     (dst) = ((dst) &\
3942                     ~0x00800000U) | ((uint32_t)(1) << 23)
3943 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__CLR(dst) \
3944                     (dst) = ((dst) &\
3945                     ~0x00800000U) | ((uint32_t)(0) << 23)
3946 
3947 /* macros for field enable_ptp_pdelay_req_frame_transmitted */
3948 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__SHIFT \
3949                     24
3950 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__WIDTH 1
3951 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__MASK \
3952                     0x01000000U
3953 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__RESET 0
3954 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \
3955                     (((uint32_t)(src)\
3956                     << 24) & 0x01000000U)
3957 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \
3958                     (dst) = ((dst) &\
3959                     ~0x01000000U) | (((uint32_t)(src) <<\
3960                     24) & 0x01000000U)
3961 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \
3962                     (!((((uint32_t)(src)\
3963                     << 24) & ~0x01000000U)))
3964 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__SET(dst) \
3965                     (dst) = ((dst) &\
3966                     ~0x01000000U) | ((uint32_t)(1) << 24)
3967 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \
3968                     (dst) = ((dst) &\
3969                     ~0x01000000U) | ((uint32_t)(0) << 24)
3970 
3971 /* macros for field enable_ptp_pdelay_resp_frame_transmitted */
3972 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__SHIFT \
3973                     25
3974 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__WIDTH \
3975                     1
3976 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__MASK \
3977                     0x02000000U
3978 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__RESET \
3979                     0
3980 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__WRITE(src) \
3981                     (((uint32_t)(src)\
3982                     << 25) & 0x02000000U)
3983 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__MODIFY(dst, src) \
3984                     (dst) = ((dst) &\
3985                     ~0x02000000U) | (((uint32_t)(src) <<\
3986                     25) & 0x02000000U)
3987 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__VERIFY(src) \
3988                     (!((((uint32_t)(src)\
3989                     << 25) & ~0x02000000U)))
3990 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__SET(dst) \
3991                     (dst) = ((dst) &\
3992                     ~0x02000000U) | ((uint32_t)(1) << 25)
3993 #define EMAC_REGS__INT_ENABLE__ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__CLR(dst) \
3994                     (dst) = ((dst) &\
3995                     ~0x02000000U) | ((uint32_t)(0) << 25)
3996 
3997 /* macros for field enable_tsu_seconds_register_increment */
3998 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__SHIFT  26
3999 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__WIDTH   1
4000 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__MASK \
4001                     0x04000000U
4002 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__RESET   0
4003 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__WRITE(src) \
4004                     (((uint32_t)(src)\
4005                     << 26) & 0x04000000U)
4006 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__MODIFY(dst, src) \
4007                     (dst) = ((dst) &\
4008                     ~0x04000000U) | (((uint32_t)(src) <<\
4009                     26) & 0x04000000U)
4010 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__VERIFY(src) \
4011                     (!((((uint32_t)(src)\
4012                     << 26) & ~0x04000000U)))
4013 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__SET(dst) \
4014                     (dst) = ((dst) &\
4015                     ~0x04000000U) | ((uint32_t)(1) << 26)
4016 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_SECONDS_REGISTER_INCREMENT__CLR(dst) \
4017                     (dst) = ((dst) &\
4018                     ~0x04000000U) | ((uint32_t)(0) << 26)
4019 
4020 /* macros for field enable_rx_lpi_indication_interrupt */
4021 #define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__SHIFT     27
4022 #define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__WIDTH      1
4023 #define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__MASK \
4024                     0x08000000U
4025 #define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__RESET      0
4026 #define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__WRITE(src) \
4027                     (((uint32_t)(src)\
4028                     << 27) & 0x08000000U)
4029 #define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__MODIFY(dst, src) \
4030                     (dst) = ((dst) &\
4031                     ~0x08000000U) | (((uint32_t)(src) <<\
4032                     27) & 0x08000000U)
4033 #define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__VERIFY(src) \
4034                     (!((((uint32_t)(src)\
4035                     << 27) & ~0x08000000U)))
4036 #define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__SET(dst) \
4037                     (dst) = ((dst) &\
4038                     ~0x08000000U) | ((uint32_t)(1) << 27)
4039 #define EMAC_REGS__INT_ENABLE__ENABLE_RX_LPI_INDICATION_INTERRUPT__CLR(dst) \
4040                     (dst) = ((dst) &\
4041                     ~0x08000000U) | ((uint32_t)(0) << 27)
4042 
4043 /* macros for field enable_wol_event_received_interrupt */
4044 #define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__SHIFT    28
4045 #define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__WIDTH     1
4046 #define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__MASK \
4047                     0x10000000U
4048 #define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__RESET     0
4049 #define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__WRITE(src) \
4050                     (((uint32_t)(src)\
4051                     << 28) & 0x10000000U)
4052 #define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__MODIFY(dst, src) \
4053                     (dst) = ((dst) &\
4054                     ~0x10000000U) | (((uint32_t)(src) <<\
4055                     28) & 0x10000000U)
4056 #define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__VERIFY(src) \
4057                     (!((((uint32_t)(src)\
4058                     << 28) & ~0x10000000U)))
4059 #define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__SET(dst) \
4060                     (dst) = ((dst) &\
4061                     ~0x10000000U) | ((uint32_t)(1) << 28)
4062 #define EMAC_REGS__INT_ENABLE__ENABLE_WOL_EVENT_RECEIVED_INTERRUPT__CLR(dst) \
4063                     (dst) = ((dst) &\
4064                     ~0x10000000U) | ((uint32_t)(0) << 28)
4065 
4066 /* macros for field enable_tsu_timer_comparison_interrupt */
4067 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__SHIFT  29
4068 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__WIDTH   1
4069 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__MASK \
4070                     0x20000000U
4071 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__RESET 0b0
4072 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__WRITE(src) \
4073                     (((uint32_t)(src)\
4074                     << 29) & 0x20000000U)
4075 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__MODIFY(dst, src) \
4076                     (dst) = ((dst) &\
4077                     ~0x20000000U) | (((uint32_t)(src) <<\
4078                     29) & 0x20000000U)
4079 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__VERIFY(src) \
4080                     (!((((uint32_t)(src)\
4081                     << 29) & ~0x20000000U)))
4082 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__SET(dst) \
4083                     (dst) = ((dst) &\
4084                     ~0x20000000U) | ((uint32_t)(1) << 29)
4085 #define EMAC_REGS__INT_ENABLE__ENABLE_TSU_TIMER_COMPARISON_INTERRUPT__CLR(dst) \
4086                     (dst) = ((dst) &\
4087                     ~0x20000000U) | ((uint32_t)(0) << 29)
4088 
4089 /* macros for field reserved_30_30 */
4090 #define EMAC_REGS__INT_ENABLE__RESERVED_30_30__SHIFT                         30
4091 #define EMAC_REGS__INT_ENABLE__RESERVED_30_30__WIDTH                          1
4092 #define EMAC_REGS__INT_ENABLE__RESERVED_30_30__MASK                 0x40000000U
4093 #define EMAC_REGS__INT_ENABLE__RESERVED_30_30__RESET                          0
4094 #define EMAC_REGS__INT_ENABLE__RESERVED_30_30__READ(src) \
4095                     (((uint32_t)(src)\
4096                     & 0x40000000U) >> 30)
4097 #define EMAC_REGS__INT_ENABLE__RESERVED_30_30__SET(dst) \
4098                     (dst) = ((dst) &\
4099                     ~0x40000000U) | ((uint32_t)(1) << 30)
4100 #define EMAC_REGS__INT_ENABLE__RESERVED_30_30__CLR(dst) \
4101                     (dst) = ((dst) &\
4102                     ~0x40000000U) | ((uint32_t)(0) << 30)
4103 
4104 /* macros for field reserved_31_31 */
4105 #define EMAC_REGS__INT_ENABLE__RESERVED_31_31__SHIFT                         31
4106 #define EMAC_REGS__INT_ENABLE__RESERVED_31_31__WIDTH                          1
4107 #define EMAC_REGS__INT_ENABLE__RESERVED_31_31__MASK                 0x80000000U
4108 #define EMAC_REGS__INT_ENABLE__RESERVED_31_31__RESET                          0
4109 #define EMAC_REGS__INT_ENABLE__RESERVED_31_31__READ(src) \
4110                     (((uint32_t)(src)\
4111                     & 0x80000000U) >> 31)
4112 #define EMAC_REGS__INT_ENABLE__RESERVED_31_31__SET(dst) \
4113                     (dst) = ((dst) &\
4114                     ~0x80000000U) | ((uint32_t)(1) << 31)
4115 #define EMAC_REGS__INT_ENABLE__RESERVED_31_31__CLR(dst) \
4116                     (dst) = ((dst) &\
4117                     ~0x80000000U) | ((uint32_t)(0) << 31)
4118 #define EMAC_REGS__INT_ENABLE__TYPE                                    uint32_t
4119 #define EMAC_REGS__INT_ENABLE__READ                                 0xc0000100U
4120 #define EMAC_REGS__INT_ENABLE__WRITE                                0xc0000100U
4121 
4122 #endif /* __EMAC_REGS__INT_ENABLE_MACRO__ */
4123 
4124 
4125 /* macros for int_enable */
4126 #define INST_INT_ENABLE__NUM                                                  1
4127 
4128 /* macros for BlueprintGlobalNameSpace::emac_regs::int_disable */
4129 #ifndef __EMAC_REGS__INT_DISABLE_MACRO__
4130 #define __EMAC_REGS__INT_DISABLE_MACRO__
4131 
4132 /* macros for field disable_management_done_interrupt */
4133 #define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__SHIFT      0
4134 #define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__WIDTH      1
4135 #define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__MASK \
4136                     0x00000001U
4137 #define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__RESET      0
4138 #define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__WRITE(src) \
4139                     ((uint32_t)(src)\
4140                     & 0x00000001U)
4141 #define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__MODIFY(dst, src) \
4142                     (dst) = ((dst) &\
4143                     ~0x00000001U) | ((uint32_t)(src) &\
4144                     0x00000001U)
4145 #define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__VERIFY(src) \
4146                     (!(((uint32_t)(src)\
4147                     & ~0x00000001U)))
4148 #define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__SET(dst) \
4149                     (dst) = ((dst) &\
4150                     ~0x00000001U) | (uint32_t)(1)
4151 #define EMAC_REGS__INT_DISABLE__DISABLE_MANAGEMENT_DONE_INTERRUPT__CLR(dst) \
4152                     (dst) = ((dst) &\
4153                     ~0x00000001U) | (uint32_t)(0)
4154 
4155 /* macros for field disable_receive_complete_interrupt */
4156 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__SHIFT     1
4157 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__WIDTH     1
4158 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__MASK \
4159                     0x00000002U
4160 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__RESET     0
4161 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__WRITE(src) \
4162                     (((uint32_t)(src)\
4163                     << 1) & 0x00000002U)
4164 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__MODIFY(dst, src) \
4165                     (dst) = ((dst) &\
4166                     ~0x00000002U) | (((uint32_t)(src) <<\
4167                     1) & 0x00000002U)
4168 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__VERIFY(src) \
4169                     (!((((uint32_t)(src)\
4170                     << 1) & ~0x00000002U)))
4171 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__SET(dst) \
4172                     (dst) = ((dst) &\
4173                     ~0x00000002U) | ((uint32_t)(1) << 1)
4174 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__CLR(dst) \
4175                     (dst) = ((dst) &\
4176                     ~0x00000002U) | ((uint32_t)(0) << 1)
4177 
4178 /* macros for field disable_receive_used_bit_read_interrupt */
4179 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__SHIFT \
4180                     2
4181 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__WIDTH \
4182                     1
4183 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__MASK \
4184                     0x00000004U
4185 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__RESET \
4186                     0
4187 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__WRITE(src) \
4188                     (((uint32_t)(src)\
4189                     << 2) & 0x00000004U)
4190 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \
4191                     (dst) = ((dst) &\
4192                     ~0x00000004U) | (((uint32_t)(src) <<\
4193                     2) & 0x00000004U)
4194 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__VERIFY(src) \
4195                     (!((((uint32_t)(src)\
4196                     << 2) & ~0x00000004U)))
4197 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__SET(dst) \
4198                     (dst) = ((dst) &\
4199                     ~0x00000004U) | ((uint32_t)(1) << 2)
4200 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT__CLR(dst) \
4201                     (dst) = ((dst) &\
4202                     ~0x00000004U) | ((uint32_t)(0) << 2)
4203 
4204 /* macros for field disable_transmit_used_bit_read_interrupt */
4205 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SHIFT \
4206                     3
4207 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__WIDTH \
4208                     1
4209 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__MASK \
4210                     0x00000008U
4211 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__RESET \
4212                     0
4213 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__WRITE(src) \
4214                     (((uint32_t)(src)\
4215                     << 3) & 0x00000008U)
4216 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \
4217                     (dst) = ((dst) &\
4218                     ~0x00000008U) | (((uint32_t)(src) <<\
4219                     3) & 0x00000008U)
4220 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__VERIFY(src) \
4221                     (!((((uint32_t)(src)\
4222                     << 3) & ~0x00000008U)))
4223 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__SET(dst) \
4224                     (dst) = ((dst) &\
4225                     ~0x00000008U) | ((uint32_t)(1) << 3)
4226 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT__CLR(dst) \
4227                     (dst) = ((dst) &\
4228                     ~0x00000008U) | ((uint32_t)(0) << 3)
4229 
4230 /* macros for field disable_transmit_buffer_under_run_interrupt */
4231 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__SHIFT \
4232                     4
4233 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__WIDTH \
4234                     1
4235 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__MASK \
4236                     0x00000010U
4237 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__RESET \
4238                     0
4239 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__WRITE(src) \
4240                     (((uint32_t)(src)\
4241                     << 4) & 0x00000010U)
4242 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__MODIFY(dst, src) \
4243                     (dst) = ((dst) &\
4244                     ~0x00000010U) | (((uint32_t)(src) <<\
4245                     4) & 0x00000010U)
4246 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__VERIFY(src) \
4247                     (!((((uint32_t)(src)\
4248                     << 4) & ~0x00000010U)))
4249 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__SET(dst) \
4250                     (dst) = ((dst) &\
4251                     ~0x00000010U) | ((uint32_t)(1) << 4)
4252 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT__CLR(dst) \
4253                     (dst) = ((dst) &\
4254                     ~0x00000010U) | ((uint32_t)(0) << 4)
4255 
4256 /* macros for field disable_retry_limit_exceeded_or_late_collision_interrupt */
4257 #define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SHIFT \
4258                     5
4259 #define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WIDTH \
4260                     1
4261 #define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MASK \
4262                     0x00000020U
4263 #define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__RESET \
4264                     0
4265 #define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WRITE(src) \
4266                     (((uint32_t)(src)\
4267                     << 5) & 0x00000020U)
4268 #define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MODIFY(dst, src) \
4269                     (dst) = ((dst) &\
4270                     ~0x00000020U) | (((uint32_t)(src) <<\
4271                     5) & 0x00000020U)
4272 #define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__VERIFY(src) \
4273                     (!((((uint32_t)(src)\
4274                     << 5) & ~0x00000020U)))
4275 #define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SET(dst) \
4276                     (dst) = ((dst) &\
4277                     ~0x00000020U) | ((uint32_t)(1) << 5)
4278 #define EMAC_REGS__INT_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__CLR(dst) \
4279                     (dst) = ((dst) &\
4280                     ~0x00000020U) | ((uint32_t)(0) << 5)
4281 
4282 /* macros for field disable_transmit_frame_corruption_due_to_amba_error_interrupt */
4283 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SHIFT \
4284                     6
4285 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WIDTH \
4286                     1
4287 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MASK \
4288                     0x00000040U
4289 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__RESET \
4290                     0
4291 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WRITE(src) \
4292                     (((uint32_t)(src)\
4293                     << 6) & 0x00000040U)
4294 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MODIFY(dst, src) \
4295                     (dst) = ((dst) &\
4296                     ~0x00000040U) | (((uint32_t)(src) <<\
4297                     6) & 0x00000040U)
4298 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__VERIFY(src) \
4299                     (!((((uint32_t)(src)\
4300                     << 6) & ~0x00000040U)))
4301 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SET(dst) \
4302                     (dst) = ((dst) &\
4303                     ~0x00000040U) | ((uint32_t)(1) << 6)
4304 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__CLR(dst) \
4305                     (dst) = ((dst) &\
4306                     ~0x00000040U) | ((uint32_t)(0) << 6)
4307 
4308 /* macros for field disable_transmit_complete_interrupt */
4309 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__SHIFT    7
4310 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__WIDTH    1
4311 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__MASK \
4312                     0x00000080U
4313 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__RESET    0
4314 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__WRITE(src) \
4315                     (((uint32_t)(src)\
4316                     << 7) & 0x00000080U)
4317 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__MODIFY(dst, src) \
4318                     (dst) = ((dst) &\
4319                     ~0x00000080U) | (((uint32_t)(src) <<\
4320                     7) & 0x00000080U)
4321 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__VERIFY(src) \
4322                     (!((((uint32_t)(src)\
4323                     << 7) & ~0x00000080U)))
4324 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__SET(dst) \
4325                     (dst) = ((dst) &\
4326                     ~0x00000080U) | ((uint32_t)(1) << 7)
4327 #define EMAC_REGS__INT_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__CLR(dst) \
4328                     (dst) = ((dst) &\
4329                     ~0x00000080U) | ((uint32_t)(0) << 7)
4330 
4331 /* macros for field not_used */
4332 #define EMAC_REGS__INT_DISABLE__NOT_USED__SHIFT                               8
4333 #define EMAC_REGS__INT_DISABLE__NOT_USED__WIDTH                               1
4334 #define EMAC_REGS__INT_DISABLE__NOT_USED__MASK                      0x00000100U
4335 #define EMAC_REGS__INT_DISABLE__NOT_USED__RESET                               0
4336 #define EMAC_REGS__INT_DISABLE__NOT_USED__READ(src) \
4337                     (((uint32_t)(src)\
4338                     & 0x00000100U) >> 8)
4339 #define EMAC_REGS__INT_DISABLE__NOT_USED__SET(dst) \
4340                     (dst) = ((dst) &\
4341                     ~0x00000100U) | ((uint32_t)(1) << 8)
4342 #define EMAC_REGS__INT_DISABLE__NOT_USED__CLR(dst) \
4343                     (dst) = ((dst) &\
4344                     ~0x00000100U) | ((uint32_t)(0) << 8)
4345 
4346 /* macros for field disable_link_change_interrupt */
4347 #define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__SHIFT          9
4348 #define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__WIDTH          1
4349 #define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__MASK 0x00000200U
4350 #define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__RESET          0
4351 #define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__WRITE(src) \
4352                     (((uint32_t)(src)\
4353                     << 9) & 0x00000200U)
4354 #define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__MODIFY(dst, src) \
4355                     (dst) = ((dst) &\
4356                     ~0x00000200U) | (((uint32_t)(src) <<\
4357                     9) & 0x00000200U)
4358 #define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__VERIFY(src) \
4359                     (!((((uint32_t)(src)\
4360                     << 9) & ~0x00000200U)))
4361 #define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__SET(dst) \
4362                     (dst) = ((dst) &\
4363                     ~0x00000200U) | ((uint32_t)(1) << 9)
4364 #define EMAC_REGS__INT_DISABLE__DISABLE_LINK_CHANGE_INTERRUPT__CLR(dst) \
4365                     (dst) = ((dst) &\
4366                     ~0x00000200U) | ((uint32_t)(0) << 9)
4367 
4368 /* macros for field disable_receive_overrun_interrupt */
4369 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__SHIFT     10
4370 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__WIDTH      1
4371 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__MASK \
4372                     0x00000400U
4373 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__RESET      0
4374 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__WRITE(src) \
4375                     (((uint32_t)(src)\
4376                     << 10) & 0x00000400U)
4377 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__MODIFY(dst, src) \
4378                     (dst) = ((dst) &\
4379                     ~0x00000400U) | (((uint32_t)(src) <<\
4380                     10) & 0x00000400U)
4381 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__VERIFY(src) \
4382                     (!((((uint32_t)(src)\
4383                     << 10) & ~0x00000400U)))
4384 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__SET(dst) \
4385                     (dst) = ((dst) &\
4386                     ~0x00000400U) | ((uint32_t)(1) << 10)
4387 #define EMAC_REGS__INT_DISABLE__DISABLE_RECEIVE_OVERRUN_INTERRUPT__CLR(dst) \
4388                     (dst) = ((dst) &\
4389                     ~0x00000400U) | ((uint32_t)(0) << 10)
4390 
4391 /* macros for field disable_resp_not_ok_interrupt */
4392 #define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__SHIFT         11
4393 #define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__WIDTH          1
4394 #define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__MASK 0x00000800U
4395 #define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__RESET          0
4396 #define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__WRITE(src) \
4397                     (((uint32_t)(src)\
4398                     << 11) & 0x00000800U)
4399 #define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__MODIFY(dst, src) \
4400                     (dst) = ((dst) &\
4401                     ~0x00000800U) | (((uint32_t)(src) <<\
4402                     11) & 0x00000800U)
4403 #define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__VERIFY(src) \
4404                     (!((((uint32_t)(src)\
4405                     << 11) & ~0x00000800U)))
4406 #define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__SET(dst) \
4407                     (dst) = ((dst) &\
4408                     ~0x00000800U) | ((uint32_t)(1) << 11)
4409 #define EMAC_REGS__INT_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__CLR(dst) \
4410                     (dst) = ((dst) &\
4411                     ~0x00000800U) | ((uint32_t)(0) << 11)
4412 
4413 /* macros for field disable_pause_frame_with_non_zero_pause_quantum_interrupt */
4414 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__SHIFT \
4415                     12
4416 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__WIDTH \
4417                     1
4418 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__MASK \
4419                     0x00001000U
4420 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__RESET \
4421                     0
4422 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__WRITE(src) \
4423                     (((uint32_t)(src)\
4424                     << 12) & 0x00001000U)
4425 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__MODIFY(dst, src) \
4426                     (dst) = ((dst) &\
4427                     ~0x00001000U) | (((uint32_t)(src) <<\
4428                     12) & 0x00001000U)
4429 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__VERIFY(src) \
4430                     (!((((uint32_t)(src)\
4431                     << 12) & ~0x00001000U)))
4432 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__SET(dst) \
4433                     (dst) = ((dst) &\
4434                     ~0x00001000U) | ((uint32_t)(1) << 12)
4435 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT__CLR(dst) \
4436                     (dst) = ((dst) &\
4437                     ~0x00001000U) | ((uint32_t)(0) << 12)
4438 
4439 /* macros for field disable_pause_time_zero_interrupt */
4440 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__SHIFT     13
4441 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__WIDTH      1
4442 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__MASK \
4443                     0x00002000U
4444 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__RESET      0
4445 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__WRITE(src) \
4446                     (((uint32_t)(src)\
4447                     << 13) & 0x00002000U)
4448 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__MODIFY(dst, src) \
4449                     (dst) = ((dst) &\
4450                     ~0x00002000U) | (((uint32_t)(src) <<\
4451                     13) & 0x00002000U)
4452 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__VERIFY(src) \
4453                     (!((((uint32_t)(src)\
4454                     << 13) & ~0x00002000U)))
4455 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__SET(dst) \
4456                     (dst) = ((dst) &\
4457                     ~0x00002000U) | ((uint32_t)(1) << 13)
4458 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_TIME_ZERO_INTERRUPT__CLR(dst) \
4459                     (dst) = ((dst) &\
4460                     ~0x00002000U) | ((uint32_t)(0) << 13)
4461 
4462 /* macros for field disable_pause_frame_transmitted_interrupt */
4463 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__SHIFT \
4464                     14
4465 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__WIDTH \
4466                     1
4467 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__MASK \
4468                     0x00004000U
4469 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__RESET \
4470                     0
4471 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__WRITE(src) \
4472                     (((uint32_t)(src)\
4473                     << 14) & 0x00004000U)
4474 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__MODIFY(dst, src) \
4475                     (dst) = ((dst) &\
4476                     ~0x00004000U) | (((uint32_t)(src) <<\
4477                     14) & 0x00004000U)
4478 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__VERIFY(src) \
4479                     (!((((uint32_t)(src)\
4480                     << 14) & ~0x00004000U)))
4481 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__SET(dst) \
4482                     (dst) = ((dst) &\
4483                     ~0x00004000U) | ((uint32_t)(1) << 14)
4484 #define EMAC_REGS__INT_DISABLE__DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT__CLR(dst) \
4485                     (dst) = ((dst) &\
4486                     ~0x00004000U) | ((uint32_t)(0) << 14)
4487 
4488 /* macros for field disable_external_interrupt */
4489 #define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__SHIFT            15
4490 #define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__WIDTH             1
4491 #define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__MASK    0x00008000U
4492 #define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__RESET             0
4493 #define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__WRITE(src) \
4494                     (((uint32_t)(src)\
4495                     << 15) & 0x00008000U)
4496 #define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__MODIFY(dst, src) \
4497                     (dst) = ((dst) &\
4498                     ~0x00008000U) | (((uint32_t)(src) <<\
4499                     15) & 0x00008000U)
4500 #define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__VERIFY(src) \
4501                     (!((((uint32_t)(src)\
4502                     << 15) & ~0x00008000U)))
4503 #define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__SET(dst) \
4504                     (dst) = ((dst) &\
4505                     ~0x00008000U) | ((uint32_t)(1) << 15)
4506 #define EMAC_REGS__INT_DISABLE__DISABLE_EXTERNAL_INTERRUPT__CLR(dst) \
4507                     (dst) = ((dst) &\
4508                     ~0x00008000U) | ((uint32_t)(0) << 15)
4509 
4510 /* macros for field disable_pcs_auto_negotiation_complete_interrupt */
4511 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__SHIFT \
4512                     16
4513 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__WIDTH \
4514                     1
4515 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__MASK \
4516                     0x00010000U
4517 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__RESET \
4518                     0
4519 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__WRITE(src) \
4520                     (((uint32_t)(src)\
4521                     << 16) & 0x00010000U)
4522 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__MODIFY(dst, src) \
4523                     (dst) = ((dst) &\
4524                     ~0x00010000U) | (((uint32_t)(src) <<\
4525                     16) & 0x00010000U)
4526 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__VERIFY(src) \
4527                     (!((((uint32_t)(src)\
4528                     << 16) & ~0x00010000U)))
4529 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__SET(dst) \
4530                     (dst) = ((dst) &\
4531                     ~0x00010000U) | ((uint32_t)(1) << 16)
4532 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT__CLR(dst) \
4533                     (dst) = ((dst) &\
4534                     ~0x00010000U) | ((uint32_t)(0) << 16)
4535 
4536 /* macros for field disable_pcs_link_partner_page_received */
4537 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__SHIFT \
4538                     17
4539 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__WIDTH 1
4540 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__MASK \
4541                     0x00020000U
4542 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__RESET 0
4543 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__WRITE(src) \
4544                     (((uint32_t)(src)\
4545                     << 17) & 0x00020000U)
4546 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__MODIFY(dst, src) \
4547                     (dst) = ((dst) &\
4548                     ~0x00020000U) | (((uint32_t)(src) <<\
4549                     17) & 0x00020000U)
4550 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__VERIFY(src) \
4551                     (!((((uint32_t)(src)\
4552                     << 17) & ~0x00020000U)))
4553 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__SET(dst) \
4554                     (dst) = ((dst) &\
4555                     ~0x00020000U) | ((uint32_t)(1) << 17)
4556 #define EMAC_REGS__INT_DISABLE__DISABLE_PCS_LINK_PARTNER_PAGE_RECEIVED__CLR(dst) \
4557                     (dst) = ((dst) &\
4558                     ~0x00020000U) | ((uint32_t)(0) << 17)
4559 
4560 /* macros for field disable_ptp_delay_req_frame_received */
4561 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__SHIFT  18
4562 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__WIDTH   1
4563 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__MASK \
4564                     0x00040000U
4565 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__RESET   0
4566 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__WRITE(src) \
4567                     (((uint32_t)(src)\
4568                     << 18) & 0x00040000U)
4569 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \
4570                     (dst) = ((dst) &\
4571                     ~0x00040000U) | (((uint32_t)(src) <<\
4572                     18) & 0x00040000U)
4573 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__VERIFY(src) \
4574                     (!((((uint32_t)(src)\
4575                     << 18) & ~0x00040000U)))
4576 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__SET(dst) \
4577                     (dst) = ((dst) &\
4578                     ~0x00040000U) | ((uint32_t)(1) << 18)
4579 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED__CLR(dst) \
4580                     (dst) = ((dst) &\
4581                     ~0x00040000U) | ((uint32_t)(0) << 18)
4582 
4583 /* macros for field disable_ptp_sync_frame_received */
4584 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__SHIFT       19
4585 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__WIDTH        1
4586 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__MASK \
4587                     0x00080000U
4588 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__RESET        0
4589 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__WRITE(src) \
4590                     (((uint32_t)(src)\
4591                     << 19) & 0x00080000U)
4592 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__MODIFY(dst, src) \
4593                     (dst) = ((dst) &\
4594                     ~0x00080000U) | (((uint32_t)(src) <<\
4595                     19) & 0x00080000U)
4596 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__VERIFY(src) \
4597                     (!((((uint32_t)(src)\
4598                     << 19) & ~0x00080000U)))
4599 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__SET(dst) \
4600                     (dst) = ((dst) &\
4601                     ~0x00080000U) | ((uint32_t)(1) << 19)
4602 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_RECEIVED__CLR(dst) \
4603                     (dst) = ((dst) &\
4604                     ~0x00080000U) | ((uint32_t)(0) << 19)
4605 
4606 /* macros for field disable_ptp_delay_req_frame_transmitted */
4607 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__SHIFT \
4608                     20
4609 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__WIDTH \
4610                     1
4611 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__MASK \
4612                     0x00100000U
4613 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__RESET \
4614                     0
4615 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \
4616                     (((uint32_t)(src)\
4617                     << 20) & 0x00100000U)
4618 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \
4619                     (dst) = ((dst) &\
4620                     ~0x00100000U) | (((uint32_t)(src) <<\
4621                     20) & 0x00100000U)
4622 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \
4623                     (!((((uint32_t)(src)\
4624                     << 20) & ~0x00100000U)))
4625 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__SET(dst) \
4626                     (dst) = ((dst) &\
4627                     ~0x00100000U) | ((uint32_t)(1) << 20)
4628 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \
4629                     (dst) = ((dst) &\
4630                     ~0x00100000U) | ((uint32_t)(0) << 20)
4631 
4632 /* macros for field disable_ptp_sync_frame_transmitted */
4633 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__SHIFT    21
4634 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__WIDTH     1
4635 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__MASK \
4636                     0x00200000U
4637 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__RESET     0
4638 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__WRITE(src) \
4639                     (((uint32_t)(src)\
4640                     << 21) & 0x00200000U)
4641 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__MODIFY(dst, src) \
4642                     (dst) = ((dst) &\
4643                     ~0x00200000U) | (((uint32_t)(src) <<\
4644                     21) & 0x00200000U)
4645 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__VERIFY(src) \
4646                     (!((((uint32_t)(src)\
4647                     << 21) & ~0x00200000U)))
4648 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__SET(dst) \
4649                     (dst) = ((dst) &\
4650                     ~0x00200000U) | ((uint32_t)(1) << 21)
4651 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_SYNC_FRAME_TRANSMITTED__CLR(dst) \
4652                     (dst) = ((dst) &\
4653                     ~0x00200000U) | ((uint32_t)(0) << 21)
4654 
4655 /* macros for field disable_ptp_pdelay_req_frame_received */
4656 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__SHIFT 22
4657 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__WIDTH  1
4658 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__MASK \
4659                     0x00400000U
4660 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__RESET  0
4661 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__WRITE(src) \
4662                     (((uint32_t)(src)\
4663                     << 22) & 0x00400000U)
4664 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__MODIFY(dst, src) \
4665                     (dst) = ((dst) &\
4666                     ~0x00400000U) | (((uint32_t)(src) <<\
4667                     22) & 0x00400000U)
4668 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__VERIFY(src) \
4669                     (!((((uint32_t)(src)\
4670                     << 22) & ~0x00400000U)))
4671 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__SET(dst) \
4672                     (dst) = ((dst) &\
4673                     ~0x00400000U) | ((uint32_t)(1) << 22)
4674 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED__CLR(dst) \
4675                     (dst) = ((dst) &\
4676                     ~0x00400000U) | ((uint32_t)(0) << 22)
4677 
4678 /* macros for field disable_ptp_pdelay_resp_frame_received */
4679 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__SHIFT \
4680                     23
4681 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__WIDTH 1
4682 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__MASK \
4683                     0x00800000U
4684 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__RESET 0
4685 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__WRITE(src) \
4686                     (((uint32_t)(src)\
4687                     << 23) & 0x00800000U)
4688 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__MODIFY(dst, src) \
4689                     (dst) = ((dst) &\
4690                     ~0x00800000U) | (((uint32_t)(src) <<\
4691                     23) & 0x00800000U)
4692 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__VERIFY(src) \
4693                     (!((((uint32_t)(src)\
4694                     << 23) & ~0x00800000U)))
4695 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__SET(dst) \
4696                     (dst) = ((dst) &\
4697                     ~0x00800000U) | ((uint32_t)(1) << 23)
4698 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED__CLR(dst) \
4699                     (dst) = ((dst) &\
4700                     ~0x00800000U) | ((uint32_t)(0) << 23)
4701 
4702 /* macros for field disable_ptp_pdelay_req_frame_transmitted */
4703 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__SHIFT \
4704                     24
4705 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__WIDTH \
4706                     1
4707 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__MASK \
4708                     0x01000000U
4709 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__RESET \
4710                     0
4711 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__WRITE(src) \
4712                     (((uint32_t)(src)\
4713                     << 24) & 0x01000000U)
4714 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__MODIFY(dst, src) \
4715                     (dst) = ((dst) &\
4716                     ~0x01000000U) | (((uint32_t)(src) <<\
4717                     24) & 0x01000000U)
4718 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__VERIFY(src) \
4719                     (!((((uint32_t)(src)\
4720                     << 24) & ~0x01000000U)))
4721 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__SET(dst) \
4722                     (dst) = ((dst) &\
4723                     ~0x01000000U) | ((uint32_t)(1) << 24)
4724 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED__CLR(dst) \
4725                     (dst) = ((dst) &\
4726                     ~0x01000000U) | ((uint32_t)(0) << 24)
4727 
4728 /* macros for field disable_ptp_pdelay_resp_frame_transmitted */
4729 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__SHIFT \
4730                     25
4731 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__WIDTH \
4732                     1
4733 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__MASK \
4734                     0x02000000U
4735 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__RESET \
4736                     0
4737 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__WRITE(src) \
4738                     (((uint32_t)(src)\
4739                     << 25) & 0x02000000U)
4740 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__MODIFY(dst, src) \
4741                     (dst) = ((dst) &\
4742                     ~0x02000000U) | (((uint32_t)(src) <<\
4743                     25) & 0x02000000U)
4744 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__VERIFY(src) \
4745                     (!((((uint32_t)(src)\
4746                     << 25) & ~0x02000000U)))
4747 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__SET(dst) \
4748                     (dst) = ((dst) &\
4749                     ~0x02000000U) | ((uint32_t)(1) << 25)
4750 #define EMAC_REGS__INT_DISABLE__DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED__CLR(dst) \
4751                     (dst) = ((dst) &\
4752                     ~0x02000000U) | ((uint32_t)(0) << 25)
4753 
4754 /* macros for field disable_tsu_seconds_register_increment */
4755 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__SHIFT \
4756                     26
4757 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__WIDTH 1
4758 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__MASK \
4759                     0x04000000U
4760 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__RESET 0
4761 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__WRITE(src) \
4762                     (((uint32_t)(src)\
4763                     << 26) & 0x04000000U)
4764 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__MODIFY(dst, src) \
4765                     (dst) = ((dst) &\
4766                     ~0x04000000U) | (((uint32_t)(src) <<\
4767                     26) & 0x04000000U)
4768 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__VERIFY(src) \
4769                     (!((((uint32_t)(src)\
4770                     << 26) & ~0x04000000U)))
4771 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__SET(dst) \
4772                     (dst) = ((dst) &\
4773                     ~0x04000000U) | ((uint32_t)(1) << 26)
4774 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_SECONDS_REGISTER_INCREMENT__CLR(dst) \
4775                     (dst) = ((dst) &\
4776                     ~0x04000000U) | ((uint32_t)(0) << 26)
4777 
4778 /* macros for field disable_rx_lpi_indication_interrupt */
4779 #define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__SHIFT   27
4780 #define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__WIDTH    1
4781 #define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__MASK \
4782                     0x08000000U
4783 #define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__RESET    0
4784 #define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__WRITE(src) \
4785                     (((uint32_t)(src)\
4786                     << 27) & 0x08000000U)
4787 #define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__MODIFY(dst, src) \
4788                     (dst) = ((dst) &\
4789                     ~0x08000000U) | (((uint32_t)(src) <<\
4790                     27) & 0x08000000U)
4791 #define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__VERIFY(src) \
4792                     (!((((uint32_t)(src)\
4793                     << 27) & ~0x08000000U)))
4794 #define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__SET(dst) \
4795                     (dst) = ((dst) &\
4796                     ~0x08000000U) | ((uint32_t)(1) << 27)
4797 #define EMAC_REGS__INT_DISABLE__DISABLE_RX_LPI_INDICATION_INTERRUPT__CLR(dst) \
4798                     (dst) = ((dst) &\
4799                     ~0x08000000U) | ((uint32_t)(0) << 27)
4800 
4801 /* macros for field disable_wol_event_received_interrupt */
4802 #define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__SHIFT  28
4803 #define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__WIDTH   1
4804 #define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__MASK \
4805                     0x10000000U
4806 #define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__RESET   0
4807 #define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__WRITE(src) \
4808                     (((uint32_t)(src)\
4809                     << 28) & 0x10000000U)
4810 #define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__MODIFY(dst, src) \
4811                     (dst) = ((dst) &\
4812                     ~0x10000000U) | (((uint32_t)(src) <<\
4813                     28) & 0x10000000U)
4814 #define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__VERIFY(src) \
4815                     (!((((uint32_t)(src)\
4816                     << 28) & ~0x10000000U)))
4817 #define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__SET(dst) \
4818                     (dst) = ((dst) &\
4819                     ~0x10000000U) | ((uint32_t)(1) << 28)
4820 #define EMAC_REGS__INT_DISABLE__DISABLE_WOL_EVENT_RECEIVED_INTERRUPT__CLR(dst) \
4821                     (dst) = ((dst) &\
4822                     ~0x10000000U) | ((uint32_t)(0) << 28)
4823 
4824 /* macros for field disable_tsu_timer_comparison_interrupt */
4825 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__SHIFT \
4826                     29
4827 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__WIDTH 1
4828 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__MASK \
4829                     0x20000000U
4830 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__RESET \
4831                     0b0
4832 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__WRITE(src) \
4833                     (((uint32_t)(src)\
4834                     << 29) & 0x20000000U)
4835 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__MODIFY(dst, src) \
4836                     (dst) = ((dst) &\
4837                     ~0x20000000U) | (((uint32_t)(src) <<\
4838                     29) & 0x20000000U)
4839 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__VERIFY(src) \
4840                     (!((((uint32_t)(src)\
4841                     << 29) & ~0x20000000U)))
4842 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__SET(dst) \
4843                     (dst) = ((dst) &\
4844                     ~0x20000000U) | ((uint32_t)(1) << 29)
4845 #define EMAC_REGS__INT_DISABLE__DISABLE_TSU_TIMER_COMPARISON_INTERRUPT__CLR(dst) \
4846                     (dst) = ((dst) &\
4847                     ~0x20000000U) | ((uint32_t)(0) << 29)
4848 
4849 /* macros for field reserved_30_30 */
4850 #define EMAC_REGS__INT_DISABLE__RESERVED_30_30__SHIFT                        30
4851 #define EMAC_REGS__INT_DISABLE__RESERVED_30_30__WIDTH                         1
4852 #define EMAC_REGS__INT_DISABLE__RESERVED_30_30__MASK                0x40000000U
4853 #define EMAC_REGS__INT_DISABLE__RESERVED_30_30__RESET                         0
4854 #define EMAC_REGS__INT_DISABLE__RESERVED_30_30__READ(src) \
4855                     (((uint32_t)(src)\
4856                     & 0x40000000U) >> 30)
4857 #define EMAC_REGS__INT_DISABLE__RESERVED_30_30__SET(dst) \
4858                     (dst) = ((dst) &\
4859                     ~0x40000000U) | ((uint32_t)(1) << 30)
4860 #define EMAC_REGS__INT_DISABLE__RESERVED_30_30__CLR(dst) \
4861                     (dst) = ((dst) &\
4862                     ~0x40000000U) | ((uint32_t)(0) << 30)
4863 
4864 /* macros for field reserved_31_31 */
4865 #define EMAC_REGS__INT_DISABLE__RESERVED_31_31__SHIFT                        31
4866 #define EMAC_REGS__INT_DISABLE__RESERVED_31_31__WIDTH                         1
4867 #define EMAC_REGS__INT_DISABLE__RESERVED_31_31__MASK                0x80000000U
4868 #define EMAC_REGS__INT_DISABLE__RESERVED_31_31__RESET                         0
4869 #define EMAC_REGS__INT_DISABLE__RESERVED_31_31__READ(src) \
4870                     (((uint32_t)(src)\
4871                     & 0x80000000U) >> 31)
4872 #define EMAC_REGS__INT_DISABLE__RESERVED_31_31__SET(dst) \
4873                     (dst) = ((dst) &\
4874                     ~0x80000000U) | ((uint32_t)(1) << 31)
4875 #define EMAC_REGS__INT_DISABLE__RESERVED_31_31__CLR(dst) \
4876                     (dst) = ((dst) &\
4877                     ~0x80000000U) | ((uint32_t)(0) << 31)
4878 #define EMAC_REGS__INT_DISABLE__TYPE                                   uint32_t
4879 #define EMAC_REGS__INT_DISABLE__READ                                0xc0000100U
4880 #define EMAC_REGS__INT_DISABLE__WRITE                               0xc0000100U
4881 
4882 #endif /* __EMAC_REGS__INT_DISABLE_MACRO__ */
4883 
4884 
4885 /* macros for int_disable */
4886 #define INST_INT_DISABLE__NUM                                                 1
4887 
4888 /* macros for BlueprintGlobalNameSpace::emac_regs::int_mask */
4889 #ifndef __EMAC_REGS__INT_MASK_MACRO__
4890 #define __EMAC_REGS__INT_MASK_MACRO__
4891 
4892 /* macros for field management_done_interrupt_mask */
4893 #define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__SHIFT            0
4894 #define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__WIDTH            1
4895 #define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__MASK   0x00000001U
4896 #define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__RESET            1
4897 #define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__READ(src) \
4898                     ((uint32_t)(src)\
4899                     & 0x00000001U)
4900 #define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__SET(dst) \
4901                     (dst) = ((dst) &\
4902                     ~0x00000001U) | (uint32_t)(1)
4903 #define EMAC_REGS__INT_MASK__MANAGEMENT_DONE_INTERRUPT_MASK__CLR(dst) \
4904                     (dst) = ((dst) &\
4905                     ~0x00000001U) | (uint32_t)(0)
4906 
4907 /* macros for field receive_complete_interrupt_mask */
4908 #define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__SHIFT           1
4909 #define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__WIDTH           1
4910 #define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__MASK  0x00000002U
4911 #define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__RESET           1
4912 #define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__READ(src) \
4913                     (((uint32_t)(src)\
4914                     & 0x00000002U) >> 1)
4915 #define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__SET(dst) \
4916                     (dst) = ((dst) &\
4917                     ~0x00000002U) | ((uint32_t)(1) << 1)
4918 #define EMAC_REGS__INT_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__CLR(dst) \
4919                     (dst) = ((dst) &\
4920                     ~0x00000002U) | ((uint32_t)(0) << 1)
4921 
4922 /* macros for field receive_used_bit_read_interrupt_mask */
4923 #define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__SHIFT      2
4924 #define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__WIDTH      1
4925 #define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__MASK \
4926                     0x00000004U
4927 #define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__RESET      1
4928 #define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__READ(src) \
4929                     (((uint32_t)(src)\
4930                     & 0x00000004U) >> 2)
4931 #define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__SET(dst) \
4932                     (dst) = ((dst) &\
4933                     ~0x00000004U) | ((uint32_t)(1) << 2)
4934 #define EMAC_REGS__INT_MASK__RECEIVE_USED_BIT_READ_INTERRUPT_MASK__CLR(dst) \
4935                     (dst) = ((dst) &\
4936                     ~0x00000004U) | ((uint32_t)(0) << 2)
4937 
4938 /* macros for field transmit_used_bit_read_interrupt_mask */
4939 #define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__SHIFT     3
4940 #define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__WIDTH     1
4941 #define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__MASK \
4942                     0x00000008U
4943 #define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__RESET     1
4944 #define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__READ(src) \
4945                     (((uint32_t)(src)\
4946                     & 0x00000008U) >> 3)
4947 #define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__SET(dst) \
4948                     (dst) = ((dst) &\
4949                     ~0x00000008U) | ((uint32_t)(1) << 3)
4950 #define EMAC_REGS__INT_MASK__TRANSMIT_USED_BIT_READ_INTERRUPT_MASK__CLR(dst) \
4951                     (dst) = ((dst) &\
4952                     ~0x00000008U) | ((uint32_t)(0) << 3)
4953 
4954 /* macros for field transmit_buffer_under_run_interrupt_mask */
4955 #define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__SHIFT  4
4956 #define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__WIDTH  1
4957 #define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__MASK \
4958                     0x00000010U
4959 #define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__RESET  1
4960 #define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__READ(src) \
4961                     (((uint32_t)(src)\
4962                     & 0x00000010U) >> 4)
4963 #define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__SET(dst) \
4964                     (dst) = ((dst) &\
4965                     ~0x00000010U) | ((uint32_t)(1) << 4)
4966 #define EMAC_REGS__INT_MASK__TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK__CLR(dst) \
4967                     (dst) = ((dst) &\
4968                     ~0x00000010U) | ((uint32_t)(0) << 4)
4969 
4970 /* macros for field retry_limit_exceeded_or_late_collision_mask */
4971 #define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__SHIFT \
4972                     5
4973 #define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__WIDTH \
4974                     1
4975 #define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__MASK \
4976                     0x00000020U
4977 #define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__RESET \
4978                     1
4979 #define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__READ(src) \
4980                     (((uint32_t)(src)\
4981                     & 0x00000020U) >> 5)
4982 #define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__SET(dst) \
4983                     (dst) = ((dst) &\
4984                     ~0x00000020U) | ((uint32_t)(1) << 5)
4985 #define EMAC_REGS__INT_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK__CLR(dst) \
4986                     (dst) = ((dst) &\
4987                     ~0x00000020U) | ((uint32_t)(0) << 5)
4988 
4989 /* macros for field amba_error_interrupt_mask */
4990 #define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__SHIFT                 6
4991 #define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__WIDTH                 1
4992 #define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__MASK        0x00000040U
4993 #define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__RESET                 1
4994 #define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__READ(src) \
4995                     (((uint32_t)(src)\
4996                     & 0x00000040U) >> 6)
4997 #define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__SET(dst) \
4998                     (dst) = ((dst) &\
4999                     ~0x00000040U) | ((uint32_t)(1) << 6)
5000 #define EMAC_REGS__INT_MASK__AMBA_ERROR_INTERRUPT_MASK__CLR(dst) \
5001                     (dst) = ((dst) &\
5002                     ~0x00000040U) | ((uint32_t)(0) << 6)
5003 
5004 /* macros for field transmit_complete_interrupt_mask */
5005 #define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__SHIFT          7
5006 #define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__WIDTH          1
5007 #define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__MASK 0x00000080U
5008 #define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__RESET          1
5009 #define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__READ(src) \
5010                     (((uint32_t)(src)\
5011                     & 0x00000080U) >> 7)
5012 #define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__SET(dst) \
5013                     (dst) = ((dst) &\
5014                     ~0x00000080U) | ((uint32_t)(1) << 7)
5015 #define EMAC_REGS__INT_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__CLR(dst) \
5016                     (dst) = ((dst) &\
5017                     ~0x00000080U) | ((uint32_t)(0) << 7)
5018 
5019 /* macros for field not_used */
5020 #define EMAC_REGS__INT_MASK__NOT_USED__SHIFT                                  8
5021 #define EMAC_REGS__INT_MASK__NOT_USED__WIDTH                                  1
5022 #define EMAC_REGS__INT_MASK__NOT_USED__MASK                         0x00000100U
5023 #define EMAC_REGS__INT_MASK__NOT_USED__RESET                                  1
5024 #define EMAC_REGS__INT_MASK__NOT_USED__READ(src) \
5025                     (((uint32_t)(src)\
5026                     & 0x00000100U) >> 8)
5027 #define EMAC_REGS__INT_MASK__NOT_USED__SET(dst) \
5028                     (dst) = ((dst) &\
5029                     ~0x00000100U) | ((uint32_t)(1) << 8)
5030 #define EMAC_REGS__INT_MASK__NOT_USED__CLR(dst) \
5031                     (dst) = ((dst) &\
5032                     ~0x00000100U) | ((uint32_t)(0) << 8)
5033 
5034 /* macros for field link_change_interrupt_mask */
5035 #define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__SHIFT                9
5036 #define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__WIDTH                1
5037 #define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__MASK       0x00000200U
5038 #define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__RESET                1
5039 #define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__READ(src) \
5040                     (((uint32_t)(src)\
5041                     & 0x00000200U) >> 9)
5042 #define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__SET(dst) \
5043                     (dst) = ((dst) &\
5044                     ~0x00000200U) | ((uint32_t)(1) << 9)
5045 #define EMAC_REGS__INT_MASK__LINK_CHANGE_INTERRUPT_MASK__CLR(dst) \
5046                     (dst) = ((dst) &\
5047                     ~0x00000200U) | ((uint32_t)(0) << 9)
5048 
5049 /* macros for field receive_overrun_interrupt_mask */
5050 #define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__SHIFT           10
5051 #define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__WIDTH            1
5052 #define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__MASK   0x00000400U
5053 #define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__RESET            1
5054 #define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__READ(src) \
5055                     (((uint32_t)(src)\
5056                     & 0x00000400U) >> 10)
5057 #define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__SET(dst) \
5058                     (dst) = ((dst) &\
5059                     ~0x00000400U) | ((uint32_t)(1) << 10)
5060 #define EMAC_REGS__INT_MASK__RECEIVE_OVERRUN_INTERRUPT_MASK__CLR(dst) \
5061                     (dst) = ((dst) &\
5062                     ~0x00000400U) | ((uint32_t)(0) << 10)
5063 
5064 /* macros for field resp_not_ok_interrupt_mask */
5065 #define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__SHIFT               11
5066 #define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__WIDTH                1
5067 #define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__MASK       0x00000800U
5068 #define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__RESET                1
5069 #define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__READ(src) \
5070                     (((uint32_t)(src)\
5071                     & 0x00000800U) >> 11)
5072 #define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__SET(dst) \
5073                     (dst) = ((dst) &\
5074                     ~0x00000800U) | ((uint32_t)(1) << 11)
5075 #define EMAC_REGS__INT_MASK__RESP_NOT_OK_INTERRUPT_MASK__CLR(dst) \
5076                     (dst) = ((dst) &\
5077                     ~0x00000800U) | ((uint32_t)(0) << 11)
5078 
5079 /* macros for field pause_frame_with_non_zero_pause_quantum_interrupt_mask */
5080 #define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__SHIFT \
5081                     12
5082 #define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__WIDTH \
5083                     1
5084 #define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__MASK \
5085                     0x00001000U
5086 #define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__RESET \
5087                     1
5088 #define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__READ(src) \
5089                     (((uint32_t)(src)\
5090                     & 0x00001000U) >> 12)
5091 #define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__SET(dst) \
5092                     (dst) = ((dst) &\
5093                     ~0x00001000U) | ((uint32_t)(1) << 12)
5094 #define EMAC_REGS__INT_MASK__PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK__CLR(dst) \
5095                     (dst) = ((dst) &\
5096                     ~0x00001000U) | ((uint32_t)(0) << 12)
5097 
5098 /* macros for field pause_time_zero_interrupt_mask */
5099 #define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__SHIFT           13
5100 #define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__WIDTH            1
5101 #define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__MASK   0x00002000U
5102 #define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__RESET            1
5103 #define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__READ(src) \
5104                     (((uint32_t)(src)\
5105                     & 0x00002000U) >> 13)
5106 #define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__SET(dst) \
5107                     (dst) = ((dst) &\
5108                     ~0x00002000U) | ((uint32_t)(1) << 13)
5109 #define EMAC_REGS__INT_MASK__PAUSE_TIME_ZERO_INTERRUPT_MASK__CLR(dst) \
5110                     (dst) = ((dst) &\
5111                     ~0x00002000U) | ((uint32_t)(0) << 13)
5112 
5113 /* macros for field pause_frame_transmitted_interrupt_mask */
5114 #define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__SHIFT   14
5115 #define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__WIDTH    1
5116 #define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__MASK \
5117                     0x00004000U
5118 #define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__RESET    1
5119 #define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__READ(src) \
5120                     (((uint32_t)(src)\
5121                     & 0x00004000U) >> 14)
5122 #define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__SET(dst) \
5123                     (dst) = ((dst) &\
5124                     ~0x00004000U) | ((uint32_t)(1) << 14)
5125 #define EMAC_REGS__INT_MASK__PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK__CLR(dst) \
5126                     (dst) = ((dst) &\
5127                     ~0x00004000U) | ((uint32_t)(0) << 14)
5128 
5129 /* macros for field external_interrupt_mask */
5130 #define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__SHIFT                  15
5131 #define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__WIDTH                   1
5132 #define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__MASK          0x00008000U
5133 #define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__RESET                   1
5134 #define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__READ(src) \
5135                     (((uint32_t)(src)\
5136                     & 0x00008000U) >> 15)
5137 #define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__SET(dst) \
5138                     (dst) = ((dst) &\
5139                     ~0x00008000U) | ((uint32_t)(1) << 15)
5140 #define EMAC_REGS__INT_MASK__EXTERNAL_INTERRUPT_MASK__CLR(dst) \
5141                     (dst) = ((dst) &\
5142                     ~0x00008000U) | ((uint32_t)(0) << 15)
5143 
5144 /* macros for field pcs_auto_negotiation_complete_interrupt_mask */
5145 #define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__SHIFT \
5146                     16
5147 #define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__WIDTH \
5148                     1
5149 #define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__MASK \
5150                     0x00010000U
5151 #define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__RESET \
5152                     1
5153 #define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__READ(src) \
5154                     (((uint32_t)(src)\
5155                     & 0x00010000U) >> 16)
5156 #define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__SET(dst) \
5157                     (dst) = ((dst) &\
5158                     ~0x00010000U) | ((uint32_t)(1) << 16)
5159 #define EMAC_REGS__INT_MASK__PCS_AUTO_NEGOTIATION_COMPLETE_INTERRUPT_MASK__CLR(dst) \
5160                     (dst) = ((dst) &\
5161                     ~0x00010000U) | ((uint32_t)(0) << 16)
5162 
5163 /* macros for field pcs_link_partner_page_mask */
5164 #define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__SHIFT               17
5165 #define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__WIDTH                1
5166 #define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__MASK       0x00020000U
5167 #define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__RESET                1
5168 #define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__READ(src) \
5169                     (((uint32_t)(src)\
5170                     & 0x00020000U) >> 17)
5171 #define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__SET(dst) \
5172                     (dst) = ((dst) &\
5173                     ~0x00020000U) | ((uint32_t)(1) << 17)
5174 #define EMAC_REGS__INT_MASK__PCS_LINK_PARTNER_PAGE_MASK__CLR(dst) \
5175                     (dst) = ((dst) &\
5176                     ~0x00020000U) | ((uint32_t)(0) << 17)
5177 
5178 /* macros for field ptp_delay_req_frame_received_mask */
5179 #define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__SHIFT        18
5180 #define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__WIDTH         1
5181 #define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__MASK \
5182                     0x00040000U
5183 #define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__RESET         1
5184 #define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__READ(src) \
5185                     (((uint32_t)(src)\
5186                     & 0x00040000U) >> 18)
5187 #define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__SET(dst) \
5188                     (dst) = ((dst) &\
5189                     ~0x00040000U) | ((uint32_t)(1) << 18)
5190 #define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_RECEIVED_MASK__CLR(dst) \
5191                     (dst) = ((dst) &\
5192                     ~0x00040000U) | ((uint32_t)(0) << 18)
5193 
5194 /* macros for field ptp_sync_frame_received_mask */
5195 #define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__SHIFT             19
5196 #define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__WIDTH              1
5197 #define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__MASK     0x00080000U
5198 #define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__RESET              1
5199 #define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__READ(src) \
5200                     (((uint32_t)(src)\
5201                     & 0x00080000U) >> 19)
5202 #define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__SET(dst) \
5203                     (dst) = ((dst) &\
5204                     ~0x00080000U) | ((uint32_t)(1) << 19)
5205 #define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_RECEIVED_MASK__CLR(dst) \
5206                     (dst) = ((dst) &\
5207                     ~0x00080000U) | ((uint32_t)(0) << 19)
5208 
5209 /* macros for field ptp_delay_req_frame_transmitted_mask */
5210 #define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__SHIFT     20
5211 #define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__WIDTH      1
5212 #define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__MASK \
5213                     0x00100000U
5214 #define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__RESET      1
5215 #define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__READ(src) \
5216                     (((uint32_t)(src)\
5217                     & 0x00100000U) >> 20)
5218 #define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__SET(dst) \
5219                     (dst) = ((dst) &\
5220                     ~0x00100000U) | ((uint32_t)(1) << 20)
5221 #define EMAC_REGS__INT_MASK__PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK__CLR(dst) \
5222                     (dst) = ((dst) &\
5223                     ~0x00100000U) | ((uint32_t)(0) << 20)
5224 
5225 /* macros for field ptp_sync_frame_transmitted_mask */
5226 #define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__SHIFT          21
5227 #define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__WIDTH           1
5228 #define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__MASK  0x00200000U
5229 #define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__RESET           1
5230 #define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__READ(src) \
5231                     (((uint32_t)(src)\
5232                     & 0x00200000U) >> 21)
5233 #define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__SET(dst) \
5234                     (dst) = ((dst) &\
5235                     ~0x00200000U) | ((uint32_t)(1) << 21)
5236 #define EMAC_REGS__INT_MASK__PTP_SYNC_FRAME_TRANSMITTED_MASK__CLR(dst) \
5237                     (dst) = ((dst) &\
5238                     ~0x00200000U) | ((uint32_t)(0) << 21)
5239 
5240 /* macros for field ptp_pdelay_req_frame_received_mask */
5241 #define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__SHIFT       22
5242 #define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__WIDTH        1
5243 #define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__MASK \
5244                     0x00400000U
5245 #define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__RESET        1
5246 #define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__READ(src) \
5247                     (((uint32_t)(src)\
5248                     & 0x00400000U) >> 22)
5249 #define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__SET(dst) \
5250                     (dst) = ((dst) &\
5251                     ~0x00400000U) | ((uint32_t)(1) << 22)
5252 #define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_RECEIVED_MASK__CLR(dst) \
5253                     (dst) = ((dst) &\
5254                     ~0x00400000U) | ((uint32_t)(0) << 22)
5255 
5256 /* macros for field ptp_pdelay_resp_frame_received_mask */
5257 #define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__SHIFT      23
5258 #define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__WIDTH       1
5259 #define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__MASK \
5260                     0x00800000U
5261 #define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__RESET       1
5262 #define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__READ(src) \
5263                     (((uint32_t)(src)\
5264                     & 0x00800000U) >> 23)
5265 #define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__SET(dst) \
5266                     (dst) = ((dst) &\
5267                     ~0x00800000U) | ((uint32_t)(1) << 23)
5268 #define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_RECEIVED_MASK__CLR(dst) \
5269                     (dst) = ((dst) &\
5270                     ~0x00800000U) | ((uint32_t)(0) << 23)
5271 
5272 /* macros for field ptp_pdelay_req_frame_transmitted_mask */
5273 #define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__SHIFT    24
5274 #define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__WIDTH     1
5275 #define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__MASK \
5276                     0x01000000U
5277 #define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__RESET     1
5278 #define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__READ(src) \
5279                     (((uint32_t)(src)\
5280                     & 0x01000000U) >> 24)
5281 #define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__SET(dst) \
5282                     (dst) = ((dst) &\
5283                     ~0x01000000U) | ((uint32_t)(1) << 24)
5284 #define EMAC_REGS__INT_MASK__PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK__CLR(dst) \
5285                     (dst) = ((dst) &\
5286                     ~0x01000000U) | ((uint32_t)(0) << 24)
5287 
5288 /* macros for field ptp_pdelay_resp_frame_transmitted_mask */
5289 #define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__SHIFT   25
5290 #define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__WIDTH    1
5291 #define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__MASK \
5292                     0x02000000U
5293 #define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__RESET    1
5294 #define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__READ(src) \
5295                     (((uint32_t)(src)\
5296                     & 0x02000000U) >> 25)
5297 #define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__SET(dst) \
5298                     (dst) = ((dst) &\
5299                     ~0x02000000U) | ((uint32_t)(1) << 25)
5300 #define EMAC_REGS__INT_MASK__PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK__CLR(dst) \
5301                     (dst) = ((dst) &\
5302                     ~0x02000000U) | ((uint32_t)(0) << 25)
5303 
5304 /* macros for field tsu_seconds_register_increment_mask */
5305 #define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__SHIFT      26
5306 #define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__WIDTH       1
5307 #define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__MASK \
5308                     0x04000000U
5309 #define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__RESET       1
5310 #define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__READ(src) \
5311                     (((uint32_t)(src)\
5312                     & 0x04000000U) >> 26)
5313 #define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__SET(dst) \
5314                     (dst) = ((dst) &\
5315                     ~0x04000000U) | ((uint32_t)(1) << 26)
5316 #define EMAC_REGS__INT_MASK__TSU_SECONDS_REGISTER_INCREMENT_MASK__CLR(dst) \
5317                     (dst) = ((dst) &\
5318                     ~0x04000000U) | ((uint32_t)(0) << 26)
5319 
5320 /* macros for field rx_lpi_indication_mask */
5321 #define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__SHIFT                   27
5322 #define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__WIDTH                    1
5323 #define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__MASK           0x08000000U
5324 #define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__RESET                    1
5325 #define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__READ(src) \
5326                     (((uint32_t)(src)\
5327                     & 0x08000000U) >> 27)
5328 #define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__SET(dst) \
5329                     (dst) = ((dst) &\
5330                     ~0x08000000U) | ((uint32_t)(1) << 27)
5331 #define EMAC_REGS__INT_MASK__RX_LPI_INDICATION_MASK__CLR(dst) \
5332                     (dst) = ((dst) &\
5333                     ~0x08000000U) | ((uint32_t)(0) << 27)
5334 
5335 /* macros for field wol_event_received_mask */
5336 #define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__SHIFT                  28
5337 #define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__WIDTH                   1
5338 #define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__MASK          0x10000000U
5339 #define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__RESET                   1
5340 #define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__READ(src) \
5341                     (((uint32_t)(src)\
5342                     & 0x10000000U) >> 28)
5343 #define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__SET(dst) \
5344                     (dst) = ((dst) &\
5345                     ~0x10000000U) | ((uint32_t)(1) << 28)
5346 #define EMAC_REGS__INT_MASK__WOL_EVENT_RECEIVED_MASK__CLR(dst) \
5347                     (dst) = ((dst) &\
5348                     ~0x10000000U) | ((uint32_t)(0) << 28)
5349 
5350 /* macros for field tsu_timer_comparison_mask */
5351 #define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__SHIFT                29
5352 #define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__WIDTH                 1
5353 #define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__MASK        0x20000000U
5354 #define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__RESET                 1
5355 #define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__READ(src) \
5356                     (((uint32_t)(src)\
5357                     & 0x20000000U) >> 29)
5358 #define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__SET(dst) \
5359                     (dst) = ((dst) &\
5360                     ~0x20000000U) | ((uint32_t)(1) << 29)
5361 #define EMAC_REGS__INT_MASK__TSU_TIMER_COMPARISON_MASK__CLR(dst) \
5362                     (dst) = ((dst) &\
5363                     ~0x20000000U) | ((uint32_t)(0) << 29)
5364 
5365 /* macros for field reserved_30_30 */
5366 #define EMAC_REGS__INT_MASK__RESERVED_30_30__SHIFT                           30
5367 #define EMAC_REGS__INT_MASK__RESERVED_30_30__WIDTH                            1
5368 #define EMAC_REGS__INT_MASK__RESERVED_30_30__MASK                   0x40000000U
5369 #define EMAC_REGS__INT_MASK__RESERVED_30_30__RESET                            0
5370 #define EMAC_REGS__INT_MASK__RESERVED_30_30__READ(src) \
5371                     (((uint32_t)(src)\
5372                     & 0x40000000U) >> 30)
5373 #define EMAC_REGS__INT_MASK__RESERVED_30_30__SET(dst) \
5374                     (dst) = ((dst) &\
5375                     ~0x40000000U) | ((uint32_t)(1) << 30)
5376 #define EMAC_REGS__INT_MASK__RESERVED_30_30__CLR(dst) \
5377                     (dst) = ((dst) &\
5378                     ~0x40000000U) | ((uint32_t)(0) << 30)
5379 
5380 /* macros for field reserved_31_31 */
5381 #define EMAC_REGS__INT_MASK__RESERVED_31_31__SHIFT                           31
5382 #define EMAC_REGS__INT_MASK__RESERVED_31_31__WIDTH                            1
5383 #define EMAC_REGS__INT_MASK__RESERVED_31_31__MASK                   0x80000000U
5384 #define EMAC_REGS__INT_MASK__RESERVED_31_31__RESET                            0
5385 #define EMAC_REGS__INT_MASK__RESERVED_31_31__READ(src) \
5386                     (((uint32_t)(src)\
5387                     & 0x80000000U) >> 31)
5388 #define EMAC_REGS__INT_MASK__RESERVED_31_31__SET(dst) \
5389                     (dst) = ((dst) &\
5390                     ~0x80000000U) | ((uint32_t)(1) << 31)
5391 #define EMAC_REGS__INT_MASK__RESERVED_31_31__CLR(dst) \
5392                     (dst) = ((dst) &\
5393                     ~0x80000000U) | ((uint32_t)(0) << 31)
5394 #define EMAC_REGS__INT_MASK__TYPE                                      uint32_t
5395 #define EMAC_REGS__INT_MASK__READ                                   0xffffffffU
5396 
5397 #endif /* __EMAC_REGS__INT_MASK_MACRO__ */
5398 
5399 
5400 /* macros for int_mask */
5401 #define INST_INT_MASK__NUM                                                    1
5402 
5403 /* macros for BlueprintGlobalNameSpace::emac_regs::phy_management */
5404 #ifndef __EMAC_REGS__PHY_MANAGEMENT_MACRO__
5405 #define __EMAC_REGS__PHY_MANAGEMENT_MACRO__
5406 
5407 /* macros for field phy_write_read_data */
5408 #define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__SHIFT                 0
5409 #define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__WIDTH                16
5410 #define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__MASK        0x0000ffffU
5411 #define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__RESET                 0
5412 #define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__READ(src) \
5413                     ((uint32_t)(src)\
5414                     & 0x0000ffffU)
5415 #define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__WRITE(src) \
5416                     ((uint32_t)(src)\
5417                     & 0x0000ffffU)
5418 #define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__MODIFY(dst, src) \
5419                     (dst) = ((dst) &\
5420                     ~0x0000ffffU) | ((uint32_t)(src) &\
5421                     0x0000ffffU)
5422 #define EMAC_REGS__PHY_MANAGEMENT__PHY_WRITE_READ_DATA__VERIFY(src) \
5423                     (!(((uint32_t)(src)\
5424                     & ~0x0000ffffU)))
5425 
5426 /* macros for field write10 */
5427 #define EMAC_REGS__PHY_MANAGEMENT__WRITE10__SHIFT                            16
5428 #define EMAC_REGS__PHY_MANAGEMENT__WRITE10__WIDTH                             2
5429 #define EMAC_REGS__PHY_MANAGEMENT__WRITE10__MASK                    0x00030000U
5430 #define EMAC_REGS__PHY_MANAGEMENT__WRITE10__RESET                             0
5431 #define EMAC_REGS__PHY_MANAGEMENT__WRITE10__READ(src) \
5432                     (((uint32_t)(src)\
5433                     & 0x00030000U) >> 16)
5434 #define EMAC_REGS__PHY_MANAGEMENT__WRITE10__WRITE(src) \
5435                     (((uint32_t)(src)\
5436                     << 16) & 0x00030000U)
5437 #define EMAC_REGS__PHY_MANAGEMENT__WRITE10__MODIFY(dst, src) \
5438                     (dst) = ((dst) &\
5439                     ~0x00030000U) | (((uint32_t)(src) <<\
5440                     16) & 0x00030000U)
5441 #define EMAC_REGS__PHY_MANAGEMENT__WRITE10__VERIFY(src) \
5442                     (!((((uint32_t)(src)\
5443                     << 16) & ~0x00030000U)))
5444 
5445 /* macros for field register_address */
5446 #define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__SHIFT                   18
5447 #define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__WIDTH                    5
5448 #define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__MASK           0x007c0000U
5449 #define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__RESET                    0
5450 #define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__READ(src) \
5451                     (((uint32_t)(src)\
5452                     & 0x007c0000U) >> 18)
5453 #define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__WRITE(src) \
5454                     (((uint32_t)(src)\
5455                     << 18) & 0x007c0000U)
5456 #define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__MODIFY(dst, src) \
5457                     (dst) = ((dst) &\
5458                     ~0x007c0000U) | (((uint32_t)(src) <<\
5459                     18) & 0x007c0000U)
5460 #define EMAC_REGS__PHY_MANAGEMENT__REGISTER_ADDRESS__VERIFY(src) \
5461                     (!((((uint32_t)(src)\
5462                     << 18) & ~0x007c0000U)))
5463 
5464 /* macros for field phy_address */
5465 #define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__SHIFT                        23
5466 #define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__WIDTH                         5
5467 #define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__MASK                0x0f800000U
5468 #define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__RESET                         0
5469 #define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__READ(src) \
5470                     (((uint32_t)(src)\
5471                     & 0x0f800000U) >> 23)
5472 #define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__WRITE(src) \
5473                     (((uint32_t)(src)\
5474                     << 23) & 0x0f800000U)
5475 #define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__MODIFY(dst, src) \
5476                     (dst) = ((dst) &\
5477                     ~0x0f800000U) | (((uint32_t)(src) <<\
5478                     23) & 0x0f800000U)
5479 #define EMAC_REGS__PHY_MANAGEMENT__PHY_ADDRESS__VERIFY(src) \
5480                     (!((((uint32_t)(src)\
5481                     << 23) & ~0x0f800000U)))
5482 
5483 /* macros for field operation */
5484 #define EMAC_REGS__PHY_MANAGEMENT__OPERATION__SHIFT                          28
5485 #define EMAC_REGS__PHY_MANAGEMENT__OPERATION__WIDTH                           2
5486 #define EMAC_REGS__PHY_MANAGEMENT__OPERATION__MASK                  0x30000000U
5487 #define EMAC_REGS__PHY_MANAGEMENT__OPERATION__RESET                           0
5488 #define EMAC_REGS__PHY_MANAGEMENT__OPERATION__READ(src) \
5489                     (((uint32_t)(src)\
5490                     & 0x30000000U) >> 28)
5491 #define EMAC_REGS__PHY_MANAGEMENT__OPERATION__WRITE(src) \
5492                     (((uint32_t)(src)\
5493                     << 28) & 0x30000000U)
5494 #define EMAC_REGS__PHY_MANAGEMENT__OPERATION__MODIFY(dst, src) \
5495                     (dst) = ((dst) &\
5496                     ~0x30000000U) | (((uint32_t)(src) <<\
5497                     28) & 0x30000000U)
5498 #define EMAC_REGS__PHY_MANAGEMENT__OPERATION__VERIFY(src) \
5499                     (!((((uint32_t)(src)\
5500                     << 28) & ~0x30000000U)))
5501 
5502 /* macros for field write1 */
5503 #define EMAC_REGS__PHY_MANAGEMENT__WRITE1__SHIFT                             30
5504 #define EMAC_REGS__PHY_MANAGEMENT__WRITE1__WIDTH                              1
5505 #define EMAC_REGS__PHY_MANAGEMENT__WRITE1__MASK                     0x40000000U
5506 #define EMAC_REGS__PHY_MANAGEMENT__WRITE1__RESET                              0
5507 #define EMAC_REGS__PHY_MANAGEMENT__WRITE1__READ(src) \
5508                     (((uint32_t)(src)\
5509                     & 0x40000000U) >> 30)
5510 #define EMAC_REGS__PHY_MANAGEMENT__WRITE1__WRITE(src) \
5511                     (((uint32_t)(src)\
5512                     << 30) & 0x40000000U)
5513 #define EMAC_REGS__PHY_MANAGEMENT__WRITE1__MODIFY(dst, src) \
5514                     (dst) = ((dst) &\
5515                     ~0x40000000U) | (((uint32_t)(src) <<\
5516                     30) & 0x40000000U)
5517 #define EMAC_REGS__PHY_MANAGEMENT__WRITE1__VERIFY(src) \
5518                     (!((((uint32_t)(src)\
5519                     << 30) & ~0x40000000U)))
5520 #define EMAC_REGS__PHY_MANAGEMENT__WRITE1__SET(dst) \
5521                     (dst) = ((dst) &\
5522                     ~0x40000000U) | ((uint32_t)(1) << 30)
5523 #define EMAC_REGS__PHY_MANAGEMENT__WRITE1__CLR(dst) \
5524                     (dst) = ((dst) &\
5525                     ~0x40000000U) | ((uint32_t)(0) << 30)
5526 
5527 /* macros for field write0 */
5528 #define EMAC_REGS__PHY_MANAGEMENT__WRITE0__SHIFT                             31
5529 #define EMAC_REGS__PHY_MANAGEMENT__WRITE0__WIDTH                              1
5530 #define EMAC_REGS__PHY_MANAGEMENT__WRITE0__MASK                     0x80000000U
5531 #define EMAC_REGS__PHY_MANAGEMENT__WRITE0__RESET                              0
5532 #define EMAC_REGS__PHY_MANAGEMENT__WRITE0__READ(src) \
5533                     (((uint32_t)(src)\
5534                     & 0x80000000U) >> 31)
5535 #define EMAC_REGS__PHY_MANAGEMENT__WRITE0__WRITE(src) \
5536                     (((uint32_t)(src)\
5537                     << 31) & 0x80000000U)
5538 #define EMAC_REGS__PHY_MANAGEMENT__WRITE0__MODIFY(dst, src) \
5539                     (dst) = ((dst) &\
5540                     ~0x80000000U) | (((uint32_t)(src) <<\
5541                     31) & 0x80000000U)
5542 #define EMAC_REGS__PHY_MANAGEMENT__WRITE0__VERIFY(src) \
5543                     (!((((uint32_t)(src)\
5544                     << 31) & ~0x80000000U)))
5545 #define EMAC_REGS__PHY_MANAGEMENT__WRITE0__SET(dst) \
5546                     (dst) = ((dst) &\
5547                     ~0x80000000U) | ((uint32_t)(1) << 31)
5548 #define EMAC_REGS__PHY_MANAGEMENT__WRITE0__CLR(dst) \
5549                     (dst) = ((dst) &\
5550                     ~0x80000000U) | ((uint32_t)(0) << 31)
5551 #define EMAC_REGS__PHY_MANAGEMENT__TYPE                                uint32_t
5552 #define EMAC_REGS__PHY_MANAGEMENT__READ                             0xffffffffU
5553 #define EMAC_REGS__PHY_MANAGEMENT__WRITE                            0xffffffffU
5554 
5555 #endif /* __EMAC_REGS__PHY_MANAGEMENT_MACRO__ */
5556 
5557 
5558 /* macros for phy_management */
5559 #define INST_PHY_MANAGEMENT__NUM                                              1
5560 
5561 /* macros for BlueprintGlobalNameSpace::emac_regs::pause_time */
5562 #ifndef __EMAC_REGS__PAUSE_TIME_MACRO__
5563 #define __EMAC_REGS__PAUSE_TIME_MACRO__
5564 
5565 /* macros for field quantum */
5566 #define EMAC_REGS__PAUSE_TIME__QUANTUM__SHIFT                                 0
5567 #define EMAC_REGS__PAUSE_TIME__QUANTUM__WIDTH                                16
5568 #define EMAC_REGS__PAUSE_TIME__QUANTUM__MASK                        0x0000ffffU
5569 #define EMAC_REGS__PAUSE_TIME__QUANTUM__RESET                                 0
5570 #define EMAC_REGS__PAUSE_TIME__QUANTUM__READ(src) \
5571                     ((uint32_t)(src)\
5572                     & 0x0000ffffU)
5573 
5574 /* macros for field reserved_31_16 */
5575 #define EMAC_REGS__PAUSE_TIME__RESERVED_31_16__SHIFT                         16
5576 #define EMAC_REGS__PAUSE_TIME__RESERVED_31_16__WIDTH                         16
5577 #define EMAC_REGS__PAUSE_TIME__RESERVED_31_16__MASK                 0xffff0000U
5578 #define EMAC_REGS__PAUSE_TIME__RESERVED_31_16__RESET                          0
5579 #define EMAC_REGS__PAUSE_TIME__RESERVED_31_16__READ(src) \
5580                     (((uint32_t)(src)\
5581                     & 0xffff0000U) >> 16)
5582 #define EMAC_REGS__PAUSE_TIME__TYPE                                    uint32_t
5583 #define EMAC_REGS__PAUSE_TIME__READ                                 0xffffffffU
5584 
5585 #endif /* __EMAC_REGS__PAUSE_TIME_MACRO__ */
5586 
5587 
5588 /* macros for pause_time */
5589 #define INST_PAUSE_TIME__NUM                                                  1
5590 
5591 /* macros for BlueprintGlobalNameSpace::emac_regs::tx_pause_quantum */
5592 #ifndef __EMAC_REGS__TX_PAUSE_QUANTUM_MACRO__
5593 #define __EMAC_REGS__TX_PAUSE_QUANTUM_MACRO__
5594 
5595 /* macros for field quantum */
5596 #define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__SHIFT                           0
5597 #define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__WIDTH                          16
5598 #define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__MASK                  0x0000ffffU
5599 #define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__RESET                      0xFFFF
5600 #define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__READ(src) \
5601                     ((uint32_t)(src)\
5602                     & 0x0000ffffU)
5603 #define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__WRITE(src) \
5604                     ((uint32_t)(src)\
5605                     & 0x0000ffffU)
5606 #define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__MODIFY(dst, src) \
5607                     (dst) = ((dst) &\
5608                     ~0x0000ffffU) | ((uint32_t)(src) &\
5609                     0x0000ffffU)
5610 #define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM__VERIFY(src) \
5611                     (!(((uint32_t)(src)\
5612                     & ~0x0000ffffU)))
5613 
5614 /* macros for field quantum_p1 */
5615 #define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__SHIFT                       16
5616 #define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__WIDTH                       16
5617 #define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__MASK               0xffff0000U
5618 #define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__RESET                   0xFFFF
5619 #define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__READ(src) \
5620                     (((uint32_t)(src)\
5621                     & 0xffff0000U) >> 16)
5622 #define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__WRITE(src) \
5623                     (((uint32_t)(src)\
5624                     << 16) & 0xffff0000U)
5625 #define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__MODIFY(dst, src) \
5626                     (dst) = ((dst) &\
5627                     ~0xffff0000U) | (((uint32_t)(src) <<\
5628                     16) & 0xffff0000U)
5629 #define EMAC_REGS__TX_PAUSE_QUANTUM__QUANTUM_P1__VERIFY(src) \
5630                     (!((((uint32_t)(src)\
5631                     << 16) & ~0xffff0000U)))
5632 #define EMAC_REGS__TX_PAUSE_QUANTUM__TYPE                              uint32_t
5633 #define EMAC_REGS__TX_PAUSE_QUANTUM__READ                           0xffffffffU
5634 #define EMAC_REGS__TX_PAUSE_QUANTUM__WRITE                          0xffffffffU
5635 
5636 #endif /* __EMAC_REGS__TX_PAUSE_QUANTUM_MACRO__ */
5637 
5638 
5639 /* macros for tx_pause_quantum */
5640 #define INST_TX_PAUSE_QUANTUM__NUM                                            1
5641 
5642 /* macros for BlueprintGlobalNameSpace::emac_regs::pbuf_txcutthru */
5643 #ifndef __EMAC_REGS__PBUF_TXCUTTHRU_MACRO__
5644 #define __EMAC_REGS__PBUF_TXCUTTHRU_MACRO__
5645 
5646 /* macros for field dma_tx_cutthru_threshold */
5647 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__SHIFT            0
5648 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__WIDTH           14
5649 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__MASK   0x00003fffU
5650 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__RESET        16383
5651 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__READ(src) \
5652                     ((uint32_t)(src)\
5653                     & 0x00003fffU)
5654 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__WRITE(src) \
5655                     ((uint32_t)(src)\
5656                     & 0x00003fffU)
5657 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__MODIFY(dst, src) \
5658                     (dst) = ((dst) &\
5659                     ~0x00003fffU) | ((uint32_t)(src) &\
5660                     0x00003fffU)
5661 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU_THRESHOLD__VERIFY(src) \
5662                     (!(((uint32_t)(src)\
5663                     & ~0x00003fffU)))
5664 
5665 /* macros for field reserved */
5666 #define EMAC_REGS__PBUF_TXCUTTHRU__RESERVED__SHIFT                           14
5667 #define EMAC_REGS__PBUF_TXCUTTHRU__RESERVED__WIDTH                           17
5668 #define EMAC_REGS__PBUF_TXCUTTHRU__RESERVED__MASK                   0x7fffc000U
5669 #define EMAC_REGS__PBUF_TXCUTTHRU__RESERVED__RESET                            0
5670 #define EMAC_REGS__PBUF_TXCUTTHRU__RESERVED__READ(src) \
5671                     (((uint32_t)(src)\
5672                     & 0x7fffc000U) >> 14)
5673 
5674 /* macros for field dma_tx_cutthru */
5675 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__SHIFT                     31
5676 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__WIDTH                      1
5677 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__MASK             0x80000000U
5678 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__RESET                      0
5679 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__READ(src) \
5680                     (((uint32_t)(src)\
5681                     & 0x80000000U) >> 31)
5682 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__WRITE(src) \
5683                     (((uint32_t)(src)\
5684                     << 31) & 0x80000000U)
5685 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__MODIFY(dst, src) \
5686                     (dst) = ((dst) &\
5687                     ~0x80000000U) | (((uint32_t)(src) <<\
5688                     31) & 0x80000000U)
5689 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__VERIFY(src) \
5690                     (!((((uint32_t)(src)\
5691                     << 31) & ~0x80000000U)))
5692 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__SET(dst) \
5693                     (dst) = ((dst) &\
5694                     ~0x80000000U) | ((uint32_t)(1) << 31)
5695 #define EMAC_REGS__PBUF_TXCUTTHRU__DMA_TX_CUTTHRU__CLR(dst) \
5696                     (dst) = ((dst) &\
5697                     ~0x80000000U) | ((uint32_t)(0) << 31)
5698 #define EMAC_REGS__PBUF_TXCUTTHRU__TYPE                                uint32_t
5699 #define EMAC_REGS__PBUF_TXCUTTHRU__READ                             0xffffffffU
5700 #define EMAC_REGS__PBUF_TXCUTTHRU__WRITE                            0xffffffffU
5701 
5702 #endif /* __EMAC_REGS__PBUF_TXCUTTHRU_MACRO__ */
5703 
5704 
5705 /* macros for pbuf_txcutthru */
5706 #define INST_PBUF_TXCUTTHRU__NUM                                              1
5707 
5708 /* macros for BlueprintGlobalNameSpace::emac_regs::pbuf_rxcutthru */
5709 #ifndef __EMAC_REGS__PBUF_RXCUTTHRU_MACRO__
5710 #define __EMAC_REGS__PBUF_RXCUTTHRU_MACRO__
5711 
5712 /* macros for field dma_rx_cutthru_threshold */
5713 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__SHIFT            0
5714 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__WIDTH           11
5715 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__MASK   0x000007ffU
5716 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__RESET         2047
5717 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__READ(src) \
5718                     ((uint32_t)(src)\
5719                     & 0x000007ffU)
5720 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__WRITE(src) \
5721                     ((uint32_t)(src)\
5722                     & 0x000007ffU)
5723 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__MODIFY(dst, src) \
5724                     (dst) = ((dst) &\
5725                     ~0x000007ffU) | ((uint32_t)(src) &\
5726                     0x000007ffU)
5727 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU_THRESHOLD__VERIFY(src) \
5728                     (!(((uint32_t)(src)\
5729                     & ~0x000007ffU)))
5730 
5731 /* macros for field reserved */
5732 #define EMAC_REGS__PBUF_RXCUTTHRU__RESERVED__SHIFT                           11
5733 #define EMAC_REGS__PBUF_RXCUTTHRU__RESERVED__WIDTH                           20
5734 #define EMAC_REGS__PBUF_RXCUTTHRU__RESERVED__MASK                   0x7ffff800U
5735 #define EMAC_REGS__PBUF_RXCUTTHRU__RESERVED__RESET                            0
5736 #define EMAC_REGS__PBUF_RXCUTTHRU__RESERVED__READ(src) \
5737                     (((uint32_t)(src)\
5738                     & 0x7ffff800U) >> 11)
5739 
5740 /* macros for field dma_rx_cutthru */
5741 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__SHIFT                     31
5742 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__WIDTH                      1
5743 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__MASK             0x80000000U
5744 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__RESET                      0
5745 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__READ(src) \
5746                     (((uint32_t)(src)\
5747                     & 0x80000000U) >> 31)
5748 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__WRITE(src) \
5749                     (((uint32_t)(src)\
5750                     << 31) & 0x80000000U)
5751 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__MODIFY(dst, src) \
5752                     (dst) = ((dst) &\
5753                     ~0x80000000U) | (((uint32_t)(src) <<\
5754                     31) & 0x80000000U)
5755 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__VERIFY(src) \
5756                     (!((((uint32_t)(src)\
5757                     << 31) & ~0x80000000U)))
5758 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__SET(dst) \
5759                     (dst) = ((dst) &\
5760                     ~0x80000000U) | ((uint32_t)(1) << 31)
5761 #define EMAC_REGS__PBUF_RXCUTTHRU__DMA_RX_CUTTHRU__CLR(dst) \
5762                     (dst) = ((dst) &\
5763                     ~0x80000000U) | ((uint32_t)(0) << 31)
5764 #define EMAC_REGS__PBUF_RXCUTTHRU__TYPE                                uint32_t
5765 #define EMAC_REGS__PBUF_RXCUTTHRU__READ                             0xffffffffU
5766 #define EMAC_REGS__PBUF_RXCUTTHRU__WRITE                            0xffffffffU
5767 
5768 #endif /* __EMAC_REGS__PBUF_RXCUTTHRU_MACRO__ */
5769 
5770 
5771 /* macros for pbuf_rxcutthru */
5772 #define INST_PBUF_RXCUTTHRU__NUM                                              1
5773 
5774 /* macros for BlueprintGlobalNameSpace::emac_regs::jumbo_max_length */
5775 #ifndef __EMAC_REGS__JUMBO_MAX_LENGTH_MACRO__
5776 #define __EMAC_REGS__JUMBO_MAX_LENGTH_MACRO__
5777 
5778 /* macros for field jumbo_max_length */
5779 #define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__SHIFT                  0
5780 #define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__WIDTH                 14
5781 #define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__MASK         0x00003fffU
5782 #define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__RESET              10240
5783 #define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__READ(src) \
5784                     ((uint32_t)(src)\
5785                     & 0x00003fffU)
5786 #define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__WRITE(src) \
5787                     ((uint32_t)(src)\
5788                     & 0x00003fffU)
5789 #define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__MODIFY(dst, src) \
5790                     (dst) = ((dst) &\
5791                     ~0x00003fffU) | ((uint32_t)(src) &\
5792                     0x00003fffU)
5793 #define EMAC_REGS__JUMBO_MAX_LENGTH__JUMBO_MAX_LENGTH__VERIFY(src) \
5794                     (!(((uint32_t)(src)\
5795                     & ~0x00003fffU)))
5796 
5797 /* macros for field reserved_31_14 */
5798 #define EMAC_REGS__JUMBO_MAX_LENGTH__RESERVED_31_14__SHIFT                   14
5799 #define EMAC_REGS__JUMBO_MAX_LENGTH__RESERVED_31_14__WIDTH                   18
5800 #define EMAC_REGS__JUMBO_MAX_LENGTH__RESERVED_31_14__MASK           0xffffc000U
5801 #define EMAC_REGS__JUMBO_MAX_LENGTH__RESERVED_31_14__RESET                    0
5802 #define EMAC_REGS__JUMBO_MAX_LENGTH__RESERVED_31_14__READ(src) \
5803                     (((uint32_t)(src)\
5804                     & 0xffffc000U) >> 14)
5805 #define EMAC_REGS__JUMBO_MAX_LENGTH__TYPE                              uint32_t
5806 #define EMAC_REGS__JUMBO_MAX_LENGTH__READ                           0xffffffffU
5807 #define EMAC_REGS__JUMBO_MAX_LENGTH__WRITE                          0xffffffffU
5808 
5809 #endif /* __EMAC_REGS__JUMBO_MAX_LENGTH_MACRO__ */
5810 
5811 
5812 /* macros for jumbo_max_length */
5813 #define INST_JUMBO_MAX_LENGTH__NUM                                            1
5814 
5815 /* macros for BlueprintGlobalNameSpace::emac_regs::external_fifo_interface */
5816 #ifndef __EMAC_REGS__EXTERNAL_FIFO_INTERFACE_MACRO__
5817 #define __EMAC_REGS__EXTERNAL_FIFO_INTERFACE_MACRO__
5818 
5819 /* macros for field external_fifo_interface */
5820 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__SHIFT    0
5821 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__WIDTH    1
5822 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__MASK \
5823                     0x00000001U
5824 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__RESET    0
5825 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__READ(src) \
5826                     ((uint32_t)(src)\
5827                     & 0x00000001U)
5828 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__WRITE(src) \
5829                     ((uint32_t)(src)\
5830                     & 0x00000001U)
5831 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__MODIFY(dst, src) \
5832                     (dst) = ((dst) &\
5833                     ~0x00000001U) | ((uint32_t)(src) &\
5834                     0x00000001U)
5835 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__VERIFY(src) \
5836                     (!(((uint32_t)(src)\
5837                     & ~0x00000001U)))
5838 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__SET(dst) \
5839                     (dst) = ((dst) &\
5840                     ~0x00000001U) | (uint32_t)(1)
5841 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__EXTERNAL_FIFO_INTERFACE__CLR(dst) \
5842                     (dst) = ((dst) &\
5843                     ~0x00000001U) | (uint32_t)(0)
5844 
5845 /* macros for field reserved_31_1 */
5846 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__RESERVED_31_1__SHIFT              1
5847 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__RESERVED_31_1__WIDTH             31
5848 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__RESERVED_31_1__MASK     0xfffffffeU
5849 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__RESERVED_31_1__RESET              0
5850 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__RESERVED_31_1__READ(src) \
5851                     (((uint32_t)(src)\
5852                     & 0xfffffffeU) >> 1)
5853 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__TYPE                       uint32_t
5854 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__READ                    0xffffffffU
5855 #define EMAC_REGS__EXTERNAL_FIFO_INTERFACE__WRITE                   0xffffffffU
5856 
5857 #endif /* __EMAC_REGS__EXTERNAL_FIFO_INTERFACE_MACRO__ */
5858 
5859 
5860 /* macros for external_fifo_interface */
5861 #define INST_EXTERNAL_FIFO_INTERFACE__NUM                                     1
5862 
5863 /* macros for BlueprintGlobalNameSpace::emac_regs::axi_max_pipeline */
5864 #ifndef __EMAC_REGS__AXI_MAX_PIPELINE_MACRO__
5865 #define __EMAC_REGS__AXI_MAX_PIPELINE_MACRO__
5866 
5867 /* macros for field ar2r_max_pipeline */
5868 #define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__SHIFT                 0
5869 #define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__WIDTH                 8
5870 #define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__MASK        0x000000ffU
5871 #define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__RESET                 1
5872 #define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__READ(src) \
5873                     ((uint32_t)(src)\
5874                     & 0x000000ffU)
5875 #define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__WRITE(src) \
5876                     ((uint32_t)(src)\
5877                     & 0x000000ffU)
5878 #define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__MODIFY(dst, src) \
5879                     (dst) = ((dst) &\
5880                     ~0x000000ffU) | ((uint32_t)(src) &\
5881                     0x000000ffU)
5882 #define EMAC_REGS__AXI_MAX_PIPELINE__AR2R_MAX_PIPELINE__VERIFY(src) \
5883                     (!(((uint32_t)(src)\
5884                     & ~0x000000ffU)))
5885 
5886 /* macros for field aw2w_max_pipeline */
5887 #define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__SHIFT                 8
5888 #define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__WIDTH                 8
5889 #define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__MASK        0x0000ff00U
5890 #define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__RESET                 1
5891 #define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__READ(src) \
5892                     (((uint32_t)(src)\
5893                     & 0x0000ff00U) >> 8)
5894 #define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__WRITE(src) \
5895                     (((uint32_t)(src)\
5896                     << 8) & 0x0000ff00U)
5897 #define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__MODIFY(dst, src) \
5898                     (dst) = ((dst) &\
5899                     ~0x0000ff00U) | (((uint32_t)(src) <<\
5900                     8) & 0x0000ff00U)
5901 #define EMAC_REGS__AXI_MAX_PIPELINE__AW2W_MAX_PIPELINE__VERIFY(src) \
5902                     (!((((uint32_t)(src)\
5903                     << 8) & ~0x0000ff00U)))
5904 
5905 /* macros for field use_aw2b_fill */
5906 #define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__SHIFT                    16
5907 #define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__WIDTH                     1
5908 #define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__MASK            0x00010000U
5909 #define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__RESET                     0
5910 #define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__READ(src) \
5911                     (((uint32_t)(src)\
5912                     & 0x00010000U) >> 16)
5913 #define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__WRITE(src) \
5914                     (((uint32_t)(src)\
5915                     << 16) & 0x00010000U)
5916 #define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__MODIFY(dst, src) \
5917                     (dst) = ((dst) &\
5918                     ~0x00010000U) | (((uint32_t)(src) <<\
5919                     16) & 0x00010000U)
5920 #define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__VERIFY(src) \
5921                     (!((((uint32_t)(src)\
5922                     << 16) & ~0x00010000U)))
5923 #define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__SET(dst) \
5924                     (dst) = ((dst) &\
5925                     ~0x00010000U) | ((uint32_t)(1) << 16)
5926 #define EMAC_REGS__AXI_MAX_PIPELINE__USE_AW2B_FILL__CLR(dst) \
5927                     (dst) = ((dst) &\
5928                     ~0x00010000U) | ((uint32_t)(0) << 16)
5929 
5930 /* macros for field reserved */
5931 #define EMAC_REGS__AXI_MAX_PIPELINE__RESERVED__SHIFT                         17
5932 #define EMAC_REGS__AXI_MAX_PIPELINE__RESERVED__WIDTH                         15
5933 #define EMAC_REGS__AXI_MAX_PIPELINE__RESERVED__MASK                 0xfffe0000U
5934 #define EMAC_REGS__AXI_MAX_PIPELINE__RESERVED__RESET                          0
5935 #define EMAC_REGS__AXI_MAX_PIPELINE__RESERVED__READ(src) \
5936                     (((uint32_t)(src)\
5937                     & 0xfffe0000U) >> 17)
5938 #define EMAC_REGS__AXI_MAX_PIPELINE__TYPE                              uint32_t
5939 #define EMAC_REGS__AXI_MAX_PIPELINE__READ                           0xffffffffU
5940 #define EMAC_REGS__AXI_MAX_PIPELINE__WRITE                          0xffffffffU
5941 
5942 #endif /* __EMAC_REGS__AXI_MAX_PIPELINE_MACRO__ */
5943 
5944 
5945 /* macros for axi_max_pipeline */
5946 #define INST_AXI_MAX_PIPELINE__NUM                                            1
5947 
5948 /* macros for BlueprintGlobalNameSpace::emac_regs::rsc_control */
5949 #ifndef __EMAC_REGS__RSC_CONTROL_MACRO__
5950 #define __EMAC_REGS__RSC_CONTROL_MACRO__
5951 
5952 /* macros for field reserved_0 */
5953 #define EMAC_REGS__RSC_CONTROL__RESERVED_0__SHIFT                             0
5954 #define EMAC_REGS__RSC_CONTROL__RESERVED_0__WIDTH                             1
5955 #define EMAC_REGS__RSC_CONTROL__RESERVED_0__MASK                    0x00000001U
5956 #define EMAC_REGS__RSC_CONTROL__RESERVED_0__RESET                             0
5957 #define EMAC_REGS__RSC_CONTROL__RESERVED_0__READ(src) \
5958                     ((uint32_t)(src)\
5959                     & 0x00000001U)
5960 #define EMAC_REGS__RSC_CONTROL__RESERVED_0__SET(dst) \
5961                     (dst) = ((dst) &\
5962                     ~0x00000001U) | (uint32_t)(1)
5963 #define EMAC_REGS__RSC_CONTROL__RESERVED_0__CLR(dst) \
5964                     (dst) = ((dst) &\
5965                     ~0x00000001U) | (uint32_t)(0)
5966 
5967 /* macros for field rsc_control */
5968 #define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__SHIFT                            1
5969 #define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__WIDTH                           15
5970 #define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__MASK                   0x0000fffeU
5971 #define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__RESET                            0
5972 #define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__READ(src) \
5973                     (((uint32_t)(src)\
5974                     & 0x0000fffeU) >> 1)
5975 #define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__WRITE(src) \
5976                     (((uint32_t)(src)\
5977                     << 1) & 0x0000fffeU)
5978 #define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__MODIFY(dst, src) \
5979                     (dst) = ((dst) &\
5980                     ~0x0000fffeU) | (((uint32_t)(src) <<\
5981                     1) & 0x0000fffeU)
5982 #define EMAC_REGS__RSC_CONTROL__RSC_CONTROL__VERIFY(src) \
5983                     (!((((uint32_t)(src)\
5984                     << 1) & ~0x0000fffeU)))
5985 
5986 /* macros for field rsc_clr_mask */
5987 #define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__SHIFT                          16
5988 #define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__WIDTH                           1
5989 #define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__MASK                  0x00010000U
5990 #define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__RESET                           0
5991 #define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__READ(src) \
5992                     (((uint32_t)(src)\
5993                     & 0x00010000U) >> 16)
5994 #define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__WRITE(src) \
5995                     (((uint32_t)(src)\
5996                     << 16) & 0x00010000U)
5997 #define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__MODIFY(dst, src) \
5998                     (dst) = ((dst) &\
5999                     ~0x00010000U) | (((uint32_t)(src) <<\
6000                     16) & 0x00010000U)
6001 #define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__VERIFY(src) \
6002                     (!((((uint32_t)(src)\
6003                     << 16) & ~0x00010000U)))
6004 #define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__SET(dst) \
6005                     (dst) = ((dst) &\
6006                     ~0x00010000U) | ((uint32_t)(1) << 16)
6007 #define EMAC_REGS__RSC_CONTROL__RSC_CLR_MASK__CLR(dst) \
6008                     (dst) = ((dst) &\
6009                     ~0x00010000U) | ((uint32_t)(0) << 16)
6010 
6011 /* macros for field reserved_31_17 */
6012 #define EMAC_REGS__RSC_CONTROL__RESERVED_31_17__SHIFT                        17
6013 #define EMAC_REGS__RSC_CONTROL__RESERVED_31_17__WIDTH                        15
6014 #define EMAC_REGS__RSC_CONTROL__RESERVED_31_17__MASK                0xfffe0000U
6015 #define EMAC_REGS__RSC_CONTROL__RESERVED_31_17__RESET                         0
6016 #define EMAC_REGS__RSC_CONTROL__RESERVED_31_17__READ(src) \
6017                     (((uint32_t)(src)\
6018                     & 0xfffe0000U) >> 17)
6019 #define EMAC_REGS__RSC_CONTROL__TYPE                                   uint32_t
6020 #define EMAC_REGS__RSC_CONTROL__READ                                0xffffffffU
6021 #define EMAC_REGS__RSC_CONTROL__WRITE                               0xffffffffU
6022 
6023 #endif /* __EMAC_REGS__RSC_CONTROL_MACRO__ */
6024 
6025 
6026 /* macros for rsc_control */
6027 #define INST_RSC_CONTROL__NUM                                                 1
6028 
6029 /* macros for BlueprintGlobalNameSpace::emac_regs::int_moderation */
6030 #ifndef __EMAC_REGS__INT_MODERATION_MACRO__
6031 #define __EMAC_REGS__INT_MODERATION_MACRO__
6032 
6033 /* macros for field rx_int_moderation */
6034 #define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__SHIFT                   0
6035 #define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__WIDTH                   8
6036 #define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__MASK          0x000000ffU
6037 #define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__RESET                   0
6038 #define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__READ(src) \
6039                     ((uint32_t)(src)\
6040                     & 0x000000ffU)
6041 #define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__WRITE(src) \
6042                     ((uint32_t)(src)\
6043                     & 0x000000ffU)
6044 #define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__MODIFY(dst, src) \
6045                     (dst) = ((dst) &\
6046                     ~0x000000ffU) | ((uint32_t)(src) &\
6047                     0x000000ffU)
6048 #define EMAC_REGS__INT_MODERATION__RX_INT_MODERATION__VERIFY(src) \
6049                     (!(((uint32_t)(src)\
6050                     & ~0x000000ffU)))
6051 
6052 /* macros for field reserved_15_8 */
6053 #define EMAC_REGS__INT_MODERATION__RESERVED_15_8__SHIFT                       8
6054 #define EMAC_REGS__INT_MODERATION__RESERVED_15_8__WIDTH                       8
6055 #define EMAC_REGS__INT_MODERATION__RESERVED_15_8__MASK              0x0000ff00U
6056 #define EMAC_REGS__INT_MODERATION__RESERVED_15_8__RESET                       0
6057 #define EMAC_REGS__INT_MODERATION__RESERVED_15_8__READ(src) \
6058                     (((uint32_t)(src)\
6059                     & 0x0000ff00U) >> 8)
6060 
6061 /* macros for field tx_int_moderation */
6062 #define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__SHIFT                  16
6063 #define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__WIDTH                   8
6064 #define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__MASK          0x00ff0000U
6065 #define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__RESET                   0
6066 #define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__READ(src) \
6067                     (((uint32_t)(src)\
6068                     & 0x00ff0000U) >> 16)
6069 #define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__WRITE(src) \
6070                     (((uint32_t)(src)\
6071                     << 16) & 0x00ff0000U)
6072 #define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__MODIFY(dst, src) \
6073                     (dst) = ((dst) &\
6074                     ~0x00ff0000U) | (((uint32_t)(src) <<\
6075                     16) & 0x00ff0000U)
6076 #define EMAC_REGS__INT_MODERATION__TX_INT_MODERATION__VERIFY(src) \
6077                     (!((((uint32_t)(src)\
6078                     << 16) & ~0x00ff0000U)))
6079 
6080 /* macros for field reserved_31_24 */
6081 #define EMAC_REGS__INT_MODERATION__RESERVED_31_24__SHIFT                     24
6082 #define EMAC_REGS__INT_MODERATION__RESERVED_31_24__WIDTH                      8
6083 #define EMAC_REGS__INT_MODERATION__RESERVED_31_24__MASK             0xff000000U
6084 #define EMAC_REGS__INT_MODERATION__RESERVED_31_24__RESET                      0
6085 #define EMAC_REGS__INT_MODERATION__RESERVED_31_24__READ(src) \
6086                     (((uint32_t)(src)\
6087                     & 0xff000000U) >> 24)
6088 #define EMAC_REGS__INT_MODERATION__TYPE                                uint32_t
6089 #define EMAC_REGS__INT_MODERATION__READ                             0xffffffffU
6090 #define EMAC_REGS__INT_MODERATION__WRITE                            0xffffffffU
6091 
6092 #endif /* __EMAC_REGS__INT_MODERATION_MACRO__ */
6093 
6094 
6095 /* macros for int_moderation */
6096 #define INST_INT_MODERATION__NUM                                              1
6097 
6098 /* macros for BlueprintGlobalNameSpace::emac_regs::sys_wake_time */
6099 #ifndef __EMAC_REGS__SYS_WAKE_TIME_MACRO__
6100 #define __EMAC_REGS__SYS_WAKE_TIME_MACRO__
6101 
6102 /* macros for field sys_wake_time */
6103 #define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__SHIFT                        0
6104 #define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__WIDTH                       16
6105 #define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__MASK               0x0000ffffU
6106 #define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__RESET                        0
6107 #define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__READ(src) \
6108                     ((uint32_t)(src)\
6109                     & 0x0000ffffU)
6110 #define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__WRITE(src) \
6111                     ((uint32_t)(src)\
6112                     & 0x0000ffffU)
6113 #define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__MODIFY(dst, src) \
6114                     (dst) = ((dst) &\
6115                     ~0x0000ffffU) | ((uint32_t)(src) &\
6116                     0x0000ffffU)
6117 #define EMAC_REGS__SYS_WAKE_TIME__SYS_WAKE_TIME__VERIFY(src) \
6118                     (!(((uint32_t)(src)\
6119                     & ~0x0000ffffU)))
6120 
6121 /* macros for field reserved_31_16 */
6122 #define EMAC_REGS__SYS_WAKE_TIME__RESERVED_31_16__SHIFT                      16
6123 #define EMAC_REGS__SYS_WAKE_TIME__RESERVED_31_16__WIDTH                      16
6124 #define EMAC_REGS__SYS_WAKE_TIME__RESERVED_31_16__MASK              0xffff0000U
6125 #define EMAC_REGS__SYS_WAKE_TIME__RESERVED_31_16__RESET                       0
6126 #define EMAC_REGS__SYS_WAKE_TIME__RESERVED_31_16__READ(src) \
6127                     (((uint32_t)(src)\
6128                     & 0xffff0000U) >> 16)
6129 #define EMAC_REGS__SYS_WAKE_TIME__TYPE                                 uint32_t
6130 #define EMAC_REGS__SYS_WAKE_TIME__READ                              0xffffffffU
6131 #define EMAC_REGS__SYS_WAKE_TIME__WRITE                             0xffffffffU
6132 
6133 #endif /* __EMAC_REGS__SYS_WAKE_TIME_MACRO__ */
6134 
6135 
6136 /* macros for sys_wake_time */
6137 #define INST_SYS_WAKE_TIME__NUM                                               1
6138 
6139 /* macros for BlueprintGlobalNameSpace::emac_regs::hash_bottom */
6140 #ifndef __EMAC_REGS__HASH_BOTTOM_MACRO__
6141 #define __EMAC_REGS__HASH_BOTTOM_MACRO__
6142 
6143 /* macros for field address */
6144 #define EMAC_REGS__HASH_BOTTOM__ADDRESS__SHIFT                                0
6145 #define EMAC_REGS__HASH_BOTTOM__ADDRESS__WIDTH                               32
6146 #define EMAC_REGS__HASH_BOTTOM__ADDRESS__MASK                       0xffffffffU
6147 #define EMAC_REGS__HASH_BOTTOM__ADDRESS__RESET                                0
6148 #define EMAC_REGS__HASH_BOTTOM__ADDRESS__READ(src) \
6149                     ((uint32_t)(src)\
6150                     & 0xffffffffU)
6151 #define EMAC_REGS__HASH_BOTTOM__ADDRESS__WRITE(src) \
6152                     ((uint32_t)(src)\
6153                     & 0xffffffffU)
6154 #define EMAC_REGS__HASH_BOTTOM__ADDRESS__MODIFY(dst, src) \
6155                     (dst) = ((dst) &\
6156                     ~0xffffffffU) | ((uint32_t)(src) &\
6157                     0xffffffffU)
6158 #define EMAC_REGS__HASH_BOTTOM__ADDRESS__VERIFY(src) \
6159                     (!(((uint32_t)(src)\
6160                     & ~0xffffffffU)))
6161 #define EMAC_REGS__HASH_BOTTOM__TYPE                                   uint32_t
6162 #define EMAC_REGS__HASH_BOTTOM__READ                                0xffffffffU
6163 #define EMAC_REGS__HASH_BOTTOM__WRITE                               0xffffffffU
6164 
6165 #endif /* __EMAC_REGS__HASH_BOTTOM_MACRO__ */
6166 
6167 
6168 /* macros for hash_bottom */
6169 #define INST_HASH_BOTTOM__NUM                                                 1
6170 
6171 /* macros for BlueprintGlobalNameSpace::emac_regs::hash_top */
6172 #ifndef __EMAC_REGS__HASH_TOP_MACRO__
6173 #define __EMAC_REGS__HASH_TOP_MACRO__
6174 
6175 /* macros for field address */
6176 #define EMAC_REGS__HASH_TOP__ADDRESS__SHIFT                                   0
6177 #define EMAC_REGS__HASH_TOP__ADDRESS__WIDTH                                  32
6178 #define EMAC_REGS__HASH_TOP__ADDRESS__MASK                          0xffffffffU
6179 #define EMAC_REGS__HASH_TOP__ADDRESS__RESET                                   0
6180 #define EMAC_REGS__HASH_TOP__ADDRESS__READ(src) ((uint32_t)(src) & 0xffffffffU)
6181 #define EMAC_REGS__HASH_TOP__ADDRESS__WRITE(src) \
6182                     ((uint32_t)(src)\
6183                     & 0xffffffffU)
6184 #define EMAC_REGS__HASH_TOP__ADDRESS__MODIFY(dst, src) \
6185                     (dst) = ((dst) &\
6186                     ~0xffffffffU) | ((uint32_t)(src) &\
6187                     0xffffffffU)
6188 #define EMAC_REGS__HASH_TOP__ADDRESS__VERIFY(src) \
6189                     (!(((uint32_t)(src)\
6190                     & ~0xffffffffU)))
6191 #define EMAC_REGS__HASH_TOP__TYPE                                      uint32_t
6192 #define EMAC_REGS__HASH_TOP__READ                                   0xffffffffU
6193 #define EMAC_REGS__HASH_TOP__WRITE                                  0xffffffffU
6194 
6195 #endif /* __EMAC_REGS__HASH_TOP_MACRO__ */
6196 
6197 
6198 /* macros for hash_top */
6199 #define INST_HASH_TOP__NUM                                                    1
6200 
6201 /* macros for BlueprintGlobalNameSpace::emac_regs::spec_add_bottom */
6202 #ifndef __EMAC_REGS__SPEC_ADD_BOTTOM_MACRO__
6203 #define __EMAC_REGS__SPEC_ADD_BOTTOM_MACRO__
6204 
6205 /* macros for field address */
6206 #define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__SHIFT                            0
6207 #define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__WIDTH                           32
6208 #define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__MASK                   0xffffffffU
6209 #define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__RESET                            0
6210 #define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__READ(src) \
6211                     ((uint32_t)(src)\
6212                     & 0xffffffffU)
6213 #define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__WRITE(src) \
6214                     ((uint32_t)(src)\
6215                     & 0xffffffffU)
6216 #define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__MODIFY(dst, src) \
6217                     (dst) = ((dst) &\
6218                     ~0xffffffffU) | ((uint32_t)(src) &\
6219                     0xffffffffU)
6220 #define EMAC_REGS__SPEC_ADD_BOTTOM__ADDRESS__VERIFY(src) \
6221                     (!(((uint32_t)(src)\
6222                     & ~0xffffffffU)))
6223 #define EMAC_REGS__SPEC_ADD_BOTTOM__TYPE                               uint32_t
6224 #define EMAC_REGS__SPEC_ADD_BOTTOM__READ                            0xffffffffU
6225 #define EMAC_REGS__SPEC_ADD_BOTTOM__WRITE                           0xffffffffU
6226 
6227 #endif /* __EMAC_REGS__SPEC_ADD_BOTTOM_MACRO__ */
6228 
6229 
6230 /* macros for spec_add1_bottom */
6231 #define INST_SPEC_ADD1_BOTTOM__NUM                                            1
6232 
6233 /* macros for BlueprintGlobalNameSpace::emac_regs::spec_add_top_no_mask */
6234 #ifndef __EMAC_REGS__SPEC_ADD_TOP_NO_MASK_MACRO__
6235 #define __EMAC_REGS__SPEC_ADD_TOP_NO_MASK_MACRO__
6236 
6237 /* macros for field address */
6238 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__SHIFT                       0
6239 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__WIDTH                      16
6240 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__MASK              0x0000ffffU
6241 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__RESET                       0
6242 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__READ(src) \
6243                     ((uint32_t)(src)\
6244                     & 0x0000ffffU)
6245 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__WRITE(src) \
6246                     ((uint32_t)(src)\
6247                     & 0x0000ffffU)
6248 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__MODIFY(dst, src) \
6249                     (dst) = ((dst) &\
6250                     ~0x0000ffffU) | ((uint32_t)(src) &\
6251                     0x0000ffffU)
6252 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__ADDRESS__VERIFY(src) \
6253                     (!(((uint32_t)(src)\
6254                     & ~0x0000ffffU)))
6255 
6256 /* macros for field filter_type */
6257 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__SHIFT                  16
6258 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__WIDTH                   1
6259 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__MASK          0x00010000U
6260 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__RESET                   0
6261 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__READ(src) \
6262                     (((uint32_t)(src)\
6263                     & 0x00010000U) >> 16)
6264 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__WRITE(src) \
6265                     (((uint32_t)(src)\
6266                     << 16) & 0x00010000U)
6267 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__MODIFY(dst, src) \
6268                     (dst) = ((dst) &\
6269                     ~0x00010000U) | (((uint32_t)(src) <<\
6270                     16) & 0x00010000U)
6271 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__VERIFY(src) \
6272                     (!((((uint32_t)(src)\
6273                     << 16) & ~0x00010000U)))
6274 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__SET(dst) \
6275                     (dst) = ((dst) &\
6276                     ~0x00010000U) | ((uint32_t)(1) << 16)
6277 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__FILTER_TYPE__CLR(dst) \
6278                     (dst) = ((dst) &\
6279                     ~0x00010000U) | ((uint32_t)(0) << 16)
6280 
6281 /* macros for field reserved_31_17 */
6282 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__RESERVED_31_17__SHIFT               17
6283 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__RESERVED_31_17__WIDTH               15
6284 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__RESERVED_31_17__MASK       0xfffe0000U
6285 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__RESERVED_31_17__RESET                0
6286 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__RESERVED_31_17__READ(src) \
6287                     (((uint32_t)(src)\
6288                     & 0xfffe0000U) >> 17)
6289 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__TYPE                          uint32_t
6290 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__READ                       0xffffffffU
6291 #define EMAC_REGS__SPEC_ADD_TOP_NO_MASK__WRITE                      0xffffffffU
6292 
6293 #endif /* __EMAC_REGS__SPEC_ADD_TOP_NO_MASK_MACRO__ */
6294 
6295 
6296 /* macros for spec_add1_top */
6297 #define INST_SPEC_ADD1_TOP__NUM                                               1
6298 
6299 /* macros for spec_add2_bottom */
6300 #define INST_SPEC_ADD2_BOTTOM__NUM                                            1
6301 
6302 /* macros for BlueprintGlobalNameSpace::emac_regs::spec_add_top */
6303 #ifndef __EMAC_REGS__SPEC_ADD_TOP_MACRO__
6304 #define __EMAC_REGS__SPEC_ADD_TOP_MACRO__
6305 
6306 /* macros for field address */
6307 #define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__SHIFT                               0
6308 #define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__WIDTH                              16
6309 #define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__MASK                      0x0000ffffU
6310 #define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__RESET                               0
6311 #define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__READ(src) \
6312                     ((uint32_t)(src)\
6313                     & 0x0000ffffU)
6314 #define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__WRITE(src) \
6315                     ((uint32_t)(src)\
6316                     & 0x0000ffffU)
6317 #define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__MODIFY(dst, src) \
6318                     (dst) = ((dst) &\
6319                     ~0x0000ffffU) | ((uint32_t)(src) &\
6320                     0x0000ffffU)
6321 #define EMAC_REGS__SPEC_ADD_TOP__ADDRESS__VERIFY(src) \
6322                     (!(((uint32_t)(src)\
6323                     & ~0x0000ffffU)))
6324 
6325 /* macros for field filter_type */
6326 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__SHIFT                          16
6327 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__WIDTH                           1
6328 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__MASK                  0x00010000U
6329 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__RESET                           0
6330 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__READ(src) \
6331                     (((uint32_t)(src)\
6332                     & 0x00010000U) >> 16)
6333 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__WRITE(src) \
6334                     (((uint32_t)(src)\
6335                     << 16) & 0x00010000U)
6336 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__MODIFY(dst, src) \
6337                     (dst) = ((dst) &\
6338                     ~0x00010000U) | (((uint32_t)(src) <<\
6339                     16) & 0x00010000U)
6340 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__VERIFY(src) \
6341                     (!((((uint32_t)(src)\
6342                     << 16) & ~0x00010000U)))
6343 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__SET(dst) \
6344                     (dst) = ((dst) &\
6345                     ~0x00010000U) | ((uint32_t)(1) << 16)
6346 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_TYPE__CLR(dst) \
6347                     (dst) = ((dst) &\
6348                     ~0x00010000U) | ((uint32_t)(0) << 16)
6349 
6350 /* macros for field reserved_23_17 */
6351 #define EMAC_REGS__SPEC_ADD_TOP__RESERVED_23_17__SHIFT                       17
6352 #define EMAC_REGS__SPEC_ADD_TOP__RESERVED_23_17__WIDTH                        7
6353 #define EMAC_REGS__SPEC_ADD_TOP__RESERVED_23_17__MASK               0x00fe0000U
6354 #define EMAC_REGS__SPEC_ADD_TOP__RESERVED_23_17__RESET                        0
6355 #define EMAC_REGS__SPEC_ADD_TOP__RESERVED_23_17__READ(src) \
6356                     (((uint32_t)(src)\
6357                     & 0x00fe0000U) >> 17)
6358 
6359 /* macros for field filter_byte_mask */
6360 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__SHIFT                     24
6361 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__WIDTH                      6
6362 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__MASK             0x3f000000U
6363 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__RESET                      0
6364 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__READ(src) \
6365                     (((uint32_t)(src)\
6366                     & 0x3f000000U) >> 24)
6367 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__WRITE(src) \
6368                     (((uint32_t)(src)\
6369                     << 24) & 0x3f000000U)
6370 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__MODIFY(dst, src) \
6371                     (dst) = ((dst) &\
6372                     ~0x3f000000U) | (((uint32_t)(src) <<\
6373                     24) & 0x3f000000U)
6374 #define EMAC_REGS__SPEC_ADD_TOP__FILTER_BYTE_MASK__VERIFY(src) \
6375                     (!((((uint32_t)(src)\
6376                     << 24) & ~0x3f000000U)))
6377 
6378 /* macros for field reserved_31_30 */
6379 #define EMAC_REGS__SPEC_ADD_TOP__RESERVED_31_30__SHIFT                       30
6380 #define EMAC_REGS__SPEC_ADD_TOP__RESERVED_31_30__WIDTH                        2
6381 #define EMAC_REGS__SPEC_ADD_TOP__RESERVED_31_30__MASK               0xc0000000U
6382 #define EMAC_REGS__SPEC_ADD_TOP__RESERVED_31_30__RESET                        0
6383 #define EMAC_REGS__SPEC_ADD_TOP__RESERVED_31_30__READ(src) \
6384                     (((uint32_t)(src)\
6385                     & 0xc0000000U) >> 30)
6386 #define EMAC_REGS__SPEC_ADD_TOP__TYPE                                  uint32_t
6387 #define EMAC_REGS__SPEC_ADD_TOP__READ                               0xffffffffU
6388 #define EMAC_REGS__SPEC_ADD_TOP__WRITE                              0xffffffffU
6389 
6390 #endif /* __EMAC_REGS__SPEC_ADD_TOP_MACRO__ */
6391 
6392 
6393 /* macros for spec_add2_top */
6394 #define INST_SPEC_ADD2_TOP__NUM                                               1
6395 
6396 /* macros for spec_add3_bottom */
6397 #define INST_SPEC_ADD3_BOTTOM__NUM                                            1
6398 
6399 /* macros for spec_add3_top */
6400 #define INST_SPEC_ADD3_TOP__NUM                                               1
6401 
6402 /* macros for spec_add4_bottom */
6403 #define INST_SPEC_ADD4_BOTTOM__NUM                                            1
6404 
6405 /* macros for spec_add4_top */
6406 #define INST_SPEC_ADD4_TOP__NUM                                               1
6407 
6408 /* macros for BlueprintGlobalNameSpace::emac_regs::spec_type1 */
6409 #ifndef __EMAC_REGS__SPEC_TYPE1_MACRO__
6410 #define __EMAC_REGS__SPEC_TYPE1_MACRO__
6411 
6412 /* macros for field match */
6413 #define EMAC_REGS__SPEC_TYPE1__MATCH__SHIFT                                   0
6414 #define EMAC_REGS__SPEC_TYPE1__MATCH__WIDTH                                  16
6415 #define EMAC_REGS__SPEC_TYPE1__MATCH__MASK                          0x0000ffffU
6416 #define EMAC_REGS__SPEC_TYPE1__MATCH__RESET                                   0
6417 #define EMAC_REGS__SPEC_TYPE1__MATCH__READ(src) ((uint32_t)(src) & 0x0000ffffU)
6418 #define EMAC_REGS__SPEC_TYPE1__MATCH__WRITE(src) \
6419                     ((uint32_t)(src)\
6420                     & 0x0000ffffU)
6421 #define EMAC_REGS__SPEC_TYPE1__MATCH__MODIFY(dst, src) \
6422                     (dst) = ((dst) &\
6423                     ~0x0000ffffU) | ((uint32_t)(src) &\
6424                     0x0000ffffU)
6425 #define EMAC_REGS__SPEC_TYPE1__MATCH__VERIFY(src) \
6426                     (!(((uint32_t)(src)\
6427                     & ~0x0000ffffU)))
6428 
6429 /* macros for field reserved_30_16 */
6430 #define EMAC_REGS__SPEC_TYPE1__RESERVED_30_16__SHIFT                         16
6431 #define EMAC_REGS__SPEC_TYPE1__RESERVED_30_16__WIDTH                         15
6432 #define EMAC_REGS__SPEC_TYPE1__RESERVED_30_16__MASK                 0x7fff0000U
6433 #define EMAC_REGS__SPEC_TYPE1__RESERVED_30_16__RESET                          0
6434 #define EMAC_REGS__SPEC_TYPE1__RESERVED_30_16__READ(src) \
6435                     (((uint32_t)(src)\
6436                     & 0x7fff0000U) >> 16)
6437 
6438 /* macros for field enable_copy */
6439 #define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__SHIFT                            31
6440 #define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__WIDTH                             1
6441 #define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__MASK                    0x80000000U
6442 #define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__RESET                             0
6443 #define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__READ(src) \
6444                     (((uint32_t)(src)\
6445                     & 0x80000000U) >> 31)
6446 #define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__WRITE(src) \
6447                     (((uint32_t)(src)\
6448                     << 31) & 0x80000000U)
6449 #define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__MODIFY(dst, src) \
6450                     (dst) = ((dst) &\
6451                     ~0x80000000U) | (((uint32_t)(src) <<\
6452                     31) & 0x80000000U)
6453 #define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__VERIFY(src) \
6454                     (!((((uint32_t)(src)\
6455                     << 31) & ~0x80000000U)))
6456 #define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__SET(dst) \
6457                     (dst) = ((dst) &\
6458                     ~0x80000000U) | ((uint32_t)(1) << 31)
6459 #define EMAC_REGS__SPEC_TYPE1__ENABLE_COPY__CLR(dst) \
6460                     (dst) = ((dst) &\
6461                     ~0x80000000U) | ((uint32_t)(0) << 31)
6462 #define EMAC_REGS__SPEC_TYPE1__TYPE                                    uint32_t
6463 #define EMAC_REGS__SPEC_TYPE1__READ                                 0xffffffffU
6464 #define EMAC_REGS__SPEC_TYPE1__WRITE                                0xffffffffU
6465 
6466 #endif /* __EMAC_REGS__SPEC_TYPE1_MACRO__ */
6467 
6468 
6469 /* macros for spec_type1 */
6470 #define INST_SPEC_TYPE1__NUM                                                  1
6471 
6472 /* macros for BlueprintGlobalNameSpace::emac_regs::spec_type2 */
6473 #ifndef __EMAC_REGS__SPEC_TYPE2_MACRO__
6474 #define __EMAC_REGS__SPEC_TYPE2_MACRO__
6475 
6476 /* macros for field match */
6477 #define EMAC_REGS__SPEC_TYPE2__MATCH__SHIFT                                   0
6478 #define EMAC_REGS__SPEC_TYPE2__MATCH__WIDTH                                  16
6479 #define EMAC_REGS__SPEC_TYPE2__MATCH__MASK                          0x0000ffffU
6480 #define EMAC_REGS__SPEC_TYPE2__MATCH__RESET                                   0
6481 #define EMAC_REGS__SPEC_TYPE2__MATCH__READ(src) ((uint32_t)(src) & 0x0000ffffU)
6482 #define EMAC_REGS__SPEC_TYPE2__MATCH__WRITE(src) \
6483                     ((uint32_t)(src)\
6484                     & 0x0000ffffU)
6485 #define EMAC_REGS__SPEC_TYPE2__MATCH__MODIFY(dst, src) \
6486                     (dst) = ((dst) &\
6487                     ~0x0000ffffU) | ((uint32_t)(src) &\
6488                     0x0000ffffU)
6489 #define EMAC_REGS__SPEC_TYPE2__MATCH__VERIFY(src) \
6490                     (!(((uint32_t)(src)\
6491                     & ~0x0000ffffU)))
6492 
6493 /* macros for field reserved_30_16 */
6494 #define EMAC_REGS__SPEC_TYPE2__RESERVED_30_16__SHIFT                         16
6495 #define EMAC_REGS__SPEC_TYPE2__RESERVED_30_16__WIDTH                         15
6496 #define EMAC_REGS__SPEC_TYPE2__RESERVED_30_16__MASK                 0x7fff0000U
6497 #define EMAC_REGS__SPEC_TYPE2__RESERVED_30_16__RESET                          0
6498 #define EMAC_REGS__SPEC_TYPE2__RESERVED_30_16__READ(src) \
6499                     (((uint32_t)(src)\
6500                     & 0x7fff0000U) >> 16)
6501 
6502 /* macros for field enable_copy */
6503 #define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__SHIFT                            31
6504 #define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__WIDTH                             1
6505 #define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__MASK                    0x80000000U
6506 #define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__RESET                             0
6507 #define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__READ(src) \
6508                     (((uint32_t)(src)\
6509                     & 0x80000000U) >> 31)
6510 #define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__WRITE(src) \
6511                     (((uint32_t)(src)\
6512                     << 31) & 0x80000000U)
6513 #define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__MODIFY(dst, src) \
6514                     (dst) = ((dst) &\
6515                     ~0x80000000U) | (((uint32_t)(src) <<\
6516                     31) & 0x80000000U)
6517 #define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__VERIFY(src) \
6518                     (!((((uint32_t)(src)\
6519                     << 31) & ~0x80000000U)))
6520 #define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__SET(dst) \
6521                     (dst) = ((dst) &\
6522                     ~0x80000000U) | ((uint32_t)(1) << 31)
6523 #define EMAC_REGS__SPEC_TYPE2__ENABLE_COPY__CLR(dst) \
6524                     (dst) = ((dst) &\
6525                     ~0x80000000U) | ((uint32_t)(0) << 31)
6526 #define EMAC_REGS__SPEC_TYPE2__TYPE                                    uint32_t
6527 #define EMAC_REGS__SPEC_TYPE2__READ                                 0xffffffffU
6528 #define EMAC_REGS__SPEC_TYPE2__WRITE                                0xffffffffU
6529 
6530 #endif /* __EMAC_REGS__SPEC_TYPE2_MACRO__ */
6531 
6532 
6533 /* macros for spec_type2 */
6534 #define INST_SPEC_TYPE2__NUM                                                  1
6535 
6536 /* macros for BlueprintGlobalNameSpace::emac_regs::spec_type3 */
6537 #ifndef __EMAC_REGS__SPEC_TYPE3_MACRO__
6538 #define __EMAC_REGS__SPEC_TYPE3_MACRO__
6539 
6540 /* macros for field match */
6541 #define EMAC_REGS__SPEC_TYPE3__MATCH__SHIFT                                   0
6542 #define EMAC_REGS__SPEC_TYPE3__MATCH__WIDTH                                  16
6543 #define EMAC_REGS__SPEC_TYPE3__MATCH__MASK                          0x0000ffffU
6544 #define EMAC_REGS__SPEC_TYPE3__MATCH__RESET                                   0
6545 #define EMAC_REGS__SPEC_TYPE3__MATCH__READ(src) ((uint32_t)(src) & 0x0000ffffU)
6546 #define EMAC_REGS__SPEC_TYPE3__MATCH__WRITE(src) \
6547                     ((uint32_t)(src)\
6548                     & 0x0000ffffU)
6549 #define EMAC_REGS__SPEC_TYPE3__MATCH__MODIFY(dst, src) \
6550                     (dst) = ((dst) &\
6551                     ~0x0000ffffU) | ((uint32_t)(src) &\
6552                     0x0000ffffU)
6553 #define EMAC_REGS__SPEC_TYPE3__MATCH__VERIFY(src) \
6554                     (!(((uint32_t)(src)\
6555                     & ~0x0000ffffU)))
6556 
6557 /* macros for field reserved_30_16 */
6558 #define EMAC_REGS__SPEC_TYPE3__RESERVED_30_16__SHIFT                         16
6559 #define EMAC_REGS__SPEC_TYPE3__RESERVED_30_16__WIDTH                         15
6560 #define EMAC_REGS__SPEC_TYPE3__RESERVED_30_16__MASK                 0x7fff0000U
6561 #define EMAC_REGS__SPEC_TYPE3__RESERVED_30_16__RESET                          0
6562 #define EMAC_REGS__SPEC_TYPE3__RESERVED_30_16__READ(src) \
6563                     (((uint32_t)(src)\
6564                     & 0x7fff0000U) >> 16)
6565 
6566 /* macros for field enable_copy */
6567 #define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__SHIFT                            31
6568 #define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__WIDTH                             1
6569 #define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__MASK                    0x80000000U
6570 #define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__RESET                             0
6571 #define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__READ(src) \
6572                     (((uint32_t)(src)\
6573                     & 0x80000000U) >> 31)
6574 #define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__WRITE(src) \
6575                     (((uint32_t)(src)\
6576                     << 31) & 0x80000000U)
6577 #define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__MODIFY(dst, src) \
6578                     (dst) = ((dst) &\
6579                     ~0x80000000U) | (((uint32_t)(src) <<\
6580                     31) & 0x80000000U)
6581 #define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__VERIFY(src) \
6582                     (!((((uint32_t)(src)\
6583                     << 31) & ~0x80000000U)))
6584 #define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__SET(dst) \
6585                     (dst) = ((dst) &\
6586                     ~0x80000000U) | ((uint32_t)(1) << 31)
6587 #define EMAC_REGS__SPEC_TYPE3__ENABLE_COPY__CLR(dst) \
6588                     (dst) = ((dst) &\
6589                     ~0x80000000U) | ((uint32_t)(0) << 31)
6590 #define EMAC_REGS__SPEC_TYPE3__TYPE                                    uint32_t
6591 #define EMAC_REGS__SPEC_TYPE3__READ                                 0xffffffffU
6592 #define EMAC_REGS__SPEC_TYPE3__WRITE                                0xffffffffU
6593 
6594 #endif /* __EMAC_REGS__SPEC_TYPE3_MACRO__ */
6595 
6596 
6597 /* macros for spec_type3 */
6598 #define INST_SPEC_TYPE3__NUM                                                  1
6599 
6600 /* macros for BlueprintGlobalNameSpace::emac_regs::spec_type4 */
6601 #ifndef __EMAC_REGS__SPEC_TYPE4_MACRO__
6602 #define __EMAC_REGS__SPEC_TYPE4_MACRO__
6603 
6604 /* macros for field match */
6605 #define EMAC_REGS__SPEC_TYPE4__MATCH__SHIFT                                   0
6606 #define EMAC_REGS__SPEC_TYPE4__MATCH__WIDTH                                  16
6607 #define EMAC_REGS__SPEC_TYPE4__MATCH__MASK                          0x0000ffffU
6608 #define EMAC_REGS__SPEC_TYPE4__MATCH__RESET                                   0
6609 #define EMAC_REGS__SPEC_TYPE4__MATCH__READ(src) ((uint32_t)(src) & 0x0000ffffU)
6610 #define EMAC_REGS__SPEC_TYPE4__MATCH__WRITE(src) \
6611                     ((uint32_t)(src)\
6612                     & 0x0000ffffU)
6613 #define EMAC_REGS__SPEC_TYPE4__MATCH__MODIFY(dst, src) \
6614                     (dst) = ((dst) &\
6615                     ~0x0000ffffU) | ((uint32_t)(src) &\
6616                     0x0000ffffU)
6617 #define EMAC_REGS__SPEC_TYPE4__MATCH__VERIFY(src) \
6618                     (!(((uint32_t)(src)\
6619                     & ~0x0000ffffU)))
6620 
6621 /* macros for field reserved_30_16 */
6622 #define EMAC_REGS__SPEC_TYPE4__RESERVED_30_16__SHIFT                         16
6623 #define EMAC_REGS__SPEC_TYPE4__RESERVED_30_16__WIDTH                         15
6624 #define EMAC_REGS__SPEC_TYPE4__RESERVED_30_16__MASK                 0x7fff0000U
6625 #define EMAC_REGS__SPEC_TYPE4__RESERVED_30_16__RESET                          0
6626 #define EMAC_REGS__SPEC_TYPE4__RESERVED_30_16__READ(src) \
6627                     (((uint32_t)(src)\
6628                     & 0x7fff0000U) >> 16)
6629 
6630 /* macros for field enable_copy */
6631 #define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__SHIFT                            31
6632 #define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__WIDTH                             1
6633 #define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__MASK                    0x80000000U
6634 #define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__RESET                             0
6635 #define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__READ(src) \
6636                     (((uint32_t)(src)\
6637                     & 0x80000000U) >> 31)
6638 #define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__WRITE(src) \
6639                     (((uint32_t)(src)\
6640                     << 31) & 0x80000000U)
6641 #define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__MODIFY(dst, src) \
6642                     (dst) = ((dst) &\
6643                     ~0x80000000U) | (((uint32_t)(src) <<\
6644                     31) & 0x80000000U)
6645 #define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__VERIFY(src) \
6646                     (!((((uint32_t)(src)\
6647                     << 31) & ~0x80000000U)))
6648 #define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__SET(dst) \
6649                     (dst) = ((dst) &\
6650                     ~0x80000000U) | ((uint32_t)(1) << 31)
6651 #define EMAC_REGS__SPEC_TYPE4__ENABLE_COPY__CLR(dst) \
6652                     (dst) = ((dst) &\
6653                     ~0x80000000U) | ((uint32_t)(0) << 31)
6654 #define EMAC_REGS__SPEC_TYPE4__TYPE                                    uint32_t
6655 #define EMAC_REGS__SPEC_TYPE4__READ                                 0xffffffffU
6656 #define EMAC_REGS__SPEC_TYPE4__WRITE                                0xffffffffU
6657 
6658 #endif /* __EMAC_REGS__SPEC_TYPE4_MACRO__ */
6659 
6660 
6661 /* macros for spec_type4 */
6662 #define INST_SPEC_TYPE4__NUM                                                  1
6663 
6664 /* macros for BlueprintGlobalNameSpace::emac_regs::wol_register */
6665 #ifndef __EMAC_REGS__WOL_REGISTER_MACRO__
6666 #define __EMAC_REGS__WOL_REGISTER_MACRO__
6667 
6668 /* macros for field addr */
6669 #define EMAC_REGS__WOL_REGISTER__ADDR__SHIFT                                  0
6670 #define EMAC_REGS__WOL_REGISTER__ADDR__WIDTH                                 16
6671 #define EMAC_REGS__WOL_REGISTER__ADDR__MASK                         0x0000ffffU
6672 #define EMAC_REGS__WOL_REGISTER__ADDR__RESET                                  0
6673 #define EMAC_REGS__WOL_REGISTER__ADDR__READ(src) \
6674                     ((uint32_t)(src)\
6675                     & 0x0000ffffU)
6676 #define EMAC_REGS__WOL_REGISTER__ADDR__WRITE(src) \
6677                     ((uint32_t)(src)\
6678                     & 0x0000ffffU)
6679 #define EMAC_REGS__WOL_REGISTER__ADDR__MODIFY(dst, src) \
6680                     (dst) = ((dst) &\
6681                     ~0x0000ffffU) | ((uint32_t)(src) &\
6682                     0x0000ffffU)
6683 #define EMAC_REGS__WOL_REGISTER__ADDR__VERIFY(src) \
6684                     (!(((uint32_t)(src)\
6685                     & ~0x0000ffffU)))
6686 
6687 /* macros for field wol_mask_0 */
6688 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__SHIFT                           16
6689 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__WIDTH                            1
6690 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__MASK                   0x00010000U
6691 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__RESET                            0
6692 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__READ(src) \
6693                     (((uint32_t)(src)\
6694                     & 0x00010000U) >> 16)
6695 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__WRITE(src) \
6696                     (((uint32_t)(src)\
6697                     << 16) & 0x00010000U)
6698 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__MODIFY(dst, src) \
6699                     (dst) = ((dst) &\
6700                     ~0x00010000U) | (((uint32_t)(src) <<\
6701                     16) & 0x00010000U)
6702 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__VERIFY(src) \
6703                     (!((((uint32_t)(src)\
6704                     << 16) & ~0x00010000U)))
6705 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__SET(dst) \
6706                     (dst) = ((dst) &\
6707                     ~0x00010000U) | ((uint32_t)(1) << 16)
6708 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_0__CLR(dst) \
6709                     (dst) = ((dst) &\
6710                     ~0x00010000U) | ((uint32_t)(0) << 16)
6711 
6712 /* macros for field wol_mask_1 */
6713 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__SHIFT                           17
6714 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__WIDTH                            1
6715 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__MASK                   0x00020000U
6716 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__RESET                            0
6717 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__READ(src) \
6718                     (((uint32_t)(src)\
6719                     & 0x00020000U) >> 17)
6720 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__WRITE(src) \
6721                     (((uint32_t)(src)\
6722                     << 17) & 0x00020000U)
6723 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__MODIFY(dst, src) \
6724                     (dst) = ((dst) &\
6725                     ~0x00020000U) | (((uint32_t)(src) <<\
6726                     17) & 0x00020000U)
6727 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__VERIFY(src) \
6728                     (!((((uint32_t)(src)\
6729                     << 17) & ~0x00020000U)))
6730 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__SET(dst) \
6731                     (dst) = ((dst) &\
6732                     ~0x00020000U) | ((uint32_t)(1) << 17)
6733 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_1__CLR(dst) \
6734                     (dst) = ((dst) &\
6735                     ~0x00020000U) | ((uint32_t)(0) << 17)
6736 
6737 /* macros for field wol_mask_2 */
6738 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__SHIFT                           18
6739 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__WIDTH                            1
6740 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__MASK                   0x00040000U
6741 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__RESET                            0
6742 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__READ(src) \
6743                     (((uint32_t)(src)\
6744                     & 0x00040000U) >> 18)
6745 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__WRITE(src) \
6746                     (((uint32_t)(src)\
6747                     << 18) & 0x00040000U)
6748 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__MODIFY(dst, src) \
6749                     (dst) = ((dst) &\
6750                     ~0x00040000U) | (((uint32_t)(src) <<\
6751                     18) & 0x00040000U)
6752 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__VERIFY(src) \
6753                     (!((((uint32_t)(src)\
6754                     << 18) & ~0x00040000U)))
6755 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__SET(dst) \
6756                     (dst) = ((dst) &\
6757                     ~0x00040000U) | ((uint32_t)(1) << 18)
6758 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_2__CLR(dst) \
6759                     (dst) = ((dst) &\
6760                     ~0x00040000U) | ((uint32_t)(0) << 18)
6761 
6762 /* macros for field wol_mask_3 */
6763 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__SHIFT                           19
6764 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__WIDTH                            1
6765 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__MASK                   0x00080000U
6766 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__RESET                            0
6767 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__READ(src) \
6768                     (((uint32_t)(src)\
6769                     & 0x00080000U) >> 19)
6770 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__WRITE(src) \
6771                     (((uint32_t)(src)\
6772                     << 19) & 0x00080000U)
6773 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__MODIFY(dst, src) \
6774                     (dst) = ((dst) &\
6775                     ~0x00080000U) | (((uint32_t)(src) <<\
6776                     19) & 0x00080000U)
6777 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__VERIFY(src) \
6778                     (!((((uint32_t)(src)\
6779                     << 19) & ~0x00080000U)))
6780 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__SET(dst) \
6781                     (dst) = ((dst) &\
6782                     ~0x00080000U) | ((uint32_t)(1) << 19)
6783 #define EMAC_REGS__WOL_REGISTER__WOL_MASK_3__CLR(dst) \
6784                     (dst) = ((dst) &\
6785                     ~0x00080000U) | ((uint32_t)(0) << 19)
6786 
6787 /* macros for field reserved_31_20 */
6788 #define EMAC_REGS__WOL_REGISTER__RESERVED_31_20__SHIFT                       20
6789 #define EMAC_REGS__WOL_REGISTER__RESERVED_31_20__WIDTH                       12
6790 #define EMAC_REGS__WOL_REGISTER__RESERVED_31_20__MASK               0xfff00000U
6791 #define EMAC_REGS__WOL_REGISTER__RESERVED_31_20__RESET                        0
6792 #define EMAC_REGS__WOL_REGISTER__RESERVED_31_20__READ(src) \
6793                     (((uint32_t)(src)\
6794                     & 0xfff00000U) >> 20)
6795 #define EMAC_REGS__WOL_REGISTER__TYPE                                  uint32_t
6796 #define EMAC_REGS__WOL_REGISTER__READ                               0xffffffffU
6797 #define EMAC_REGS__WOL_REGISTER__WRITE                              0xffffffffU
6798 
6799 #endif /* __EMAC_REGS__WOL_REGISTER_MACRO__ */
6800 
6801 
6802 /* macros for wol_register */
6803 #define INST_WOL_REGISTER__NUM                                                1
6804 
6805 /* macros for BlueprintGlobalNameSpace::emac_regs::stretch_ratio */
6806 #ifndef __EMAC_REGS__STRETCH_RATIO_MACRO__
6807 #define __EMAC_REGS__STRETCH_RATIO_MACRO__
6808 
6809 /* macros for field ipg_stretch */
6810 #define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__SHIFT                          0
6811 #define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__WIDTH                         16
6812 #define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__MASK                 0x0000ffffU
6813 #define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__RESET                          0
6814 #define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__READ(src) \
6815                     ((uint32_t)(src)\
6816                     & 0x0000ffffU)
6817 #define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__WRITE(src) \
6818                     ((uint32_t)(src)\
6819                     & 0x0000ffffU)
6820 #define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__MODIFY(dst, src) \
6821                     (dst) = ((dst) &\
6822                     ~0x0000ffffU) | ((uint32_t)(src) &\
6823                     0x0000ffffU)
6824 #define EMAC_REGS__STRETCH_RATIO__IPG_STRETCH__VERIFY(src) \
6825                     (!(((uint32_t)(src)\
6826                     & ~0x0000ffffU)))
6827 
6828 /* macros for field reserved_31_16 */
6829 #define EMAC_REGS__STRETCH_RATIO__RESERVED_31_16__SHIFT                      16
6830 #define EMAC_REGS__STRETCH_RATIO__RESERVED_31_16__WIDTH                      16
6831 #define EMAC_REGS__STRETCH_RATIO__RESERVED_31_16__MASK              0xffff0000U
6832 #define EMAC_REGS__STRETCH_RATIO__RESERVED_31_16__RESET                       0
6833 #define EMAC_REGS__STRETCH_RATIO__RESERVED_31_16__READ(src) \
6834                     (((uint32_t)(src)\
6835                     & 0xffff0000U) >> 16)
6836 #define EMAC_REGS__STRETCH_RATIO__TYPE                                 uint32_t
6837 #define EMAC_REGS__STRETCH_RATIO__READ                              0xffffffffU
6838 #define EMAC_REGS__STRETCH_RATIO__WRITE                             0xffffffffU
6839 
6840 #endif /* __EMAC_REGS__STRETCH_RATIO_MACRO__ */
6841 
6842 
6843 /* macros for stretch_ratio */
6844 #define INST_STRETCH_RATIO__NUM                                               1
6845 
6846 /* macros for BlueprintGlobalNameSpace::emac_regs::stacked_vlan */
6847 #ifndef __EMAC_REGS__STACKED_VLAN_MACRO__
6848 #define __EMAC_REGS__STACKED_VLAN_MACRO__
6849 
6850 /* macros for field match */
6851 #define EMAC_REGS__STACKED_VLAN__MATCH__SHIFT                                 0
6852 #define EMAC_REGS__STACKED_VLAN__MATCH__WIDTH                                16
6853 #define EMAC_REGS__STACKED_VLAN__MATCH__MASK                        0x0000ffffU
6854 #define EMAC_REGS__STACKED_VLAN__MATCH__RESET                            0x0000
6855 #define EMAC_REGS__STACKED_VLAN__MATCH__READ(src) \
6856                     ((uint32_t)(src)\
6857                     & 0x0000ffffU)
6858 #define EMAC_REGS__STACKED_VLAN__MATCH__WRITE(src) \
6859                     ((uint32_t)(src)\
6860                     & 0x0000ffffU)
6861 #define EMAC_REGS__STACKED_VLAN__MATCH__MODIFY(dst, src) \
6862                     (dst) = ((dst) &\
6863                     ~0x0000ffffU) | ((uint32_t)(src) &\
6864                     0x0000ffffU)
6865 #define EMAC_REGS__STACKED_VLAN__MATCH__VERIFY(src) \
6866                     (!(((uint32_t)(src)\
6867                     & ~0x0000ffffU)))
6868 
6869 /* macros for field reserved_30_16 */
6870 #define EMAC_REGS__STACKED_VLAN__RESERVED_30_16__SHIFT                       16
6871 #define EMAC_REGS__STACKED_VLAN__RESERVED_30_16__WIDTH                       15
6872 #define EMAC_REGS__STACKED_VLAN__RESERVED_30_16__MASK               0x7fff0000U
6873 #define EMAC_REGS__STACKED_VLAN__RESERVED_30_16__RESET                        0
6874 #define EMAC_REGS__STACKED_VLAN__RESERVED_30_16__READ(src) \
6875                     (((uint32_t)(src)\
6876                     & 0x7fff0000U) >> 16)
6877 
6878 /* macros for field enable_processing */
6879 #define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__SHIFT                    31
6880 #define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__WIDTH                     1
6881 #define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__MASK            0x80000000U
6882 #define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__RESET                     0
6883 #define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__READ(src) \
6884                     (((uint32_t)(src)\
6885                     & 0x80000000U) >> 31)
6886 #define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__WRITE(src) \
6887                     (((uint32_t)(src)\
6888                     << 31) & 0x80000000U)
6889 #define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__MODIFY(dst, src) \
6890                     (dst) = ((dst) &\
6891                     ~0x80000000U) | (((uint32_t)(src) <<\
6892                     31) & 0x80000000U)
6893 #define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__VERIFY(src) \
6894                     (!((((uint32_t)(src)\
6895                     << 31) & ~0x80000000U)))
6896 #define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__SET(dst) \
6897                     (dst) = ((dst) &\
6898                     ~0x80000000U) | ((uint32_t)(1) << 31)
6899 #define EMAC_REGS__STACKED_VLAN__ENABLE_PROCESSING__CLR(dst) \
6900                     (dst) = ((dst) &\
6901                     ~0x80000000U) | ((uint32_t)(0) << 31)
6902 #define EMAC_REGS__STACKED_VLAN__TYPE                                  uint32_t
6903 #define EMAC_REGS__STACKED_VLAN__READ                               0xffffffffU
6904 #define EMAC_REGS__STACKED_VLAN__WRITE                              0xffffffffU
6905 
6906 #endif /* __EMAC_REGS__STACKED_VLAN_MACRO__ */
6907 
6908 
6909 /* macros for stacked_vlan */
6910 #define INST_STACKED_VLAN__NUM                                                1
6911 
6912 /* macros for BlueprintGlobalNameSpace::emac_regs::tx_pfc_pause */
6913 #ifndef __EMAC_REGS__TX_PFC_PAUSE_MACRO__
6914 #define __EMAC_REGS__TX_PFC_PAUSE_MACRO__
6915 
6916 /* macros for field vector_enable */
6917 #define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__SHIFT                         0
6918 #define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__WIDTH                         8
6919 #define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__MASK                0x000000ffU
6920 #define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__RESET                         0
6921 #define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__READ(src) \
6922                     ((uint32_t)(src)\
6923                     & 0x000000ffU)
6924 #define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__WRITE(src) \
6925                     ((uint32_t)(src)\
6926                     & 0x000000ffU)
6927 #define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__MODIFY(dst, src) \
6928                     (dst) = ((dst) &\
6929                     ~0x000000ffU) | ((uint32_t)(src) &\
6930                     0x000000ffU)
6931 #define EMAC_REGS__TX_PFC_PAUSE__VECTOR_ENABLE__VERIFY(src) \
6932                     (!(((uint32_t)(src)\
6933                     & ~0x000000ffU)))
6934 
6935 /* macros for field vector */
6936 #define EMAC_REGS__TX_PFC_PAUSE__VECTOR__SHIFT                                8
6937 #define EMAC_REGS__TX_PFC_PAUSE__VECTOR__WIDTH                                8
6938 #define EMAC_REGS__TX_PFC_PAUSE__VECTOR__MASK                       0x0000ff00U
6939 #define EMAC_REGS__TX_PFC_PAUSE__VECTOR__RESET                                0
6940 #define EMAC_REGS__TX_PFC_PAUSE__VECTOR__READ(src) \
6941                     (((uint32_t)(src)\
6942                     & 0x0000ff00U) >> 8)
6943 #define EMAC_REGS__TX_PFC_PAUSE__VECTOR__WRITE(src) \
6944                     (((uint32_t)(src)\
6945                     << 8) & 0x0000ff00U)
6946 #define EMAC_REGS__TX_PFC_PAUSE__VECTOR__MODIFY(dst, src) \
6947                     (dst) = ((dst) &\
6948                     ~0x0000ff00U) | (((uint32_t)(src) <<\
6949                     8) & 0x0000ff00U)
6950 #define EMAC_REGS__TX_PFC_PAUSE__VECTOR__VERIFY(src) \
6951                     (!((((uint32_t)(src)\
6952                     << 8) & ~0x0000ff00U)))
6953 
6954 /* macros for field reserved_31_16 */
6955 #define EMAC_REGS__TX_PFC_PAUSE__RESERVED_31_16__SHIFT                       16
6956 #define EMAC_REGS__TX_PFC_PAUSE__RESERVED_31_16__WIDTH                       16
6957 #define EMAC_REGS__TX_PFC_PAUSE__RESERVED_31_16__MASK               0xffff0000U
6958 #define EMAC_REGS__TX_PFC_PAUSE__RESERVED_31_16__RESET                        0
6959 #define EMAC_REGS__TX_PFC_PAUSE__RESERVED_31_16__READ(src) \
6960                     (((uint32_t)(src)\
6961                     & 0xffff0000U) >> 16)
6962 #define EMAC_REGS__TX_PFC_PAUSE__TYPE                                  uint32_t
6963 #define EMAC_REGS__TX_PFC_PAUSE__READ                               0xffffffffU
6964 #define EMAC_REGS__TX_PFC_PAUSE__WRITE                              0xffffffffU
6965 
6966 #endif /* __EMAC_REGS__TX_PFC_PAUSE_MACRO__ */
6967 
6968 
6969 /* macros for tx_pfc_pause */
6970 #define INST_TX_PFC_PAUSE__NUM                                                1
6971 
6972 /* macros for BlueprintGlobalNameSpace::emac_regs::mask_add1_bottom */
6973 #ifndef __EMAC_REGS__MASK_ADD1_BOTTOM_MACRO__
6974 #define __EMAC_REGS__MASK_ADD1_BOTTOM_MACRO__
6975 
6976 /* macros for field address_mask */
6977 #define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__SHIFT                      0
6978 #define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__WIDTH                     32
6979 #define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__MASK             0xffffffffU
6980 #define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__RESET                      0
6981 #define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__READ(src) \
6982                     ((uint32_t)(src)\
6983                     & 0xffffffffU)
6984 #define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__WRITE(src) \
6985                     ((uint32_t)(src)\
6986                     & 0xffffffffU)
6987 #define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__MODIFY(dst, src) \
6988                     (dst) = ((dst) &\
6989                     ~0xffffffffU) | ((uint32_t)(src) &\
6990                     0xffffffffU)
6991 #define EMAC_REGS__MASK_ADD1_BOTTOM__ADDRESS_MASK__VERIFY(src) \
6992                     (!(((uint32_t)(src)\
6993                     & ~0xffffffffU)))
6994 #define EMAC_REGS__MASK_ADD1_BOTTOM__TYPE                              uint32_t
6995 #define EMAC_REGS__MASK_ADD1_BOTTOM__READ                           0xffffffffU
6996 #define EMAC_REGS__MASK_ADD1_BOTTOM__WRITE                          0xffffffffU
6997 
6998 #endif /* __EMAC_REGS__MASK_ADD1_BOTTOM_MACRO__ */
6999 
7000 
7001 /* macros for mask_add1_bottom */
7002 #define INST_MASK_ADD1_BOTTOM__NUM                                            1
7003 
7004 /* macros for BlueprintGlobalNameSpace::emac_regs::mask_add1_top */
7005 #ifndef __EMAC_REGS__MASK_ADD1_TOP_MACRO__
7006 #define __EMAC_REGS__MASK_ADD1_TOP_MACRO__
7007 
7008 /* macros for field address_mask */
7009 #define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__SHIFT                         0
7010 #define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__WIDTH                        16
7011 #define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__MASK                0x0000ffffU
7012 #define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__RESET                         0
7013 #define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__READ(src) \
7014                     ((uint32_t)(src)\
7015                     & 0x0000ffffU)
7016 #define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__WRITE(src) \
7017                     ((uint32_t)(src)\
7018                     & 0x0000ffffU)
7019 #define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__MODIFY(dst, src) \
7020                     (dst) = ((dst) &\
7021                     ~0x0000ffffU) | ((uint32_t)(src) &\
7022                     0x0000ffffU)
7023 #define EMAC_REGS__MASK_ADD1_TOP__ADDRESS_MASK__VERIFY(src) \
7024                     (!(((uint32_t)(src)\
7025                     & ~0x0000ffffU)))
7026 
7027 /* macros for field reserved_31_16 */
7028 #define EMAC_REGS__MASK_ADD1_TOP__RESERVED_31_16__SHIFT                      16
7029 #define EMAC_REGS__MASK_ADD1_TOP__RESERVED_31_16__WIDTH                      16
7030 #define EMAC_REGS__MASK_ADD1_TOP__RESERVED_31_16__MASK              0xffff0000U
7031 #define EMAC_REGS__MASK_ADD1_TOP__RESERVED_31_16__RESET                       0
7032 #define EMAC_REGS__MASK_ADD1_TOP__RESERVED_31_16__READ(src) \
7033                     (((uint32_t)(src)\
7034                     & 0xffff0000U) >> 16)
7035 #define EMAC_REGS__MASK_ADD1_TOP__TYPE                                 uint32_t
7036 #define EMAC_REGS__MASK_ADD1_TOP__READ                              0xffffffffU
7037 #define EMAC_REGS__MASK_ADD1_TOP__WRITE                             0xffffffffU
7038 
7039 #endif /* __EMAC_REGS__MASK_ADD1_TOP_MACRO__ */
7040 
7041 
7042 /* macros for mask_add1_top */
7043 #define INST_MASK_ADD1_TOP__NUM                                               1
7044 
7045 /* macros for BlueprintGlobalNameSpace::emac_regs::dma_addr_or_mask */
7046 #ifndef __EMAC_REGS__DMA_ADDR_OR_MASK_MACRO__
7047 #define __EMAC_REGS__DMA_ADDR_OR_MASK_MACRO__
7048 
7049 /* macros for field mask_enable */
7050 #define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__SHIFT                       0
7051 #define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__WIDTH                       4
7052 #define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__MASK              0x0000000fU
7053 #define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__RESET                       0
7054 #define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__READ(src) \
7055                     ((uint32_t)(src)\
7056                     & 0x0000000fU)
7057 #define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__WRITE(src) \
7058                     ((uint32_t)(src)\
7059                     & 0x0000000fU)
7060 #define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__MODIFY(dst, src) \
7061                     (dst) = ((dst) &\
7062                     ~0x0000000fU) | ((uint32_t)(src) &\
7063                     0x0000000fU)
7064 #define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_ENABLE__VERIFY(src) \
7065                     (!(((uint32_t)(src)\
7066                     & ~0x0000000fU)))
7067 
7068 /* macros for field reserved_27_4 */
7069 #define EMAC_REGS__DMA_ADDR_OR_MASK__RESERVED_27_4__SHIFT                     4
7070 #define EMAC_REGS__DMA_ADDR_OR_MASK__RESERVED_27_4__WIDTH                    24
7071 #define EMAC_REGS__DMA_ADDR_OR_MASK__RESERVED_27_4__MASK            0x0ffffff0U
7072 #define EMAC_REGS__DMA_ADDR_OR_MASK__RESERVED_27_4__RESET                     0
7073 #define EMAC_REGS__DMA_ADDR_OR_MASK__RESERVED_27_4__READ(src) \
7074                     (((uint32_t)(src)\
7075                     & 0x0ffffff0U) >> 4)
7076 
7077 /* macros for field mask_value */
7078 #define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__SHIFT                       28
7079 #define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__WIDTH                        4
7080 #define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__MASK               0xf0000000U
7081 #define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__RESET                        0
7082 #define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__READ(src) \
7083                     (((uint32_t)(src)\
7084                     & 0xf0000000U) >> 28)
7085 #define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__WRITE(src) \
7086                     (((uint32_t)(src)\
7087                     << 28) & 0xf0000000U)
7088 #define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__MODIFY(dst, src) \
7089                     (dst) = ((dst) &\
7090                     ~0xf0000000U) | (((uint32_t)(src) <<\
7091                     28) & 0xf0000000U)
7092 #define EMAC_REGS__DMA_ADDR_OR_MASK__MASK_VALUE__VERIFY(src) \
7093                     (!((((uint32_t)(src)\
7094                     << 28) & ~0xf0000000U)))
7095 #define EMAC_REGS__DMA_ADDR_OR_MASK__TYPE                              uint32_t
7096 #define EMAC_REGS__DMA_ADDR_OR_MASK__READ                           0xffffffffU
7097 #define EMAC_REGS__DMA_ADDR_OR_MASK__WRITE                          0xffffffffU
7098 
7099 #endif /* __EMAC_REGS__DMA_ADDR_OR_MASK_MACRO__ */
7100 
7101 
7102 /* macros for dma_addr_or_mask */
7103 #define INST_DMA_ADDR_OR_MASK__NUM                                            1
7104 
7105 /* macros for BlueprintGlobalNameSpace::emac_regs::rx_ptp_unicast */
7106 #ifndef __EMAC_REGS__RX_PTP_UNICAST_MACRO__
7107 #define __EMAC_REGS__RX_PTP_UNICAST_MACRO__
7108 
7109 /* macros for field address */
7110 #define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__SHIFT                             0
7111 #define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__WIDTH                            32
7112 #define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__MASK                    0xffffffffU
7113 #define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__RESET                             0
7114 #define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__READ(src) \
7115                     ((uint32_t)(src)\
7116                     & 0xffffffffU)
7117 #define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__WRITE(src) \
7118                     ((uint32_t)(src)\
7119                     & 0xffffffffU)
7120 #define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__MODIFY(dst, src) \
7121                     (dst) = ((dst) &\
7122                     ~0xffffffffU) | ((uint32_t)(src) &\
7123                     0xffffffffU)
7124 #define EMAC_REGS__RX_PTP_UNICAST__ADDRESS__VERIFY(src) \
7125                     (!(((uint32_t)(src)\
7126                     & ~0xffffffffU)))
7127 #define EMAC_REGS__RX_PTP_UNICAST__TYPE                                uint32_t
7128 #define EMAC_REGS__RX_PTP_UNICAST__READ                             0xffffffffU
7129 #define EMAC_REGS__RX_PTP_UNICAST__WRITE                            0xffffffffU
7130 
7131 #endif /* __EMAC_REGS__RX_PTP_UNICAST_MACRO__ */
7132 
7133 
7134 /* macros for rx_ptp_unicast */
7135 #define INST_RX_PTP_UNICAST__NUM                                              1
7136 
7137 /* macros for BlueprintGlobalNameSpace::emac_regs::tx_ptp_unicast */
7138 #ifndef __EMAC_REGS__TX_PTP_UNICAST_MACRO__
7139 #define __EMAC_REGS__TX_PTP_UNICAST_MACRO__
7140 
7141 /* macros for field address */
7142 #define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__SHIFT                             0
7143 #define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__WIDTH                            32
7144 #define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__MASK                    0xffffffffU
7145 #define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__RESET                             0
7146 #define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__READ(src) \
7147                     ((uint32_t)(src)\
7148                     & 0xffffffffU)
7149 #define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__WRITE(src) \
7150                     ((uint32_t)(src)\
7151                     & 0xffffffffU)
7152 #define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__MODIFY(dst, src) \
7153                     (dst) = ((dst) &\
7154                     ~0xffffffffU) | ((uint32_t)(src) &\
7155                     0xffffffffU)
7156 #define EMAC_REGS__TX_PTP_UNICAST__ADDRESS__VERIFY(src) \
7157                     (!(((uint32_t)(src)\
7158                     & ~0xffffffffU)))
7159 #define EMAC_REGS__TX_PTP_UNICAST__TYPE                                uint32_t
7160 #define EMAC_REGS__TX_PTP_UNICAST__READ                             0xffffffffU
7161 #define EMAC_REGS__TX_PTP_UNICAST__WRITE                            0xffffffffU
7162 
7163 #endif /* __EMAC_REGS__TX_PTP_UNICAST_MACRO__ */
7164 
7165 
7166 /* macros for tx_ptp_unicast */
7167 #define INST_TX_PTP_UNICAST__NUM                                              1
7168 
7169 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_nsec_cmp */
7170 #ifndef __EMAC_REGS__TSU_NSEC_CMP_MACRO__
7171 #define __EMAC_REGS__TSU_NSEC_CMP_MACRO__
7172 
7173 /* macros for field comparison_value */
7174 #define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__SHIFT                      0
7175 #define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__WIDTH                     22
7176 #define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__MASK             0x003fffffU
7177 #define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__RESET                      0
7178 #define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__READ(src) \
7179                     ((uint32_t)(src)\
7180                     & 0x003fffffU)
7181 #define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__WRITE(src) \
7182                     ((uint32_t)(src)\
7183                     & 0x003fffffU)
7184 #define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__MODIFY(dst, src) \
7185                     (dst) = ((dst) &\
7186                     ~0x003fffffU) | ((uint32_t)(src) &\
7187                     0x003fffffU)
7188 #define EMAC_REGS__TSU_NSEC_CMP__COMPARISON_VALUE__VERIFY(src) \
7189                     (!(((uint32_t)(src)\
7190                     & ~0x003fffffU)))
7191 
7192 /* macros for field reserved_31_22 */
7193 #define EMAC_REGS__TSU_NSEC_CMP__RESERVED_31_22__SHIFT                       22
7194 #define EMAC_REGS__TSU_NSEC_CMP__RESERVED_31_22__WIDTH                       10
7195 #define EMAC_REGS__TSU_NSEC_CMP__RESERVED_31_22__MASK               0xffc00000U
7196 #define EMAC_REGS__TSU_NSEC_CMP__RESERVED_31_22__RESET                        0
7197 #define EMAC_REGS__TSU_NSEC_CMP__RESERVED_31_22__READ(src) \
7198                     (((uint32_t)(src)\
7199                     & 0xffc00000U) >> 22)
7200 #define EMAC_REGS__TSU_NSEC_CMP__TYPE                                  uint32_t
7201 #define EMAC_REGS__TSU_NSEC_CMP__READ                               0xffffffffU
7202 #define EMAC_REGS__TSU_NSEC_CMP__WRITE                              0xffffffffU
7203 
7204 #endif /* __EMAC_REGS__TSU_NSEC_CMP_MACRO__ */
7205 
7206 
7207 /* macros for tsu_nsec_cmp */
7208 #define INST_TSU_NSEC_CMP__NUM                                                1
7209 
7210 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_sec_cmp */
7211 #ifndef __EMAC_REGS__TSU_SEC_CMP_MACRO__
7212 #define __EMAC_REGS__TSU_SEC_CMP_MACRO__
7213 
7214 /* macros for field comparison_value */
7215 #define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__SHIFT                       0
7216 #define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__WIDTH                      32
7217 #define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__MASK              0xffffffffU
7218 #define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__RESET                       0
7219 #define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__READ(src) \
7220                     ((uint32_t)(src)\
7221                     & 0xffffffffU)
7222 #define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__WRITE(src) \
7223                     ((uint32_t)(src)\
7224                     & 0xffffffffU)
7225 #define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__MODIFY(dst, src) \
7226                     (dst) = ((dst) &\
7227                     ~0xffffffffU) | ((uint32_t)(src) &\
7228                     0xffffffffU)
7229 #define EMAC_REGS__TSU_SEC_CMP__COMPARISON_VALUE__VERIFY(src) \
7230                     (!(((uint32_t)(src)\
7231                     & ~0xffffffffU)))
7232 #define EMAC_REGS__TSU_SEC_CMP__TYPE                                   uint32_t
7233 #define EMAC_REGS__TSU_SEC_CMP__READ                                0xffffffffU
7234 #define EMAC_REGS__TSU_SEC_CMP__WRITE                               0xffffffffU
7235 
7236 #endif /* __EMAC_REGS__TSU_SEC_CMP_MACRO__ */
7237 
7238 
7239 /* macros for tsu_sec_cmp */
7240 #define INST_TSU_SEC_CMP__NUM                                                 1
7241 
7242 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_msb_sec_cmp */
7243 #ifndef __EMAC_REGS__TSU_MSB_SEC_CMP_MACRO__
7244 #define __EMAC_REGS__TSU_MSB_SEC_CMP_MACRO__
7245 
7246 /* macros for field comparison_value */
7247 #define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__SHIFT                   0
7248 #define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__WIDTH                  16
7249 #define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__MASK          0x0000ffffU
7250 #define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__RESET                   0
7251 #define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__READ(src) \
7252                     ((uint32_t)(src)\
7253                     & 0x0000ffffU)
7254 #define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__WRITE(src) \
7255                     ((uint32_t)(src)\
7256                     & 0x0000ffffU)
7257 #define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__MODIFY(dst, src) \
7258                     (dst) = ((dst) &\
7259                     ~0x0000ffffU) | ((uint32_t)(src) &\
7260                     0x0000ffffU)
7261 #define EMAC_REGS__TSU_MSB_SEC_CMP__COMPARISON_VALUE__VERIFY(src) \
7262                     (!(((uint32_t)(src)\
7263                     & ~0x0000ffffU)))
7264 
7265 /* macros for field reserved_31_16 */
7266 #define EMAC_REGS__TSU_MSB_SEC_CMP__RESERVED_31_16__SHIFT                    16
7267 #define EMAC_REGS__TSU_MSB_SEC_CMP__RESERVED_31_16__WIDTH                    16
7268 #define EMAC_REGS__TSU_MSB_SEC_CMP__RESERVED_31_16__MASK            0xffff0000U
7269 #define EMAC_REGS__TSU_MSB_SEC_CMP__RESERVED_31_16__RESET                     0
7270 #define EMAC_REGS__TSU_MSB_SEC_CMP__RESERVED_31_16__READ(src) \
7271                     (((uint32_t)(src)\
7272                     & 0xffff0000U) >> 16)
7273 #define EMAC_REGS__TSU_MSB_SEC_CMP__TYPE                               uint32_t
7274 #define EMAC_REGS__TSU_MSB_SEC_CMP__READ                            0xffffffffU
7275 #define EMAC_REGS__TSU_MSB_SEC_CMP__WRITE                           0xffffffffU
7276 
7277 #endif /* __EMAC_REGS__TSU_MSB_SEC_CMP_MACRO__ */
7278 
7279 
7280 /* macros for tsu_msb_sec_cmp */
7281 #define INST_TSU_MSB_SEC_CMP__NUM                                             1
7282 
7283 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_ptp_tx_msb_sec */
7284 #ifndef __EMAC_REGS__TSU_PTP_TX_MSB_SEC_MACRO__
7285 #define __EMAC_REGS__TSU_PTP_TX_MSB_SEC_MACRO__
7286 
7287 /* macros for field timer_seconds */
7288 #define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TIMER_SECONDS__SHIFT                   0
7289 #define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TIMER_SECONDS__WIDTH                  16
7290 #define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TIMER_SECONDS__MASK          0x0000ffffU
7291 #define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TIMER_SECONDS__RESET                   0
7292 #define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TIMER_SECONDS__READ(src) \
7293                     ((uint32_t)(src)\
7294                     & 0x0000ffffU)
7295 
7296 /* macros for field reserved_31_16 */
7297 #define EMAC_REGS__TSU_PTP_TX_MSB_SEC__RESERVED_31_16__SHIFT                 16
7298 #define EMAC_REGS__TSU_PTP_TX_MSB_SEC__RESERVED_31_16__WIDTH                 16
7299 #define EMAC_REGS__TSU_PTP_TX_MSB_SEC__RESERVED_31_16__MASK         0xffff0000U
7300 #define EMAC_REGS__TSU_PTP_TX_MSB_SEC__RESERVED_31_16__RESET                  0
7301 #define EMAC_REGS__TSU_PTP_TX_MSB_SEC__RESERVED_31_16__READ(src) \
7302                     (((uint32_t)(src)\
7303                     & 0xffff0000U) >> 16)
7304 #define EMAC_REGS__TSU_PTP_TX_MSB_SEC__TYPE                            uint32_t
7305 #define EMAC_REGS__TSU_PTP_TX_MSB_SEC__READ                         0xffffffffU
7306 
7307 #endif /* __EMAC_REGS__TSU_PTP_TX_MSB_SEC_MACRO__ */
7308 
7309 
7310 /* macros for tsu_ptp_tx_msb_sec */
7311 #define INST_TSU_PTP_TX_MSB_SEC__NUM                                          1
7312 
7313 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_ptp_rx_msb_sec */
7314 #ifndef __EMAC_REGS__TSU_PTP_RX_MSB_SEC_MACRO__
7315 #define __EMAC_REGS__TSU_PTP_RX_MSB_SEC_MACRO__
7316 
7317 /* macros for field timer_seconds */
7318 #define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TIMER_SECONDS__SHIFT                   0
7319 #define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TIMER_SECONDS__WIDTH                  16
7320 #define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TIMER_SECONDS__MASK          0x0000ffffU
7321 #define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TIMER_SECONDS__RESET                   0
7322 #define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TIMER_SECONDS__READ(src) \
7323                     ((uint32_t)(src)\
7324                     & 0x0000ffffU)
7325 
7326 /* macros for field reserved_31_16 */
7327 #define EMAC_REGS__TSU_PTP_RX_MSB_SEC__RESERVED_31_16__SHIFT                 16
7328 #define EMAC_REGS__TSU_PTP_RX_MSB_SEC__RESERVED_31_16__WIDTH                 16
7329 #define EMAC_REGS__TSU_PTP_RX_MSB_SEC__RESERVED_31_16__MASK         0xffff0000U
7330 #define EMAC_REGS__TSU_PTP_RX_MSB_SEC__RESERVED_31_16__RESET                  0
7331 #define EMAC_REGS__TSU_PTP_RX_MSB_SEC__RESERVED_31_16__READ(src) \
7332                     (((uint32_t)(src)\
7333                     & 0xffff0000U) >> 16)
7334 #define EMAC_REGS__TSU_PTP_RX_MSB_SEC__TYPE                            uint32_t
7335 #define EMAC_REGS__TSU_PTP_RX_MSB_SEC__READ                         0xffffffffU
7336 
7337 #endif /* __EMAC_REGS__TSU_PTP_RX_MSB_SEC_MACRO__ */
7338 
7339 
7340 /* macros for tsu_ptp_rx_msb_sec */
7341 #define INST_TSU_PTP_RX_MSB_SEC__NUM                                          1
7342 
7343 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_peer_tx_msb_sec */
7344 #ifndef __EMAC_REGS__TSU_PEER_TX_MSB_SEC_MACRO__
7345 #define __EMAC_REGS__TSU_PEER_TX_MSB_SEC_MACRO__
7346 
7347 /* macros for field timer_seconds */
7348 #define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TIMER_SECONDS__SHIFT                  0
7349 #define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TIMER_SECONDS__WIDTH                 16
7350 #define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TIMER_SECONDS__MASK         0x0000ffffU
7351 #define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TIMER_SECONDS__RESET                  0
7352 #define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TIMER_SECONDS__READ(src) \
7353                     ((uint32_t)(src)\
7354                     & 0x0000ffffU)
7355 
7356 /* macros for field reserved_31_16 */
7357 #define EMAC_REGS__TSU_PEER_TX_MSB_SEC__RESERVED_31_16__SHIFT                16
7358 #define EMAC_REGS__TSU_PEER_TX_MSB_SEC__RESERVED_31_16__WIDTH                16
7359 #define EMAC_REGS__TSU_PEER_TX_MSB_SEC__RESERVED_31_16__MASK        0xffff0000U
7360 #define EMAC_REGS__TSU_PEER_TX_MSB_SEC__RESERVED_31_16__RESET                 0
7361 #define EMAC_REGS__TSU_PEER_TX_MSB_SEC__RESERVED_31_16__READ(src) \
7362                     (((uint32_t)(src)\
7363                     & 0xffff0000U) >> 16)
7364 #define EMAC_REGS__TSU_PEER_TX_MSB_SEC__TYPE                           uint32_t
7365 #define EMAC_REGS__TSU_PEER_TX_MSB_SEC__READ                        0xffffffffU
7366 
7367 #endif /* __EMAC_REGS__TSU_PEER_TX_MSB_SEC_MACRO__ */
7368 
7369 
7370 /* macros for tsu_peer_tx_msb_sec */
7371 #define INST_TSU_PEER_TX_MSB_SEC__NUM                                         1
7372 
7373 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_peer_rx_msb_sec */
7374 #ifndef __EMAC_REGS__TSU_PEER_RX_MSB_SEC_MACRO__
7375 #define __EMAC_REGS__TSU_PEER_RX_MSB_SEC_MACRO__
7376 
7377 /* macros for field timer_seconds */
7378 #define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TIMER_SECONDS__SHIFT                  0
7379 #define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TIMER_SECONDS__WIDTH                 16
7380 #define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TIMER_SECONDS__MASK         0x0000ffffU
7381 #define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TIMER_SECONDS__RESET                  0
7382 #define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TIMER_SECONDS__READ(src) \
7383                     ((uint32_t)(src)\
7384                     & 0x0000ffffU)
7385 
7386 /* macros for field reserved_31_16 */
7387 #define EMAC_REGS__TSU_PEER_RX_MSB_SEC__RESERVED_31_16__SHIFT                16
7388 #define EMAC_REGS__TSU_PEER_RX_MSB_SEC__RESERVED_31_16__WIDTH                16
7389 #define EMAC_REGS__TSU_PEER_RX_MSB_SEC__RESERVED_31_16__MASK        0xffff0000U
7390 #define EMAC_REGS__TSU_PEER_RX_MSB_SEC__RESERVED_31_16__RESET                 0
7391 #define EMAC_REGS__TSU_PEER_RX_MSB_SEC__RESERVED_31_16__READ(src) \
7392                     (((uint32_t)(src)\
7393                     & 0xffff0000U) >> 16)
7394 #define EMAC_REGS__TSU_PEER_RX_MSB_SEC__TYPE                           uint32_t
7395 #define EMAC_REGS__TSU_PEER_RX_MSB_SEC__READ                        0xffffffffU
7396 
7397 #endif /* __EMAC_REGS__TSU_PEER_RX_MSB_SEC_MACRO__ */
7398 
7399 
7400 /* macros for tsu_peer_rx_msb_sec */
7401 #define INST_TSU_PEER_RX_MSB_SEC__NUM                                         1
7402 
7403 /* macros for BlueprintGlobalNameSpace::emac_regs::dpram_fill_dbg */
7404 #ifndef __EMAC_REGS__DPRAM_FILL_DBG_MACRO__
7405 #define __EMAC_REGS__DPRAM_FILL_DBG_MACRO__
7406 
7407 /* macros for field dma_tx_rx_fill_level_select */
7408 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__SHIFT         0
7409 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__WIDTH         1
7410 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__MASK \
7411                     0x00000001U
7412 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__RESET         0
7413 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__READ(src) \
7414                     ((uint32_t)(src)\
7415                     & 0x00000001U)
7416 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__WRITE(src) \
7417                     ((uint32_t)(src)\
7418                     & 0x00000001U)
7419 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__MODIFY(dst, src) \
7420                     (dst) = ((dst) &\
7421                     ~0x00000001U) | ((uint32_t)(src) &\
7422                     0x00000001U)
7423 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__VERIFY(src) \
7424                     (!(((uint32_t)(src)\
7425                     & ~0x00000001U)))
7426 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__SET(dst) \
7427                     (dst) = ((dst) &\
7428                     ~0x00000001U) | (uint32_t)(1)
7429 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL_SELECT__CLR(dst) \
7430                     (dst) = ((dst) &\
7431                     ~0x00000001U) | (uint32_t)(0)
7432 
7433 /* macros for field reserved_3_1 */
7434 #define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_3_1__SHIFT                        1
7435 #define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_3_1__WIDTH                        3
7436 #define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_3_1__MASK               0x0000000eU
7437 #define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_3_1__RESET                        0
7438 #define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_3_1__READ(src) \
7439                     (((uint32_t)(src)\
7440                     & 0x0000000eU) >> 1)
7441 
7442 /* macros for field dma_tx_q_fill_level_select */
7443 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__SHIFT          4
7444 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__WIDTH          4
7445 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__MASK 0x000000f0U
7446 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__RESET          0
7447 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__READ(src) \
7448                     (((uint32_t)(src)\
7449                     & 0x000000f0U) >> 4)
7450 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__WRITE(src) \
7451                     (((uint32_t)(src)\
7452                     << 4) & 0x000000f0U)
7453 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__MODIFY(dst, src) \
7454                     (dst) = ((dst) &\
7455                     ~0x000000f0U) | (((uint32_t)(src) <<\
7456                     4) & 0x000000f0U)
7457 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_Q_FILL_LEVEL_SELECT__VERIFY(src) \
7458                     (!((((uint32_t)(src)\
7459                     << 4) & ~0x000000f0U)))
7460 
7461 /* macros for field reserved_15_8 */
7462 #define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_15_8__SHIFT                       8
7463 #define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_15_8__WIDTH                       8
7464 #define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_15_8__MASK              0x0000ff00U
7465 #define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_15_8__RESET                       0
7466 #define EMAC_REGS__DPRAM_FILL_DBG__RESERVED_15_8__READ(src) \
7467                     (((uint32_t)(src)\
7468                     & 0x0000ff00U) >> 8)
7469 
7470 /* macros for field dma_tx_rx_fill_level */
7471 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL__SHIFT               16
7472 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL__WIDTH               16
7473 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL__MASK       0xffff0000U
7474 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL__RESET                0
7475 #define EMAC_REGS__DPRAM_FILL_DBG__DMA_TX_RX_FILL_LEVEL__READ(src) \
7476                     (((uint32_t)(src)\
7477                     & 0xffff0000U) >> 16)
7478 #define EMAC_REGS__DPRAM_FILL_DBG__TYPE                                uint32_t
7479 #define EMAC_REGS__DPRAM_FILL_DBG__READ                             0xffffffffU
7480 #define EMAC_REGS__DPRAM_FILL_DBG__WRITE                            0xffffffffU
7481 
7482 #endif /* __EMAC_REGS__DPRAM_FILL_DBG_MACRO__ */
7483 
7484 
7485 /* macros for dpram_fill_dbg */
7486 #define INST_DPRAM_FILL_DBG__NUM                                              1
7487 
7488 /* macros for BlueprintGlobalNameSpace::emac_regs::revision_reg */
7489 #ifndef __EMAC_REGS__REVISION_REG_MACRO__
7490 #define __EMAC_REGS__REVISION_REG_MACRO__
7491 
7492 /* macros for field module_revision */
7493 #define EMAC_REGS__REVISION_REG__MODULE_REVISION__SHIFT                       0
7494 #define EMAC_REGS__REVISION_REG__MODULE_REVISION__WIDTH                      16
7495 #define EMAC_REGS__REVISION_REG__MODULE_REVISION__MASK              0x0000ffffU
7496 #define EMAC_REGS__REVISION_REG__MODULE_REVISION__RESET                     265
7497 #define EMAC_REGS__REVISION_REG__MODULE_REVISION__READ(src) \
7498                     ((uint32_t)(src)\
7499                     & 0x0000ffffU)
7500 
7501 /* macros for field module_identification_number */
7502 #define EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__SHIFT         16
7503 #define EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__WIDTH         12
7504 #define EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__MASK 0x0fff0000U
7505 #define EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__RESET        263
7506 #define EMAC_REGS__REVISION_REG__MODULE_IDENTIFICATION_NUMBER__READ(src) \
7507                     (((uint32_t)(src)\
7508                     & 0x0fff0000U) >> 16)
7509 
7510 /* macros for field fix_number */
7511 #define EMAC_REGS__REVISION_REG__FIX_NUMBER__SHIFT                           28
7512 #define EMAC_REGS__REVISION_REG__FIX_NUMBER__WIDTH                            4
7513 #define EMAC_REGS__REVISION_REG__FIX_NUMBER__MASK                   0xf0000000U
7514 #define EMAC_REGS__REVISION_REG__FIX_NUMBER__RESET                            0
7515 #define EMAC_REGS__REVISION_REG__FIX_NUMBER__READ(src) \
7516                     (((uint32_t)(src)\
7517                     & 0xf0000000U) >> 28)
7518 #define EMAC_REGS__REVISION_REG__TYPE                                  uint32_t
7519 #define EMAC_REGS__REVISION_REG__READ                               0xffffffffU
7520 
7521 #endif /* __EMAC_REGS__REVISION_REG_MACRO__ */
7522 
7523 
7524 /* macros for revision_reg */
7525 #define INST_REVISION_REG__NUM                                                1
7526 
7527 /* macros for BlueprintGlobalNameSpace::emac_regs::octets_txed_bottom */
7528 #ifndef __EMAC_REGS__OCTETS_TXED_BOTTOM_MACRO__
7529 #define __EMAC_REGS__OCTETS_TXED_BOTTOM_MACRO__
7530 
7531 /* macros for field count */
7532 #define EMAC_REGS__OCTETS_TXED_BOTTOM__COUNT__SHIFT                           0
7533 #define EMAC_REGS__OCTETS_TXED_BOTTOM__COUNT__WIDTH                          32
7534 #define EMAC_REGS__OCTETS_TXED_BOTTOM__COUNT__MASK                  0xffffffffU
7535 #define EMAC_REGS__OCTETS_TXED_BOTTOM__COUNT__RESET                           0
7536 #define EMAC_REGS__OCTETS_TXED_BOTTOM__COUNT__READ(src) \
7537                     ((uint32_t)(src)\
7538                     & 0xffffffffU)
7539 #define EMAC_REGS__OCTETS_TXED_BOTTOM__TYPE                            uint32_t
7540 #define EMAC_REGS__OCTETS_TXED_BOTTOM__READ                         0xffffffffU
7541 #define EMAC_REGS__OCTETS_TXED_BOTTOM__RCLR                         0xffffffffU
7542 
7543 #endif /* __EMAC_REGS__OCTETS_TXED_BOTTOM_MACRO__ */
7544 
7545 
7546 /* macros for octets_txed_bottom */
7547 #define INST_OCTETS_TXED_BOTTOM__NUM                                          1
7548 
7549 /* macros for BlueprintGlobalNameSpace::emac_regs::octets_txed_top */
7550 #ifndef __EMAC_REGS__OCTETS_TXED_TOP_MACRO__
7551 #define __EMAC_REGS__OCTETS_TXED_TOP_MACRO__
7552 
7553 /* macros for field count */
7554 #define EMAC_REGS__OCTETS_TXED_TOP__COUNT__SHIFT                              0
7555 #define EMAC_REGS__OCTETS_TXED_TOP__COUNT__WIDTH                             16
7556 #define EMAC_REGS__OCTETS_TXED_TOP__COUNT__MASK                     0x0000ffffU
7557 #define EMAC_REGS__OCTETS_TXED_TOP__COUNT__RESET                              0
7558 #define EMAC_REGS__OCTETS_TXED_TOP__COUNT__READ(src) \
7559                     ((uint32_t)(src)\
7560                     & 0x0000ffffU)
7561 
7562 /* macros for field reserved_31_16 */
7563 #define EMAC_REGS__OCTETS_TXED_TOP__RESERVED_31_16__SHIFT                    16
7564 #define EMAC_REGS__OCTETS_TXED_TOP__RESERVED_31_16__WIDTH                    16
7565 #define EMAC_REGS__OCTETS_TXED_TOP__RESERVED_31_16__MASK            0xffff0000U
7566 #define EMAC_REGS__OCTETS_TXED_TOP__RESERVED_31_16__RESET                     0
7567 #define EMAC_REGS__OCTETS_TXED_TOP__RESERVED_31_16__READ(src) \
7568                     (((uint32_t)(src)\
7569                     & 0xffff0000U) >> 16)
7570 #define EMAC_REGS__OCTETS_TXED_TOP__TYPE                               uint32_t
7571 #define EMAC_REGS__OCTETS_TXED_TOP__READ                            0xffffffffU
7572 #define EMAC_REGS__OCTETS_TXED_TOP__RCLR                            0x0000ffffU
7573 
7574 #endif /* __EMAC_REGS__OCTETS_TXED_TOP_MACRO__ */
7575 
7576 
7577 /* macros for octets_txed_top */
7578 #define INST_OCTETS_TXED_TOP__NUM                                             1
7579 
7580 /* macros for BlueprintGlobalNameSpace::emac_regs::frames_txed_ok */
7581 #ifndef __EMAC_REGS__FRAMES_TXED_OK_MACRO__
7582 #define __EMAC_REGS__FRAMES_TXED_OK_MACRO__
7583 
7584 /* macros for field count */
7585 #define EMAC_REGS__FRAMES_TXED_OK__COUNT__SHIFT                               0
7586 #define EMAC_REGS__FRAMES_TXED_OK__COUNT__WIDTH                              32
7587 #define EMAC_REGS__FRAMES_TXED_OK__COUNT__MASK                      0xffffffffU
7588 #define EMAC_REGS__FRAMES_TXED_OK__COUNT__RESET                               0
7589 #define EMAC_REGS__FRAMES_TXED_OK__COUNT__READ(src) \
7590                     ((uint32_t)(src)\
7591                     & 0xffffffffU)
7592 #define EMAC_REGS__FRAMES_TXED_OK__TYPE                                uint32_t
7593 #define EMAC_REGS__FRAMES_TXED_OK__READ                             0xffffffffU
7594 #define EMAC_REGS__FRAMES_TXED_OK__RCLR                             0xffffffffU
7595 
7596 #endif /* __EMAC_REGS__FRAMES_TXED_OK_MACRO__ */
7597 
7598 
7599 /* macros for frames_txed_ok */
7600 #define INST_FRAMES_TXED_OK__NUM                                              1
7601 
7602 /* macros for BlueprintGlobalNameSpace::emac_regs::broadcast_txed */
7603 #ifndef __EMAC_REGS__BROADCAST_TXED_MACRO__
7604 #define __EMAC_REGS__BROADCAST_TXED_MACRO__
7605 
7606 /* macros for field count */
7607 #define EMAC_REGS__BROADCAST_TXED__COUNT__SHIFT                               0
7608 #define EMAC_REGS__BROADCAST_TXED__COUNT__WIDTH                              32
7609 #define EMAC_REGS__BROADCAST_TXED__COUNT__MASK                      0xffffffffU
7610 #define EMAC_REGS__BROADCAST_TXED__COUNT__RESET                               0
7611 #define EMAC_REGS__BROADCAST_TXED__COUNT__READ(src) \
7612                     ((uint32_t)(src)\
7613                     & 0xffffffffU)
7614 #define EMAC_REGS__BROADCAST_TXED__TYPE                                uint32_t
7615 #define EMAC_REGS__BROADCAST_TXED__READ                             0xffffffffU
7616 #define EMAC_REGS__BROADCAST_TXED__RCLR                             0xffffffffU
7617 
7618 #endif /* __EMAC_REGS__BROADCAST_TXED_MACRO__ */
7619 
7620 
7621 /* macros for broadcast_txed */
7622 #define INST_BROADCAST_TXED__NUM                                              1
7623 
7624 /* macros for BlueprintGlobalNameSpace::emac_regs::multicast_txed */
7625 #ifndef __EMAC_REGS__MULTICAST_TXED_MACRO__
7626 #define __EMAC_REGS__MULTICAST_TXED_MACRO__
7627 
7628 /* macros for field count */
7629 #define EMAC_REGS__MULTICAST_TXED__COUNT__SHIFT                               0
7630 #define EMAC_REGS__MULTICAST_TXED__COUNT__WIDTH                              32
7631 #define EMAC_REGS__MULTICAST_TXED__COUNT__MASK                      0xffffffffU
7632 #define EMAC_REGS__MULTICAST_TXED__COUNT__RESET                               0
7633 #define EMAC_REGS__MULTICAST_TXED__COUNT__READ(src) \
7634                     ((uint32_t)(src)\
7635                     & 0xffffffffU)
7636 #define EMAC_REGS__MULTICAST_TXED__TYPE                                uint32_t
7637 #define EMAC_REGS__MULTICAST_TXED__READ                             0xffffffffU
7638 #define EMAC_REGS__MULTICAST_TXED__RCLR                             0xffffffffU
7639 
7640 #endif /* __EMAC_REGS__MULTICAST_TXED_MACRO__ */
7641 
7642 
7643 /* macros for multicast_txed */
7644 #define INST_MULTICAST_TXED__NUM                                              1
7645 
7646 /* macros for BlueprintGlobalNameSpace::emac_regs::pause_frames_txed */
7647 #ifndef __EMAC_REGS__PAUSE_FRAMES_TXED_MACRO__
7648 #define __EMAC_REGS__PAUSE_FRAMES_TXED_MACRO__
7649 
7650 /* macros for field count */
7651 #define EMAC_REGS__PAUSE_FRAMES_TXED__COUNT__SHIFT                            0
7652 #define EMAC_REGS__PAUSE_FRAMES_TXED__COUNT__WIDTH                           16
7653 #define EMAC_REGS__PAUSE_FRAMES_TXED__COUNT__MASK                   0x0000ffffU
7654 #define EMAC_REGS__PAUSE_FRAMES_TXED__COUNT__RESET                            0
7655 #define EMAC_REGS__PAUSE_FRAMES_TXED__COUNT__READ(src) \
7656                     ((uint32_t)(src)\
7657                     & 0x0000ffffU)
7658 
7659 /* macros for field reserved_31_16 */
7660 #define EMAC_REGS__PAUSE_FRAMES_TXED__RESERVED_31_16__SHIFT                  16
7661 #define EMAC_REGS__PAUSE_FRAMES_TXED__RESERVED_31_16__WIDTH                  16
7662 #define EMAC_REGS__PAUSE_FRAMES_TXED__RESERVED_31_16__MASK          0xffff0000U
7663 #define EMAC_REGS__PAUSE_FRAMES_TXED__RESERVED_31_16__RESET                   0
7664 #define EMAC_REGS__PAUSE_FRAMES_TXED__RESERVED_31_16__READ(src) \
7665                     (((uint32_t)(src)\
7666                     & 0xffff0000U) >> 16)
7667 #define EMAC_REGS__PAUSE_FRAMES_TXED__TYPE                             uint32_t
7668 #define EMAC_REGS__PAUSE_FRAMES_TXED__READ                          0xffffffffU
7669 #define EMAC_REGS__PAUSE_FRAMES_TXED__RCLR                          0x0000ffffU
7670 
7671 #endif /* __EMAC_REGS__PAUSE_FRAMES_TXED_MACRO__ */
7672 
7673 
7674 /* macros for pause_frames_txed */
7675 #define INST_PAUSE_FRAMES_TXED__NUM                                           1
7676 
7677 /* macros for BlueprintGlobalNameSpace::emac_regs::frames_txed_64 */
7678 #ifndef __EMAC_REGS__FRAMES_TXED_64_MACRO__
7679 #define __EMAC_REGS__FRAMES_TXED_64_MACRO__
7680 
7681 /* macros for field count */
7682 #define EMAC_REGS__FRAMES_TXED_64__COUNT__SHIFT                               0
7683 #define EMAC_REGS__FRAMES_TXED_64__COUNT__WIDTH                              32
7684 #define EMAC_REGS__FRAMES_TXED_64__COUNT__MASK                      0xffffffffU
7685 #define EMAC_REGS__FRAMES_TXED_64__COUNT__RESET                               0
7686 #define EMAC_REGS__FRAMES_TXED_64__COUNT__READ(src) \
7687                     ((uint32_t)(src)\
7688                     & 0xffffffffU)
7689 #define EMAC_REGS__FRAMES_TXED_64__TYPE                                uint32_t
7690 #define EMAC_REGS__FRAMES_TXED_64__READ                             0xffffffffU
7691 #define EMAC_REGS__FRAMES_TXED_64__RCLR                             0xffffffffU
7692 
7693 #endif /* __EMAC_REGS__FRAMES_TXED_64_MACRO__ */
7694 
7695 
7696 /* macros for frames_txed_64 */
7697 #define INST_FRAMES_TXED_64__NUM                                              1
7698 
7699 /* macros for BlueprintGlobalNameSpace::emac_regs::frames_txed_65 */
7700 #ifndef __EMAC_REGS__FRAMES_TXED_65_MACRO__
7701 #define __EMAC_REGS__FRAMES_TXED_65_MACRO__
7702 
7703 /* macros for field count */
7704 #define EMAC_REGS__FRAMES_TXED_65__COUNT__SHIFT                               0
7705 #define EMAC_REGS__FRAMES_TXED_65__COUNT__WIDTH                              32
7706 #define EMAC_REGS__FRAMES_TXED_65__COUNT__MASK                      0xffffffffU
7707 #define EMAC_REGS__FRAMES_TXED_65__COUNT__RESET                               0
7708 #define EMAC_REGS__FRAMES_TXED_65__COUNT__READ(src) \
7709                     ((uint32_t)(src)\
7710                     & 0xffffffffU)
7711 #define EMAC_REGS__FRAMES_TXED_65__TYPE                                uint32_t
7712 #define EMAC_REGS__FRAMES_TXED_65__READ                             0xffffffffU
7713 #define EMAC_REGS__FRAMES_TXED_65__RCLR                             0xffffffffU
7714 
7715 #endif /* __EMAC_REGS__FRAMES_TXED_65_MACRO__ */
7716 
7717 
7718 /* macros for frames_txed_65 */
7719 #define INST_FRAMES_TXED_65__NUM                                              1
7720 
7721 /* macros for BlueprintGlobalNameSpace::emac_regs::frames_txed_128 */
7722 #ifndef __EMAC_REGS__FRAMES_TXED_128_MACRO__
7723 #define __EMAC_REGS__FRAMES_TXED_128_MACRO__
7724 
7725 /* macros for field count */
7726 #define EMAC_REGS__FRAMES_TXED_128__COUNT__SHIFT                              0
7727 #define EMAC_REGS__FRAMES_TXED_128__COUNT__WIDTH                             32
7728 #define EMAC_REGS__FRAMES_TXED_128__COUNT__MASK                     0xffffffffU
7729 #define EMAC_REGS__FRAMES_TXED_128__COUNT__RESET                              0
7730 #define EMAC_REGS__FRAMES_TXED_128__COUNT__READ(src) \
7731                     ((uint32_t)(src)\
7732                     & 0xffffffffU)
7733 #define EMAC_REGS__FRAMES_TXED_128__TYPE                               uint32_t
7734 #define EMAC_REGS__FRAMES_TXED_128__READ                            0xffffffffU
7735 #define EMAC_REGS__FRAMES_TXED_128__RCLR                            0xffffffffU
7736 
7737 #endif /* __EMAC_REGS__FRAMES_TXED_128_MACRO__ */
7738 
7739 
7740 /* macros for frames_txed_128 */
7741 #define INST_FRAMES_TXED_128__NUM                                             1
7742 
7743 /* macros for BlueprintGlobalNameSpace::emac_regs::frames_txed_256 */
7744 #ifndef __EMAC_REGS__FRAMES_TXED_256_MACRO__
7745 #define __EMAC_REGS__FRAMES_TXED_256_MACRO__
7746 
7747 /* macros for field count */
7748 #define EMAC_REGS__FRAMES_TXED_256__COUNT__SHIFT                              0
7749 #define EMAC_REGS__FRAMES_TXED_256__COUNT__WIDTH                             32
7750 #define EMAC_REGS__FRAMES_TXED_256__COUNT__MASK                     0xffffffffU
7751 #define EMAC_REGS__FRAMES_TXED_256__COUNT__RESET                              0
7752 #define EMAC_REGS__FRAMES_TXED_256__COUNT__READ(src) \
7753                     ((uint32_t)(src)\
7754                     & 0xffffffffU)
7755 #define EMAC_REGS__FRAMES_TXED_256__TYPE                               uint32_t
7756 #define EMAC_REGS__FRAMES_TXED_256__READ                            0xffffffffU
7757 #define EMAC_REGS__FRAMES_TXED_256__RCLR                            0xffffffffU
7758 
7759 #endif /* __EMAC_REGS__FRAMES_TXED_256_MACRO__ */
7760 
7761 
7762 /* macros for frames_txed_256 */
7763 #define INST_FRAMES_TXED_256__NUM                                             1
7764 
7765 /* macros for BlueprintGlobalNameSpace::emac_regs::frames_txed_512 */
7766 #ifndef __EMAC_REGS__FRAMES_TXED_512_MACRO__
7767 #define __EMAC_REGS__FRAMES_TXED_512_MACRO__
7768 
7769 /* macros for field count */
7770 #define EMAC_REGS__FRAMES_TXED_512__COUNT__SHIFT                              0
7771 #define EMAC_REGS__FRAMES_TXED_512__COUNT__WIDTH                             32
7772 #define EMAC_REGS__FRAMES_TXED_512__COUNT__MASK                     0xffffffffU
7773 #define EMAC_REGS__FRAMES_TXED_512__COUNT__RESET                              0
7774 #define EMAC_REGS__FRAMES_TXED_512__COUNT__READ(src) \
7775                     ((uint32_t)(src)\
7776                     & 0xffffffffU)
7777 #define EMAC_REGS__FRAMES_TXED_512__TYPE                               uint32_t
7778 #define EMAC_REGS__FRAMES_TXED_512__READ                            0xffffffffU
7779 #define EMAC_REGS__FRAMES_TXED_512__RCLR                            0xffffffffU
7780 
7781 #endif /* __EMAC_REGS__FRAMES_TXED_512_MACRO__ */
7782 
7783 
7784 /* macros for frames_txed_512 */
7785 #define INST_FRAMES_TXED_512__NUM                                             1
7786 
7787 /* macros for BlueprintGlobalNameSpace::emac_regs::frames_txed_1024 */
7788 #ifndef __EMAC_REGS__FRAMES_TXED_1024_MACRO__
7789 #define __EMAC_REGS__FRAMES_TXED_1024_MACRO__
7790 
7791 /* macros for field count */
7792 #define EMAC_REGS__FRAMES_TXED_1024__COUNT__SHIFT                             0
7793 #define EMAC_REGS__FRAMES_TXED_1024__COUNT__WIDTH                            32
7794 #define EMAC_REGS__FRAMES_TXED_1024__COUNT__MASK                    0xffffffffU
7795 #define EMAC_REGS__FRAMES_TXED_1024__COUNT__RESET                             0
7796 #define EMAC_REGS__FRAMES_TXED_1024__COUNT__READ(src) \
7797                     ((uint32_t)(src)\
7798                     & 0xffffffffU)
7799 #define EMAC_REGS__FRAMES_TXED_1024__TYPE                              uint32_t
7800 #define EMAC_REGS__FRAMES_TXED_1024__READ                           0xffffffffU
7801 #define EMAC_REGS__FRAMES_TXED_1024__RCLR                           0xffffffffU
7802 
7803 #endif /* __EMAC_REGS__FRAMES_TXED_1024_MACRO__ */
7804 
7805 
7806 /* macros for frames_txed_1024 */
7807 #define INST_FRAMES_TXED_1024__NUM                                            1
7808 
7809 /* macros for BlueprintGlobalNameSpace::emac_regs::frames_txed_1519 */
7810 #ifndef __EMAC_REGS__FRAMES_TXED_1519_MACRO__
7811 #define __EMAC_REGS__FRAMES_TXED_1519_MACRO__
7812 
7813 /* macros for field count */
7814 #define EMAC_REGS__FRAMES_TXED_1519__COUNT__SHIFT                             0
7815 #define EMAC_REGS__FRAMES_TXED_1519__COUNT__WIDTH                            32
7816 #define EMAC_REGS__FRAMES_TXED_1519__COUNT__MASK                    0xffffffffU
7817 #define EMAC_REGS__FRAMES_TXED_1519__COUNT__RESET                             0
7818 #define EMAC_REGS__FRAMES_TXED_1519__COUNT__READ(src) \
7819                     ((uint32_t)(src)\
7820                     & 0xffffffffU)
7821 #define EMAC_REGS__FRAMES_TXED_1519__TYPE                              uint32_t
7822 #define EMAC_REGS__FRAMES_TXED_1519__READ                           0xffffffffU
7823 #define EMAC_REGS__FRAMES_TXED_1519__RCLR                           0xffffffffU
7824 
7825 #endif /* __EMAC_REGS__FRAMES_TXED_1519_MACRO__ */
7826 
7827 
7828 /* macros for frames_txed_1519 */
7829 #define INST_FRAMES_TXED_1519__NUM                                            1
7830 
7831 /* macros for BlueprintGlobalNameSpace::emac_regs::tx_underruns */
7832 #ifndef __EMAC_REGS__TX_UNDERRUNS_MACRO__
7833 #define __EMAC_REGS__TX_UNDERRUNS_MACRO__
7834 
7835 /* macros for field count */
7836 #define EMAC_REGS__TX_UNDERRUNS__COUNT__SHIFT                                 0
7837 #define EMAC_REGS__TX_UNDERRUNS__COUNT__WIDTH                                10
7838 #define EMAC_REGS__TX_UNDERRUNS__COUNT__MASK                        0x000003ffU
7839 #define EMAC_REGS__TX_UNDERRUNS__COUNT__RESET                                 0
7840 #define EMAC_REGS__TX_UNDERRUNS__COUNT__READ(src) \
7841                     ((uint32_t)(src)\
7842                     & 0x000003ffU)
7843 
7844 /* macros for field reserved_22 */
7845 #define EMAC_REGS__TX_UNDERRUNS__RESERVED_22__SHIFT                          10
7846 #define EMAC_REGS__TX_UNDERRUNS__RESERVED_22__WIDTH                          22
7847 #define EMAC_REGS__TX_UNDERRUNS__RESERVED_22__MASK                  0xfffffc00U
7848 #define EMAC_REGS__TX_UNDERRUNS__RESERVED_22__RESET                           0
7849 #define EMAC_REGS__TX_UNDERRUNS__RESERVED_22__READ(src) \
7850                     (((uint32_t)(src)\
7851                     & 0xfffffc00U) >> 10)
7852 #define EMAC_REGS__TX_UNDERRUNS__TYPE                                  uint32_t
7853 #define EMAC_REGS__TX_UNDERRUNS__READ                               0xffffffffU
7854 #define EMAC_REGS__TX_UNDERRUNS__RCLR                               0x000003ffU
7855 
7856 #endif /* __EMAC_REGS__TX_UNDERRUNS_MACRO__ */
7857 
7858 
7859 /* macros for tx_underruns */
7860 #define INST_TX_UNDERRUNS__NUM                                                1
7861 
7862 /* macros for BlueprintGlobalNameSpace::emac_regs::single_collisions */
7863 #ifndef __EMAC_REGS__SINGLE_COLLISIONS_MACRO__
7864 #define __EMAC_REGS__SINGLE_COLLISIONS_MACRO__
7865 
7866 /* macros for field count */
7867 #define EMAC_REGS__SINGLE_COLLISIONS__COUNT__SHIFT                            0
7868 #define EMAC_REGS__SINGLE_COLLISIONS__COUNT__WIDTH                           18
7869 #define EMAC_REGS__SINGLE_COLLISIONS__COUNT__MASK                   0x0003ffffU
7870 #define EMAC_REGS__SINGLE_COLLISIONS__COUNT__RESET                            0
7871 #define EMAC_REGS__SINGLE_COLLISIONS__COUNT__READ(src) \
7872                     ((uint32_t)(src)\
7873                     & 0x0003ffffU)
7874 
7875 /* macros for field reserved_31_18 */
7876 #define EMAC_REGS__SINGLE_COLLISIONS__RESERVED_31_18__SHIFT                  18
7877 #define EMAC_REGS__SINGLE_COLLISIONS__RESERVED_31_18__WIDTH                  14
7878 #define EMAC_REGS__SINGLE_COLLISIONS__RESERVED_31_18__MASK          0xfffc0000U
7879 #define EMAC_REGS__SINGLE_COLLISIONS__RESERVED_31_18__RESET                   0
7880 #define EMAC_REGS__SINGLE_COLLISIONS__RESERVED_31_18__READ(src) \
7881                     (((uint32_t)(src)\
7882                     & 0xfffc0000U) >> 18)
7883 #define EMAC_REGS__SINGLE_COLLISIONS__TYPE                             uint32_t
7884 #define EMAC_REGS__SINGLE_COLLISIONS__READ                          0xffffffffU
7885 #define EMAC_REGS__SINGLE_COLLISIONS__RCLR                          0x0003ffffU
7886 
7887 #endif /* __EMAC_REGS__SINGLE_COLLISIONS_MACRO__ */
7888 
7889 
7890 /* macros for single_collisions */
7891 #define INST_SINGLE_COLLISIONS__NUM                                           1
7892 
7893 /* macros for BlueprintGlobalNameSpace::emac_regs::multiple_collisions */
7894 #ifndef __EMAC_REGS__MULTIPLE_COLLISIONS_MACRO__
7895 #define __EMAC_REGS__MULTIPLE_COLLISIONS_MACRO__
7896 
7897 /* macros for field count */
7898 #define EMAC_REGS__MULTIPLE_COLLISIONS__COUNT__SHIFT                          0
7899 #define EMAC_REGS__MULTIPLE_COLLISIONS__COUNT__WIDTH                         18
7900 #define EMAC_REGS__MULTIPLE_COLLISIONS__COUNT__MASK                 0x0003ffffU
7901 #define EMAC_REGS__MULTIPLE_COLLISIONS__COUNT__RESET                          0
7902 #define EMAC_REGS__MULTIPLE_COLLISIONS__COUNT__READ(src) \
7903                     ((uint32_t)(src)\
7904                     & 0x0003ffffU)
7905 
7906 /* macros for field reserved_31_18 */
7907 #define EMAC_REGS__MULTIPLE_COLLISIONS__RESERVED_31_18__SHIFT                18
7908 #define EMAC_REGS__MULTIPLE_COLLISIONS__RESERVED_31_18__WIDTH                14
7909 #define EMAC_REGS__MULTIPLE_COLLISIONS__RESERVED_31_18__MASK        0xfffc0000U
7910 #define EMAC_REGS__MULTIPLE_COLLISIONS__RESERVED_31_18__RESET                 0
7911 #define EMAC_REGS__MULTIPLE_COLLISIONS__RESERVED_31_18__READ(src) \
7912                     (((uint32_t)(src)\
7913                     & 0xfffc0000U) >> 18)
7914 #define EMAC_REGS__MULTIPLE_COLLISIONS__TYPE                           uint32_t
7915 #define EMAC_REGS__MULTIPLE_COLLISIONS__READ                        0xffffffffU
7916 #define EMAC_REGS__MULTIPLE_COLLISIONS__RCLR                        0x0003ffffU
7917 
7918 #endif /* __EMAC_REGS__MULTIPLE_COLLISIONS_MACRO__ */
7919 
7920 
7921 /* macros for multiple_collisions */
7922 #define INST_MULTIPLE_COLLISIONS__NUM                                         1
7923 
7924 /* macros for BlueprintGlobalNameSpace::emac_regs::excessive_collisions */
7925 #ifndef __EMAC_REGS__EXCESSIVE_COLLISIONS_MACRO__
7926 #define __EMAC_REGS__EXCESSIVE_COLLISIONS_MACRO__
7927 
7928 /* macros for field count */
7929 #define EMAC_REGS__EXCESSIVE_COLLISIONS__COUNT__SHIFT                         0
7930 #define EMAC_REGS__EXCESSIVE_COLLISIONS__COUNT__WIDTH                        10
7931 #define EMAC_REGS__EXCESSIVE_COLLISIONS__COUNT__MASK                0x000003ffU
7932 #define EMAC_REGS__EXCESSIVE_COLLISIONS__COUNT__RESET                         0
7933 #define EMAC_REGS__EXCESSIVE_COLLISIONS__COUNT__READ(src) \
7934                     ((uint32_t)(src)\
7935                     & 0x000003ffU)
7936 
7937 /* macros for field reserved_31_10 */
7938 #define EMAC_REGS__EXCESSIVE_COLLISIONS__RESERVED_31_10__SHIFT               10
7939 #define EMAC_REGS__EXCESSIVE_COLLISIONS__RESERVED_31_10__WIDTH               22
7940 #define EMAC_REGS__EXCESSIVE_COLLISIONS__RESERVED_31_10__MASK       0xfffffc00U
7941 #define EMAC_REGS__EXCESSIVE_COLLISIONS__RESERVED_31_10__RESET                0
7942 #define EMAC_REGS__EXCESSIVE_COLLISIONS__RESERVED_31_10__READ(src) \
7943                     (((uint32_t)(src)\
7944                     & 0xfffffc00U) >> 10)
7945 #define EMAC_REGS__EXCESSIVE_COLLISIONS__TYPE                          uint32_t
7946 #define EMAC_REGS__EXCESSIVE_COLLISIONS__READ                       0xffffffffU
7947 #define EMAC_REGS__EXCESSIVE_COLLISIONS__RCLR                       0x000003ffU
7948 
7949 #endif /* __EMAC_REGS__EXCESSIVE_COLLISIONS_MACRO__ */
7950 
7951 
7952 /* macros for excessive_collisions */
7953 #define INST_EXCESSIVE_COLLISIONS__NUM                                        1
7954 
7955 /* macros for BlueprintGlobalNameSpace::emac_regs::late_collisions */
7956 #ifndef __EMAC_REGS__LATE_COLLISIONS_MACRO__
7957 #define __EMAC_REGS__LATE_COLLISIONS_MACRO__
7958 
7959 /* macros for field count */
7960 #define EMAC_REGS__LATE_COLLISIONS__COUNT__SHIFT                              0
7961 #define EMAC_REGS__LATE_COLLISIONS__COUNT__WIDTH                             10
7962 #define EMAC_REGS__LATE_COLLISIONS__COUNT__MASK                     0x000003ffU
7963 #define EMAC_REGS__LATE_COLLISIONS__COUNT__RESET                              0
7964 #define EMAC_REGS__LATE_COLLISIONS__COUNT__READ(src) \
7965                     ((uint32_t)(src)\
7966                     & 0x000003ffU)
7967 
7968 /* macros for field reserved_31_10 */
7969 #define EMAC_REGS__LATE_COLLISIONS__RESERVED_31_10__SHIFT                    10
7970 #define EMAC_REGS__LATE_COLLISIONS__RESERVED_31_10__WIDTH                    22
7971 #define EMAC_REGS__LATE_COLLISIONS__RESERVED_31_10__MASK            0xfffffc00U
7972 #define EMAC_REGS__LATE_COLLISIONS__RESERVED_31_10__RESET                     0
7973 #define EMAC_REGS__LATE_COLLISIONS__RESERVED_31_10__READ(src) \
7974                     (((uint32_t)(src)\
7975                     & 0xfffffc00U) >> 10)
7976 #define EMAC_REGS__LATE_COLLISIONS__TYPE                               uint32_t
7977 #define EMAC_REGS__LATE_COLLISIONS__READ                            0xffffffffU
7978 #define EMAC_REGS__LATE_COLLISIONS__RCLR                            0x000003ffU
7979 
7980 #endif /* __EMAC_REGS__LATE_COLLISIONS_MACRO__ */
7981 
7982 
7983 /* macros for late_collisions */
7984 #define INST_LATE_COLLISIONS__NUM                                             1
7985 
7986 /* macros for BlueprintGlobalNameSpace::emac_regs::deferred_frames */
7987 #ifndef __EMAC_REGS__DEFERRED_FRAMES_MACRO__
7988 #define __EMAC_REGS__DEFERRED_FRAMES_MACRO__
7989 
7990 /* macros for field count */
7991 #define EMAC_REGS__DEFERRED_FRAMES__COUNT__SHIFT                              0
7992 #define EMAC_REGS__DEFERRED_FRAMES__COUNT__WIDTH                             18
7993 #define EMAC_REGS__DEFERRED_FRAMES__COUNT__MASK                     0x0003ffffU
7994 #define EMAC_REGS__DEFERRED_FRAMES__COUNT__RESET                              0
7995 #define EMAC_REGS__DEFERRED_FRAMES__COUNT__READ(src) \
7996                     ((uint32_t)(src)\
7997                     & 0x0003ffffU)
7998 
7999 /* macros for field reserved_31_18 */
8000 #define EMAC_REGS__DEFERRED_FRAMES__RESERVED_31_18__SHIFT                    18
8001 #define EMAC_REGS__DEFERRED_FRAMES__RESERVED_31_18__WIDTH                    14
8002 #define EMAC_REGS__DEFERRED_FRAMES__RESERVED_31_18__MASK            0xfffc0000U
8003 #define EMAC_REGS__DEFERRED_FRAMES__RESERVED_31_18__RESET                     0
8004 #define EMAC_REGS__DEFERRED_FRAMES__RESERVED_31_18__READ(src) \
8005                     (((uint32_t)(src)\
8006                     & 0xfffc0000U) >> 18)
8007 #define EMAC_REGS__DEFERRED_FRAMES__TYPE                               uint32_t
8008 #define EMAC_REGS__DEFERRED_FRAMES__READ                            0xffffffffU
8009 #define EMAC_REGS__DEFERRED_FRAMES__RCLR                            0x0003ffffU
8010 
8011 #endif /* __EMAC_REGS__DEFERRED_FRAMES_MACRO__ */
8012 
8013 
8014 /* macros for deferred_frames */
8015 #define INST_DEFERRED_FRAMES__NUM                                             1
8016 
8017 /* macros for BlueprintGlobalNameSpace::emac_regs::crs_errors */
8018 #ifndef __EMAC_REGS__CRS_ERRORS_MACRO__
8019 #define __EMAC_REGS__CRS_ERRORS_MACRO__
8020 
8021 /* macros for field count */
8022 #define EMAC_REGS__CRS_ERRORS__COUNT__SHIFT                                   0
8023 #define EMAC_REGS__CRS_ERRORS__COUNT__WIDTH                                  10
8024 #define EMAC_REGS__CRS_ERRORS__COUNT__MASK                          0x000003ffU
8025 #define EMAC_REGS__CRS_ERRORS__COUNT__RESET                                   0
8026 #define EMAC_REGS__CRS_ERRORS__COUNT__READ(src) ((uint32_t)(src) & 0x000003ffU)
8027 
8028 /* macros for field reserved_31_10 */
8029 #define EMAC_REGS__CRS_ERRORS__RESERVED_31_10__SHIFT                         10
8030 #define EMAC_REGS__CRS_ERRORS__RESERVED_31_10__WIDTH                         22
8031 #define EMAC_REGS__CRS_ERRORS__RESERVED_31_10__MASK                 0xfffffc00U
8032 #define EMAC_REGS__CRS_ERRORS__RESERVED_31_10__RESET                          0
8033 #define EMAC_REGS__CRS_ERRORS__RESERVED_31_10__READ(src) \
8034                     (((uint32_t)(src)\
8035                     & 0xfffffc00U) >> 10)
8036 #define EMAC_REGS__CRS_ERRORS__TYPE                                    uint32_t
8037 #define EMAC_REGS__CRS_ERRORS__READ                                 0xffffffffU
8038 #define EMAC_REGS__CRS_ERRORS__RCLR                                 0x000003ffU
8039 
8040 #endif /* __EMAC_REGS__CRS_ERRORS_MACRO__ */
8041 
8042 
8043 /* macros for crs_errors */
8044 #define INST_CRS_ERRORS__NUM                                                  1
8045 
8046 /* macros for BlueprintGlobalNameSpace::emac_regs::octets_rxed_bottom */
8047 #ifndef __EMAC_REGS__OCTETS_RXED_BOTTOM_MACRO__
8048 #define __EMAC_REGS__OCTETS_RXED_BOTTOM_MACRO__
8049 
8050 /* macros for field count */
8051 #define EMAC_REGS__OCTETS_RXED_BOTTOM__COUNT__SHIFT                           0
8052 #define EMAC_REGS__OCTETS_RXED_BOTTOM__COUNT__WIDTH                          32
8053 #define EMAC_REGS__OCTETS_RXED_BOTTOM__COUNT__MASK                  0xffffffffU
8054 #define EMAC_REGS__OCTETS_RXED_BOTTOM__COUNT__RESET                           0
8055 #define EMAC_REGS__OCTETS_RXED_BOTTOM__COUNT__READ(src) \
8056                     ((uint32_t)(src)\
8057                     & 0xffffffffU)
8058 #define EMAC_REGS__OCTETS_RXED_BOTTOM__TYPE                            uint32_t
8059 #define EMAC_REGS__OCTETS_RXED_BOTTOM__READ                         0xffffffffU
8060 #define EMAC_REGS__OCTETS_RXED_BOTTOM__RCLR                         0xffffffffU
8061 
8062 #endif /* __EMAC_REGS__OCTETS_RXED_BOTTOM_MACRO__ */
8063 
8064 
8065 /* macros for octets_rxed_bottom */
8066 #define INST_OCTETS_RXED_BOTTOM__NUM                                          1
8067 
8068 /* macros for BlueprintGlobalNameSpace::emac_regs::octets_rxed_top */
8069 #ifndef __EMAC_REGS__OCTETS_RXED_TOP_MACRO__
8070 #define __EMAC_REGS__OCTETS_RXED_TOP_MACRO__
8071 
8072 /* macros for field count */
8073 #define EMAC_REGS__OCTETS_RXED_TOP__COUNT__SHIFT                              0
8074 #define EMAC_REGS__OCTETS_RXED_TOP__COUNT__WIDTH                             16
8075 #define EMAC_REGS__OCTETS_RXED_TOP__COUNT__MASK                     0x0000ffffU
8076 #define EMAC_REGS__OCTETS_RXED_TOP__COUNT__RESET                              0
8077 #define EMAC_REGS__OCTETS_RXED_TOP__COUNT__READ(src) \
8078                     ((uint32_t)(src)\
8079                     & 0x0000ffffU)
8080 
8081 /* macros for field reserved_31_16 */
8082 #define EMAC_REGS__OCTETS_RXED_TOP__RESERVED_31_16__SHIFT                    16
8083 #define EMAC_REGS__OCTETS_RXED_TOP__RESERVED_31_16__WIDTH                    16
8084 #define EMAC_REGS__OCTETS_RXED_TOP__RESERVED_31_16__MASK            0xffff0000U
8085 #define EMAC_REGS__OCTETS_RXED_TOP__RESERVED_31_16__RESET                     0
8086 #define EMAC_REGS__OCTETS_RXED_TOP__RESERVED_31_16__READ(src) \
8087                     (((uint32_t)(src)\
8088                     & 0xffff0000U) >> 16)
8089 #define EMAC_REGS__OCTETS_RXED_TOP__TYPE                               uint32_t
8090 #define EMAC_REGS__OCTETS_RXED_TOP__READ                            0xffffffffU
8091 #define EMAC_REGS__OCTETS_RXED_TOP__RCLR                            0x0000ffffU
8092 
8093 #endif /* __EMAC_REGS__OCTETS_RXED_TOP_MACRO__ */
8094 
8095 
8096 /* macros for octets_rxed_top */
8097 #define INST_OCTETS_RXED_TOP__NUM                                             1
8098 
8099 /* macros for BlueprintGlobalNameSpace::emac_regs::frames_rxed_ok */
8100 #ifndef __EMAC_REGS__FRAMES_RXED_OK_MACRO__
8101 #define __EMAC_REGS__FRAMES_RXED_OK_MACRO__
8102 
8103 /* macros for field count */
8104 #define EMAC_REGS__FRAMES_RXED_OK__COUNT__SHIFT                               0
8105 #define EMAC_REGS__FRAMES_RXED_OK__COUNT__WIDTH                              32
8106 #define EMAC_REGS__FRAMES_RXED_OK__COUNT__MASK                      0xffffffffU
8107 #define EMAC_REGS__FRAMES_RXED_OK__COUNT__RESET                               0
8108 #define EMAC_REGS__FRAMES_RXED_OK__COUNT__READ(src) \
8109                     ((uint32_t)(src)\
8110                     & 0xffffffffU)
8111 #define EMAC_REGS__FRAMES_RXED_OK__TYPE                                uint32_t
8112 #define EMAC_REGS__FRAMES_RXED_OK__READ                             0xffffffffU
8113 #define EMAC_REGS__FRAMES_RXED_OK__RCLR                             0xffffffffU
8114 
8115 #endif /* __EMAC_REGS__FRAMES_RXED_OK_MACRO__ */
8116 
8117 
8118 /* macros for frames_rxed_ok */
8119 #define INST_FRAMES_RXED_OK__NUM                                              1
8120 
8121 /* macros for BlueprintGlobalNameSpace::emac_regs::broadcast_rxed */
8122 #ifndef __EMAC_REGS__BROADCAST_RXED_MACRO__
8123 #define __EMAC_REGS__BROADCAST_RXED_MACRO__
8124 
8125 /* macros for field count */
8126 #define EMAC_REGS__BROADCAST_RXED__COUNT__SHIFT                               0
8127 #define EMAC_REGS__BROADCAST_RXED__COUNT__WIDTH                              32
8128 #define EMAC_REGS__BROADCAST_RXED__COUNT__MASK                      0xffffffffU
8129 #define EMAC_REGS__BROADCAST_RXED__COUNT__RESET                               0
8130 #define EMAC_REGS__BROADCAST_RXED__COUNT__READ(src) \
8131                     ((uint32_t)(src)\
8132                     & 0xffffffffU)
8133 #define EMAC_REGS__BROADCAST_RXED__TYPE                                uint32_t
8134 #define EMAC_REGS__BROADCAST_RXED__READ                             0xffffffffU
8135 #define EMAC_REGS__BROADCAST_RXED__RCLR                             0xffffffffU
8136 
8137 #endif /* __EMAC_REGS__BROADCAST_RXED_MACRO__ */
8138 
8139 
8140 /* macros for broadcast_rxed */
8141 #define INST_BROADCAST_RXED__NUM                                              1
8142 
8143 /* macros for BlueprintGlobalNameSpace::emac_regs::multicast_rxed */
8144 #ifndef __EMAC_REGS__MULTICAST_RXED_MACRO__
8145 #define __EMAC_REGS__MULTICAST_RXED_MACRO__
8146 
8147 /* macros for field count */
8148 #define EMAC_REGS__MULTICAST_RXED__COUNT__SHIFT                               0
8149 #define EMAC_REGS__MULTICAST_RXED__COUNT__WIDTH                              32
8150 #define EMAC_REGS__MULTICAST_RXED__COUNT__MASK                      0xffffffffU
8151 #define EMAC_REGS__MULTICAST_RXED__COUNT__RESET                               0
8152 #define EMAC_REGS__MULTICAST_RXED__COUNT__READ(src) \
8153                     ((uint32_t)(src)\
8154                     & 0xffffffffU)
8155 #define EMAC_REGS__MULTICAST_RXED__TYPE                                uint32_t
8156 #define EMAC_REGS__MULTICAST_RXED__READ                             0xffffffffU
8157 #define EMAC_REGS__MULTICAST_RXED__RCLR                             0xffffffffU
8158 
8159 #endif /* __EMAC_REGS__MULTICAST_RXED_MACRO__ */
8160 
8161 
8162 /* macros for multicast_rxed */
8163 #define INST_MULTICAST_RXED__NUM                                              1
8164 
8165 /* macros for BlueprintGlobalNameSpace::emac_regs::pause_frames_rxed */
8166 #ifndef __EMAC_REGS__PAUSE_FRAMES_RXED_MACRO__
8167 #define __EMAC_REGS__PAUSE_FRAMES_RXED_MACRO__
8168 
8169 /* macros for field count */
8170 #define EMAC_REGS__PAUSE_FRAMES_RXED__COUNT__SHIFT                            0
8171 #define EMAC_REGS__PAUSE_FRAMES_RXED__COUNT__WIDTH                           16
8172 #define EMAC_REGS__PAUSE_FRAMES_RXED__COUNT__MASK                   0x0000ffffU
8173 #define EMAC_REGS__PAUSE_FRAMES_RXED__COUNT__RESET                            0
8174 #define EMAC_REGS__PAUSE_FRAMES_RXED__COUNT__READ(src) \
8175                     ((uint32_t)(src)\
8176                     & 0x0000ffffU)
8177 
8178 /* macros for field reserved_31_16 */
8179 #define EMAC_REGS__PAUSE_FRAMES_RXED__RESERVED_31_16__SHIFT                  16
8180 #define EMAC_REGS__PAUSE_FRAMES_RXED__RESERVED_31_16__WIDTH                  16
8181 #define EMAC_REGS__PAUSE_FRAMES_RXED__RESERVED_31_16__MASK          0xffff0000U
8182 #define EMAC_REGS__PAUSE_FRAMES_RXED__RESERVED_31_16__RESET                   0
8183 #define EMAC_REGS__PAUSE_FRAMES_RXED__RESERVED_31_16__READ(src) \
8184                     (((uint32_t)(src)\
8185                     & 0xffff0000U) >> 16)
8186 #define EMAC_REGS__PAUSE_FRAMES_RXED__TYPE                             uint32_t
8187 #define EMAC_REGS__PAUSE_FRAMES_RXED__READ                          0xffffffffU
8188 #define EMAC_REGS__PAUSE_FRAMES_RXED__RCLR                          0x0000ffffU
8189 
8190 #endif /* __EMAC_REGS__PAUSE_FRAMES_RXED_MACRO__ */
8191 
8192 
8193 /* macros for pause_frames_rxed */
8194 #define INST_PAUSE_FRAMES_RXED__NUM                                           1
8195 
8196 /* macros for BlueprintGlobalNameSpace::emac_regs::frames_rxed_64 */
8197 #ifndef __EMAC_REGS__FRAMES_RXED_64_MACRO__
8198 #define __EMAC_REGS__FRAMES_RXED_64_MACRO__
8199 
8200 /* macros for field count */
8201 #define EMAC_REGS__FRAMES_RXED_64__COUNT__SHIFT                               0
8202 #define EMAC_REGS__FRAMES_RXED_64__COUNT__WIDTH                              32
8203 #define EMAC_REGS__FRAMES_RXED_64__COUNT__MASK                      0xffffffffU
8204 #define EMAC_REGS__FRAMES_RXED_64__COUNT__RESET                               0
8205 #define EMAC_REGS__FRAMES_RXED_64__COUNT__READ(src) \
8206                     ((uint32_t)(src)\
8207                     & 0xffffffffU)
8208 #define EMAC_REGS__FRAMES_RXED_64__TYPE                                uint32_t
8209 #define EMAC_REGS__FRAMES_RXED_64__READ                             0xffffffffU
8210 #define EMAC_REGS__FRAMES_RXED_64__RCLR                             0xffffffffU
8211 
8212 #endif /* __EMAC_REGS__FRAMES_RXED_64_MACRO__ */
8213 
8214 
8215 /* macros for frames_rxed_64 */
8216 #define INST_FRAMES_RXED_64__NUM                                              1
8217 
8218 /* macros for BlueprintGlobalNameSpace::emac_regs::frames_rxed_65 */
8219 #ifndef __EMAC_REGS__FRAMES_RXED_65_MACRO__
8220 #define __EMAC_REGS__FRAMES_RXED_65_MACRO__
8221 
8222 /* macros for field count */
8223 #define EMAC_REGS__FRAMES_RXED_65__COUNT__SHIFT                               0
8224 #define EMAC_REGS__FRAMES_RXED_65__COUNT__WIDTH                              32
8225 #define EMAC_REGS__FRAMES_RXED_65__COUNT__MASK                      0xffffffffU
8226 #define EMAC_REGS__FRAMES_RXED_65__COUNT__RESET                               0
8227 #define EMAC_REGS__FRAMES_RXED_65__COUNT__READ(src) \
8228                     ((uint32_t)(src)\
8229                     & 0xffffffffU)
8230 #define EMAC_REGS__FRAMES_RXED_65__TYPE                                uint32_t
8231 #define EMAC_REGS__FRAMES_RXED_65__READ                             0xffffffffU
8232 #define EMAC_REGS__FRAMES_RXED_65__RCLR                             0xffffffffU
8233 
8234 #endif /* __EMAC_REGS__FRAMES_RXED_65_MACRO__ */
8235 
8236 
8237 /* macros for frames_rxed_65 */
8238 #define INST_FRAMES_RXED_65__NUM                                              1
8239 
8240 /* macros for BlueprintGlobalNameSpace::emac_regs::frames_rxed_128 */
8241 #ifndef __EMAC_REGS__FRAMES_RXED_128_MACRO__
8242 #define __EMAC_REGS__FRAMES_RXED_128_MACRO__
8243 
8244 /* macros for field count */
8245 #define EMAC_REGS__FRAMES_RXED_128__COUNT__SHIFT                              0
8246 #define EMAC_REGS__FRAMES_RXED_128__COUNT__WIDTH                             32
8247 #define EMAC_REGS__FRAMES_RXED_128__COUNT__MASK                     0xffffffffU
8248 #define EMAC_REGS__FRAMES_RXED_128__COUNT__RESET                              0
8249 #define EMAC_REGS__FRAMES_RXED_128__COUNT__READ(src) \
8250                     ((uint32_t)(src)\
8251                     & 0xffffffffU)
8252 #define EMAC_REGS__FRAMES_RXED_128__TYPE                               uint32_t
8253 #define EMAC_REGS__FRAMES_RXED_128__READ                            0xffffffffU
8254 #define EMAC_REGS__FRAMES_RXED_128__RCLR                            0xffffffffU
8255 
8256 #endif /* __EMAC_REGS__FRAMES_RXED_128_MACRO__ */
8257 
8258 
8259 /* macros for frames_rxed_128 */
8260 #define INST_FRAMES_RXED_128__NUM                                             1
8261 
8262 /* macros for BlueprintGlobalNameSpace::emac_regs::frames_rxed_256 */
8263 #ifndef __EMAC_REGS__FRAMES_RXED_256_MACRO__
8264 #define __EMAC_REGS__FRAMES_RXED_256_MACRO__
8265 
8266 /* macros for field count */
8267 #define EMAC_REGS__FRAMES_RXED_256__COUNT__SHIFT                              0
8268 #define EMAC_REGS__FRAMES_RXED_256__COUNT__WIDTH                             32
8269 #define EMAC_REGS__FRAMES_RXED_256__COUNT__MASK                     0xffffffffU
8270 #define EMAC_REGS__FRAMES_RXED_256__COUNT__RESET                              0
8271 #define EMAC_REGS__FRAMES_RXED_256__COUNT__READ(src) \
8272                     ((uint32_t)(src)\
8273                     & 0xffffffffU)
8274 #define EMAC_REGS__FRAMES_RXED_256__TYPE                               uint32_t
8275 #define EMAC_REGS__FRAMES_RXED_256__READ                            0xffffffffU
8276 #define EMAC_REGS__FRAMES_RXED_256__RCLR                            0xffffffffU
8277 
8278 #endif /* __EMAC_REGS__FRAMES_RXED_256_MACRO__ */
8279 
8280 
8281 /* macros for frames_rxed_256 */
8282 #define INST_FRAMES_RXED_256__NUM                                             1
8283 
8284 /* macros for BlueprintGlobalNameSpace::emac_regs::frames_rxed_512 */
8285 #ifndef __EMAC_REGS__FRAMES_RXED_512_MACRO__
8286 #define __EMAC_REGS__FRAMES_RXED_512_MACRO__
8287 
8288 /* macros for field count */
8289 #define EMAC_REGS__FRAMES_RXED_512__COUNT__SHIFT                              0
8290 #define EMAC_REGS__FRAMES_RXED_512__COUNT__WIDTH                             32
8291 #define EMAC_REGS__FRAMES_RXED_512__COUNT__MASK                     0xffffffffU
8292 #define EMAC_REGS__FRAMES_RXED_512__COUNT__RESET                              0
8293 #define EMAC_REGS__FRAMES_RXED_512__COUNT__READ(src) \
8294                     ((uint32_t)(src)\
8295                     & 0xffffffffU)
8296 #define EMAC_REGS__FRAMES_RXED_512__TYPE                               uint32_t
8297 #define EMAC_REGS__FRAMES_RXED_512__READ                            0xffffffffU
8298 #define EMAC_REGS__FRAMES_RXED_512__RCLR                            0xffffffffU
8299 
8300 #endif /* __EMAC_REGS__FRAMES_RXED_512_MACRO__ */
8301 
8302 
8303 /* macros for frames_rxed_512 */
8304 #define INST_FRAMES_RXED_512__NUM                                             1
8305 
8306 /* macros for BlueprintGlobalNameSpace::emac_regs::frames_rxed_1024 */
8307 #ifndef __EMAC_REGS__FRAMES_RXED_1024_MACRO__
8308 #define __EMAC_REGS__FRAMES_RXED_1024_MACRO__
8309 
8310 /* macros for field count */
8311 #define EMAC_REGS__FRAMES_RXED_1024__COUNT__SHIFT                             0
8312 #define EMAC_REGS__FRAMES_RXED_1024__COUNT__WIDTH                            32
8313 #define EMAC_REGS__FRAMES_RXED_1024__COUNT__MASK                    0xffffffffU
8314 #define EMAC_REGS__FRAMES_RXED_1024__COUNT__RESET                             0
8315 #define EMAC_REGS__FRAMES_RXED_1024__COUNT__READ(src) \
8316                     ((uint32_t)(src)\
8317                     & 0xffffffffU)
8318 #define EMAC_REGS__FRAMES_RXED_1024__TYPE                              uint32_t
8319 #define EMAC_REGS__FRAMES_RXED_1024__READ                           0xffffffffU
8320 #define EMAC_REGS__FRAMES_RXED_1024__RCLR                           0xffffffffU
8321 
8322 #endif /* __EMAC_REGS__FRAMES_RXED_1024_MACRO__ */
8323 
8324 
8325 /* macros for frames_rxed_1024 */
8326 #define INST_FRAMES_RXED_1024__NUM                                            1
8327 
8328 /* macros for BlueprintGlobalNameSpace::emac_regs::frames_rxed_1519 */
8329 #ifndef __EMAC_REGS__FRAMES_RXED_1519_MACRO__
8330 #define __EMAC_REGS__FRAMES_RXED_1519_MACRO__
8331 
8332 /* macros for field count */
8333 #define EMAC_REGS__FRAMES_RXED_1519__COUNT__SHIFT                             0
8334 #define EMAC_REGS__FRAMES_RXED_1519__COUNT__WIDTH                            32
8335 #define EMAC_REGS__FRAMES_RXED_1519__COUNT__MASK                    0xffffffffU
8336 #define EMAC_REGS__FRAMES_RXED_1519__COUNT__RESET                             0
8337 #define EMAC_REGS__FRAMES_RXED_1519__COUNT__READ(src) \
8338                     ((uint32_t)(src)\
8339                     & 0xffffffffU)
8340 #define EMAC_REGS__FRAMES_RXED_1519__TYPE                              uint32_t
8341 #define EMAC_REGS__FRAMES_RXED_1519__READ                           0xffffffffU
8342 #define EMAC_REGS__FRAMES_RXED_1519__RCLR                           0xffffffffU
8343 
8344 #endif /* __EMAC_REGS__FRAMES_RXED_1519_MACRO__ */
8345 
8346 
8347 /* macros for frames_rxed_1519 */
8348 #define INST_FRAMES_RXED_1519__NUM                                            1
8349 
8350 /* macros for BlueprintGlobalNameSpace::emac_regs::undersize_frames */
8351 #ifndef __EMAC_REGS__UNDERSIZE_FRAMES_MACRO__
8352 #define __EMAC_REGS__UNDERSIZE_FRAMES_MACRO__
8353 
8354 /* macros for field count */
8355 #define EMAC_REGS__UNDERSIZE_FRAMES__COUNT__SHIFT                             0
8356 #define EMAC_REGS__UNDERSIZE_FRAMES__COUNT__WIDTH                            10
8357 #define EMAC_REGS__UNDERSIZE_FRAMES__COUNT__MASK                    0x000003ffU
8358 #define EMAC_REGS__UNDERSIZE_FRAMES__COUNT__RESET                             0
8359 #define EMAC_REGS__UNDERSIZE_FRAMES__COUNT__READ(src) \
8360                     ((uint32_t)(src)\
8361                     & 0x000003ffU)
8362 
8363 /* macros for field reserved_31_10 */
8364 #define EMAC_REGS__UNDERSIZE_FRAMES__RESERVED_31_10__SHIFT                   10
8365 #define EMAC_REGS__UNDERSIZE_FRAMES__RESERVED_31_10__WIDTH                   22
8366 #define EMAC_REGS__UNDERSIZE_FRAMES__RESERVED_31_10__MASK           0xfffffc00U
8367 #define EMAC_REGS__UNDERSIZE_FRAMES__RESERVED_31_10__RESET                    0
8368 #define EMAC_REGS__UNDERSIZE_FRAMES__RESERVED_31_10__READ(src) \
8369                     (((uint32_t)(src)\
8370                     & 0xfffffc00U) >> 10)
8371 #define EMAC_REGS__UNDERSIZE_FRAMES__TYPE                              uint32_t
8372 #define EMAC_REGS__UNDERSIZE_FRAMES__READ                           0xffffffffU
8373 #define EMAC_REGS__UNDERSIZE_FRAMES__RCLR                           0x000003ffU
8374 
8375 #endif /* __EMAC_REGS__UNDERSIZE_FRAMES_MACRO__ */
8376 
8377 
8378 /* macros for undersize_frames */
8379 #define INST_UNDERSIZE_FRAMES__NUM                                            1
8380 
8381 /* macros for BlueprintGlobalNameSpace::emac_regs::excessive_rx_length */
8382 #ifndef __EMAC_REGS__EXCESSIVE_RX_LENGTH_MACRO__
8383 #define __EMAC_REGS__EXCESSIVE_RX_LENGTH_MACRO__
8384 
8385 /* macros for field count */
8386 #define EMAC_REGS__EXCESSIVE_RX_LENGTH__COUNT__SHIFT                          0
8387 #define EMAC_REGS__EXCESSIVE_RX_LENGTH__COUNT__WIDTH                         10
8388 #define EMAC_REGS__EXCESSIVE_RX_LENGTH__COUNT__MASK                 0x000003ffU
8389 #define EMAC_REGS__EXCESSIVE_RX_LENGTH__COUNT__RESET                          0
8390 #define EMAC_REGS__EXCESSIVE_RX_LENGTH__COUNT__READ(src) \
8391                     ((uint32_t)(src)\
8392                     & 0x000003ffU)
8393 
8394 /* macros for field reserved_31_10 */
8395 #define EMAC_REGS__EXCESSIVE_RX_LENGTH__RESERVED_31_10__SHIFT                10
8396 #define EMAC_REGS__EXCESSIVE_RX_LENGTH__RESERVED_31_10__WIDTH                22
8397 #define EMAC_REGS__EXCESSIVE_RX_LENGTH__RESERVED_31_10__MASK        0xfffffc00U
8398 #define EMAC_REGS__EXCESSIVE_RX_LENGTH__RESERVED_31_10__RESET                 0
8399 #define EMAC_REGS__EXCESSIVE_RX_LENGTH__RESERVED_31_10__READ(src) \
8400                     (((uint32_t)(src)\
8401                     & 0xfffffc00U) >> 10)
8402 #define EMAC_REGS__EXCESSIVE_RX_LENGTH__TYPE                           uint32_t
8403 #define EMAC_REGS__EXCESSIVE_RX_LENGTH__READ                        0xffffffffU
8404 #define EMAC_REGS__EXCESSIVE_RX_LENGTH__RCLR                        0x000003ffU
8405 
8406 #endif /* __EMAC_REGS__EXCESSIVE_RX_LENGTH_MACRO__ */
8407 
8408 
8409 /* macros for excessive_rx_length */
8410 #define INST_EXCESSIVE_RX_LENGTH__NUM                                         1
8411 
8412 /* macros for BlueprintGlobalNameSpace::emac_regs::rx_jabbers */
8413 #ifndef __EMAC_REGS__RX_JABBERS_MACRO__
8414 #define __EMAC_REGS__RX_JABBERS_MACRO__
8415 
8416 /* macros for field count */
8417 #define EMAC_REGS__RX_JABBERS__COUNT__SHIFT                                   0
8418 #define EMAC_REGS__RX_JABBERS__COUNT__WIDTH                                  10
8419 #define EMAC_REGS__RX_JABBERS__COUNT__MASK                          0x000003ffU
8420 #define EMAC_REGS__RX_JABBERS__COUNT__RESET                                   0
8421 #define EMAC_REGS__RX_JABBERS__COUNT__READ(src) ((uint32_t)(src) & 0x000003ffU)
8422 
8423 /* macros for field reserved_31_10 */
8424 #define EMAC_REGS__RX_JABBERS__RESERVED_31_10__SHIFT                         10
8425 #define EMAC_REGS__RX_JABBERS__RESERVED_31_10__WIDTH                         22
8426 #define EMAC_REGS__RX_JABBERS__RESERVED_31_10__MASK                 0xfffffc00U
8427 #define EMAC_REGS__RX_JABBERS__RESERVED_31_10__RESET                          0
8428 #define EMAC_REGS__RX_JABBERS__RESERVED_31_10__READ(src) \
8429                     (((uint32_t)(src)\
8430                     & 0xfffffc00U) >> 10)
8431 #define EMAC_REGS__RX_JABBERS__TYPE                                    uint32_t
8432 #define EMAC_REGS__RX_JABBERS__READ                                 0xffffffffU
8433 #define EMAC_REGS__RX_JABBERS__RCLR                                 0x000003ffU
8434 
8435 #endif /* __EMAC_REGS__RX_JABBERS_MACRO__ */
8436 
8437 
8438 /* macros for rx_jabbers */
8439 #define INST_RX_JABBERS__NUM                                                  1
8440 
8441 /* macros for BlueprintGlobalNameSpace::emac_regs::fcs_errors */
8442 #ifndef __EMAC_REGS__FCS_ERRORS_MACRO__
8443 #define __EMAC_REGS__FCS_ERRORS_MACRO__
8444 
8445 /* macros for field count */
8446 #define EMAC_REGS__FCS_ERRORS__COUNT__SHIFT                                   0
8447 #define EMAC_REGS__FCS_ERRORS__COUNT__WIDTH                                  10
8448 #define EMAC_REGS__FCS_ERRORS__COUNT__MASK                          0x000003ffU
8449 #define EMAC_REGS__FCS_ERRORS__COUNT__RESET                                   0
8450 #define EMAC_REGS__FCS_ERRORS__COUNT__READ(src) ((uint32_t)(src) & 0x000003ffU)
8451 
8452 /* macros for field reserved_31_10 */
8453 #define EMAC_REGS__FCS_ERRORS__RESERVED_31_10__SHIFT                         10
8454 #define EMAC_REGS__FCS_ERRORS__RESERVED_31_10__WIDTH                         22
8455 #define EMAC_REGS__FCS_ERRORS__RESERVED_31_10__MASK                 0xfffffc00U
8456 #define EMAC_REGS__FCS_ERRORS__RESERVED_31_10__RESET                          0
8457 #define EMAC_REGS__FCS_ERRORS__RESERVED_31_10__READ(src) \
8458                     (((uint32_t)(src)\
8459                     & 0xfffffc00U) >> 10)
8460 #define EMAC_REGS__FCS_ERRORS__TYPE                                    uint32_t
8461 #define EMAC_REGS__FCS_ERRORS__READ                                 0xffffffffU
8462 #define EMAC_REGS__FCS_ERRORS__RCLR                                 0x000003ffU
8463 
8464 #endif /* __EMAC_REGS__FCS_ERRORS_MACRO__ */
8465 
8466 
8467 /* macros for fcs_errors */
8468 #define INST_FCS_ERRORS__NUM                                                  1
8469 
8470 /* macros for BlueprintGlobalNameSpace::emac_regs::rx_length_errors */
8471 #ifndef __EMAC_REGS__RX_LENGTH_ERRORS_MACRO__
8472 #define __EMAC_REGS__RX_LENGTH_ERRORS_MACRO__
8473 
8474 /* macros for field count */
8475 #define EMAC_REGS__RX_LENGTH_ERRORS__COUNT__SHIFT                             0
8476 #define EMAC_REGS__RX_LENGTH_ERRORS__COUNT__WIDTH                            10
8477 #define EMAC_REGS__RX_LENGTH_ERRORS__COUNT__MASK                    0x000003ffU
8478 #define EMAC_REGS__RX_LENGTH_ERRORS__COUNT__RESET                             0
8479 #define EMAC_REGS__RX_LENGTH_ERRORS__COUNT__READ(src) \
8480                     ((uint32_t)(src)\
8481                     & 0x000003ffU)
8482 
8483 /* macros for field reserved_31_10 */
8484 #define EMAC_REGS__RX_LENGTH_ERRORS__RESERVED_31_10__SHIFT                   10
8485 #define EMAC_REGS__RX_LENGTH_ERRORS__RESERVED_31_10__WIDTH                   22
8486 #define EMAC_REGS__RX_LENGTH_ERRORS__RESERVED_31_10__MASK           0xfffffc00U
8487 #define EMAC_REGS__RX_LENGTH_ERRORS__RESERVED_31_10__RESET                    0
8488 #define EMAC_REGS__RX_LENGTH_ERRORS__RESERVED_31_10__READ(src) \
8489                     (((uint32_t)(src)\
8490                     & 0xfffffc00U) >> 10)
8491 #define EMAC_REGS__RX_LENGTH_ERRORS__TYPE                              uint32_t
8492 #define EMAC_REGS__RX_LENGTH_ERRORS__READ                           0xffffffffU
8493 #define EMAC_REGS__RX_LENGTH_ERRORS__RCLR                           0x000003ffU
8494 
8495 #endif /* __EMAC_REGS__RX_LENGTH_ERRORS_MACRO__ */
8496 
8497 
8498 /* macros for rx_length_errors */
8499 #define INST_RX_LENGTH_ERRORS__NUM                                            1
8500 
8501 /* macros for BlueprintGlobalNameSpace::emac_regs::rx_symbol_errors */
8502 #ifndef __EMAC_REGS__RX_SYMBOL_ERRORS_MACRO__
8503 #define __EMAC_REGS__RX_SYMBOL_ERRORS_MACRO__
8504 
8505 /* macros for field count */
8506 #define EMAC_REGS__RX_SYMBOL_ERRORS__COUNT__SHIFT                             0
8507 #define EMAC_REGS__RX_SYMBOL_ERRORS__COUNT__WIDTH                            10
8508 #define EMAC_REGS__RX_SYMBOL_ERRORS__COUNT__MASK                    0x000003ffU
8509 #define EMAC_REGS__RX_SYMBOL_ERRORS__COUNT__RESET                             0
8510 #define EMAC_REGS__RX_SYMBOL_ERRORS__COUNT__READ(src) \
8511                     ((uint32_t)(src)\
8512                     & 0x000003ffU)
8513 
8514 /* macros for field reserved_31_10 */
8515 #define EMAC_REGS__RX_SYMBOL_ERRORS__RESERVED_31_10__SHIFT                   10
8516 #define EMAC_REGS__RX_SYMBOL_ERRORS__RESERVED_31_10__WIDTH                   22
8517 #define EMAC_REGS__RX_SYMBOL_ERRORS__RESERVED_31_10__MASK           0xfffffc00U
8518 #define EMAC_REGS__RX_SYMBOL_ERRORS__RESERVED_31_10__RESET                    0
8519 #define EMAC_REGS__RX_SYMBOL_ERRORS__RESERVED_31_10__READ(src) \
8520                     (((uint32_t)(src)\
8521                     & 0xfffffc00U) >> 10)
8522 #define EMAC_REGS__RX_SYMBOL_ERRORS__TYPE                              uint32_t
8523 #define EMAC_REGS__RX_SYMBOL_ERRORS__READ                           0xffffffffU
8524 #define EMAC_REGS__RX_SYMBOL_ERRORS__RCLR                           0x000003ffU
8525 
8526 #endif /* __EMAC_REGS__RX_SYMBOL_ERRORS_MACRO__ */
8527 
8528 
8529 /* macros for rx_symbol_errors */
8530 #define INST_RX_SYMBOL_ERRORS__NUM                                            1
8531 
8532 /* macros for BlueprintGlobalNameSpace::emac_regs::alignment_errors */
8533 #ifndef __EMAC_REGS__ALIGNMENT_ERRORS_MACRO__
8534 #define __EMAC_REGS__ALIGNMENT_ERRORS_MACRO__
8535 
8536 /* macros for field count */
8537 #define EMAC_REGS__ALIGNMENT_ERRORS__COUNT__SHIFT                             0
8538 #define EMAC_REGS__ALIGNMENT_ERRORS__COUNT__WIDTH                            10
8539 #define EMAC_REGS__ALIGNMENT_ERRORS__COUNT__MASK                    0x000003ffU
8540 #define EMAC_REGS__ALIGNMENT_ERRORS__COUNT__RESET                             0
8541 #define EMAC_REGS__ALIGNMENT_ERRORS__COUNT__READ(src) \
8542                     ((uint32_t)(src)\
8543                     & 0x000003ffU)
8544 
8545 /* macros for field reserved_31_10 */
8546 #define EMAC_REGS__ALIGNMENT_ERRORS__RESERVED_31_10__SHIFT                   10
8547 #define EMAC_REGS__ALIGNMENT_ERRORS__RESERVED_31_10__WIDTH                   22
8548 #define EMAC_REGS__ALIGNMENT_ERRORS__RESERVED_31_10__MASK           0xfffffc00U
8549 #define EMAC_REGS__ALIGNMENT_ERRORS__RESERVED_31_10__RESET                    0
8550 #define EMAC_REGS__ALIGNMENT_ERRORS__RESERVED_31_10__READ(src) \
8551                     (((uint32_t)(src)\
8552                     & 0xfffffc00U) >> 10)
8553 #define EMAC_REGS__ALIGNMENT_ERRORS__TYPE                              uint32_t
8554 #define EMAC_REGS__ALIGNMENT_ERRORS__READ                           0xffffffffU
8555 #define EMAC_REGS__ALIGNMENT_ERRORS__RCLR                           0x000003ffU
8556 
8557 #endif /* __EMAC_REGS__ALIGNMENT_ERRORS_MACRO__ */
8558 
8559 
8560 /* macros for alignment_errors */
8561 #define INST_ALIGNMENT_ERRORS__NUM                                            1
8562 
8563 /* macros for BlueprintGlobalNameSpace::emac_regs::rx_resource_errors */
8564 #ifndef __EMAC_REGS__RX_RESOURCE_ERRORS_MACRO__
8565 #define __EMAC_REGS__RX_RESOURCE_ERRORS_MACRO__
8566 
8567 /* macros for field count */
8568 #define EMAC_REGS__RX_RESOURCE_ERRORS__COUNT__SHIFT                           0
8569 #define EMAC_REGS__RX_RESOURCE_ERRORS__COUNT__WIDTH                          18
8570 #define EMAC_REGS__RX_RESOURCE_ERRORS__COUNT__MASK                  0x0003ffffU
8571 #define EMAC_REGS__RX_RESOURCE_ERRORS__COUNT__RESET                           0
8572 #define EMAC_REGS__RX_RESOURCE_ERRORS__COUNT__READ(src) \
8573                     ((uint32_t)(src)\
8574                     & 0x0003ffffU)
8575 
8576 /* macros for field reserved_31_18 */
8577 #define EMAC_REGS__RX_RESOURCE_ERRORS__RESERVED_31_18__SHIFT                 18
8578 #define EMAC_REGS__RX_RESOURCE_ERRORS__RESERVED_31_18__WIDTH                 14
8579 #define EMAC_REGS__RX_RESOURCE_ERRORS__RESERVED_31_18__MASK         0xfffc0000U
8580 #define EMAC_REGS__RX_RESOURCE_ERRORS__RESERVED_31_18__RESET                  0
8581 #define EMAC_REGS__RX_RESOURCE_ERRORS__RESERVED_31_18__READ(src) \
8582                     (((uint32_t)(src)\
8583                     & 0xfffc0000U) >> 18)
8584 #define EMAC_REGS__RX_RESOURCE_ERRORS__TYPE                            uint32_t
8585 #define EMAC_REGS__RX_RESOURCE_ERRORS__READ                         0xffffffffU
8586 #define EMAC_REGS__RX_RESOURCE_ERRORS__RCLR                         0x0003ffffU
8587 
8588 #endif /* __EMAC_REGS__RX_RESOURCE_ERRORS_MACRO__ */
8589 
8590 
8591 /* macros for rx_resource_errors */
8592 #define INST_RX_RESOURCE_ERRORS__NUM                                          1
8593 
8594 /* macros for BlueprintGlobalNameSpace::emac_regs::rx_overruns */
8595 #ifndef __EMAC_REGS__RX_OVERRUNS_MACRO__
8596 #define __EMAC_REGS__RX_OVERRUNS_MACRO__
8597 
8598 /* macros for field count */
8599 #define EMAC_REGS__RX_OVERRUNS__COUNT__SHIFT                                  0
8600 #define EMAC_REGS__RX_OVERRUNS__COUNT__WIDTH                                 10
8601 #define EMAC_REGS__RX_OVERRUNS__COUNT__MASK                         0x000003ffU
8602 #define EMAC_REGS__RX_OVERRUNS__COUNT__RESET                                  0
8603 #define EMAC_REGS__RX_OVERRUNS__COUNT__READ(src) \
8604                     ((uint32_t)(src)\
8605                     & 0x000003ffU)
8606 
8607 /* macros for field reserved_31_10 */
8608 #define EMAC_REGS__RX_OVERRUNS__RESERVED_31_10__SHIFT                        10
8609 #define EMAC_REGS__RX_OVERRUNS__RESERVED_31_10__WIDTH                        22
8610 #define EMAC_REGS__RX_OVERRUNS__RESERVED_31_10__MASK                0xfffffc00U
8611 #define EMAC_REGS__RX_OVERRUNS__RESERVED_31_10__RESET                         0
8612 #define EMAC_REGS__RX_OVERRUNS__RESERVED_31_10__READ(src) \
8613                     (((uint32_t)(src)\
8614                     & 0xfffffc00U) >> 10)
8615 #define EMAC_REGS__RX_OVERRUNS__TYPE                                   uint32_t
8616 #define EMAC_REGS__RX_OVERRUNS__READ                                0xffffffffU
8617 #define EMAC_REGS__RX_OVERRUNS__RCLR                                0x000003ffU
8618 
8619 #endif /* __EMAC_REGS__RX_OVERRUNS_MACRO__ */
8620 
8621 
8622 /* macros for rx_overruns */
8623 #define INST_RX_OVERRUNS__NUM                                                 1
8624 
8625 /* macros for BlueprintGlobalNameSpace::emac_regs::rx_ip_ck_errors */
8626 #ifndef __EMAC_REGS__RX_IP_CK_ERRORS_MACRO__
8627 #define __EMAC_REGS__RX_IP_CK_ERRORS_MACRO__
8628 
8629 /* macros for field count */
8630 #define EMAC_REGS__RX_IP_CK_ERRORS__COUNT__SHIFT                              0
8631 #define EMAC_REGS__RX_IP_CK_ERRORS__COUNT__WIDTH                              8
8632 #define EMAC_REGS__RX_IP_CK_ERRORS__COUNT__MASK                     0x000000ffU
8633 #define EMAC_REGS__RX_IP_CK_ERRORS__COUNT__RESET                              0
8634 #define EMAC_REGS__RX_IP_CK_ERRORS__COUNT__READ(src) \
8635                     ((uint32_t)(src)\
8636                     & 0x000000ffU)
8637 
8638 /* macros for field reserved_31_8 */
8639 #define EMAC_REGS__RX_IP_CK_ERRORS__RESERVED_31_8__SHIFT                      8
8640 #define EMAC_REGS__RX_IP_CK_ERRORS__RESERVED_31_8__WIDTH                     24
8641 #define EMAC_REGS__RX_IP_CK_ERRORS__RESERVED_31_8__MASK             0xffffff00U
8642 #define EMAC_REGS__RX_IP_CK_ERRORS__RESERVED_31_8__RESET                      0
8643 #define EMAC_REGS__RX_IP_CK_ERRORS__RESERVED_31_8__READ(src) \
8644                     (((uint32_t)(src)\
8645                     & 0xffffff00U) >> 8)
8646 #define EMAC_REGS__RX_IP_CK_ERRORS__TYPE                               uint32_t
8647 #define EMAC_REGS__RX_IP_CK_ERRORS__READ                            0xffffffffU
8648 #define EMAC_REGS__RX_IP_CK_ERRORS__RCLR                            0x000000ffU
8649 
8650 #endif /* __EMAC_REGS__RX_IP_CK_ERRORS_MACRO__ */
8651 
8652 
8653 /* macros for rx_ip_ck_errors */
8654 #define INST_RX_IP_CK_ERRORS__NUM                                             1
8655 
8656 /* macros for BlueprintGlobalNameSpace::emac_regs::rx_tcp_ck_errors */
8657 #ifndef __EMAC_REGS__RX_TCP_CK_ERRORS_MACRO__
8658 #define __EMAC_REGS__RX_TCP_CK_ERRORS_MACRO__
8659 
8660 /* macros for field count */
8661 #define EMAC_REGS__RX_TCP_CK_ERRORS__COUNT__SHIFT                             0
8662 #define EMAC_REGS__RX_TCP_CK_ERRORS__COUNT__WIDTH                             8
8663 #define EMAC_REGS__RX_TCP_CK_ERRORS__COUNT__MASK                    0x000000ffU
8664 #define EMAC_REGS__RX_TCP_CK_ERRORS__COUNT__RESET                             0
8665 #define EMAC_REGS__RX_TCP_CK_ERRORS__COUNT__READ(src) \
8666                     ((uint32_t)(src)\
8667                     & 0x000000ffU)
8668 
8669 /* macros for field reserved_31_8 */
8670 #define EMAC_REGS__RX_TCP_CK_ERRORS__RESERVED_31_8__SHIFT                     8
8671 #define EMAC_REGS__RX_TCP_CK_ERRORS__RESERVED_31_8__WIDTH                    24
8672 #define EMAC_REGS__RX_TCP_CK_ERRORS__RESERVED_31_8__MASK            0xffffff00U
8673 #define EMAC_REGS__RX_TCP_CK_ERRORS__RESERVED_31_8__RESET                     0
8674 #define EMAC_REGS__RX_TCP_CK_ERRORS__RESERVED_31_8__READ(src) \
8675                     (((uint32_t)(src)\
8676                     & 0xffffff00U) >> 8)
8677 #define EMAC_REGS__RX_TCP_CK_ERRORS__TYPE                              uint32_t
8678 #define EMAC_REGS__RX_TCP_CK_ERRORS__READ                           0xffffffffU
8679 #define EMAC_REGS__RX_TCP_CK_ERRORS__RCLR                           0x000000ffU
8680 
8681 #endif /* __EMAC_REGS__RX_TCP_CK_ERRORS_MACRO__ */
8682 
8683 
8684 /* macros for rx_tcp_ck_errors */
8685 #define INST_RX_TCP_CK_ERRORS__NUM                                            1
8686 
8687 /* macros for BlueprintGlobalNameSpace::emac_regs::rx_udp_ck_errors */
8688 #ifndef __EMAC_REGS__RX_UDP_CK_ERRORS_MACRO__
8689 #define __EMAC_REGS__RX_UDP_CK_ERRORS_MACRO__
8690 
8691 /* macros for field count */
8692 #define EMAC_REGS__RX_UDP_CK_ERRORS__COUNT__SHIFT                             0
8693 #define EMAC_REGS__RX_UDP_CK_ERRORS__COUNT__WIDTH                             8
8694 #define EMAC_REGS__RX_UDP_CK_ERRORS__COUNT__MASK                    0x000000ffU
8695 #define EMAC_REGS__RX_UDP_CK_ERRORS__COUNT__RESET                             0
8696 #define EMAC_REGS__RX_UDP_CK_ERRORS__COUNT__READ(src) \
8697                     ((uint32_t)(src)\
8698                     & 0x000000ffU)
8699 
8700 /* macros for field reserved_31_8 */
8701 #define EMAC_REGS__RX_UDP_CK_ERRORS__RESERVED_31_8__SHIFT                     8
8702 #define EMAC_REGS__RX_UDP_CK_ERRORS__RESERVED_31_8__WIDTH                    24
8703 #define EMAC_REGS__RX_UDP_CK_ERRORS__RESERVED_31_8__MASK            0xffffff00U
8704 #define EMAC_REGS__RX_UDP_CK_ERRORS__RESERVED_31_8__RESET                     0
8705 #define EMAC_REGS__RX_UDP_CK_ERRORS__RESERVED_31_8__READ(src) \
8706                     (((uint32_t)(src)\
8707                     & 0xffffff00U) >> 8)
8708 #define EMAC_REGS__RX_UDP_CK_ERRORS__TYPE                              uint32_t
8709 #define EMAC_REGS__RX_UDP_CK_ERRORS__READ                           0xffffffffU
8710 #define EMAC_REGS__RX_UDP_CK_ERRORS__RCLR                           0x000000ffU
8711 
8712 #endif /* __EMAC_REGS__RX_UDP_CK_ERRORS_MACRO__ */
8713 
8714 
8715 /* macros for rx_udp_ck_errors */
8716 #define INST_RX_UDP_CK_ERRORS__NUM                                            1
8717 
8718 /* macros for BlueprintGlobalNameSpace::emac_regs::auto_flushed_pkts */
8719 #ifndef __EMAC_REGS__AUTO_FLUSHED_PKTS_MACRO__
8720 #define __EMAC_REGS__AUTO_FLUSHED_PKTS_MACRO__
8721 
8722 /* macros for field count */
8723 #define EMAC_REGS__AUTO_FLUSHED_PKTS__COUNT__SHIFT                            0
8724 #define EMAC_REGS__AUTO_FLUSHED_PKTS__COUNT__WIDTH                           16
8725 #define EMAC_REGS__AUTO_FLUSHED_PKTS__COUNT__MASK                   0x0000ffffU
8726 #define EMAC_REGS__AUTO_FLUSHED_PKTS__COUNT__RESET                            0
8727 #define EMAC_REGS__AUTO_FLUSHED_PKTS__COUNT__READ(src) \
8728                     ((uint32_t)(src)\
8729                     & 0x0000ffffU)
8730 
8731 /* macros for field reserved_31_16 */
8732 #define EMAC_REGS__AUTO_FLUSHED_PKTS__RESERVED_31_16__SHIFT                  16
8733 #define EMAC_REGS__AUTO_FLUSHED_PKTS__RESERVED_31_16__WIDTH                  16
8734 #define EMAC_REGS__AUTO_FLUSHED_PKTS__RESERVED_31_16__MASK          0xffff0000U
8735 #define EMAC_REGS__AUTO_FLUSHED_PKTS__RESERVED_31_16__RESET                   0
8736 #define EMAC_REGS__AUTO_FLUSHED_PKTS__RESERVED_31_16__READ(src) \
8737                     (((uint32_t)(src)\
8738                     & 0xffff0000U) >> 16)
8739 #define EMAC_REGS__AUTO_FLUSHED_PKTS__TYPE                             uint32_t
8740 #define EMAC_REGS__AUTO_FLUSHED_PKTS__READ                          0xffffffffU
8741 #define EMAC_REGS__AUTO_FLUSHED_PKTS__RCLR                          0x0000ffffU
8742 
8743 #endif /* __EMAC_REGS__AUTO_FLUSHED_PKTS_MACRO__ */
8744 
8745 
8746 /* macros for auto_flushed_pkts */
8747 #define INST_AUTO_FLUSHED_PKTS__NUM                                           1
8748 
8749 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_timer_incr_sub_nsec */
8750 #ifndef __EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC_MACRO__
8751 #define __EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC_MACRO__
8752 
8753 /* macros for field sub_ns_incr */
8754 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__SHIFT                0
8755 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__WIDTH               16
8756 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__MASK       0x0000ffffU
8757 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__RESET                0
8758 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__READ(src) \
8759                     ((uint32_t)(src)\
8760                     & 0x0000ffffU)
8761 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__WRITE(src) \
8762                     ((uint32_t)(src)\
8763                     & 0x0000ffffU)
8764 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__MODIFY(dst, src) \
8765                     (dst) = ((dst) &\
8766                     ~0x0000ffffU) | ((uint32_t)(src) &\
8767                     0x0000ffffU)
8768 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR__VERIFY(src) \
8769                     (!(((uint32_t)(src)\
8770                     & ~0x0000ffffU)))
8771 
8772 /* macros for field reserved_23_16 */
8773 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__RESERVED_23_16__SHIFT            16
8774 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__RESERVED_23_16__WIDTH             8
8775 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__RESERVED_23_16__MASK    0x00ff0000U
8776 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__RESERVED_23_16__RESET             0
8777 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__RESERVED_23_16__READ(src) \
8778                     (((uint32_t)(src)\
8779                     & 0x00ff0000U) >> 16)
8780 
8781 /* macros for field sub_ns_incr_lsb */
8782 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__SHIFT           24
8783 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__WIDTH            8
8784 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__MASK   0xff000000U
8785 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__RESET            0
8786 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__READ(src) \
8787                     (((uint32_t)(src)\
8788                     & 0xff000000U) >> 24)
8789 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__WRITE(src) \
8790                     (((uint32_t)(src)\
8791                     << 24) & 0xff000000U)
8792 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__MODIFY(dst, src) \
8793                     (dst) = ((dst) &\
8794                     ~0xff000000U) | (((uint32_t)(src) <<\
8795                     24) & 0xff000000U)
8796 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__SUB_NS_INCR_LSB__VERIFY(src) \
8797                     (!((((uint32_t)(src)\
8798                     << 24) & ~0xff000000U)))
8799 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__TYPE                       uint32_t
8800 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__READ                    0xffffffffU
8801 #define EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC__WRITE                   0xffffffffU
8802 
8803 #endif /* __EMAC_REGS__TSU_TIMER_INCR_SUB_NSEC_MACRO__ */
8804 
8805 
8806 /* macros for tsu_timer_incr_sub_nsec */
8807 #define INST_TSU_TIMER_INCR_SUB_NSEC__NUM                                     1
8808 
8809 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_timer_msb_sec */
8810 #ifndef __EMAC_REGS__TSU_TIMER_MSB_SEC_MACRO__
8811 #define __EMAC_REGS__TSU_TIMER_MSB_SEC_MACRO__
8812 
8813 /* macros for field timer */
8814 #define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__SHIFT                            0
8815 #define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__WIDTH                           16
8816 #define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__MASK                   0x0000ffffU
8817 #define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__RESET                            0
8818 #define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__READ(src) \
8819                     ((uint32_t)(src)\
8820                     & 0x0000ffffU)
8821 #define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__WRITE(src) \
8822                     ((uint32_t)(src)\
8823                     & 0x0000ffffU)
8824 #define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__MODIFY(dst, src) \
8825                     (dst) = ((dst) &\
8826                     ~0x0000ffffU) | ((uint32_t)(src) &\
8827                     0x0000ffffU)
8828 #define EMAC_REGS__TSU_TIMER_MSB_SEC__TIMER__VERIFY(src) \
8829                     (!(((uint32_t)(src)\
8830                     & ~0x0000ffffU)))
8831 
8832 /* macros for field reserved_31_16 */
8833 #define EMAC_REGS__TSU_TIMER_MSB_SEC__RESERVED_31_16__SHIFT                  16
8834 #define EMAC_REGS__TSU_TIMER_MSB_SEC__RESERVED_31_16__WIDTH                  16
8835 #define EMAC_REGS__TSU_TIMER_MSB_SEC__RESERVED_31_16__MASK          0xffff0000U
8836 #define EMAC_REGS__TSU_TIMER_MSB_SEC__RESERVED_31_16__RESET                   0
8837 #define EMAC_REGS__TSU_TIMER_MSB_SEC__RESERVED_31_16__READ(src) \
8838                     (((uint32_t)(src)\
8839                     & 0xffff0000U) >> 16)
8840 #define EMAC_REGS__TSU_TIMER_MSB_SEC__TYPE                             uint32_t
8841 #define EMAC_REGS__TSU_TIMER_MSB_SEC__READ                          0xffffffffU
8842 #define EMAC_REGS__TSU_TIMER_MSB_SEC__WRITE                         0xffffffffU
8843 
8844 #endif /* __EMAC_REGS__TSU_TIMER_MSB_SEC_MACRO__ */
8845 
8846 
8847 /* macros for tsu_timer_msb_sec */
8848 #define INST_TSU_TIMER_MSB_SEC__NUM                                           1
8849 
8850 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_strobe_msb_sec */
8851 #ifndef __EMAC_REGS__TSU_STROBE_MSB_SEC_MACRO__
8852 #define __EMAC_REGS__TSU_STROBE_MSB_SEC_MACRO__
8853 
8854 /* macros for field strobe */
8855 #define EMAC_REGS__TSU_STROBE_MSB_SEC__STROBE__SHIFT                          0
8856 #define EMAC_REGS__TSU_STROBE_MSB_SEC__STROBE__WIDTH                         16
8857 #define EMAC_REGS__TSU_STROBE_MSB_SEC__STROBE__MASK                 0x0000ffffU
8858 #define EMAC_REGS__TSU_STROBE_MSB_SEC__STROBE__RESET                          0
8859 #define EMAC_REGS__TSU_STROBE_MSB_SEC__STROBE__READ(src) \
8860                     ((uint32_t)(src)\
8861                     & 0x0000ffffU)
8862 
8863 /* macros for field reserved_31_16 */
8864 #define EMAC_REGS__TSU_STROBE_MSB_SEC__RESERVED_31_16__SHIFT                 16
8865 #define EMAC_REGS__TSU_STROBE_MSB_SEC__RESERVED_31_16__WIDTH                 16
8866 #define EMAC_REGS__TSU_STROBE_MSB_SEC__RESERVED_31_16__MASK         0xffff0000U
8867 #define EMAC_REGS__TSU_STROBE_MSB_SEC__RESERVED_31_16__RESET                  0
8868 #define EMAC_REGS__TSU_STROBE_MSB_SEC__RESERVED_31_16__READ(src) \
8869                     (((uint32_t)(src)\
8870                     & 0xffff0000U) >> 16)
8871 #define EMAC_REGS__TSU_STROBE_MSB_SEC__TYPE                            uint32_t
8872 #define EMAC_REGS__TSU_STROBE_MSB_SEC__READ                         0xffffffffU
8873 
8874 #endif /* __EMAC_REGS__TSU_STROBE_MSB_SEC_MACRO__ */
8875 
8876 
8877 /* macros for tsu_strobe_msb_sec */
8878 #define INST_TSU_STROBE_MSB_SEC__NUM                                          1
8879 
8880 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_strobe_sec */
8881 #ifndef __EMAC_REGS__TSU_STROBE_SEC_MACRO__
8882 #define __EMAC_REGS__TSU_STROBE_SEC_MACRO__
8883 
8884 /* macros for field strobe */
8885 #define EMAC_REGS__TSU_STROBE_SEC__STROBE__SHIFT                              0
8886 #define EMAC_REGS__TSU_STROBE_SEC__STROBE__WIDTH                             32
8887 #define EMAC_REGS__TSU_STROBE_SEC__STROBE__MASK                     0xffffffffU
8888 #define EMAC_REGS__TSU_STROBE_SEC__STROBE__RESET                              0
8889 #define EMAC_REGS__TSU_STROBE_SEC__STROBE__READ(src) \
8890                     ((uint32_t)(src)\
8891                     & 0xffffffffU)
8892 #define EMAC_REGS__TSU_STROBE_SEC__TYPE                                uint32_t
8893 #define EMAC_REGS__TSU_STROBE_SEC__READ                             0xffffffffU
8894 
8895 #endif /* __EMAC_REGS__TSU_STROBE_SEC_MACRO__ */
8896 
8897 
8898 /* macros for tsu_strobe_sec */
8899 #define INST_TSU_STROBE_SEC__NUM                                              1
8900 
8901 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_strobe_nsec */
8902 #ifndef __EMAC_REGS__TSU_STROBE_NSEC_MACRO__
8903 #define __EMAC_REGS__TSU_STROBE_NSEC_MACRO__
8904 
8905 /* macros for field strobe */
8906 #define EMAC_REGS__TSU_STROBE_NSEC__STROBE__SHIFT                             0
8907 #define EMAC_REGS__TSU_STROBE_NSEC__STROBE__WIDTH                            30
8908 #define EMAC_REGS__TSU_STROBE_NSEC__STROBE__MASK                    0x3fffffffU
8909 #define EMAC_REGS__TSU_STROBE_NSEC__STROBE__RESET                             0
8910 #define EMAC_REGS__TSU_STROBE_NSEC__STROBE__READ(src) \
8911                     ((uint32_t)(src)\
8912                     & 0x3fffffffU)
8913 
8914 /* macros for field reserved_31_30 */
8915 #define EMAC_REGS__TSU_STROBE_NSEC__RESERVED_31_30__SHIFT                    30
8916 #define EMAC_REGS__TSU_STROBE_NSEC__RESERVED_31_30__WIDTH                     2
8917 #define EMAC_REGS__TSU_STROBE_NSEC__RESERVED_31_30__MASK            0xc0000000U
8918 #define EMAC_REGS__TSU_STROBE_NSEC__RESERVED_31_30__RESET                     0
8919 #define EMAC_REGS__TSU_STROBE_NSEC__RESERVED_31_30__READ(src) \
8920                     (((uint32_t)(src)\
8921                     & 0xc0000000U) >> 30)
8922 #define EMAC_REGS__TSU_STROBE_NSEC__TYPE                               uint32_t
8923 #define EMAC_REGS__TSU_STROBE_NSEC__READ                            0xffffffffU
8924 
8925 #endif /* __EMAC_REGS__TSU_STROBE_NSEC_MACRO__ */
8926 
8927 
8928 /* macros for tsu_strobe_nsec */
8929 #define INST_TSU_STROBE_NSEC__NUM                                             1
8930 
8931 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_timer_sec */
8932 #ifndef __EMAC_REGS__TSU_TIMER_SEC_MACRO__
8933 #define __EMAC_REGS__TSU_TIMER_SEC_MACRO__
8934 
8935 /* macros for field timer */
8936 #define EMAC_REGS__TSU_TIMER_SEC__TIMER__SHIFT                                0
8937 #define EMAC_REGS__TSU_TIMER_SEC__TIMER__WIDTH                               32
8938 #define EMAC_REGS__TSU_TIMER_SEC__TIMER__MASK                       0xffffffffU
8939 #define EMAC_REGS__TSU_TIMER_SEC__TIMER__RESET                                0
8940 #define EMAC_REGS__TSU_TIMER_SEC__TIMER__READ(src) \
8941                     ((uint32_t)(src)\
8942                     & 0xffffffffU)
8943 #define EMAC_REGS__TSU_TIMER_SEC__TIMER__WRITE(src) \
8944                     ((uint32_t)(src)\
8945                     & 0xffffffffU)
8946 #define EMAC_REGS__TSU_TIMER_SEC__TIMER__MODIFY(dst, src) \
8947                     (dst) = ((dst) &\
8948                     ~0xffffffffU) | ((uint32_t)(src) &\
8949                     0xffffffffU)
8950 #define EMAC_REGS__TSU_TIMER_SEC__TIMER__VERIFY(src) \
8951                     (!(((uint32_t)(src)\
8952                     & ~0xffffffffU)))
8953 #define EMAC_REGS__TSU_TIMER_SEC__TYPE                                 uint32_t
8954 #define EMAC_REGS__TSU_TIMER_SEC__READ                              0xffffffffU
8955 #define EMAC_REGS__TSU_TIMER_SEC__WRITE                             0xffffffffU
8956 
8957 #endif /* __EMAC_REGS__TSU_TIMER_SEC_MACRO__ */
8958 
8959 
8960 /* macros for tsu_timer_sec */
8961 #define INST_TSU_TIMER_SEC__NUM                                               1
8962 
8963 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_timer_nsec */
8964 #ifndef __EMAC_REGS__TSU_TIMER_NSEC_MACRO__
8965 #define __EMAC_REGS__TSU_TIMER_NSEC_MACRO__
8966 
8967 /* macros for field timer */
8968 #define EMAC_REGS__TSU_TIMER_NSEC__TIMER__SHIFT                               0
8969 #define EMAC_REGS__TSU_TIMER_NSEC__TIMER__WIDTH                              30
8970 #define EMAC_REGS__TSU_TIMER_NSEC__TIMER__MASK                      0x3fffffffU
8971 #define EMAC_REGS__TSU_TIMER_NSEC__TIMER__RESET                               0
8972 #define EMAC_REGS__TSU_TIMER_NSEC__TIMER__READ(src) \
8973                     ((uint32_t)(src)\
8974                     & 0x3fffffffU)
8975 #define EMAC_REGS__TSU_TIMER_NSEC__TIMER__WRITE(src) \
8976                     ((uint32_t)(src)\
8977                     & 0x3fffffffU)
8978 #define EMAC_REGS__TSU_TIMER_NSEC__TIMER__MODIFY(dst, src) \
8979                     (dst) = ((dst) &\
8980                     ~0x3fffffffU) | ((uint32_t)(src) &\
8981                     0x3fffffffU)
8982 #define EMAC_REGS__TSU_TIMER_NSEC__TIMER__VERIFY(src) \
8983                     (!(((uint32_t)(src)\
8984                     & ~0x3fffffffU)))
8985 
8986 /* macros for field reserved_31_30 */
8987 #define EMAC_REGS__TSU_TIMER_NSEC__RESERVED_31_30__SHIFT                     30
8988 #define EMAC_REGS__TSU_TIMER_NSEC__RESERVED_31_30__WIDTH                      2
8989 #define EMAC_REGS__TSU_TIMER_NSEC__RESERVED_31_30__MASK             0xc0000000U
8990 #define EMAC_REGS__TSU_TIMER_NSEC__RESERVED_31_30__RESET                      0
8991 #define EMAC_REGS__TSU_TIMER_NSEC__RESERVED_31_30__READ(src) \
8992                     (((uint32_t)(src)\
8993                     & 0xc0000000U) >> 30)
8994 #define EMAC_REGS__TSU_TIMER_NSEC__TYPE                                uint32_t
8995 #define EMAC_REGS__TSU_TIMER_NSEC__READ                             0xffffffffU
8996 #define EMAC_REGS__TSU_TIMER_NSEC__WRITE                            0xffffffffU
8997 
8998 #endif /* __EMAC_REGS__TSU_TIMER_NSEC_MACRO__ */
8999 
9000 
9001 /* macros for tsu_timer_nsec */
9002 #define INST_TSU_TIMER_NSEC__NUM                                              1
9003 
9004 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_timer_adjust */
9005 #ifndef __EMAC_REGS__TSU_TIMER_ADJUST_MACRO__
9006 #define __EMAC_REGS__TSU_TIMER_ADJUST_MACRO__
9007 
9008 /* macros for field increment_value */
9009 #define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__SHIFT                   0
9010 #define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__WIDTH                  30
9011 #define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__MASK          0x3fffffffU
9012 #define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__RESET                   0
9013 #define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__WRITE(src) \
9014                     ((uint32_t)(src)\
9015                     & 0x3fffffffU)
9016 #define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__MODIFY(dst, src) \
9017                     (dst) = ((dst) &\
9018                     ~0x3fffffffU) | ((uint32_t)(src) &\
9019                     0x3fffffffU)
9020 #define EMAC_REGS__TSU_TIMER_ADJUST__INCREMENT_VALUE__VERIFY(src) \
9021                     (!(((uint32_t)(src)\
9022                     & ~0x3fffffffU)))
9023 
9024 /* macros for field reserved_30_30 */
9025 #define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30_30__SHIFT                   30
9026 #define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30_30__WIDTH                    1
9027 #define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30_30__MASK           0x40000000U
9028 #define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30_30__RESET                    0
9029 #define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30_30__READ(src) \
9030                     (((uint32_t)(src)\
9031                     & 0x40000000U) >> 30)
9032 #define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30_30__SET(dst) \
9033                     (dst) = ((dst) &\
9034                     ~0x40000000U) | ((uint32_t)(1) << 30)
9035 #define EMAC_REGS__TSU_TIMER_ADJUST__RESERVED_30_30__CLR(dst) \
9036                     (dst) = ((dst) &\
9037                     ~0x40000000U) | ((uint32_t)(0) << 30)
9038 
9039 /* macros for field add_subtract */
9040 #define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__SHIFT                     31
9041 #define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__WIDTH                      1
9042 #define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__MASK             0x80000000U
9043 #define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__RESET                      0
9044 #define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__WRITE(src) \
9045                     (((uint32_t)(src)\
9046                     << 31) & 0x80000000U)
9047 #define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__MODIFY(dst, src) \
9048                     (dst) = ((dst) &\
9049                     ~0x80000000U) | (((uint32_t)(src) <<\
9050                     31) & 0x80000000U)
9051 #define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__VERIFY(src) \
9052                     (!((((uint32_t)(src)\
9053                     << 31) & ~0x80000000U)))
9054 #define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__SET(dst) \
9055                     (dst) = ((dst) &\
9056                     ~0x80000000U) | ((uint32_t)(1) << 31)
9057 #define EMAC_REGS__TSU_TIMER_ADJUST__ADD_SUBTRACT__CLR(dst) \
9058                     (dst) = ((dst) &\
9059                     ~0x80000000U) | ((uint32_t)(0) << 31)
9060 #define EMAC_REGS__TSU_TIMER_ADJUST__TYPE                              uint32_t
9061 #define EMAC_REGS__TSU_TIMER_ADJUST__READ                           0x40000000U
9062 #define EMAC_REGS__TSU_TIMER_ADJUST__WRITE                          0x40000000U
9063 
9064 #endif /* __EMAC_REGS__TSU_TIMER_ADJUST_MACRO__ */
9065 
9066 
9067 /* macros for tsu_timer_adjust */
9068 #define INST_TSU_TIMER_ADJUST__NUM                                            1
9069 
9070 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_timer_incr */
9071 #ifndef __EMAC_REGS__TSU_TIMER_INCR_MACRO__
9072 #define __EMAC_REGS__TSU_TIMER_INCR_MACRO__
9073 
9074 /* macros for field ns_increment */
9075 #define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__SHIFT                        0
9076 #define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__WIDTH                        8
9077 #define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__MASK               0x000000ffU
9078 #define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__RESET                        0
9079 #define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__READ(src) \
9080                     ((uint32_t)(src)\
9081                     & 0x000000ffU)
9082 #define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__WRITE(src) \
9083                     ((uint32_t)(src)\
9084                     & 0x000000ffU)
9085 #define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__MODIFY(dst, src) \
9086                     (dst) = ((dst) &\
9087                     ~0x000000ffU) | ((uint32_t)(src) &\
9088                     0x000000ffU)
9089 #define EMAC_REGS__TSU_TIMER_INCR__NS_INCREMENT__VERIFY(src) \
9090                     (!(((uint32_t)(src)\
9091                     & ~0x000000ffU)))
9092 
9093 /* macros for field alt_ns_incr */
9094 #define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__SHIFT                         8
9095 #define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__WIDTH                         8
9096 #define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__MASK                0x0000ff00U
9097 #define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__RESET                         0
9098 #define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__READ(src) \
9099                     (((uint32_t)(src)\
9100                     & 0x0000ff00U) >> 8)
9101 #define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__WRITE(src) \
9102                     (((uint32_t)(src)\
9103                     << 8) & 0x0000ff00U)
9104 #define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__MODIFY(dst, src) \
9105                     (dst) = ((dst) &\
9106                     ~0x0000ff00U) | (((uint32_t)(src) <<\
9107                     8) & 0x0000ff00U)
9108 #define EMAC_REGS__TSU_TIMER_INCR__ALT_NS_INCR__VERIFY(src) \
9109                     (!((((uint32_t)(src)\
9110                     << 8) & ~0x0000ff00U)))
9111 
9112 /* macros for field num_incs */
9113 #define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__SHIFT                           16
9114 #define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__WIDTH                            8
9115 #define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__MASK                   0x00ff0000U
9116 #define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__RESET                            0
9117 #define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__READ(src) \
9118                     (((uint32_t)(src)\
9119                     & 0x00ff0000U) >> 16)
9120 #define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__WRITE(src) \
9121                     (((uint32_t)(src)\
9122                     << 16) & 0x00ff0000U)
9123 #define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__MODIFY(dst, src) \
9124                     (dst) = ((dst) &\
9125                     ~0x00ff0000U) | (((uint32_t)(src) <<\
9126                     16) & 0x00ff0000U)
9127 #define EMAC_REGS__TSU_TIMER_INCR__NUM_INCS__VERIFY(src) \
9128                     (!((((uint32_t)(src)\
9129                     << 16) & ~0x00ff0000U)))
9130 
9131 /* macros for field reserved_31_24 */
9132 #define EMAC_REGS__TSU_TIMER_INCR__RESERVED_31_24__SHIFT                     24
9133 #define EMAC_REGS__TSU_TIMER_INCR__RESERVED_31_24__WIDTH                      8
9134 #define EMAC_REGS__TSU_TIMER_INCR__RESERVED_31_24__MASK             0xff000000U
9135 #define EMAC_REGS__TSU_TIMER_INCR__RESERVED_31_24__RESET                      0
9136 #define EMAC_REGS__TSU_TIMER_INCR__RESERVED_31_24__READ(src) \
9137                     (((uint32_t)(src)\
9138                     & 0xff000000U) >> 24)
9139 #define EMAC_REGS__TSU_TIMER_INCR__TYPE                                uint32_t
9140 #define EMAC_REGS__TSU_TIMER_INCR__READ                             0xffffffffU
9141 #define EMAC_REGS__TSU_TIMER_INCR__WRITE                            0xffffffffU
9142 
9143 #endif /* __EMAC_REGS__TSU_TIMER_INCR_MACRO__ */
9144 
9145 
9146 /* macros for tsu_timer_incr */
9147 #define INST_TSU_TIMER_INCR__NUM                                              1
9148 
9149 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_ptp_tx_sec */
9150 #ifndef __EMAC_REGS__TSU_PTP_TX_SEC_MACRO__
9151 #define __EMAC_REGS__TSU_PTP_TX_SEC_MACRO__
9152 
9153 /* macros for field timer */
9154 #define EMAC_REGS__TSU_PTP_TX_SEC__TIMER__SHIFT                               0
9155 #define EMAC_REGS__TSU_PTP_TX_SEC__TIMER__WIDTH                              32
9156 #define EMAC_REGS__TSU_PTP_TX_SEC__TIMER__MASK                      0xffffffffU
9157 #define EMAC_REGS__TSU_PTP_TX_SEC__TIMER__RESET                               0
9158 #define EMAC_REGS__TSU_PTP_TX_SEC__TIMER__READ(src) \
9159                     ((uint32_t)(src)\
9160                     & 0xffffffffU)
9161 #define EMAC_REGS__TSU_PTP_TX_SEC__TYPE                                uint32_t
9162 #define EMAC_REGS__TSU_PTP_TX_SEC__READ                             0xffffffffU
9163 
9164 #endif /* __EMAC_REGS__TSU_PTP_TX_SEC_MACRO__ */
9165 
9166 
9167 /* macros for tsu_ptp_tx_sec */
9168 #define INST_TSU_PTP_TX_SEC__NUM                                              1
9169 
9170 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_ptp_tx_nsec */
9171 #ifndef __EMAC_REGS__TSU_PTP_TX_NSEC_MACRO__
9172 #define __EMAC_REGS__TSU_PTP_TX_NSEC_MACRO__
9173 
9174 /* macros for field timer */
9175 #define EMAC_REGS__TSU_PTP_TX_NSEC__TIMER__SHIFT                              0
9176 #define EMAC_REGS__TSU_PTP_TX_NSEC__TIMER__WIDTH                             30
9177 #define EMAC_REGS__TSU_PTP_TX_NSEC__TIMER__MASK                     0x3fffffffU
9178 #define EMAC_REGS__TSU_PTP_TX_NSEC__TIMER__RESET                              0
9179 #define EMAC_REGS__TSU_PTP_TX_NSEC__TIMER__READ(src) \
9180                     ((uint32_t)(src)\
9181                     & 0x3fffffffU)
9182 
9183 /* macros for field reserved_31_30 */
9184 #define EMAC_REGS__TSU_PTP_TX_NSEC__RESERVED_31_30__SHIFT                    30
9185 #define EMAC_REGS__TSU_PTP_TX_NSEC__RESERVED_31_30__WIDTH                     2
9186 #define EMAC_REGS__TSU_PTP_TX_NSEC__RESERVED_31_30__MASK            0xc0000000U
9187 #define EMAC_REGS__TSU_PTP_TX_NSEC__RESERVED_31_30__RESET                     0
9188 #define EMAC_REGS__TSU_PTP_TX_NSEC__RESERVED_31_30__READ(src) \
9189                     (((uint32_t)(src)\
9190                     & 0xc0000000U) >> 30)
9191 #define EMAC_REGS__TSU_PTP_TX_NSEC__TYPE                               uint32_t
9192 #define EMAC_REGS__TSU_PTP_TX_NSEC__READ                            0xffffffffU
9193 
9194 #endif /* __EMAC_REGS__TSU_PTP_TX_NSEC_MACRO__ */
9195 
9196 
9197 /* macros for tsu_ptp_tx_nsec */
9198 #define INST_TSU_PTP_TX_NSEC__NUM                                             1
9199 
9200 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_ptp_rx_sec */
9201 #ifndef __EMAC_REGS__TSU_PTP_RX_SEC_MACRO__
9202 #define __EMAC_REGS__TSU_PTP_RX_SEC_MACRO__
9203 
9204 /* macros for field timer */
9205 #define EMAC_REGS__TSU_PTP_RX_SEC__TIMER__SHIFT                               0
9206 #define EMAC_REGS__TSU_PTP_RX_SEC__TIMER__WIDTH                              32
9207 #define EMAC_REGS__TSU_PTP_RX_SEC__TIMER__MASK                      0xffffffffU
9208 #define EMAC_REGS__TSU_PTP_RX_SEC__TIMER__RESET                               0
9209 #define EMAC_REGS__TSU_PTP_RX_SEC__TIMER__READ(src) \
9210                     ((uint32_t)(src)\
9211                     & 0xffffffffU)
9212 #define EMAC_REGS__TSU_PTP_RX_SEC__TYPE                                uint32_t
9213 #define EMAC_REGS__TSU_PTP_RX_SEC__READ                             0xffffffffU
9214 
9215 #endif /* __EMAC_REGS__TSU_PTP_RX_SEC_MACRO__ */
9216 
9217 
9218 /* macros for tsu_ptp_rx_sec */
9219 #define INST_TSU_PTP_RX_SEC__NUM                                              1
9220 
9221 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_ptp_rx_nsec */
9222 #ifndef __EMAC_REGS__TSU_PTP_RX_NSEC_MACRO__
9223 #define __EMAC_REGS__TSU_PTP_RX_NSEC_MACRO__
9224 
9225 /* macros for field timer */
9226 #define EMAC_REGS__TSU_PTP_RX_NSEC__TIMER__SHIFT                              0
9227 #define EMAC_REGS__TSU_PTP_RX_NSEC__TIMER__WIDTH                             30
9228 #define EMAC_REGS__TSU_PTP_RX_NSEC__TIMER__MASK                     0x3fffffffU
9229 #define EMAC_REGS__TSU_PTP_RX_NSEC__TIMER__RESET                              0
9230 #define EMAC_REGS__TSU_PTP_RX_NSEC__TIMER__READ(src) \
9231                     ((uint32_t)(src)\
9232                     & 0x3fffffffU)
9233 
9234 /* macros for field reserved_31_30 */
9235 #define EMAC_REGS__TSU_PTP_RX_NSEC__RESERVED_31_30__SHIFT                    30
9236 #define EMAC_REGS__TSU_PTP_RX_NSEC__RESERVED_31_30__WIDTH                     2
9237 #define EMAC_REGS__TSU_PTP_RX_NSEC__RESERVED_31_30__MASK            0xc0000000U
9238 #define EMAC_REGS__TSU_PTP_RX_NSEC__RESERVED_31_30__RESET                     0
9239 #define EMAC_REGS__TSU_PTP_RX_NSEC__RESERVED_31_30__READ(src) \
9240                     (((uint32_t)(src)\
9241                     & 0xc0000000U) >> 30)
9242 #define EMAC_REGS__TSU_PTP_RX_NSEC__TYPE                               uint32_t
9243 #define EMAC_REGS__TSU_PTP_RX_NSEC__READ                            0xffffffffU
9244 
9245 #endif /* __EMAC_REGS__TSU_PTP_RX_NSEC_MACRO__ */
9246 
9247 
9248 /* macros for tsu_ptp_rx_nsec */
9249 #define INST_TSU_PTP_RX_NSEC__NUM                                             1
9250 
9251 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_peer_tx_sec */
9252 #ifndef __EMAC_REGS__TSU_PEER_TX_SEC_MACRO__
9253 #define __EMAC_REGS__TSU_PEER_TX_SEC_MACRO__
9254 
9255 /* macros for field timer */
9256 #define EMAC_REGS__TSU_PEER_TX_SEC__TIMER__SHIFT                              0
9257 #define EMAC_REGS__TSU_PEER_TX_SEC__TIMER__WIDTH                             32
9258 #define EMAC_REGS__TSU_PEER_TX_SEC__TIMER__MASK                     0xffffffffU
9259 #define EMAC_REGS__TSU_PEER_TX_SEC__TIMER__RESET                              0
9260 #define EMAC_REGS__TSU_PEER_TX_SEC__TIMER__READ(src) \
9261                     ((uint32_t)(src)\
9262                     & 0xffffffffU)
9263 #define EMAC_REGS__TSU_PEER_TX_SEC__TYPE                               uint32_t
9264 #define EMAC_REGS__TSU_PEER_TX_SEC__READ                            0xffffffffU
9265 
9266 #endif /* __EMAC_REGS__TSU_PEER_TX_SEC_MACRO__ */
9267 
9268 
9269 /* macros for tsu_peer_tx_sec */
9270 #define INST_TSU_PEER_TX_SEC__NUM                                             1
9271 
9272 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_peer_tx_nsec */
9273 #ifndef __EMAC_REGS__TSU_PEER_TX_NSEC_MACRO__
9274 #define __EMAC_REGS__TSU_PEER_TX_NSEC_MACRO__
9275 
9276 /* macros for field timer */
9277 #define EMAC_REGS__TSU_PEER_TX_NSEC__TIMER__SHIFT                             0
9278 #define EMAC_REGS__TSU_PEER_TX_NSEC__TIMER__WIDTH                            30
9279 #define EMAC_REGS__TSU_PEER_TX_NSEC__TIMER__MASK                    0x3fffffffU
9280 #define EMAC_REGS__TSU_PEER_TX_NSEC__TIMER__RESET                             0
9281 #define EMAC_REGS__TSU_PEER_TX_NSEC__TIMER__READ(src) \
9282                     ((uint32_t)(src)\
9283                     & 0x3fffffffU)
9284 
9285 /* macros for field reserved_31_30 */
9286 #define EMAC_REGS__TSU_PEER_TX_NSEC__RESERVED_31_30__SHIFT                   30
9287 #define EMAC_REGS__TSU_PEER_TX_NSEC__RESERVED_31_30__WIDTH                    2
9288 #define EMAC_REGS__TSU_PEER_TX_NSEC__RESERVED_31_30__MASK           0xc0000000U
9289 #define EMAC_REGS__TSU_PEER_TX_NSEC__RESERVED_31_30__RESET                    0
9290 #define EMAC_REGS__TSU_PEER_TX_NSEC__RESERVED_31_30__READ(src) \
9291                     (((uint32_t)(src)\
9292                     & 0xc0000000U) >> 30)
9293 #define EMAC_REGS__TSU_PEER_TX_NSEC__TYPE                              uint32_t
9294 #define EMAC_REGS__TSU_PEER_TX_NSEC__READ                           0xffffffffU
9295 
9296 #endif /* __EMAC_REGS__TSU_PEER_TX_NSEC_MACRO__ */
9297 
9298 
9299 /* macros for tsu_peer_tx_nsec */
9300 #define INST_TSU_PEER_TX_NSEC__NUM                                            1
9301 
9302 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_peer_rx_sec */
9303 #ifndef __EMAC_REGS__TSU_PEER_RX_SEC_MACRO__
9304 #define __EMAC_REGS__TSU_PEER_RX_SEC_MACRO__
9305 
9306 /* macros for field timer */
9307 #define EMAC_REGS__TSU_PEER_RX_SEC__TIMER__SHIFT                              0
9308 #define EMAC_REGS__TSU_PEER_RX_SEC__TIMER__WIDTH                             32
9309 #define EMAC_REGS__TSU_PEER_RX_SEC__TIMER__MASK                     0xffffffffU
9310 #define EMAC_REGS__TSU_PEER_RX_SEC__TIMER__RESET                              0
9311 #define EMAC_REGS__TSU_PEER_RX_SEC__TIMER__READ(src) \
9312                     ((uint32_t)(src)\
9313                     & 0xffffffffU)
9314 #define EMAC_REGS__TSU_PEER_RX_SEC__TYPE                               uint32_t
9315 #define EMAC_REGS__TSU_PEER_RX_SEC__READ                            0xffffffffU
9316 
9317 #endif /* __EMAC_REGS__TSU_PEER_RX_SEC_MACRO__ */
9318 
9319 
9320 /* macros for tsu_peer_rx_sec */
9321 #define INST_TSU_PEER_RX_SEC__NUM                                             1
9322 
9323 /* macros for BlueprintGlobalNameSpace::emac_regs::tsu_peer_rx_nsec */
9324 #ifndef __EMAC_REGS__TSU_PEER_RX_NSEC_MACRO__
9325 #define __EMAC_REGS__TSU_PEER_RX_NSEC_MACRO__
9326 
9327 /* macros for field timer */
9328 #define EMAC_REGS__TSU_PEER_RX_NSEC__TIMER__SHIFT                             0
9329 #define EMAC_REGS__TSU_PEER_RX_NSEC__TIMER__WIDTH                            30
9330 #define EMAC_REGS__TSU_PEER_RX_NSEC__TIMER__MASK                    0x3fffffffU
9331 #define EMAC_REGS__TSU_PEER_RX_NSEC__TIMER__RESET                             0
9332 #define EMAC_REGS__TSU_PEER_RX_NSEC__TIMER__READ(src) \
9333                     ((uint32_t)(src)\
9334                     & 0x3fffffffU)
9335 
9336 /* macros for field reserved_31_30 */
9337 #define EMAC_REGS__TSU_PEER_RX_NSEC__RESERVED_31_30__SHIFT                   30
9338 #define EMAC_REGS__TSU_PEER_RX_NSEC__RESERVED_31_30__WIDTH                    2
9339 #define EMAC_REGS__TSU_PEER_RX_NSEC__RESERVED_31_30__MASK           0xc0000000U
9340 #define EMAC_REGS__TSU_PEER_RX_NSEC__RESERVED_31_30__RESET                    0
9341 #define EMAC_REGS__TSU_PEER_RX_NSEC__RESERVED_31_30__READ(src) \
9342                     (((uint32_t)(src)\
9343                     & 0xc0000000U) >> 30)
9344 #define EMAC_REGS__TSU_PEER_RX_NSEC__TYPE                              uint32_t
9345 #define EMAC_REGS__TSU_PEER_RX_NSEC__READ                           0xffffffffU
9346 
9347 #endif /* __EMAC_REGS__TSU_PEER_RX_NSEC_MACRO__ */
9348 
9349 
9350 /* macros for tsu_peer_rx_nsec */
9351 #define INST_TSU_PEER_RX_NSEC__NUM                                            1
9352 
9353 /* macros for BlueprintGlobalNameSpace::emac_regs::pcs_control */
9354 #ifndef __EMAC_REGS__PCS_CONTROL_MACRO__
9355 #define __EMAC_REGS__PCS_CONTROL_MACRO__
9356 
9357 /* macros for field reserved_5_0 */
9358 #define EMAC_REGS__PCS_CONTROL__RESERVED_5_0__SHIFT                           0
9359 #define EMAC_REGS__PCS_CONTROL__RESERVED_5_0__WIDTH                           6
9360 #define EMAC_REGS__PCS_CONTROL__RESERVED_5_0__MASK                  0x0000003fU
9361 #define EMAC_REGS__PCS_CONTROL__RESERVED_5_0__RESET                           0
9362 #define EMAC_REGS__PCS_CONTROL__RESERVED_5_0__READ(src) \
9363                     ((uint32_t)(src)\
9364                     & 0x0000003fU)
9365 
9366 /* macros for field speed_select_bit_0 */
9367 #define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__SHIFT                     6
9368 #define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__WIDTH                     1
9369 #define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__MASK            0x00000040U
9370 #define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__RESET                     1
9371 #define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__READ(src) \
9372                     (((uint32_t)(src)\
9373                     & 0x00000040U) >> 6)
9374 #define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__SET(dst) \
9375                     (dst) = ((dst) &\
9376                     ~0x00000040U) | ((uint32_t)(1) << 6)
9377 #define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_0__CLR(dst) \
9378                     (dst) = ((dst) &\
9379                     ~0x00000040U) | ((uint32_t)(0) << 6)
9380 
9381 /* macros for field collision_test */
9382 #define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__SHIFT                         7
9383 #define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__WIDTH                         1
9384 #define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__MASK                0x00000080U
9385 #define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__RESET                         0
9386 #define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__READ(src) \
9387                     (((uint32_t)(src)\
9388                     & 0x00000080U) >> 7)
9389 #define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__WRITE(src) \
9390                     (((uint32_t)(src)\
9391                     << 7) & 0x00000080U)
9392 #define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__MODIFY(dst, src) \
9393                     (dst) = ((dst) &\
9394                     ~0x00000080U) | (((uint32_t)(src) <<\
9395                     7) & 0x00000080U)
9396 #define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__VERIFY(src) \
9397                     (!((((uint32_t)(src)\
9398                     << 7) & ~0x00000080U)))
9399 #define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__SET(dst) \
9400                     (dst) = ((dst) &\
9401                     ~0x00000080U) | ((uint32_t)(1) << 7)
9402 #define EMAC_REGS__PCS_CONTROL__COLLISION_TEST__CLR(dst) \
9403                     (dst) = ((dst) &\
9404                     ~0x00000080U) | ((uint32_t)(0) << 7)
9405 
9406 /* macros for field mac_duplex_state */
9407 #define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__SHIFT                       8
9408 #define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__WIDTH                       1
9409 #define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__MASK              0x00000100U
9410 #define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__RESET                       0
9411 #define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__READ(src) \
9412                     (((uint32_t)(src)\
9413                     & 0x00000100U) >> 8)
9414 #define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__SET(dst) \
9415                     (dst) = ((dst) &\
9416                     ~0x00000100U) | ((uint32_t)(1) << 8)
9417 #define EMAC_REGS__PCS_CONTROL__MAC_DUPLEX_STATE__CLR(dst) \
9418                     (dst) = ((dst) &\
9419                     ~0x00000100U) | ((uint32_t)(0) << 8)
9420 
9421 /* macros for field restart_auto_neg */
9422 #define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__SHIFT                       9
9423 #define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__WIDTH                       1
9424 #define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__MASK              0x00000200U
9425 #define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__RESET                       0
9426 #define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__READ(src) \
9427                     (((uint32_t)(src)\
9428                     & 0x00000200U) >> 9)
9429 #define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__WRITE(src) \
9430                     (((uint32_t)(src)\
9431                     << 9) & 0x00000200U)
9432 #define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__MODIFY(dst, src) \
9433                     (dst) = ((dst) &\
9434                     ~0x00000200U) | (((uint32_t)(src) <<\
9435                     9) & 0x00000200U)
9436 #define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__VERIFY(src) \
9437                     (!((((uint32_t)(src)\
9438                     << 9) & ~0x00000200U)))
9439 #define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__SET(dst) \
9440                     (dst) = ((dst) &\
9441                     ~0x00000200U) | ((uint32_t)(1) << 9)
9442 #define EMAC_REGS__PCS_CONTROL__RESTART_AUTO_NEG__CLR(dst) \
9443                     (dst) = ((dst) &\
9444                     ~0x00000200U) | ((uint32_t)(0) << 9)
9445 
9446 /* macros for field reserved_11_10 */
9447 #define EMAC_REGS__PCS_CONTROL__RESERVED_11_10__SHIFT                        10
9448 #define EMAC_REGS__PCS_CONTROL__RESERVED_11_10__WIDTH                         2
9449 #define EMAC_REGS__PCS_CONTROL__RESERVED_11_10__MASK                0x00000c00U
9450 #define EMAC_REGS__PCS_CONTROL__RESERVED_11_10__RESET                         0
9451 #define EMAC_REGS__PCS_CONTROL__RESERVED_11_10__READ(src) \
9452                     (((uint32_t)(src)\
9453                     & 0x00000c00U) >> 10)
9454 
9455 /* macros for field enable_auto_neg */
9456 #define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__SHIFT                       12
9457 #define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__WIDTH                        1
9458 #define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__MASK               0x00001000U
9459 #define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__RESET                        1
9460 #define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__READ(src) \
9461                     (((uint32_t)(src)\
9462                     & 0x00001000U) >> 12)
9463 #define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__WRITE(src) \
9464                     (((uint32_t)(src)\
9465                     << 12) & 0x00001000U)
9466 #define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__MODIFY(dst, src) \
9467                     (dst) = ((dst) &\
9468                     ~0x00001000U) | (((uint32_t)(src) <<\
9469                     12) & 0x00001000U)
9470 #define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__VERIFY(src) \
9471                     (!((((uint32_t)(src)\
9472                     << 12) & ~0x00001000U)))
9473 #define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__SET(dst) \
9474                     (dst) = ((dst) &\
9475                     ~0x00001000U) | ((uint32_t)(1) << 12)
9476 #define EMAC_REGS__PCS_CONTROL__ENABLE_AUTO_NEG__CLR(dst) \
9477                     (dst) = ((dst) &\
9478                     ~0x00001000U) | ((uint32_t)(0) << 12)
9479 
9480 /* macros for field speed_select_bit_1 */
9481 #define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__SHIFT                    13
9482 #define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__WIDTH                     1
9483 #define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__MASK            0x00002000U
9484 #define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__RESET                     0
9485 #define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__READ(src) \
9486                     (((uint32_t)(src)\
9487                     & 0x00002000U) >> 13)
9488 #define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__SET(dst) \
9489                     (dst) = ((dst) &\
9490                     ~0x00002000U) | ((uint32_t)(1) << 13)
9491 #define EMAC_REGS__PCS_CONTROL__SPEED_SELECT_BIT_1__CLR(dst) \
9492                     (dst) = ((dst) &\
9493                     ~0x00002000U) | ((uint32_t)(0) << 13)
9494 
9495 /* macros for field loopback_mode */
9496 #define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__SHIFT                         14
9497 #define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__WIDTH                          1
9498 #define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__MASK                 0x00004000U
9499 #define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__RESET                          0
9500 #define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__READ(src) \
9501                     (((uint32_t)(src)\
9502                     & 0x00004000U) >> 14)
9503 #define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__WRITE(src) \
9504                     (((uint32_t)(src)\
9505                     << 14) & 0x00004000U)
9506 #define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__MODIFY(dst, src) \
9507                     (dst) = ((dst) &\
9508                     ~0x00004000U) | (((uint32_t)(src) <<\
9509                     14) & 0x00004000U)
9510 #define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__VERIFY(src) \
9511                     (!((((uint32_t)(src)\
9512                     << 14) & ~0x00004000U)))
9513 #define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__SET(dst) \
9514                     (dst) = ((dst) &\
9515                     ~0x00004000U) | ((uint32_t)(1) << 14)
9516 #define EMAC_REGS__PCS_CONTROL__LOOPBACK_MODE__CLR(dst) \
9517                     (dst) = ((dst) &\
9518                     ~0x00004000U) | ((uint32_t)(0) << 14)
9519 
9520 /* macros for field pcs_software_reset */
9521 #define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__SHIFT                    15
9522 #define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__WIDTH                     1
9523 #define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__MASK            0x00008000U
9524 #define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__RESET                     1
9525 #define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__READ(src) \
9526                     (((uint32_t)(src)\
9527                     & 0x00008000U) >> 15)
9528 #define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__WRITE(src) \
9529                     (((uint32_t)(src)\
9530                     << 15) & 0x00008000U)
9531 #define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__MODIFY(dst, src) \
9532                     (dst) = ((dst) &\
9533                     ~0x00008000U) | (((uint32_t)(src) <<\
9534                     15) & 0x00008000U)
9535 #define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__VERIFY(src) \
9536                     (!((((uint32_t)(src)\
9537                     << 15) & ~0x00008000U)))
9538 #define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__SET(dst) \
9539                     (dst) = ((dst) &\
9540                     ~0x00008000U) | ((uint32_t)(1) << 15)
9541 #define EMAC_REGS__PCS_CONTROL__PCS_SOFTWARE_RESET__CLR(dst) \
9542                     (dst) = ((dst) &\
9543                     ~0x00008000U) | ((uint32_t)(0) << 15)
9544 
9545 /* macros for field reserved_31_16 */
9546 #define EMAC_REGS__PCS_CONTROL__RESERVED_31_16__SHIFT                        16
9547 #define EMAC_REGS__PCS_CONTROL__RESERVED_31_16__WIDTH                        16
9548 #define EMAC_REGS__PCS_CONTROL__RESERVED_31_16__MASK                0xffff0000U
9549 #define EMAC_REGS__PCS_CONTROL__RESERVED_31_16__RESET                         0
9550 #define EMAC_REGS__PCS_CONTROL__RESERVED_31_16__READ(src) \
9551                     (((uint32_t)(src)\
9552                     & 0xffff0000U) >> 16)
9553 #define EMAC_REGS__PCS_CONTROL__TYPE                                   uint32_t
9554 #define EMAC_REGS__PCS_CONTROL__READ                                0xffffffffU
9555 #define EMAC_REGS__PCS_CONTROL__WRITE                               0xffffffffU
9556 
9557 #endif /* __EMAC_REGS__PCS_CONTROL_MACRO__ */
9558 
9559 
9560 /* macros for pcs_control */
9561 #define INST_PCS_CONTROL__NUM                                                 1
9562 
9563 /* macros for BlueprintGlobalNameSpace::emac_regs::pcs_status */
9564 #ifndef __EMAC_REGS__PCS_STATUS_MACRO__
9565 #define __EMAC_REGS__PCS_STATUS_MACRO__
9566 
9567 /* macros for field extended_capabilities */
9568 #define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__SHIFT                   0
9569 #define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__WIDTH                   1
9570 #define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__MASK          0x00000001U
9571 #define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__RESET                   1
9572 #define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__READ(src) \
9573                     ((uint32_t)(src)\
9574                     & 0x00000001U)
9575 #define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__SET(dst) \
9576                     (dst) = ((dst) &\
9577                     ~0x00000001U) | (uint32_t)(1)
9578 #define EMAC_REGS__PCS_STATUS__EXTENDED_CAPABILITIES__CLR(dst) \
9579                     (dst) = ((dst) &\
9580                     ~0x00000001U) | (uint32_t)(0)
9581 
9582 /* macros for field reserved_1 */
9583 #define EMAC_REGS__PCS_STATUS__RESERVED_1__SHIFT                              1
9584 #define EMAC_REGS__PCS_STATUS__RESERVED_1__WIDTH                              1
9585 #define EMAC_REGS__PCS_STATUS__RESERVED_1__MASK                     0x00000002U
9586 #define EMAC_REGS__PCS_STATUS__RESERVED_1__RESET                              0
9587 #define EMAC_REGS__PCS_STATUS__RESERVED_1__READ(src) \
9588                     (((uint32_t)(src)\
9589                     & 0x00000002U) >> 1)
9590 #define EMAC_REGS__PCS_STATUS__RESERVED_1__SET(dst) \
9591                     (dst) = ((dst) &\
9592                     ~0x00000002U) | ((uint32_t)(1) << 1)
9593 #define EMAC_REGS__PCS_STATUS__RESERVED_1__CLR(dst) \
9594                     (dst) = ((dst) &\
9595                     ~0x00000002U) | ((uint32_t)(0) << 1)
9596 
9597 /* macros for field link_status */
9598 #define EMAC_REGS__PCS_STATUS__LINK_STATUS__SHIFT                             2
9599 #define EMAC_REGS__PCS_STATUS__LINK_STATUS__WIDTH                             1
9600 #define EMAC_REGS__PCS_STATUS__LINK_STATUS__MASK                    0x00000004U
9601 #define EMAC_REGS__PCS_STATUS__LINK_STATUS__RESET                             0
9602 #define EMAC_REGS__PCS_STATUS__LINK_STATUS__READ(src) \
9603                     (((uint32_t)(src)\
9604                     & 0x00000004U) >> 2)
9605 #define EMAC_REGS__PCS_STATUS__LINK_STATUS__SET(dst) \
9606                     (dst) = ((dst) &\
9607                     ~0x00000004U) | ((uint32_t)(1) << 2)
9608 #define EMAC_REGS__PCS_STATUS__LINK_STATUS__CLR(dst) \
9609                     (dst) = ((dst) &\
9610                     ~0x00000004U) | ((uint32_t)(0) << 2)
9611 
9612 /* macros for field auto_neg_ability */
9613 #define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__SHIFT                        3
9614 #define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__WIDTH                        1
9615 #define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__MASK               0x00000008U
9616 #define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__RESET                        1
9617 #define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__READ(src) \
9618                     (((uint32_t)(src)\
9619                     & 0x00000008U) >> 3)
9620 #define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__SET(dst) \
9621                     (dst) = ((dst) &\
9622                     ~0x00000008U) | ((uint32_t)(1) << 3)
9623 #define EMAC_REGS__PCS_STATUS__AUTO_NEG_ABILITY__CLR(dst) \
9624                     (dst) = ((dst) &\
9625                     ~0x00000008U) | ((uint32_t)(0) << 3)
9626 
9627 /* macros for field remote_fault */
9628 #define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__SHIFT                            4
9629 #define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__WIDTH                            1
9630 #define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__MASK                   0x00000010U
9631 #define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__RESET                            0
9632 #define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__READ(src) \
9633                     (((uint32_t)(src)\
9634                     & 0x00000010U) >> 4)
9635 #define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__SET(dst) \
9636                     (dst) = ((dst) &\
9637                     ~0x00000010U) | ((uint32_t)(1) << 4)
9638 #define EMAC_REGS__PCS_STATUS__REMOTE_FAULT__CLR(dst) \
9639                     (dst) = ((dst) &\
9640                     ~0x00000010U) | ((uint32_t)(0) << 4)
9641 
9642 /* macros for field auto_neg_complete */
9643 #define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__SHIFT                       5
9644 #define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__WIDTH                       1
9645 #define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__MASK              0x00000020U
9646 #define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__RESET                       0
9647 #define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__READ(src) \
9648                     (((uint32_t)(src)\
9649                     & 0x00000020U) >> 5)
9650 #define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__SET(dst) \
9651                     (dst) = ((dst) &\
9652                     ~0x00000020U) | ((uint32_t)(1) << 5)
9653 #define EMAC_REGS__PCS_STATUS__AUTO_NEG_COMPLETE__CLR(dst) \
9654                     (dst) = ((dst) &\
9655                     ~0x00000020U) | ((uint32_t)(0) << 5)
9656 
9657 /* macros for field reserved_7_6 */
9658 #define EMAC_REGS__PCS_STATUS__RESERVED_7_6__SHIFT                            6
9659 #define EMAC_REGS__PCS_STATUS__RESERVED_7_6__WIDTH                            2
9660 #define EMAC_REGS__PCS_STATUS__RESERVED_7_6__MASK                   0x000000c0U
9661 #define EMAC_REGS__PCS_STATUS__RESERVED_7_6__RESET                            0
9662 #define EMAC_REGS__PCS_STATUS__RESERVED_7_6__READ(src) \
9663                     (((uint32_t)(src)\
9664                     & 0x000000c0U) >> 6)
9665 
9666 /* macros for field extended_status */
9667 #define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__SHIFT                         8
9668 #define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__WIDTH                         1
9669 #define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__MASK                0x00000100U
9670 #define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__RESET                         1
9671 #define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__READ(src) \
9672                     (((uint32_t)(src)\
9673                     & 0x00000100U) >> 8)
9674 #define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__SET(dst) \
9675                     (dst) = ((dst) &\
9676                     ~0x00000100U) | ((uint32_t)(1) << 8)
9677 #define EMAC_REGS__PCS_STATUS__EXTENDED_STATUS__CLR(dst) \
9678                     (dst) = ((dst) &\
9679                     ~0x00000100U) | ((uint32_t)(0) << 8)
9680 
9681 /* macros for field base_100_t2_half_duplex */
9682 #define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__SHIFT                 9
9683 #define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__WIDTH                 1
9684 #define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__MASK        0x00000200U
9685 #define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__RESET                 0
9686 #define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__READ(src) \
9687                     (((uint32_t)(src)\
9688                     & 0x00000200U) >> 9)
9689 #define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__SET(dst) \
9690                     (dst) = ((dst) &\
9691                     ~0x00000200U) | ((uint32_t)(1) << 9)
9692 #define EMAC_REGS__PCS_STATUS__BASE_100_T2_HALF_DUPLEX__CLR(dst) \
9693                     (dst) = ((dst) &\
9694                     ~0x00000200U) | ((uint32_t)(0) << 9)
9695 
9696 /* macros for field base_100_t2_full_duplex */
9697 #define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__SHIFT                10
9698 #define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__WIDTH                 1
9699 #define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__MASK        0x00000400U
9700 #define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__RESET                 0
9701 #define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__READ(src) \
9702                     (((uint32_t)(src)\
9703                     & 0x00000400U) >> 10)
9704 #define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__SET(dst) \
9705                     (dst) = ((dst) &\
9706                     ~0x00000400U) | ((uint32_t)(1) << 10)
9707 #define EMAC_REGS__PCS_STATUS__BASE_100_T2_FULL_DUPLEX__CLR(dst) \
9708                     (dst) = ((dst) &\
9709                     ~0x00000400U) | ((uint32_t)(0) << 10)
9710 
9711 /* macros for field mbps_10_half_duplex */
9712 #define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__SHIFT                    11
9713 #define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__WIDTH                     1
9714 #define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__MASK            0x00000800U
9715 #define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__RESET                     0
9716 #define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__READ(src) \
9717                     (((uint32_t)(src)\
9718                     & 0x00000800U) >> 11)
9719 #define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__SET(dst) \
9720                     (dst) = ((dst) &\
9721                     ~0x00000800U) | ((uint32_t)(1) << 11)
9722 #define EMAC_REGS__PCS_STATUS__MBPS_10_HALF_DUPLEX__CLR(dst) \
9723                     (dst) = ((dst) &\
9724                     ~0x00000800U) | ((uint32_t)(0) << 11)
9725 
9726 /* macros for field mbps_10_full_duplex */
9727 #define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__SHIFT                    12
9728 #define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__WIDTH                     1
9729 #define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__MASK            0x00001000U
9730 #define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__RESET                     0
9731 #define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__READ(src) \
9732                     (((uint32_t)(src)\
9733                     & 0x00001000U) >> 12)
9734 #define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__SET(dst) \
9735                     (dst) = ((dst) &\
9736                     ~0x00001000U) | ((uint32_t)(1) << 12)
9737 #define EMAC_REGS__PCS_STATUS__MBPS_10_FULL_DUPLEX__CLR(dst) \
9738                     (dst) = ((dst) &\
9739                     ~0x00001000U) | ((uint32_t)(0) << 12)
9740 
9741 /* macros for field base_100_x_half_duplex */
9742 #define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__SHIFT                 13
9743 #define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__WIDTH                  1
9744 #define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__MASK         0x00002000U
9745 #define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__RESET                  0
9746 #define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__READ(src) \
9747                     (((uint32_t)(src)\
9748                     & 0x00002000U) >> 13)
9749 #define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__SET(dst) \
9750                     (dst) = ((dst) &\
9751                     ~0x00002000U) | ((uint32_t)(1) << 13)
9752 #define EMAC_REGS__PCS_STATUS__BASE_100_X_HALF_DUPLEX__CLR(dst) \
9753                     (dst) = ((dst) &\
9754                     ~0x00002000U) | ((uint32_t)(0) << 13)
9755 
9756 /* macros for field base_100_x_full_duplex */
9757 #define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__SHIFT                 14
9758 #define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__WIDTH                  1
9759 #define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__MASK         0x00004000U
9760 #define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__RESET                  0
9761 #define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__READ(src) \
9762                     (((uint32_t)(src)\
9763                     & 0x00004000U) >> 14)
9764 #define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__SET(dst) \
9765                     (dst) = ((dst) &\
9766                     ~0x00004000U) | ((uint32_t)(1) << 14)
9767 #define EMAC_REGS__PCS_STATUS__BASE_100_X_FULL_DUPLEX__CLR(dst) \
9768                     (dst) = ((dst) &\
9769                     ~0x00004000U) | ((uint32_t)(0) << 14)
9770 
9771 /* macros for field base_100_t4 */
9772 #define EMAC_REGS__PCS_STATUS__BASE_100_T4__SHIFT                            15
9773 #define EMAC_REGS__PCS_STATUS__BASE_100_T4__WIDTH                             1
9774 #define EMAC_REGS__PCS_STATUS__BASE_100_T4__MASK                    0x00008000U
9775 #define EMAC_REGS__PCS_STATUS__BASE_100_T4__RESET                             0
9776 #define EMAC_REGS__PCS_STATUS__BASE_100_T4__READ(src) \
9777                     (((uint32_t)(src)\
9778                     & 0x00008000U) >> 15)
9779 #define EMAC_REGS__PCS_STATUS__BASE_100_T4__SET(dst) \
9780                     (dst) = ((dst) &\
9781                     ~0x00008000U) | ((uint32_t)(1) << 15)
9782 #define EMAC_REGS__PCS_STATUS__BASE_100_T4__CLR(dst) \
9783                     (dst) = ((dst) &\
9784                     ~0x00008000U) | ((uint32_t)(0) << 15)
9785 
9786 /* macros for field reserved_31_16 */
9787 #define EMAC_REGS__PCS_STATUS__RESERVED_31_16__SHIFT                         16
9788 #define EMAC_REGS__PCS_STATUS__RESERVED_31_16__WIDTH                         16
9789 #define EMAC_REGS__PCS_STATUS__RESERVED_31_16__MASK                 0xffff0000U
9790 #define EMAC_REGS__PCS_STATUS__RESERVED_31_16__RESET                          0
9791 #define EMAC_REGS__PCS_STATUS__RESERVED_31_16__READ(src) \
9792                     (((uint32_t)(src)\
9793                     & 0xffff0000U) >> 16)
9794 #define EMAC_REGS__PCS_STATUS__TYPE                                    uint32_t
9795 #define EMAC_REGS__PCS_STATUS__READ                                 0xffffffffU
9796 
9797 #endif /* __EMAC_REGS__PCS_STATUS_MACRO__ */
9798 
9799 
9800 /* macros for pcs_status */
9801 #define INST_PCS_STATUS__NUM                                                  1
9802 
9803 /* macros for BlueprintGlobalNameSpace::emac_regs::pcs_an_adv */
9804 #ifndef __EMAC_REGS__PCS_AN_ADV_MACRO__
9805 #define __EMAC_REGS__PCS_AN_ADV_MACRO__
9806 
9807 /* macros for field reserved_4_0 */
9808 #define EMAC_REGS__PCS_AN_ADV__RESERVED_4_0__SHIFT                            0
9809 #define EMAC_REGS__PCS_AN_ADV__RESERVED_4_0__WIDTH                            5
9810 #define EMAC_REGS__PCS_AN_ADV__RESERVED_4_0__MASK                   0x0000001fU
9811 #define EMAC_REGS__PCS_AN_ADV__RESERVED_4_0__RESET                            0
9812 #define EMAC_REGS__PCS_AN_ADV__RESERVED_4_0__READ(src) \
9813                     ((uint32_t)(src)\
9814                     & 0x0000001fU)
9815 
9816 /* macros for field full_duplex */
9817 #define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__SHIFT                             5
9818 #define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__WIDTH                             1
9819 #define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__MASK                    0x00000020U
9820 #define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__RESET                             1
9821 #define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__READ(src) \
9822                     (((uint32_t)(src)\
9823                     & 0x00000020U) >> 5)
9824 #define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__WRITE(src) \
9825                     (((uint32_t)(src)\
9826                     << 5) & 0x00000020U)
9827 #define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__MODIFY(dst, src) \
9828                     (dst) = ((dst) &\
9829                     ~0x00000020U) | (((uint32_t)(src) <<\
9830                     5) & 0x00000020U)
9831 #define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__VERIFY(src) \
9832                     (!((((uint32_t)(src)\
9833                     << 5) & ~0x00000020U)))
9834 #define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__SET(dst) \
9835                     (dst) = ((dst) &\
9836                     ~0x00000020U) | ((uint32_t)(1) << 5)
9837 #define EMAC_REGS__PCS_AN_ADV__FULL_DUPLEX__CLR(dst) \
9838                     (dst) = ((dst) &\
9839                     ~0x00000020U) | ((uint32_t)(0) << 5)
9840 
9841 /* macros for field half_duplex */
9842 #define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__SHIFT                             6
9843 #define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__WIDTH                             1
9844 #define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__MASK                    0x00000040U
9845 #define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__RESET                             0
9846 #define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__READ(src) \
9847                     (((uint32_t)(src)\
9848                     & 0x00000040U) >> 6)
9849 #define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__WRITE(src) \
9850                     (((uint32_t)(src)\
9851                     << 6) & 0x00000040U)
9852 #define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__MODIFY(dst, src) \
9853                     (dst) = ((dst) &\
9854                     ~0x00000040U) | (((uint32_t)(src) <<\
9855                     6) & 0x00000040U)
9856 #define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__VERIFY(src) \
9857                     (!((((uint32_t)(src)\
9858                     << 6) & ~0x00000040U)))
9859 #define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__SET(dst) \
9860                     (dst) = ((dst) &\
9861                     ~0x00000040U) | ((uint32_t)(1) << 6)
9862 #define EMAC_REGS__PCS_AN_ADV__HALF_DUPLEX__CLR(dst) \
9863                     (dst) = ((dst) &\
9864                     ~0x00000040U) | ((uint32_t)(0) << 6)
9865 
9866 /* macros for field pause */
9867 #define EMAC_REGS__PCS_AN_ADV__PAUSE__SHIFT                                   7
9868 #define EMAC_REGS__PCS_AN_ADV__PAUSE__WIDTH                                   2
9869 #define EMAC_REGS__PCS_AN_ADV__PAUSE__MASK                          0x00000180U
9870 #define EMAC_REGS__PCS_AN_ADV__PAUSE__RESET                                   0
9871 #define EMAC_REGS__PCS_AN_ADV__PAUSE__READ(src) \
9872                     (((uint32_t)(src)\
9873                     & 0x00000180U) >> 7)
9874 #define EMAC_REGS__PCS_AN_ADV__PAUSE__WRITE(src) \
9875                     (((uint32_t)(src)\
9876                     << 7) & 0x00000180U)
9877 #define EMAC_REGS__PCS_AN_ADV__PAUSE__MODIFY(dst, src) \
9878                     (dst) = ((dst) &\
9879                     ~0x00000180U) | (((uint32_t)(src) <<\
9880                     7) & 0x00000180U)
9881 #define EMAC_REGS__PCS_AN_ADV__PAUSE__VERIFY(src) \
9882                     (!((((uint32_t)(src)\
9883                     << 7) & ~0x00000180U)))
9884 
9885 /* macros for field reserved_11_9 */
9886 #define EMAC_REGS__PCS_AN_ADV__RESERVED_11_9__SHIFT                           9
9887 #define EMAC_REGS__PCS_AN_ADV__RESERVED_11_9__WIDTH                           3
9888 #define EMAC_REGS__PCS_AN_ADV__RESERVED_11_9__MASK                  0x00000e00U
9889 #define EMAC_REGS__PCS_AN_ADV__RESERVED_11_9__RESET                           0
9890 #define EMAC_REGS__PCS_AN_ADV__RESERVED_11_9__READ(src) \
9891                     (((uint32_t)(src)\
9892                     & 0x00000e00U) >> 9)
9893 
9894 /* macros for field remote_fault */
9895 #define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__SHIFT                           12
9896 #define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__WIDTH                            2
9897 #define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__MASK                   0x00003000U
9898 #define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__RESET                            0
9899 #define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__READ(src) \
9900                     (((uint32_t)(src)\
9901                     & 0x00003000U) >> 12)
9902 #define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__WRITE(src) \
9903                     (((uint32_t)(src)\
9904                     << 12) & 0x00003000U)
9905 #define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__MODIFY(dst, src) \
9906                     (dst) = ((dst) &\
9907                     ~0x00003000U) | (((uint32_t)(src) <<\
9908                     12) & 0x00003000U)
9909 #define EMAC_REGS__PCS_AN_ADV__REMOTE_FAULT__VERIFY(src) \
9910                     (!((((uint32_t)(src)\
9911                     << 12) & ~0x00003000U)))
9912 
9913 /* macros for field reserved_14 */
9914 #define EMAC_REGS__PCS_AN_ADV__RESERVED_14__SHIFT                            14
9915 #define EMAC_REGS__PCS_AN_ADV__RESERVED_14__WIDTH                             1
9916 #define EMAC_REGS__PCS_AN_ADV__RESERVED_14__MASK                    0x00004000U
9917 #define EMAC_REGS__PCS_AN_ADV__RESERVED_14__RESET                             0
9918 #define EMAC_REGS__PCS_AN_ADV__RESERVED_14__READ(src) \
9919                     (((uint32_t)(src)\
9920                     & 0x00004000U) >> 14)
9921 #define EMAC_REGS__PCS_AN_ADV__RESERVED_14__SET(dst) \
9922                     (dst) = ((dst) &\
9923                     ~0x00004000U) | ((uint32_t)(1) << 14)
9924 #define EMAC_REGS__PCS_AN_ADV__RESERVED_14__CLR(dst) \
9925                     (dst) = ((dst) &\
9926                     ~0x00004000U) | ((uint32_t)(0) << 14)
9927 
9928 /* macros for field next_page */
9929 #define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__SHIFT                              15
9930 #define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__WIDTH                               1
9931 #define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__MASK                      0x00008000U
9932 #define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__RESET                               0
9933 #define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__READ(src) \
9934                     (((uint32_t)(src)\
9935                     & 0x00008000U) >> 15)
9936 #define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__WRITE(src) \
9937                     (((uint32_t)(src)\
9938                     << 15) & 0x00008000U)
9939 #define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__MODIFY(dst, src) \
9940                     (dst) = ((dst) &\
9941                     ~0x00008000U) | (((uint32_t)(src) <<\
9942                     15) & 0x00008000U)
9943 #define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__VERIFY(src) \
9944                     (!((((uint32_t)(src)\
9945                     << 15) & ~0x00008000U)))
9946 #define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__SET(dst) \
9947                     (dst) = ((dst) &\
9948                     ~0x00008000U) | ((uint32_t)(1) << 15)
9949 #define EMAC_REGS__PCS_AN_ADV__NEXT_PAGE__CLR(dst) \
9950                     (dst) = ((dst) &\
9951                     ~0x00008000U) | ((uint32_t)(0) << 15)
9952 
9953 /* macros for field reserved_31_16 */
9954 #define EMAC_REGS__PCS_AN_ADV__RESERVED_31_16__SHIFT                         16
9955 #define EMAC_REGS__PCS_AN_ADV__RESERVED_31_16__WIDTH                         16
9956 #define EMAC_REGS__PCS_AN_ADV__RESERVED_31_16__MASK                 0xffff0000U
9957 #define EMAC_REGS__PCS_AN_ADV__RESERVED_31_16__RESET                          0
9958 #define EMAC_REGS__PCS_AN_ADV__RESERVED_31_16__READ(src) \
9959                     (((uint32_t)(src)\
9960                     & 0xffff0000U) >> 16)
9961 #define EMAC_REGS__PCS_AN_ADV__TYPE                                    uint32_t
9962 #define EMAC_REGS__PCS_AN_ADV__READ                                 0xffffffffU
9963 #define EMAC_REGS__PCS_AN_ADV__WRITE                                0xffffffffU
9964 
9965 #endif /* __EMAC_REGS__PCS_AN_ADV_MACRO__ */
9966 
9967 
9968 /* macros for pcs_an_adv */
9969 #define INST_PCS_AN_ADV__NUM                                                  1
9970 
9971 /* macros for BlueprintGlobalNameSpace::emac_regs::pcs_an_lp_base */
9972 #ifndef __EMAC_REGS__PCS_AN_LP_BASE_MACRO__
9973 #define __EMAC_REGS__PCS_AN_LP_BASE_MACRO__
9974 
9975 /* macros for field reserved_4_0 */
9976 #define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_4_0__SHIFT                        0
9977 #define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_4_0__WIDTH                        5
9978 #define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_4_0__MASK               0x0000001fU
9979 #define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_4_0__RESET                        0
9980 #define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_4_0__READ(src) \
9981                     ((uint32_t)(src)\
9982                     & 0x0000001fU)
9983 
9984 /* macros for field link_partner_full_duplex */
9985 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__SHIFT            5
9986 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__WIDTH            1
9987 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__MASK   0x00000020U
9988 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__RESET            0
9989 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__READ(src) \
9990                     (((uint32_t)(src)\
9991                     & 0x00000020U) >> 5)
9992 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__SET(dst) \
9993                     (dst) = ((dst) &\
9994                     ~0x00000020U) | ((uint32_t)(1) << 5)
9995 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_FULL_DUPLEX__CLR(dst) \
9996                     (dst) = ((dst) &\
9997                     ~0x00000020U) | ((uint32_t)(0) << 5)
9998 
9999 /* macros for field link_partner_half_duplex */
10000 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__SHIFT            6
10001 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__WIDTH            1
10002 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__MASK   0x00000040U
10003 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__RESET            0
10004 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__READ(src) \
10005                     (((uint32_t)(src)\
10006                     & 0x00000040U) >> 6)
10007 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__SET(dst) \
10008                     (dst) = ((dst) &\
10009                     ~0x00000040U) | ((uint32_t)(1) << 6)
10010 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_HALF_DUPLEX__CLR(dst) \
10011                     (dst) = ((dst) &\
10012                     ~0x00000040U) | ((uint32_t)(0) << 6)
10013 
10014 /* macros for field pause */
10015 #define EMAC_REGS__PCS_AN_LP_BASE__PAUSE__SHIFT                               7
10016 #define EMAC_REGS__PCS_AN_LP_BASE__PAUSE__WIDTH                               2
10017 #define EMAC_REGS__PCS_AN_LP_BASE__PAUSE__MASK                      0x00000180U
10018 #define EMAC_REGS__PCS_AN_LP_BASE__PAUSE__RESET                               0
10019 #define EMAC_REGS__PCS_AN_LP_BASE__PAUSE__READ(src) \
10020                     (((uint32_t)(src)\
10021                     & 0x00000180U) >> 7)
10022 
10023 /* macros for field speed_reserved */
10024 #define EMAC_REGS__PCS_AN_LP_BASE__SPEED_RESERVED__SHIFT                      9
10025 #define EMAC_REGS__PCS_AN_LP_BASE__SPEED_RESERVED__WIDTH                      3
10026 #define EMAC_REGS__PCS_AN_LP_BASE__SPEED_RESERVED__MASK             0x00000e00U
10027 #define EMAC_REGS__PCS_AN_LP_BASE__SPEED_RESERVED__RESET                      0
10028 #define EMAC_REGS__PCS_AN_LP_BASE__SPEED_RESERVED__READ(src) \
10029                     (((uint32_t)(src)\
10030                     & 0x00000e00U) >> 9)
10031 
10032 /* macros for field link_partner_remote_fault_duplex_mode */
10033 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__SHIFT \
10034                     12
10035 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__WIDTH \
10036                     2
10037 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__MASK \
10038                     0x00003000U
10039 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__RESET \
10040                     0
10041 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE__READ(src) \
10042                     (((uint32_t)(src)\
10043                     & 0x00003000U) >> 12)
10044 
10045 /* macros for field link_partner_acknowledge */
10046 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__SHIFT           14
10047 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__WIDTH            1
10048 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__MASK   0x00004000U
10049 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__RESET            0
10050 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__READ(src) \
10051                     (((uint32_t)(src)\
10052                     & 0x00004000U) >> 14)
10053 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__SET(dst) \
10054                     (dst) = ((dst) &\
10055                     ~0x00004000U) | ((uint32_t)(1) << 14)
10056 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_ACKNOWLEDGE__CLR(dst) \
10057                     (dst) = ((dst) &\
10058                     ~0x00004000U) | ((uint32_t)(0) << 14)
10059 
10060 /* macros for field link_partner_next_page_status */
10061 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__SHIFT      15
10062 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__WIDTH       1
10063 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__MASK \
10064                     0x00008000U
10065 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__RESET       0
10066 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__READ(src) \
10067                     (((uint32_t)(src)\
10068                     & 0x00008000U) >> 15)
10069 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__SET(dst) \
10070                     (dst) = ((dst) &\
10071                     ~0x00008000U) | ((uint32_t)(1) << 15)
10072 #define EMAC_REGS__PCS_AN_LP_BASE__LINK_PARTNER_NEXT_PAGE_STATUS__CLR(dst) \
10073                     (dst) = ((dst) &\
10074                     ~0x00008000U) | ((uint32_t)(0) << 15)
10075 
10076 /* macros for field reserved_31_16 */
10077 #define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_31_16__SHIFT                     16
10078 #define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_31_16__WIDTH                     16
10079 #define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_31_16__MASK             0xffff0000U
10080 #define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_31_16__RESET                      0
10081 #define EMAC_REGS__PCS_AN_LP_BASE__RESERVED_31_16__READ(src) \
10082                     (((uint32_t)(src)\
10083                     & 0xffff0000U) >> 16)
10084 #define EMAC_REGS__PCS_AN_LP_BASE__TYPE                                uint32_t
10085 #define EMAC_REGS__PCS_AN_LP_BASE__READ                             0xffffffffU
10086 
10087 #endif /* __EMAC_REGS__PCS_AN_LP_BASE_MACRO__ */
10088 
10089 
10090 /* macros for pcs_an_lp_base */
10091 #define INST_PCS_AN_LP_BASE__NUM                                              1
10092 
10093 /* macros for BlueprintGlobalNameSpace::emac_regs::pcs_an_exp */
10094 #ifndef __EMAC_REGS__PCS_AN_EXP_MACRO__
10095 #define __EMAC_REGS__PCS_AN_EXP_MACRO__
10096 
10097 /* macros for field reserved_0 */
10098 #define EMAC_REGS__PCS_AN_EXP__RESERVED_0__SHIFT                              0
10099 #define EMAC_REGS__PCS_AN_EXP__RESERVED_0__WIDTH                              1
10100 #define EMAC_REGS__PCS_AN_EXP__RESERVED_0__MASK                     0x00000001U
10101 #define EMAC_REGS__PCS_AN_EXP__RESERVED_0__RESET                              0
10102 #define EMAC_REGS__PCS_AN_EXP__RESERVED_0__READ(src) \
10103                     ((uint32_t)(src)\
10104                     & 0x00000001U)
10105 #define EMAC_REGS__PCS_AN_EXP__RESERVED_0__SET(dst) \
10106                     (dst) = ((dst) &\
10107                     ~0x00000001U) | (uint32_t)(1)
10108 #define EMAC_REGS__PCS_AN_EXP__RESERVED_0__CLR(dst) \
10109                     (dst) = ((dst) &\
10110                     ~0x00000001U) | (uint32_t)(0)
10111 
10112 /* macros for field page_received */
10113 #define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__SHIFT                           1
10114 #define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__WIDTH                           1
10115 #define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__MASK                  0x00000002U
10116 #define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__RESET                           0
10117 #define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__READ(src) \
10118                     (((uint32_t)(src)\
10119                     & 0x00000002U) >> 1)
10120 #define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__SET(dst) \
10121                     (dst) = ((dst) &\
10122                     ~0x00000002U) | ((uint32_t)(1) << 1)
10123 #define EMAC_REGS__PCS_AN_EXP__PAGE_RECEIVED__CLR(dst) \
10124                     (dst) = ((dst) &\
10125                     ~0x00000002U) | ((uint32_t)(0) << 1)
10126 
10127 /* macros for field next_page_capability */
10128 #define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__SHIFT                    2
10129 #define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__WIDTH                    1
10130 #define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__MASK           0x00000004U
10131 #define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__RESET                    1
10132 #define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__READ(src) \
10133                     (((uint32_t)(src)\
10134                     & 0x00000004U) >> 2)
10135 #define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__SET(dst) \
10136                     (dst) = ((dst) &\
10137                     ~0x00000004U) | ((uint32_t)(1) << 2)
10138 #define EMAC_REGS__PCS_AN_EXP__NEXT_PAGE_CAPABILITY__CLR(dst) \
10139                     (dst) = ((dst) &\
10140                     ~0x00000004U) | ((uint32_t)(0) << 2)
10141 
10142 /* macros for field reserved_31_3 */
10143 #define EMAC_REGS__PCS_AN_EXP__RESERVED_31_3__SHIFT                           3
10144 #define EMAC_REGS__PCS_AN_EXP__RESERVED_31_3__WIDTH                          29
10145 #define EMAC_REGS__PCS_AN_EXP__RESERVED_31_3__MASK                  0xfffffff8U
10146 #define EMAC_REGS__PCS_AN_EXP__RESERVED_31_3__RESET                           0
10147 #define EMAC_REGS__PCS_AN_EXP__RESERVED_31_3__READ(src) \
10148                     (((uint32_t)(src)\
10149                     & 0xfffffff8U) >> 3)
10150 #define EMAC_REGS__PCS_AN_EXP__TYPE                                    uint32_t
10151 #define EMAC_REGS__PCS_AN_EXP__READ                                 0xffffffffU
10152 
10153 #endif /* __EMAC_REGS__PCS_AN_EXP_MACRO__ */
10154 
10155 
10156 /* macros for pcs_an_exp */
10157 #define INST_PCS_AN_EXP__NUM                                                  1
10158 
10159 /* macros for BlueprintGlobalNameSpace::emac_regs::pcs_an_np_tx */
10160 #ifndef __EMAC_REGS__PCS_AN_NP_TX_MACRO__
10161 #define __EMAC_REGS__PCS_AN_NP_TX_MACRO__
10162 
10163 /* macros for field message */
10164 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__SHIFT                               0
10165 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__WIDTH                              11
10166 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__MASK                      0x000007ffU
10167 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__RESET                               0
10168 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__READ(src) \
10169                     ((uint32_t)(src)\
10170                     & 0x000007ffU)
10171 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__WRITE(src) \
10172                     ((uint32_t)(src)\
10173                     & 0x000007ffU)
10174 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__MODIFY(dst, src) \
10175                     (dst) = ((dst) &\
10176                     ~0x000007ffU) | ((uint32_t)(src) &\
10177                     0x000007ffU)
10178 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE__VERIFY(src) \
10179                     (!(((uint32_t)(src)\
10180                     & ~0x000007ffU)))
10181 
10182 /* macros for field reserved_11 */
10183 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__SHIFT                          11
10184 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__WIDTH                           1
10185 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__MASK                  0x00000800U
10186 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__RESET                           0
10187 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__READ(src) \
10188                     (((uint32_t)(src)\
10189                     & 0x00000800U) >> 11)
10190 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__SET(dst) \
10191                     (dst) = ((dst) &\
10192                     ~0x00000800U) | ((uint32_t)(1) << 11)
10193 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_11__CLR(dst) \
10194                     (dst) = ((dst) &\
10195                     ~0x00000800U) | ((uint32_t)(0) << 11)
10196 
10197 /* macros for field acknowledge_2 */
10198 #define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__SHIFT                        12
10199 #define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__WIDTH                         1
10200 #define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__MASK                0x00001000U
10201 #define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__RESET                         0
10202 #define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__READ(src) \
10203                     (((uint32_t)(src)\
10204                     & 0x00001000U) >> 12)
10205 #define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__WRITE(src) \
10206                     (((uint32_t)(src)\
10207                     << 12) & 0x00001000U)
10208 #define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__MODIFY(dst, src) \
10209                     (dst) = ((dst) &\
10210                     ~0x00001000U) | (((uint32_t)(src) <<\
10211                     12) & 0x00001000U)
10212 #define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__VERIFY(src) \
10213                     (!((((uint32_t)(src)\
10214                     << 12) & ~0x00001000U)))
10215 #define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__SET(dst) \
10216                     (dst) = ((dst) &\
10217                     ~0x00001000U) | ((uint32_t)(1) << 12)
10218 #define EMAC_REGS__PCS_AN_NP_TX__ACKNOWLEDGE_2__CLR(dst) \
10219                     (dst) = ((dst) &\
10220                     ~0x00001000U) | ((uint32_t)(0) << 12)
10221 
10222 /* macros for field message_page_indicator */
10223 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__SHIFT               13
10224 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__WIDTH                1
10225 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__MASK       0x00002000U
10226 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__RESET                0
10227 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__READ(src) \
10228                     (((uint32_t)(src)\
10229                     & 0x00002000U) >> 13)
10230 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__WRITE(src) \
10231                     (((uint32_t)(src)\
10232                     << 13) & 0x00002000U)
10233 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__MODIFY(dst, src) \
10234                     (dst) = ((dst) &\
10235                     ~0x00002000U) | (((uint32_t)(src) <<\
10236                     13) & 0x00002000U)
10237 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__VERIFY(src) \
10238                     (!((((uint32_t)(src)\
10239                     << 13) & ~0x00002000U)))
10240 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__SET(dst) \
10241                     (dst) = ((dst) &\
10242                     ~0x00002000U) | ((uint32_t)(1) << 13)
10243 #define EMAC_REGS__PCS_AN_NP_TX__MESSAGE_PAGE_INDICATOR__CLR(dst) \
10244                     (dst) = ((dst) &\
10245                     ~0x00002000U) | ((uint32_t)(0) << 13)
10246 
10247 /* macros for field reserved_14 */
10248 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__SHIFT                          14
10249 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__WIDTH                           1
10250 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__MASK                  0x00004000U
10251 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__RESET                           0
10252 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__READ(src) \
10253                     (((uint32_t)(src)\
10254                     & 0x00004000U) >> 14)
10255 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__SET(dst) \
10256                     (dst) = ((dst) &\
10257                     ~0x00004000U) | ((uint32_t)(1) << 14)
10258 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_14__CLR(dst) \
10259                     (dst) = ((dst) &\
10260                     ~0x00004000U) | ((uint32_t)(0) << 14)
10261 
10262 /* macros for field next_page_to_transmit */
10263 #define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__SHIFT                15
10264 #define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__WIDTH                 1
10265 #define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__MASK        0x00008000U
10266 #define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__RESET                 0
10267 #define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__READ(src) \
10268                     (((uint32_t)(src)\
10269                     & 0x00008000U) >> 15)
10270 #define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__WRITE(src) \
10271                     (((uint32_t)(src)\
10272                     << 15) & 0x00008000U)
10273 #define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__MODIFY(dst, src) \
10274                     (dst) = ((dst) &\
10275                     ~0x00008000U) | (((uint32_t)(src) <<\
10276                     15) & 0x00008000U)
10277 #define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__VERIFY(src) \
10278                     (!((((uint32_t)(src)\
10279                     << 15) & ~0x00008000U)))
10280 #define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__SET(dst) \
10281                     (dst) = ((dst) &\
10282                     ~0x00008000U) | ((uint32_t)(1) << 15)
10283 #define EMAC_REGS__PCS_AN_NP_TX__NEXT_PAGE_TO_TRANSMIT__CLR(dst) \
10284                     (dst) = ((dst) &\
10285                     ~0x00008000U) | ((uint32_t)(0) << 15)
10286 
10287 /* macros for field reserved_31_16 */
10288 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_31_16__SHIFT                       16
10289 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_31_16__WIDTH                       16
10290 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_31_16__MASK               0xffff0000U
10291 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_31_16__RESET                        0
10292 #define EMAC_REGS__PCS_AN_NP_TX__RESERVED_31_16__READ(src) \
10293                     (((uint32_t)(src)\
10294                     & 0xffff0000U) >> 16)
10295 #define EMAC_REGS__PCS_AN_NP_TX__TYPE                                  uint32_t
10296 #define EMAC_REGS__PCS_AN_NP_TX__READ                               0xffffffffU
10297 #define EMAC_REGS__PCS_AN_NP_TX__WRITE                              0xffffffffU
10298 
10299 #endif /* __EMAC_REGS__PCS_AN_NP_TX_MACRO__ */
10300 
10301 
10302 /* macros for pcs_an_np_tx */
10303 #define INST_PCS_AN_NP_TX__NUM                                                1
10304 
10305 /* macros for BlueprintGlobalNameSpace::emac_regs::pcs_an_lp_np */
10306 #ifndef __EMAC_REGS__PCS_AN_LP_NP_MACRO__
10307 #define __EMAC_REGS__PCS_AN_LP_NP_MACRO__
10308 
10309 /* macros for field message */
10310 #define EMAC_REGS__PCS_AN_LP_NP__MESSAGE__SHIFT                               0
10311 #define EMAC_REGS__PCS_AN_LP_NP__MESSAGE__WIDTH                              11
10312 #define EMAC_REGS__PCS_AN_LP_NP__MESSAGE__MASK                      0x000007ffU
10313 #define EMAC_REGS__PCS_AN_LP_NP__MESSAGE__RESET                               0
10314 #define EMAC_REGS__PCS_AN_LP_NP__MESSAGE__READ(src) \
10315                     ((uint32_t)(src)\
10316                     & 0x000007ffU)
10317 
10318 /* macros for field toggle */
10319 #define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__SHIFT                               11
10320 #define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__WIDTH                                1
10321 #define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__MASK                       0x00000800U
10322 #define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__RESET                                0
10323 #define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__READ(src) \
10324                     (((uint32_t)(src)\
10325                     & 0x00000800U) >> 11)
10326 #define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__SET(dst) \
10327                     (dst) = ((dst) &\
10328                     ~0x00000800U) | ((uint32_t)(1) << 11)
10329 #define EMAC_REGS__PCS_AN_LP_NP__TOGGLE__CLR(dst) \
10330                     (dst) = ((dst) &\
10331                     ~0x00000800U) | ((uint32_t)(0) << 11)
10332 
10333 /* macros for field acknowledge_2 */
10334 #define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__SHIFT                        12
10335 #define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__WIDTH                         1
10336 #define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__MASK                0x00001000U
10337 #define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__RESET                         0
10338 #define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__READ(src) \
10339                     (((uint32_t)(src)\
10340                     & 0x00001000U) >> 12)
10341 #define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__SET(dst) \
10342                     (dst) = ((dst) &\
10343                     ~0x00001000U) | ((uint32_t)(1) << 12)
10344 #define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE_2__CLR(dst) \
10345                     (dst) = ((dst) &\
10346                     ~0x00001000U) | ((uint32_t)(0) << 12)
10347 
10348 /* macros for field message_page_indicator */
10349 #define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__SHIFT               13
10350 #define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__WIDTH                1
10351 #define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__MASK       0x00002000U
10352 #define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__RESET                0
10353 #define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__READ(src) \
10354                     (((uint32_t)(src)\
10355                     & 0x00002000U) >> 13)
10356 #define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__SET(dst) \
10357                     (dst) = ((dst) &\
10358                     ~0x00002000U) | ((uint32_t)(1) << 13)
10359 #define EMAC_REGS__PCS_AN_LP_NP__MESSAGE_PAGE_INDICATOR__CLR(dst) \
10360                     (dst) = ((dst) &\
10361                     ~0x00002000U) | ((uint32_t)(0) << 13)
10362 
10363 /* macros for field acknowledge */
10364 #define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__SHIFT                          14
10365 #define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__WIDTH                           1
10366 #define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__MASK                  0x00004000U
10367 #define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__RESET                           0
10368 #define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__READ(src) \
10369                     (((uint32_t)(src)\
10370                     & 0x00004000U) >> 14)
10371 #define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__SET(dst) \
10372                     (dst) = ((dst) &\
10373                     ~0x00004000U) | ((uint32_t)(1) << 14)
10374 #define EMAC_REGS__PCS_AN_LP_NP__ACKNOWLEDGE__CLR(dst) \
10375                     (dst) = ((dst) &\
10376                     ~0x00004000U) | ((uint32_t)(0) << 14)
10377 
10378 /* macros for field next_page_to_receive */
10379 #define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__SHIFT                 15
10380 #define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__WIDTH                  1
10381 #define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__MASK         0x00008000U
10382 #define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__RESET                  0
10383 #define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__READ(src) \
10384                     (((uint32_t)(src)\
10385                     & 0x00008000U) >> 15)
10386 #define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__SET(dst) \
10387                     (dst) = ((dst) &\
10388                     ~0x00008000U) | ((uint32_t)(1) << 15)
10389 #define EMAC_REGS__PCS_AN_LP_NP__NEXT_PAGE_TO_RECEIVE__CLR(dst) \
10390                     (dst) = ((dst) &\
10391                     ~0x00008000U) | ((uint32_t)(0) << 15)
10392 
10393 /* macros for field reserved_31_16 */
10394 #define EMAC_REGS__PCS_AN_LP_NP__RESERVED_31_16__SHIFT                       16
10395 #define EMAC_REGS__PCS_AN_LP_NP__RESERVED_31_16__WIDTH                       16
10396 #define EMAC_REGS__PCS_AN_LP_NP__RESERVED_31_16__MASK               0xffff0000U
10397 #define EMAC_REGS__PCS_AN_LP_NP__RESERVED_31_16__RESET                        0
10398 #define EMAC_REGS__PCS_AN_LP_NP__RESERVED_31_16__READ(src) \
10399                     (((uint32_t)(src)\
10400                     & 0xffff0000U) >> 16)
10401 #define EMAC_REGS__PCS_AN_LP_NP__TYPE                                  uint32_t
10402 #define EMAC_REGS__PCS_AN_LP_NP__READ                               0xffffffffU
10403 
10404 #endif /* __EMAC_REGS__PCS_AN_LP_NP_MACRO__ */
10405 
10406 
10407 /* macros for pcs_an_lp_np */
10408 #define INST_PCS_AN_LP_NP__NUM                                                1
10409 
10410 /* macros for BlueprintGlobalNameSpace::emac_regs::pcs_an_ext_status */
10411 #ifndef __EMAC_REGS__PCS_AN_EXT_STATUS_MACRO__
10412 #define __EMAC_REGS__PCS_AN_EXT_STATUS_MACRO__
10413 
10414 /* macros for field reserved_11_0 */
10415 #define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_11_0__SHIFT                    0
10416 #define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_11_0__WIDTH                   12
10417 #define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_11_0__MASK           0x00000fffU
10418 #define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_11_0__RESET                    0
10419 #define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_11_0__READ(src) \
10420                     ((uint32_t)(src)\
10421                     & 0x00000fffU)
10422 
10423 /* macros for field half_duplex_1000base_t */
10424 #define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__SHIFT          12
10425 #define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__WIDTH           1
10426 #define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__MASK  0x00001000U
10427 #define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__RESET           0
10428 #define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__READ(src) \
10429                     (((uint32_t)(src)\
10430                     & 0x00001000U) >> 12)
10431 #define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__SET(dst) \
10432                     (dst) = ((dst) &\
10433                     ~0x00001000U) | ((uint32_t)(1) << 12)
10434 #define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_T__CLR(dst) \
10435                     (dst) = ((dst) &\
10436                     ~0x00001000U) | ((uint32_t)(0) << 12)
10437 
10438 /* macros for field full_duplex_1000base_t */
10439 #define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__SHIFT          13
10440 #define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__WIDTH           1
10441 #define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__MASK  0x00002000U
10442 #define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__RESET           0
10443 #define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__READ(src) \
10444                     (((uint32_t)(src)\
10445                     & 0x00002000U) >> 13)
10446 #define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__SET(dst) \
10447                     (dst) = ((dst) &\
10448                     ~0x00002000U) | ((uint32_t)(1) << 13)
10449 #define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_T__CLR(dst) \
10450                     (dst) = ((dst) &\
10451                     ~0x00002000U) | ((uint32_t)(0) << 13)
10452 
10453 /* macros for field half_duplex_1000base_x */
10454 #define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__SHIFT          14
10455 #define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__WIDTH           1
10456 #define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__MASK  0x00004000U
10457 #define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__RESET           0
10458 #define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__READ(src) \
10459                     (((uint32_t)(src)\
10460                     & 0x00004000U) >> 14)
10461 #define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__SET(dst) \
10462                     (dst) = ((dst) &\
10463                     ~0x00004000U) | ((uint32_t)(1) << 14)
10464 #define EMAC_REGS__PCS_AN_EXT_STATUS__HALF_DUPLEX_1000BASE_X__CLR(dst) \
10465                     (dst) = ((dst) &\
10466                     ~0x00004000U) | ((uint32_t)(0) << 14)
10467 
10468 /* macros for field full_duplex_1000base_x */
10469 #define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__SHIFT          15
10470 #define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__WIDTH           1
10471 #define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__MASK  0x00008000U
10472 #define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__RESET           1
10473 #define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__READ(src) \
10474                     (((uint32_t)(src)\
10475                     & 0x00008000U) >> 15)
10476 #define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__SET(dst) \
10477                     (dst) = ((dst) &\
10478                     ~0x00008000U) | ((uint32_t)(1) << 15)
10479 #define EMAC_REGS__PCS_AN_EXT_STATUS__FULL_DUPLEX_1000BASE_X__CLR(dst) \
10480                     (dst) = ((dst) &\
10481                     ~0x00008000U) | ((uint32_t)(0) << 15)
10482 
10483 /* macros for field reserved_31_16 */
10484 #define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_31_16__SHIFT                  16
10485 #define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_31_16__WIDTH                  16
10486 #define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_31_16__MASK          0xffff0000U
10487 #define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_31_16__RESET                   0
10488 #define EMAC_REGS__PCS_AN_EXT_STATUS__RESERVED_31_16__READ(src) \
10489                     (((uint32_t)(src)\
10490                     & 0xffff0000U) >> 16)
10491 #define EMAC_REGS__PCS_AN_EXT_STATUS__TYPE                             uint32_t
10492 #define EMAC_REGS__PCS_AN_EXT_STATUS__READ                          0xffffffffU
10493 
10494 #endif /* __EMAC_REGS__PCS_AN_EXT_STATUS_MACRO__ */
10495 
10496 
10497 /* macros for pcs_an_ext_status */
10498 #define INST_PCS_AN_EXT_STATUS__NUM                                           1
10499 
10500 /* macros for BlueprintGlobalNameSpace::emac_regs::tx_pause_quantum1 */
10501 #ifndef __EMAC_REGS__TX_PAUSE_QUANTUM1_MACRO__
10502 #define __EMAC_REGS__TX_PAUSE_QUANTUM1_MACRO__
10503 
10504 /* macros for field quantum_p2 */
10505 #define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__SHIFT                       0
10506 #define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__WIDTH                      16
10507 #define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__MASK              0x0000ffffU
10508 #define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__RESET                  0xFFFF
10509 #define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__READ(src) \
10510                     ((uint32_t)(src)\
10511                     & 0x0000ffffU)
10512 #define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__WRITE(src) \
10513                     ((uint32_t)(src)\
10514                     & 0x0000ffffU)
10515 #define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__MODIFY(dst, src) \
10516                     (dst) = ((dst) &\
10517                     ~0x0000ffffU) | ((uint32_t)(src) &\
10518                     0x0000ffffU)
10519 #define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P2__VERIFY(src) \
10520                     (!(((uint32_t)(src)\
10521                     & ~0x0000ffffU)))
10522 
10523 /* macros for field quantum_p3 */
10524 #define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__SHIFT                      16
10525 #define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__WIDTH                      16
10526 #define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__MASK              0xffff0000U
10527 #define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__RESET                  0xFFFF
10528 #define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__READ(src) \
10529                     (((uint32_t)(src)\
10530                     & 0xffff0000U) >> 16)
10531 #define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__WRITE(src) \
10532                     (((uint32_t)(src)\
10533                     << 16) & 0xffff0000U)
10534 #define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__MODIFY(dst, src) \
10535                     (dst) = ((dst) &\
10536                     ~0xffff0000U) | (((uint32_t)(src) <<\
10537                     16) & 0xffff0000U)
10538 #define EMAC_REGS__TX_PAUSE_QUANTUM1__QUANTUM_P3__VERIFY(src) \
10539                     (!((((uint32_t)(src)\
10540                     << 16) & ~0xffff0000U)))
10541 #define EMAC_REGS__TX_PAUSE_QUANTUM1__TYPE                             uint32_t
10542 #define EMAC_REGS__TX_PAUSE_QUANTUM1__READ                          0xffffffffU
10543 #define EMAC_REGS__TX_PAUSE_QUANTUM1__WRITE                         0xffffffffU
10544 
10545 #endif /* __EMAC_REGS__TX_PAUSE_QUANTUM1_MACRO__ */
10546 
10547 
10548 /* macros for tx_pause_quantum1 */
10549 #define INST_TX_PAUSE_QUANTUM1__NUM                                           1
10550 
10551 /* macros for BlueprintGlobalNameSpace::emac_regs::tx_pause_quantum2 */
10552 #ifndef __EMAC_REGS__TX_PAUSE_QUANTUM2_MACRO__
10553 #define __EMAC_REGS__TX_PAUSE_QUANTUM2_MACRO__
10554 
10555 /* macros for field quantum_p4 */
10556 #define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__SHIFT                       0
10557 #define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__WIDTH                      16
10558 #define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__MASK              0x0000ffffU
10559 #define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__RESET                  0xFFFF
10560 #define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__READ(src) \
10561                     ((uint32_t)(src)\
10562                     & 0x0000ffffU)
10563 #define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__WRITE(src) \
10564                     ((uint32_t)(src)\
10565                     & 0x0000ffffU)
10566 #define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__MODIFY(dst, src) \
10567                     (dst) = ((dst) &\
10568                     ~0x0000ffffU) | ((uint32_t)(src) &\
10569                     0x0000ffffU)
10570 #define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P4__VERIFY(src) \
10571                     (!(((uint32_t)(src)\
10572                     & ~0x0000ffffU)))
10573 
10574 /* macros for field quantum_p5 */
10575 #define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__SHIFT                      16
10576 #define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__WIDTH                      16
10577 #define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__MASK              0xffff0000U
10578 #define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__RESET                  0xFFFF
10579 #define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__READ(src) \
10580                     (((uint32_t)(src)\
10581                     & 0xffff0000U) >> 16)
10582 #define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__WRITE(src) \
10583                     (((uint32_t)(src)\
10584                     << 16) & 0xffff0000U)
10585 #define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__MODIFY(dst, src) \
10586                     (dst) = ((dst) &\
10587                     ~0xffff0000U) | (((uint32_t)(src) <<\
10588                     16) & 0xffff0000U)
10589 #define EMAC_REGS__TX_PAUSE_QUANTUM2__QUANTUM_P5__VERIFY(src) \
10590                     (!((((uint32_t)(src)\
10591                     << 16) & ~0xffff0000U)))
10592 #define EMAC_REGS__TX_PAUSE_QUANTUM2__TYPE                             uint32_t
10593 #define EMAC_REGS__TX_PAUSE_QUANTUM2__READ                          0xffffffffU
10594 #define EMAC_REGS__TX_PAUSE_QUANTUM2__WRITE                         0xffffffffU
10595 
10596 #endif /* __EMAC_REGS__TX_PAUSE_QUANTUM2_MACRO__ */
10597 
10598 
10599 /* macros for tx_pause_quantum2 */
10600 #define INST_TX_PAUSE_QUANTUM2__NUM                                           1
10601 
10602 /* macros for BlueprintGlobalNameSpace::emac_regs::tx_pause_quantum3 */
10603 #ifndef __EMAC_REGS__TX_PAUSE_QUANTUM3_MACRO__
10604 #define __EMAC_REGS__TX_PAUSE_QUANTUM3_MACRO__
10605 
10606 /* macros for field quantum_p6 */
10607 #define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__SHIFT                       0
10608 #define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__WIDTH                      16
10609 #define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__MASK              0x0000ffffU
10610 #define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__RESET                  0xFFFF
10611 #define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__READ(src) \
10612                     ((uint32_t)(src)\
10613                     & 0x0000ffffU)
10614 #define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__WRITE(src) \
10615                     ((uint32_t)(src)\
10616                     & 0x0000ffffU)
10617 #define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__MODIFY(dst, src) \
10618                     (dst) = ((dst) &\
10619                     ~0x0000ffffU) | ((uint32_t)(src) &\
10620                     0x0000ffffU)
10621 #define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P6__VERIFY(src) \
10622                     (!(((uint32_t)(src)\
10623                     & ~0x0000ffffU)))
10624 
10625 /* macros for field quantum_p7 */
10626 #define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__SHIFT                      16
10627 #define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__WIDTH                      16
10628 #define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__MASK              0xffff0000U
10629 #define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__RESET                  0xFFFF
10630 #define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__READ(src) \
10631                     (((uint32_t)(src)\
10632                     & 0xffff0000U) >> 16)
10633 #define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__WRITE(src) \
10634                     (((uint32_t)(src)\
10635                     << 16) & 0xffff0000U)
10636 #define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__MODIFY(dst, src) \
10637                     (dst) = ((dst) &\
10638                     ~0xffff0000U) | (((uint32_t)(src) <<\
10639                     16) & 0xffff0000U)
10640 #define EMAC_REGS__TX_PAUSE_QUANTUM3__QUANTUM_P7__VERIFY(src) \
10641                     (!((((uint32_t)(src)\
10642                     << 16) & ~0xffff0000U)))
10643 #define EMAC_REGS__TX_PAUSE_QUANTUM3__TYPE                             uint32_t
10644 #define EMAC_REGS__TX_PAUSE_QUANTUM3__READ                          0xffffffffU
10645 #define EMAC_REGS__TX_PAUSE_QUANTUM3__WRITE                         0xffffffffU
10646 
10647 #endif /* __EMAC_REGS__TX_PAUSE_QUANTUM3_MACRO__ */
10648 
10649 
10650 /* macros for tx_pause_quantum3 */
10651 #define INST_TX_PAUSE_QUANTUM3__NUM                                           1
10652 
10653 /* macros for BlueprintGlobalNameSpace::emac_regs::rx_lpi */
10654 #ifndef __EMAC_REGS__RX_LPI_MACRO__
10655 #define __EMAC_REGS__RX_LPI_MACRO__
10656 
10657 /* macros for field count */
10658 #define EMAC_REGS__RX_LPI__COUNT__SHIFT                                       0
10659 #define EMAC_REGS__RX_LPI__COUNT__WIDTH                                      16
10660 #define EMAC_REGS__RX_LPI__COUNT__MASK                              0x0000ffffU
10661 #define EMAC_REGS__RX_LPI__COUNT__RESET                                       0
10662 #define EMAC_REGS__RX_LPI__COUNT__READ(src)     ((uint32_t)(src) & 0x0000ffffU)
10663 
10664 /* macros for field reserved_31_16 */
10665 #define EMAC_REGS__RX_LPI__RESERVED_31_16__SHIFT                             16
10666 #define EMAC_REGS__RX_LPI__RESERVED_31_16__WIDTH                             16
10667 #define EMAC_REGS__RX_LPI__RESERVED_31_16__MASK                     0xffff0000U
10668 #define EMAC_REGS__RX_LPI__RESERVED_31_16__RESET                              0
10669 #define EMAC_REGS__RX_LPI__RESERVED_31_16__READ(src) \
10670                     (((uint32_t)(src)\
10671                     & 0xffff0000U) >> 16)
10672 #define EMAC_REGS__RX_LPI__TYPE                                        uint32_t
10673 #define EMAC_REGS__RX_LPI__READ                                     0xffffffffU
10674 #define EMAC_REGS__RX_LPI__RCLR                                     0x0000ffffU
10675 
10676 #endif /* __EMAC_REGS__RX_LPI_MACRO__ */
10677 
10678 
10679 /* macros for rx_lpi */
10680 #define INST_RX_LPI__NUM                                                      1
10681 
10682 /* macros for BlueprintGlobalNameSpace::emac_regs::rx_lpi_time */
10683 #ifndef __EMAC_REGS__RX_LPI_TIME_MACRO__
10684 #define __EMAC_REGS__RX_LPI_TIME_MACRO__
10685 
10686 /* macros for field lpi_time */
10687 #define EMAC_REGS__RX_LPI_TIME__LPI_TIME__SHIFT                               0
10688 #define EMAC_REGS__RX_LPI_TIME__LPI_TIME__WIDTH                              24
10689 #define EMAC_REGS__RX_LPI_TIME__LPI_TIME__MASK                      0x00ffffffU
10690 #define EMAC_REGS__RX_LPI_TIME__LPI_TIME__RESET                               0
10691 #define EMAC_REGS__RX_LPI_TIME__LPI_TIME__READ(src) \
10692                     ((uint32_t)(src)\
10693                     & 0x00ffffffU)
10694 
10695 /* macros for field reserved_31_24 */
10696 #define EMAC_REGS__RX_LPI_TIME__RESERVED_31_24__SHIFT                        24
10697 #define EMAC_REGS__RX_LPI_TIME__RESERVED_31_24__WIDTH                         8
10698 #define EMAC_REGS__RX_LPI_TIME__RESERVED_31_24__MASK                0xff000000U
10699 #define EMAC_REGS__RX_LPI_TIME__RESERVED_31_24__RESET                         0
10700 #define EMAC_REGS__RX_LPI_TIME__RESERVED_31_24__READ(src) \
10701                     (((uint32_t)(src)\
10702                     & 0xff000000U) >> 24)
10703 #define EMAC_REGS__RX_LPI_TIME__TYPE                                   uint32_t
10704 #define EMAC_REGS__RX_LPI_TIME__READ                                0xffffffffU
10705 #define EMAC_REGS__RX_LPI_TIME__RCLR                                0x00ffffffU
10706 
10707 #endif /* __EMAC_REGS__RX_LPI_TIME_MACRO__ */
10708 
10709 
10710 /* macros for rx_lpi_time */
10711 #define INST_RX_LPI_TIME__NUM                                                 1
10712 
10713 /* macros for BlueprintGlobalNameSpace::emac_regs::tx_lpi */
10714 #ifndef __EMAC_REGS__TX_LPI_MACRO__
10715 #define __EMAC_REGS__TX_LPI_MACRO__
10716 
10717 /* macros for field count */
10718 #define EMAC_REGS__TX_LPI__COUNT__SHIFT                                       0
10719 #define EMAC_REGS__TX_LPI__COUNT__WIDTH                                      16
10720 #define EMAC_REGS__TX_LPI__COUNT__MASK                              0x0000ffffU
10721 #define EMAC_REGS__TX_LPI__COUNT__RESET                                       0
10722 #define EMAC_REGS__TX_LPI__COUNT__READ(src)     ((uint32_t)(src) & 0x0000ffffU)
10723 
10724 /* macros for field reserved_31_16 */
10725 #define EMAC_REGS__TX_LPI__RESERVED_31_16__SHIFT                             16
10726 #define EMAC_REGS__TX_LPI__RESERVED_31_16__WIDTH                             16
10727 #define EMAC_REGS__TX_LPI__RESERVED_31_16__MASK                     0xffff0000U
10728 #define EMAC_REGS__TX_LPI__RESERVED_31_16__RESET                              0
10729 #define EMAC_REGS__TX_LPI__RESERVED_31_16__READ(src) \
10730                     (((uint32_t)(src)\
10731                     & 0xffff0000U) >> 16)
10732 #define EMAC_REGS__TX_LPI__TYPE                                        uint32_t
10733 #define EMAC_REGS__TX_LPI__READ                                     0xffffffffU
10734 #define EMAC_REGS__TX_LPI__RCLR                                     0x0000ffffU
10735 
10736 #endif /* __EMAC_REGS__TX_LPI_MACRO__ */
10737 
10738 
10739 /* macros for tx_lpi */
10740 #define INST_TX_LPI__NUM                                                      1
10741 
10742 /* macros for BlueprintGlobalNameSpace::emac_regs::tx_lpi_time */
10743 #ifndef __EMAC_REGS__TX_LPI_TIME_MACRO__
10744 #define __EMAC_REGS__TX_LPI_TIME_MACRO__
10745 
10746 /* macros for field lpi_time */
10747 #define EMAC_REGS__TX_LPI_TIME__LPI_TIME__SHIFT                               0
10748 #define EMAC_REGS__TX_LPI_TIME__LPI_TIME__WIDTH                              24
10749 #define EMAC_REGS__TX_LPI_TIME__LPI_TIME__MASK                      0x00ffffffU
10750 #define EMAC_REGS__TX_LPI_TIME__LPI_TIME__RESET                               0
10751 #define EMAC_REGS__TX_LPI_TIME__LPI_TIME__READ(src) \
10752                     ((uint32_t)(src)\
10753                     & 0x00ffffffU)
10754 
10755 /* macros for field reserved_31_24 */
10756 #define EMAC_REGS__TX_LPI_TIME__RESERVED_31_24__SHIFT                        24
10757 #define EMAC_REGS__TX_LPI_TIME__RESERVED_31_24__WIDTH                         8
10758 #define EMAC_REGS__TX_LPI_TIME__RESERVED_31_24__MASK                0xff000000U
10759 #define EMAC_REGS__TX_LPI_TIME__RESERVED_31_24__RESET                         0
10760 #define EMAC_REGS__TX_LPI_TIME__RESERVED_31_24__READ(src) \
10761                     (((uint32_t)(src)\
10762                     & 0xff000000U) >> 24)
10763 #define EMAC_REGS__TX_LPI_TIME__TYPE                                   uint32_t
10764 #define EMAC_REGS__TX_LPI_TIME__READ                                0xffffffffU
10765 #define EMAC_REGS__TX_LPI_TIME__RCLR                                0x00ffffffU
10766 
10767 #endif /* __EMAC_REGS__TX_LPI_TIME_MACRO__ */
10768 
10769 
10770 /* macros for tx_lpi_time */
10771 #define INST_TX_LPI_TIME__NUM                                                 1
10772 
10773 /* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug1 */
10774 #ifndef __EMAC_REGS__DESIGNCFG_DEBUG1_MACRO__
10775 #define __EMAC_REGS__DESIGNCFG_DEBUG1_MACRO__
10776 
10777 /* macros for field no_pcs */
10778 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__SHIFT                            0
10779 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__WIDTH                            1
10780 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__MASK                   0x00000001U
10781 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__RESET                            0
10782 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__READ(src) \
10783                     ((uint32_t)(src)\
10784                     & 0x00000001U)
10785 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__SET(dst) \
10786                     (dst) = ((dst) &\
10787                     ~0x00000001U) | (uint32_t)(1)
10788 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_PCS__CLR(dst) \
10789                     (dst) = ((dst) &\
10790                     ~0x00000001U) | (uint32_t)(0)
10791 
10792 /* macros for field exclude_qbv */
10793 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__SHIFT                       1
10794 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__WIDTH                       1
10795 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__MASK              0x00000002U
10796 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__RESET                       0
10797 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__READ(src) \
10798                     (((uint32_t)(src)\
10799                     & 0x00000002U) >> 1)
10800 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__SET(dst) \
10801                     (dst) = ((dst) &\
10802                     ~0x00000002U) | ((uint32_t)(1) << 1)
10803 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_QBV__CLR(dst) \
10804                     (dst) = ((dst) &\
10805                     ~0x00000002U) | ((uint32_t)(0) << 1)
10806 
10807 /* macros for field reserved_3_2 */
10808 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_3_2__SHIFT                      2
10809 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_3_2__WIDTH                      2
10810 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_3_2__MASK             0x0000000cU
10811 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_3_2__RESET                      0
10812 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_3_2__READ(src) \
10813                     (((uint32_t)(src)\
10814                     & 0x0000000cU) >> 2)
10815 
10816 /* macros for field int_loopback */
10817 #define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__SHIFT                      4
10818 #define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__WIDTH                      1
10819 #define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__MASK             0x00000010U
10820 #define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__RESET                      1
10821 #define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__READ(src) \
10822                     (((uint32_t)(src)\
10823                     & 0x00000010U) >> 4)
10824 #define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__SET(dst) \
10825                     (dst) = ((dst) &\
10826                     ~0x00000010U) | ((uint32_t)(1) << 4)
10827 #define EMAC_REGS__DESIGNCFG_DEBUG1__INT_LOOPBACK__CLR(dst) \
10828                     (dst) = ((dst) &\
10829                     ~0x00000010U) | ((uint32_t)(0) << 4)
10830 
10831 /* macros for field reserved_5 */
10832 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__SHIFT                        5
10833 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__WIDTH                        1
10834 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__MASK               0x00000020U
10835 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__RESET                        0
10836 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__READ(src) \
10837                     (((uint32_t)(src)\
10838                     & 0x00000020U) >> 5)
10839 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__SET(dst) \
10840                     (dst) = ((dst) &\
10841                     ~0x00000020U) | ((uint32_t)(1) << 5)
10842 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_5__CLR(dst) \
10843                     (dst) = ((dst) &\
10844                     ~0x00000020U) | ((uint32_t)(0) << 5)
10845 
10846 /* macros for field ext_fifo_interface */
10847 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__SHIFT                6
10848 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__WIDTH                1
10849 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__MASK       0x00000040U
10850 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__RESET                0
10851 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__READ(src) \
10852                     (((uint32_t)(src)\
10853                     & 0x00000040U) >> 6)
10854 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__SET(dst) \
10855                     (dst) = ((dst) &\
10856                     ~0x00000040U) | ((uint32_t)(1) << 6)
10857 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXT_FIFO_INTERFACE__CLR(dst) \
10858                     (dst) = ((dst) &\
10859                     ~0x00000040U) | ((uint32_t)(0) << 6)
10860 
10861 /* macros for field reserved_7 */
10862 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__SHIFT                        7
10863 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__WIDTH                        1
10864 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__MASK               0x00000080U
10865 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__RESET                        0
10866 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__READ(src) \
10867                     (((uint32_t)(src)\
10868                     & 0x00000080U) >> 7)
10869 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__SET(dst) \
10870                     (dst) = ((dst) &\
10871                     ~0x00000080U) | ((uint32_t)(1) << 7)
10872 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_7__CLR(dst) \
10873                     (dst) = ((dst) &\
10874                     ~0x00000080U) | ((uint32_t)(0) << 7)
10875 
10876 /* macros for field reserved_8 */
10877 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__SHIFT                        8
10878 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__WIDTH                        1
10879 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__MASK               0x00000100U
10880 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__RESET                        1
10881 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__READ(src) \
10882                     (((uint32_t)(src)\
10883                     & 0x00000100U) >> 8)
10884 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__SET(dst) \
10885                     (dst) = ((dst) &\
10886                     ~0x00000100U) | ((uint32_t)(1) << 8)
10887 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_8__CLR(dst) \
10888                     (dst) = ((dst) &\
10889                     ~0x00000100U) | ((uint32_t)(0) << 8)
10890 
10891 /* macros for field user_io */
10892 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__SHIFT                           9
10893 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__WIDTH                           1
10894 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__MASK                  0x00000200U
10895 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__RESET                           1
10896 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__READ(src) \
10897                     (((uint32_t)(src)\
10898                     & 0x00000200U) >> 9)
10899 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__SET(dst) \
10900                     (dst) = ((dst) &\
10901                     ~0x00000200U) | ((uint32_t)(1) << 9)
10902 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IO__CLR(dst) \
10903                     (dst) = ((dst) &\
10904                     ~0x00000200U) | ((uint32_t)(0) << 9)
10905 
10906 /* macros for field user_out_width */
10907 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_OUT_WIDTH__SHIFT                   10
10908 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_OUT_WIDTH__WIDTH                    5
10909 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_OUT_WIDTH__MASK           0x00007c00U
10910 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_OUT_WIDTH__RESET                   16
10911 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_OUT_WIDTH__READ(src) \
10912                     (((uint32_t)(src)\
10913                     & 0x00007c00U) >> 10)
10914 
10915 /* macros for field user_in_width */
10916 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IN_WIDTH__SHIFT                    15
10917 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IN_WIDTH__WIDTH                     5
10918 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IN_WIDTH__MASK            0x000f8000U
10919 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IN_WIDTH__RESET                    16
10920 #define EMAC_REGS__DESIGNCFG_DEBUG1__USER_IN_WIDTH__READ(src) \
10921                     (((uint32_t)(src)\
10922                     & 0x000f8000U) >> 15)
10923 
10924 /* macros for field reserved_20 */
10925 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__SHIFT                      20
10926 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__WIDTH                       1
10927 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__MASK              0x00100000U
10928 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__RESET                       1
10929 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__READ(src) \
10930                     (((uint32_t)(src)\
10931                     & 0x00100000U) >> 20)
10932 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__SET(dst) \
10933                     (dst) = ((dst) &\
10934                     ~0x00100000U) | ((uint32_t)(1) << 20)
10935 #define EMAC_REGS__DESIGNCFG_DEBUG1__RESERVED_20__CLR(dst) \
10936                     (dst) = ((dst) &\
10937                     ~0x00100000U) | ((uint32_t)(0) << 20)
10938 
10939 /* macros for field no_stats */
10940 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__SHIFT                         21
10941 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__WIDTH                          1
10942 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__MASK                 0x00200000U
10943 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__RESET                          0
10944 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__READ(src) \
10945                     (((uint32_t)(src)\
10946                     & 0x00200000U) >> 21)
10947 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__SET(dst) \
10948                     (dst) = ((dst) &\
10949                     ~0x00200000U) | ((uint32_t)(1) << 21)
10950 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_STATS__CLR(dst) \
10951                     (dst) = ((dst) &\
10952                     ~0x00200000U) | ((uint32_t)(0) << 21)
10953 
10954 /* macros for field no_snapshot */
10955 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__SHIFT                      22
10956 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__WIDTH                       1
10957 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__MASK              0x00400000U
10958 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__RESET                       0
10959 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__READ(src) \
10960                     (((uint32_t)(src)\
10961                     & 0x00400000U) >> 22)
10962 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__SET(dst) \
10963                     (dst) = ((dst) &\
10964                     ~0x00400000U) | ((uint32_t)(1) << 22)
10965 #define EMAC_REGS__DESIGNCFG_DEBUG1__NO_SNAPSHOT__CLR(dst) \
10966                     (dst) = ((dst) &\
10967                     ~0x00400000U) | ((uint32_t)(0) << 22)
10968 
10969 /* macros for field irq_read_clear */
10970 #define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__SHIFT                   23
10971 #define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__WIDTH                    1
10972 #define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__MASK           0x00800000U
10973 #define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__RESET                    1
10974 #define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__READ(src) \
10975                     (((uint32_t)(src)\
10976                     & 0x00800000U) >> 23)
10977 #define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__SET(dst) \
10978                     (dst) = ((dst) &\
10979                     ~0x00800000U) | ((uint32_t)(1) << 23)
10980 #define EMAC_REGS__DESIGNCFG_DEBUG1__IRQ_READ_CLEAR__CLR(dst) \
10981                     (dst) = ((dst) &\
10982                     ~0x00800000U) | ((uint32_t)(0) << 23)
10983 
10984 /* macros for field exclude_cbs */
10985 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__SHIFT                      24
10986 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__WIDTH                       1
10987 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__MASK              0x01000000U
10988 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__RESET                       0
10989 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__READ(src) \
10990                     (((uint32_t)(src)\
10991                     & 0x01000000U) >> 24)
10992 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__SET(dst) \
10993                     (dst) = ((dst) &\
10994                     ~0x01000000U) | ((uint32_t)(1) << 24)
10995 #define EMAC_REGS__DESIGNCFG_DEBUG1__EXCLUDE_CBS__CLR(dst) \
10996                     (dst) = ((dst) &\
10997                     ~0x01000000U) | ((uint32_t)(0) << 24)
10998 
10999 /* macros for field dma_bus_width */
11000 #define EMAC_REGS__DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__SHIFT                    25
11001 #define EMAC_REGS__DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__WIDTH                     3
11002 #define EMAC_REGS__DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__MASK            0x0e000000U
11003 #define EMAC_REGS__DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__RESET                     2
11004 #define EMAC_REGS__DESIGNCFG_DEBUG1__DMA_BUS_WIDTH__READ(src) \
11005                     (((uint32_t)(src)\
11006                     & 0x0e000000U) >> 25)
11007 
11008 /* macros for field axi_cache_value */
11009 #define EMAC_REGS__DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__SHIFT                  28
11010 #define EMAC_REGS__DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__WIDTH                   4
11011 #define EMAC_REGS__DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__MASK          0xf0000000U
11012 #define EMAC_REGS__DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__RESET                   0
11013 #define EMAC_REGS__DESIGNCFG_DEBUG1__AXI_CACHE_VALUE__READ(src) \
11014                     (((uint32_t)(src)\
11015                     & 0xf0000000U) >> 28)
11016 #define EMAC_REGS__DESIGNCFG_DEBUG1__TYPE                              uint32_t
11017 #define EMAC_REGS__DESIGNCFG_DEBUG1__READ                           0xffffffffU
11018 
11019 #endif /* __EMAC_REGS__DESIGNCFG_DEBUG1_MACRO__ */
11020 
11021 
11022 /* macros for designcfg_debug1 */
11023 #define INST_DESIGNCFG_DEBUG1__NUM                                            1
11024 
11025 /* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug2 */
11026 #ifndef __EMAC_REGS__DESIGNCFG_DEBUG2_MACRO__
11027 #define __EMAC_REGS__DESIGNCFG_DEBUG2_MACRO__
11028 
11029 /* macros for field jumbo_max_length */
11030 #define EMAC_REGS__DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__SHIFT                  0
11031 #define EMAC_REGS__DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__WIDTH                 14
11032 #define EMAC_REGS__DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__MASK         0x00003fffU
11033 #define EMAC_REGS__DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__RESET              10240
11034 #define EMAC_REGS__DESIGNCFG_DEBUG2__JUMBO_MAX_LENGTH__READ(src) \
11035                     ((uint32_t)(src)\
11036                     & 0x00003fffU)
11037 
11038 /* macros for field reserved_15_14 */
11039 #define EMAC_REGS__DESIGNCFG_DEBUG2__RESERVED_15_14__SHIFT                   14
11040 #define EMAC_REGS__DESIGNCFG_DEBUG2__RESERVED_15_14__WIDTH                    2
11041 #define EMAC_REGS__DESIGNCFG_DEBUG2__RESERVED_15_14__MASK           0x0000c000U
11042 #define EMAC_REGS__DESIGNCFG_DEBUG2__RESERVED_15_14__RESET                    0
11043 #define EMAC_REGS__DESIGNCFG_DEBUG2__RESERVED_15_14__READ(src) \
11044                     (((uint32_t)(src)\
11045                     & 0x0000c000U) >> 14)
11046 
11047 /* macros for field hprot_value */
11048 #define EMAC_REGS__DESIGNCFG_DEBUG2__HPROT_VALUE__SHIFT                      16
11049 #define EMAC_REGS__DESIGNCFG_DEBUG2__HPROT_VALUE__WIDTH                       4
11050 #define EMAC_REGS__DESIGNCFG_DEBUG2__HPROT_VALUE__MASK              0x000f0000U
11051 #define EMAC_REGS__DESIGNCFG_DEBUG2__HPROT_VALUE__RESET                       1
11052 #define EMAC_REGS__DESIGNCFG_DEBUG2__HPROT_VALUE__READ(src) \
11053                     (((uint32_t)(src)\
11054                     & 0x000f0000U) >> 16)
11055 
11056 /* macros for field rx_pkt_buffer */
11057 #define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__SHIFT                    20
11058 #define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__WIDTH                     1
11059 #define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__MASK            0x00100000U
11060 #define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__RESET                     1
11061 #define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__READ(src) \
11062                     (((uint32_t)(src)\
11063                     & 0x00100000U) >> 20)
11064 #define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__SET(dst) \
11065                     (dst) = ((dst) &\
11066                     ~0x00100000U) | ((uint32_t)(1) << 20)
11067 #define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PKT_BUFFER__CLR(dst) \
11068                     (dst) = ((dst) &\
11069                     ~0x00100000U) | ((uint32_t)(0) << 20)
11070 
11071 /* macros for field tx_pkt_buffer */
11072 #define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__SHIFT                    21
11073 #define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__WIDTH                     1
11074 #define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__MASK            0x00200000U
11075 #define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__RESET                     1
11076 #define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__READ(src) \
11077                     (((uint32_t)(src)\
11078                     & 0x00200000U) >> 21)
11079 #define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__SET(dst) \
11080                     (dst) = ((dst) &\
11081                     ~0x00200000U) | ((uint32_t)(1) << 21)
11082 #define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PKT_BUFFER__CLR(dst) \
11083                     (dst) = ((dst) &\
11084                     ~0x00200000U) | ((uint32_t)(0) << 21)
11085 
11086 /* macros for field rx_pbuf_addr */
11087 #define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PBUF_ADDR__SHIFT                     22
11088 #define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PBUF_ADDR__WIDTH                      4
11089 #define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PBUF_ADDR__MASK             0x03c00000U
11090 #define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PBUF_ADDR__RESET                     11
11091 #define EMAC_REGS__DESIGNCFG_DEBUG2__RX_PBUF_ADDR__READ(src) \
11092                     (((uint32_t)(src)\
11093                     & 0x03c00000U) >> 22)
11094 
11095 /* macros for field tx_pbuf_addr */
11096 #define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PBUF_ADDR__SHIFT                     26
11097 #define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PBUF_ADDR__WIDTH                      4
11098 #define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PBUF_ADDR__MASK             0x3c000000U
11099 #define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PBUF_ADDR__RESET                     14
11100 #define EMAC_REGS__DESIGNCFG_DEBUG2__TX_PBUF_ADDR__READ(src) \
11101                     (((uint32_t)(src)\
11102                     & 0x3c000000U) >> 26)
11103 
11104 /* macros for field axi */
11105 #define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__SHIFT                              30
11106 #define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__WIDTH                               1
11107 #define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__MASK                      0x40000000U
11108 #define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__RESET                               1
11109 #define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__READ(src) \
11110                     (((uint32_t)(src)\
11111                     & 0x40000000U) >> 30)
11112 #define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__SET(dst) \
11113                     (dst) = ((dst) &\
11114                     ~0x40000000U) | ((uint32_t)(1) << 30)
11115 #define EMAC_REGS__DESIGNCFG_DEBUG2__AXI__CLR(dst) \
11116                     (dst) = ((dst) &\
11117                     ~0x40000000U) | ((uint32_t)(0) << 30)
11118 
11119 /* macros for field spram */
11120 #define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__SHIFT                            31
11121 #define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__WIDTH                             1
11122 #define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__MASK                    0x80000000U
11123 #define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__RESET                             0
11124 #define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__READ(src) \
11125                     (((uint32_t)(src)\
11126                     & 0x80000000U) >> 31)
11127 #define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__SET(dst) \
11128                     (dst) = ((dst) &\
11129                     ~0x80000000U) | ((uint32_t)(1) << 31)
11130 #define EMAC_REGS__DESIGNCFG_DEBUG2__SPRAM__CLR(dst) \
11131                     (dst) = ((dst) &\
11132                     ~0x80000000U) | ((uint32_t)(0) << 31)
11133 #define EMAC_REGS__DESIGNCFG_DEBUG2__TYPE                              uint32_t
11134 #define EMAC_REGS__DESIGNCFG_DEBUG2__READ                           0xffffffffU
11135 
11136 #endif /* __EMAC_REGS__DESIGNCFG_DEBUG2_MACRO__ */
11137 
11138 
11139 /* macros for designcfg_debug2 */
11140 #define INST_DESIGNCFG_DEBUG2__NUM                                            1
11141 
11142 /* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug3 */
11143 #ifndef __EMAC_REGS__DESIGNCFG_DEBUG3_MACRO__
11144 #define __EMAC_REGS__DESIGNCFG_DEBUG3_MACRO__
11145 
11146 /* macros for field reserved_23_0 */
11147 #define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_23_0__SHIFT                     0
11148 #define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_23_0__WIDTH                    24
11149 #define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_23_0__MASK            0x00ffffffU
11150 #define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_23_0__RESET                     0
11151 #define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_23_0__READ(src) \
11152                     ((uint32_t)(src)\
11153                     & 0x00ffffffU)
11154 
11155 /* macros for field num_spec_add_filters */
11156 #define EMAC_REGS__DESIGNCFG_DEBUG3__NUM_SPEC_ADD_FILTERS__SHIFT             24
11157 #define EMAC_REGS__DESIGNCFG_DEBUG3__NUM_SPEC_ADD_FILTERS__WIDTH              6
11158 #define EMAC_REGS__DESIGNCFG_DEBUG3__NUM_SPEC_ADD_FILTERS__MASK     0x3f000000U
11159 #define EMAC_REGS__DESIGNCFG_DEBUG3__NUM_SPEC_ADD_FILTERS__RESET             36
11160 #define EMAC_REGS__DESIGNCFG_DEBUG3__NUM_SPEC_ADD_FILTERS__READ(src) \
11161                     (((uint32_t)(src)\
11162                     & 0x3f000000U) >> 24)
11163 
11164 /* macros for field reserved_31_30 */
11165 #define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_31_30__SHIFT                   30
11166 #define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_31_30__WIDTH                    2
11167 #define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_31_30__MASK           0xc0000000U
11168 #define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_31_30__RESET                    0
11169 #define EMAC_REGS__DESIGNCFG_DEBUG3__RESERVED_31_30__READ(src) \
11170                     (((uint32_t)(src)\
11171                     & 0xc0000000U) >> 30)
11172 #define EMAC_REGS__DESIGNCFG_DEBUG3__TYPE                              uint32_t
11173 #define EMAC_REGS__DESIGNCFG_DEBUG3__READ                           0xffffffffU
11174 
11175 #endif /* __EMAC_REGS__DESIGNCFG_DEBUG3_MACRO__ */
11176 
11177 
11178 /* macros for designcfg_debug3 */
11179 #define INST_DESIGNCFG_DEBUG3__NUM                                            1
11180 
11181 /* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug4 */
11182 #ifndef __EMAC_REGS__DESIGNCFG_DEBUG4_MACRO__
11183 #define __EMAC_REGS__DESIGNCFG_DEBUG4_MACRO__
11184 
11185 /* macros for field reserved_31_0 */
11186 #define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_31_0__SHIFT                     0
11187 #define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_31_0__WIDTH                    32
11188 #define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_31_0__MASK            0xffffffffU
11189 #define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_31_0__RESET                     0
11190 #define EMAC_REGS__DESIGNCFG_DEBUG4__RESERVED_31_0__READ(src) \
11191                     ((uint32_t)(src)\
11192                     & 0xffffffffU)
11193 #define EMAC_REGS__DESIGNCFG_DEBUG4__TYPE                              uint32_t
11194 #define EMAC_REGS__DESIGNCFG_DEBUG4__READ                           0xffffffffU
11195 
11196 #endif /* __EMAC_REGS__DESIGNCFG_DEBUG4_MACRO__ */
11197 
11198 
11199 /* macros for designcfg_debug4 */
11200 #define INST_DESIGNCFG_DEBUG4__NUM                                            1
11201 
11202 /* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug5 */
11203 #ifndef __EMAC_REGS__DESIGNCFG_DEBUG5_MACRO__
11204 #define __EMAC_REGS__DESIGNCFG_DEBUG5_MACRO__
11205 
11206 /* macros for field rx_fifo_cnt_width */
11207 #define EMAC_REGS__DESIGNCFG_DEBUG5__RX_FIFO_CNT_WIDTH__SHIFT                 0
11208 #define EMAC_REGS__DESIGNCFG_DEBUG5__RX_FIFO_CNT_WIDTH__WIDTH                 4
11209 #define EMAC_REGS__DESIGNCFG_DEBUG5__RX_FIFO_CNT_WIDTH__MASK        0x0000000fU
11210 #define EMAC_REGS__DESIGNCFG_DEBUG5__RX_FIFO_CNT_WIDTH__RESET                 5
11211 #define EMAC_REGS__DESIGNCFG_DEBUG5__RX_FIFO_CNT_WIDTH__READ(src) \
11212                     ((uint32_t)(src)\
11213                     & 0x0000000fU)
11214 
11215 /* macros for field tx_fifo_cnt_width */
11216 #define EMAC_REGS__DESIGNCFG_DEBUG5__TX_FIFO_CNT_WIDTH__SHIFT                 4
11217 #define EMAC_REGS__DESIGNCFG_DEBUG5__TX_FIFO_CNT_WIDTH__WIDTH                 4
11218 #define EMAC_REGS__DESIGNCFG_DEBUG5__TX_FIFO_CNT_WIDTH__MASK        0x000000f0U
11219 #define EMAC_REGS__DESIGNCFG_DEBUG5__TX_FIFO_CNT_WIDTH__RESET                 4
11220 #define EMAC_REGS__DESIGNCFG_DEBUG5__TX_FIFO_CNT_WIDTH__READ(src) \
11221                     (((uint32_t)(src)\
11222                     & 0x000000f0U) >> 4)
11223 
11224 /* macros for field tsu */
11225 #define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__SHIFT                               8
11226 #define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__WIDTH                               1
11227 #define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__MASK                      0x00000100U
11228 #define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__RESET                               1
11229 #define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__READ(src) \
11230                     (((uint32_t)(src)\
11231                     & 0x00000100U) >> 8)
11232 #define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__SET(dst) \
11233                     (dst) = ((dst) &\
11234                     ~0x00000100U) | ((uint32_t)(1) << 8)
11235 #define EMAC_REGS__DESIGNCFG_DEBUG5__TSU__CLR(dst) \
11236                     (dst) = ((dst) &\
11237                     ~0x00000100U) | ((uint32_t)(0) << 8)
11238 
11239 /* macros for field phy_ident */
11240 #define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__SHIFT                         9
11241 #define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__WIDTH                         1
11242 #define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__MASK                0x00000200U
11243 #define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__RESET                         1
11244 #define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__READ(src) \
11245                     (((uint32_t)(src)\
11246                     & 0x00000200U) >> 9)
11247 #define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__SET(dst) \
11248                     (dst) = ((dst) &\
11249                     ~0x00000200U) | ((uint32_t)(1) << 9)
11250 #define EMAC_REGS__DESIGNCFG_DEBUG5__PHY_IDENT__CLR(dst) \
11251                     (dst) = ((dst) &\
11252                     ~0x00000200U) | ((uint32_t)(0) << 9)
11253 
11254 /* macros for field dma_bus_width_def */
11255 #define EMAC_REGS__DESIGNCFG_DEBUG5__DMA_BUS_WIDTH_DEF__SHIFT                10
11256 #define EMAC_REGS__DESIGNCFG_DEBUG5__DMA_BUS_WIDTH_DEF__WIDTH                 2
11257 #define EMAC_REGS__DESIGNCFG_DEBUG5__DMA_BUS_WIDTH_DEF__MASK        0x00000c00U
11258 #define EMAC_REGS__DESIGNCFG_DEBUG5__DMA_BUS_WIDTH_DEF__RESET                 0
11259 #define EMAC_REGS__DESIGNCFG_DEBUG5__DMA_BUS_WIDTH_DEF__READ(src) \
11260                     (((uint32_t)(src)\
11261                     & 0x00000c00U) >> 10)
11262 
11263 /* macros for field mdc_clock_div */
11264 #define EMAC_REGS__DESIGNCFG_DEBUG5__MDC_CLOCK_DIV__SHIFT                    12
11265 #define EMAC_REGS__DESIGNCFG_DEBUG5__MDC_CLOCK_DIV__WIDTH                     3
11266 #define EMAC_REGS__DESIGNCFG_DEBUG5__MDC_CLOCK_DIV__MASK            0x00007000U
11267 #define EMAC_REGS__DESIGNCFG_DEBUG5__MDC_CLOCK_DIV__RESET                     2
11268 #define EMAC_REGS__DESIGNCFG_DEBUG5__MDC_CLOCK_DIV__READ(src) \
11269                     (((uint32_t)(src)\
11270                     & 0x00007000U) >> 12)
11271 
11272 /* macros for field endian_swap_def */
11273 #define EMAC_REGS__DESIGNCFG_DEBUG5__ENDIAN_SWAP_DEF__SHIFT                  15
11274 #define EMAC_REGS__DESIGNCFG_DEBUG5__ENDIAN_SWAP_DEF__WIDTH                   2
11275 #define EMAC_REGS__DESIGNCFG_DEBUG5__ENDIAN_SWAP_DEF__MASK          0x00018000U
11276 #define EMAC_REGS__DESIGNCFG_DEBUG5__ENDIAN_SWAP_DEF__RESET                   3
11277 #define EMAC_REGS__DESIGNCFG_DEBUG5__ENDIAN_SWAP_DEF__READ(src) \
11278                     (((uint32_t)(src)\
11279                     & 0x00018000U) >> 15)
11280 
11281 /* macros for field rx_pbuf_size_def */
11282 #define EMAC_REGS__DESIGNCFG_DEBUG5__RX_PBUF_SIZE_DEF__SHIFT                 17
11283 #define EMAC_REGS__DESIGNCFG_DEBUG5__RX_PBUF_SIZE_DEF__WIDTH                  2
11284 #define EMAC_REGS__DESIGNCFG_DEBUG5__RX_PBUF_SIZE_DEF__MASK         0x00060000U
11285 #define EMAC_REGS__DESIGNCFG_DEBUG5__RX_PBUF_SIZE_DEF__RESET                  3
11286 #define EMAC_REGS__DESIGNCFG_DEBUG5__RX_PBUF_SIZE_DEF__READ(src) \
11287                     (((uint32_t)(src)\
11288                     & 0x00060000U) >> 17)
11289 
11290 /* macros for field tx_pbuf_size_def */
11291 #define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__SHIFT                 19
11292 #define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__WIDTH                  1
11293 #define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__MASK         0x00080000U
11294 #define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__RESET                  1
11295 #define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__READ(src) \
11296                     (((uint32_t)(src)\
11297                     & 0x00080000U) >> 19)
11298 #define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__SET(dst) \
11299                     (dst) = ((dst) &\
11300                     ~0x00080000U) | ((uint32_t)(1) << 19)
11301 #define EMAC_REGS__DESIGNCFG_DEBUG5__TX_PBUF_SIZE_DEF__CLR(dst) \
11302                     (dst) = ((dst) &\
11303                     ~0x00080000U) | ((uint32_t)(0) << 19)
11304 
11305 /* macros for field rx_buffer_length_def */
11306 #define EMAC_REGS__DESIGNCFG_DEBUG5__RX_BUFFER_LENGTH_DEF__SHIFT             20
11307 #define EMAC_REGS__DESIGNCFG_DEBUG5__RX_BUFFER_LENGTH_DEF__WIDTH              8
11308 #define EMAC_REGS__DESIGNCFG_DEBUG5__RX_BUFFER_LENGTH_DEF__MASK     0x0ff00000U
11309 #define EMAC_REGS__DESIGNCFG_DEBUG5__RX_BUFFER_LENGTH_DEF__RESET              2
11310 #define EMAC_REGS__DESIGNCFG_DEBUG5__RX_BUFFER_LENGTH_DEF__READ(src) \
11311                     (((uint32_t)(src)\
11312                     & 0x0ff00000U) >> 20)
11313 
11314 /* macros for field tsu_clk */
11315 #define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__SHIFT                          28
11316 #define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__WIDTH                           1
11317 #define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__MASK                  0x10000000U
11318 #define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__RESET                           1
11319 #define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__READ(src) \
11320                     (((uint32_t)(src)\
11321                     & 0x10000000U) >> 28)
11322 #define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__SET(dst) \
11323                     (dst) = ((dst) &\
11324                     ~0x10000000U) | ((uint32_t)(1) << 28)
11325 #define EMAC_REGS__DESIGNCFG_DEBUG5__TSU_CLK__CLR(dst) \
11326                     (dst) = ((dst) &\
11327                     ~0x10000000U) | ((uint32_t)(0) << 28)
11328 
11329 /* macros for field axi_prot_value */
11330 #define EMAC_REGS__DESIGNCFG_DEBUG5__AXI_PROT_VALUE__SHIFT                   29
11331 #define EMAC_REGS__DESIGNCFG_DEBUG5__AXI_PROT_VALUE__WIDTH                    3
11332 #define EMAC_REGS__DESIGNCFG_DEBUG5__AXI_PROT_VALUE__MASK           0xe0000000U
11333 #define EMAC_REGS__DESIGNCFG_DEBUG5__AXI_PROT_VALUE__RESET                    2
11334 #define EMAC_REGS__DESIGNCFG_DEBUG5__AXI_PROT_VALUE__READ(src) \
11335                     (((uint32_t)(src)\
11336                     & 0xe0000000U) >> 29)
11337 #define EMAC_REGS__DESIGNCFG_DEBUG5__TYPE                              uint32_t
11338 #define EMAC_REGS__DESIGNCFG_DEBUG5__READ                           0xffffffffU
11339 
11340 #endif /* __EMAC_REGS__DESIGNCFG_DEBUG5_MACRO__ */
11341 
11342 
11343 /* macros for designcfg_debug5 */
11344 #define INST_DESIGNCFG_DEBUG5__NUM                                            1
11345 
11346 /* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug6 */
11347 #ifndef __EMAC_REGS__DESIGNCFG_DEBUG6_MACRO__
11348 #define __EMAC_REGS__DESIGNCFG_DEBUG6_MACRO__
11349 
11350 /* macros for field reserved_0 */
11351 #define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__SHIFT                        0
11352 #define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__WIDTH                        1
11353 #define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__MASK               0x00000001U
11354 #define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__RESET                        0
11355 #define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__READ(src) \
11356                     ((uint32_t)(src)\
11357                     & 0x00000001U)
11358 #define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__SET(dst) \
11359                     (dst) = ((dst) &\
11360                     ~0x00000001U) | (uint32_t)(1)
11361 #define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_0__CLR(dst) \
11362                     (dst) = ((dst) &\
11363                     ~0x00000001U) | (uint32_t)(0)
11364 
11365 /* macros for field dma_priority_queue1 */
11366 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__SHIFT               1
11367 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__WIDTH               1
11368 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__MASK      0x00000002U
11369 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__RESET               1
11370 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__READ(src) \
11371                     (((uint32_t)(src)\
11372                     & 0x00000002U) >> 1)
11373 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__SET(dst) \
11374                     (dst) = ((dst) &\
11375                     ~0x00000002U) | ((uint32_t)(1) << 1)
11376 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE1__CLR(dst) \
11377                     (dst) = ((dst) &\
11378                     ~0x00000002U) | ((uint32_t)(0) << 1)
11379 
11380 /* macros for field dma_priority_queue2 */
11381 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__SHIFT               2
11382 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__WIDTH               1
11383 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__MASK      0x00000004U
11384 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__RESET               1
11385 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__READ(src) \
11386                     (((uint32_t)(src)\
11387                     & 0x00000004U) >> 2)
11388 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__SET(dst) \
11389                     (dst) = ((dst) &\
11390                     ~0x00000004U) | ((uint32_t)(1) << 2)
11391 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE2__CLR(dst) \
11392                     (dst) = ((dst) &\
11393                     ~0x00000004U) | ((uint32_t)(0) << 2)
11394 
11395 /* macros for field dma_priority_queue3 */
11396 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__SHIFT               3
11397 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__WIDTH               1
11398 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__MASK      0x00000008U
11399 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__RESET               1
11400 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__READ(src) \
11401                     (((uint32_t)(src)\
11402                     & 0x00000008U) >> 3)
11403 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__SET(dst) \
11404                     (dst) = ((dst) &\
11405                     ~0x00000008U) | ((uint32_t)(1) << 3)
11406 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE3__CLR(dst) \
11407                     (dst) = ((dst) &\
11408                     ~0x00000008U) | ((uint32_t)(0) << 3)
11409 
11410 /* macros for field dma_priority_queue4 */
11411 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__SHIFT               4
11412 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__WIDTH               1
11413 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__MASK      0x00000010U
11414 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__RESET               1
11415 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__READ(src) \
11416                     (((uint32_t)(src)\
11417                     & 0x00000010U) >> 4)
11418 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__SET(dst) \
11419                     (dst) = ((dst) &\
11420                     ~0x00000010U) | ((uint32_t)(1) << 4)
11421 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE4__CLR(dst) \
11422                     (dst) = ((dst) &\
11423                     ~0x00000010U) | ((uint32_t)(0) << 4)
11424 
11425 /* macros for field dma_priority_queue5 */
11426 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__SHIFT               5
11427 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__WIDTH               1
11428 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__MASK      0x00000020U
11429 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__RESET               1
11430 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__READ(src) \
11431                     (((uint32_t)(src)\
11432                     & 0x00000020U) >> 5)
11433 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__SET(dst) \
11434                     (dst) = ((dst) &\
11435                     ~0x00000020U) | ((uint32_t)(1) << 5)
11436 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE5__CLR(dst) \
11437                     (dst) = ((dst) &\
11438                     ~0x00000020U) | ((uint32_t)(0) << 5)
11439 
11440 /* macros for field dma_priority_queue6 */
11441 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__SHIFT               6
11442 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__WIDTH               1
11443 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__MASK      0x00000040U
11444 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__RESET               1
11445 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__READ(src) \
11446                     (((uint32_t)(src)\
11447                     & 0x00000040U) >> 6)
11448 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__SET(dst) \
11449                     (dst) = ((dst) &\
11450                     ~0x00000040U) | ((uint32_t)(1) << 6)
11451 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE6__CLR(dst) \
11452                     (dst) = ((dst) &\
11453                     ~0x00000040U) | ((uint32_t)(0) << 6)
11454 
11455 /* macros for field dma_priority_queue7 */
11456 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__SHIFT               7
11457 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__WIDTH               1
11458 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__MASK      0x00000080U
11459 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__RESET               1
11460 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__READ(src) \
11461                     (((uint32_t)(src)\
11462                     & 0x00000080U) >> 7)
11463 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__SET(dst) \
11464                     (dst) = ((dst) &\
11465                     ~0x00000080U) | ((uint32_t)(1) << 7)
11466 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE7__CLR(dst) \
11467                     (dst) = ((dst) &\
11468                     ~0x00000080U) | ((uint32_t)(0) << 7)
11469 
11470 /* macros for field dma_priority_queue8 */
11471 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__SHIFT               8
11472 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__WIDTH               1
11473 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__MASK      0x00000100U
11474 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__RESET               1
11475 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__READ(src) \
11476                     (((uint32_t)(src)\
11477                     & 0x00000100U) >> 8)
11478 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__SET(dst) \
11479                     (dst) = ((dst) &\
11480                     ~0x00000100U) | ((uint32_t)(1) << 8)
11481 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE8__CLR(dst) \
11482                     (dst) = ((dst) &\
11483                     ~0x00000100U) | ((uint32_t)(0) << 8)
11484 
11485 /* macros for field dma_priority_queue9 */
11486 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__SHIFT               9
11487 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__WIDTH               1
11488 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__MASK      0x00000200U
11489 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__RESET               1
11490 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__READ(src) \
11491                     (((uint32_t)(src)\
11492                     & 0x00000200U) >> 9)
11493 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__SET(dst) \
11494                     (dst) = ((dst) &\
11495                     ~0x00000200U) | ((uint32_t)(1) << 9)
11496 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE9__CLR(dst) \
11497                     (dst) = ((dst) &\
11498                     ~0x00000200U) | ((uint32_t)(0) << 9)
11499 
11500 /* macros for field dma_priority_queue10 */
11501 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__SHIFT             10
11502 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__WIDTH              1
11503 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__MASK     0x00000400U
11504 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__RESET              1
11505 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__READ(src) \
11506                     (((uint32_t)(src)\
11507                     & 0x00000400U) >> 10)
11508 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__SET(dst) \
11509                     (dst) = ((dst) &\
11510                     ~0x00000400U) | ((uint32_t)(1) << 10)
11511 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE10__CLR(dst) \
11512                     (dst) = ((dst) &\
11513                     ~0x00000400U) | ((uint32_t)(0) << 10)
11514 
11515 /* macros for field dma_priority_queue11 */
11516 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__SHIFT             11
11517 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__WIDTH              1
11518 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__MASK     0x00000800U
11519 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__RESET              1
11520 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__READ(src) \
11521                     (((uint32_t)(src)\
11522                     & 0x00000800U) >> 11)
11523 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__SET(dst) \
11524                     (dst) = ((dst) &\
11525                     ~0x00000800U) | ((uint32_t)(1) << 11)
11526 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE11__CLR(dst) \
11527                     (dst) = ((dst) &\
11528                     ~0x00000800U) | ((uint32_t)(0) << 11)
11529 
11530 /* macros for field dma_priority_queue12 */
11531 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__SHIFT             12
11532 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__WIDTH              1
11533 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__MASK     0x00001000U
11534 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__RESET              1
11535 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__READ(src) \
11536                     (((uint32_t)(src)\
11537                     & 0x00001000U) >> 12)
11538 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__SET(dst) \
11539                     (dst) = ((dst) &\
11540                     ~0x00001000U) | ((uint32_t)(1) << 12)
11541 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE12__CLR(dst) \
11542                     (dst) = ((dst) &\
11543                     ~0x00001000U) | ((uint32_t)(0) << 12)
11544 
11545 /* macros for field dma_priority_queue13 */
11546 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__SHIFT             13
11547 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__WIDTH              1
11548 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__MASK     0x00002000U
11549 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__RESET              1
11550 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__READ(src) \
11551                     (((uint32_t)(src)\
11552                     & 0x00002000U) >> 13)
11553 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__SET(dst) \
11554                     (dst) = ((dst) &\
11555                     ~0x00002000U) | ((uint32_t)(1) << 13)
11556 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE13__CLR(dst) \
11557                     (dst) = ((dst) &\
11558                     ~0x00002000U) | ((uint32_t)(0) << 13)
11559 
11560 /* macros for field dma_priority_queue14 */
11561 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__SHIFT             14
11562 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__WIDTH              1
11563 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__MASK     0x00004000U
11564 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__RESET              1
11565 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__READ(src) \
11566                     (((uint32_t)(src)\
11567                     & 0x00004000U) >> 14)
11568 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__SET(dst) \
11569                     (dst) = ((dst) &\
11570                     ~0x00004000U) | ((uint32_t)(1) << 14)
11571 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE14__CLR(dst) \
11572                     (dst) = ((dst) &\
11573                     ~0x00004000U) | ((uint32_t)(0) << 14)
11574 
11575 /* macros for field dma_priority_queue15 */
11576 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__SHIFT             15
11577 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__WIDTH              1
11578 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__MASK     0x00008000U
11579 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__RESET              1
11580 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__READ(src) \
11581                     (((uint32_t)(src)\
11582                     & 0x00008000U) >> 15)
11583 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__SET(dst) \
11584                     (dst) = ((dst) &\
11585                     ~0x00008000U) | ((uint32_t)(1) << 15)
11586 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_PRIORITY_QUEUE15__CLR(dst) \
11587                     (dst) = ((dst) &\
11588                     ~0x00008000U) | ((uint32_t)(0) << 15)
11589 
11590 /* macros for field tx_pbuf_queue_segment_size */
11591 #define EMAC_REGS__DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__SHIFT       16
11592 #define EMAC_REGS__DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__WIDTH        4
11593 #define EMAC_REGS__DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__MASK \
11594                     0x000f0000U
11595 #define EMAC_REGS__DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__RESET        4
11596 #define EMAC_REGS__DESIGNCFG_DEBUG6__TX_PBUF_QUEUE_SEGMENT_SIZE__READ(src) \
11597                     (((uint32_t)(src)\
11598                     & 0x000f0000U) >> 16)
11599 
11600 /* macros for field ext_tsu_timer */
11601 #define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__SHIFT                    20
11602 #define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__WIDTH                     1
11603 #define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__MASK            0x00100000U
11604 #define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__RESET                     1
11605 #define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__READ(src) \
11606                     (((uint32_t)(src)\
11607                     & 0x00100000U) >> 20)
11608 #define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__SET(dst) \
11609                     (dst) = ((dst) &\
11610                     ~0x00100000U) | ((uint32_t)(1) << 20)
11611 #define EMAC_REGS__DESIGNCFG_DEBUG6__EXT_TSU_TIMER__CLR(dst) \
11612                     (dst) = ((dst) &\
11613                     ~0x00100000U) | ((uint32_t)(0) << 20)
11614 
11615 /* macros for field tx_add_fifo_if */
11616 #define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__SHIFT                   21
11617 #define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__WIDTH                    1
11618 #define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__MASK           0x00200000U
11619 #define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__RESET                    0
11620 #define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__READ(src) \
11621                     (((uint32_t)(src)\
11622                     & 0x00200000U) >> 21)
11623 #define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__SET(dst) \
11624                     (dst) = ((dst) &\
11625                     ~0x00200000U) | ((uint32_t)(1) << 21)
11626 #define EMAC_REGS__DESIGNCFG_DEBUG6__TX_ADD_FIFO_IF__CLR(dst) \
11627                     (dst) = ((dst) &\
11628                     ~0x00200000U) | ((uint32_t)(0) << 21)
11629 
11630 /* macros for field host_if_soft_select */
11631 #define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__SHIFT              22
11632 #define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__WIDTH               1
11633 #define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__MASK      0x00400000U
11634 #define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__RESET               1
11635 #define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__READ(src) \
11636                     (((uint32_t)(src)\
11637                     & 0x00400000U) >> 22)
11638 #define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__SET(dst) \
11639                     (dst) = ((dst) &\
11640                     ~0x00400000U) | ((uint32_t)(1) << 22)
11641 #define EMAC_REGS__DESIGNCFG_DEBUG6__HOST_IF_SOFT_SELECT__CLR(dst) \
11642                     (dst) = ((dst) &\
11643                     ~0x00400000U) | ((uint32_t)(0) << 22)
11644 
11645 /* macros for field dma_addr_width_is_64b */
11646 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__SHIFT            23
11647 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__WIDTH             1
11648 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__MASK    0x00800000U
11649 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__RESET             0
11650 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__READ(src) \
11651                     (((uint32_t)(src)\
11652                     & 0x00800000U) >> 23)
11653 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__SET(dst) \
11654                     (dst) = ((dst) &\
11655                     ~0x00800000U) | ((uint32_t)(1) << 23)
11656 #define EMAC_REGS__DESIGNCFG_DEBUG6__DMA_ADDR_WIDTH_IS_64B__CLR(dst) \
11657                     (dst) = ((dst) &\
11658                     ~0x00800000U) | ((uint32_t)(0) << 23)
11659 
11660 /* macros for field pfc_multi_quantum */
11661 #define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__SHIFT                24
11662 #define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__WIDTH                 1
11663 #define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__MASK        0x01000000U
11664 #define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__RESET                 1
11665 #define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__READ(src) \
11666                     (((uint32_t)(src)\
11667                     & 0x01000000U) >> 24)
11668 #define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__SET(dst) \
11669                     (dst) = ((dst) &\
11670                     ~0x01000000U) | ((uint32_t)(1) << 24)
11671 #define EMAC_REGS__DESIGNCFG_DEBUG6__PFC_MULTI_QUANTUM__CLR(dst) \
11672                     (dst) = ((dst) &\
11673                     ~0x01000000U) | ((uint32_t)(0) << 24)
11674 
11675 /* macros for field pbuf_cutthru */
11676 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__SHIFT                     25
11677 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__WIDTH                      1
11678 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__MASK             0x02000000U
11679 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__RESET                      1
11680 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__READ(src) \
11681                     (((uint32_t)(src)\
11682                     & 0x02000000U) >> 25)
11683 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__SET(dst) \
11684                     (dst) = ((dst) &\
11685                     ~0x02000000U) | ((uint32_t)(1) << 25)
11686 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_CUTTHRU__CLR(dst) \
11687                     (dst) = ((dst) &\
11688                     ~0x02000000U) | ((uint32_t)(0) << 25)
11689 
11690 /* macros for field pbuf_rsc */
11691 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__SHIFT                         26
11692 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__WIDTH                          1
11693 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__MASK                 0x04000000U
11694 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__RESET                          1
11695 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__READ(src) \
11696                     (((uint32_t)(src)\
11697                     & 0x04000000U) >> 26)
11698 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__SET(dst) \
11699                     (dst) = ((dst) &\
11700                     ~0x04000000U) | ((uint32_t)(1) << 26)
11701 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_RSC__CLR(dst) \
11702                     (dst) = ((dst) &\
11703                     ~0x04000000U) | ((uint32_t)(0) << 26)
11704 
11705 /* macros for field pbuf_lso */
11706 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__SHIFT                         27
11707 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__WIDTH                          1
11708 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__MASK                 0x08000000U
11709 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__RESET                          0
11710 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__READ(src) \
11711                     (((uint32_t)(src)\
11712                     & 0x08000000U) >> 27)
11713 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__SET(dst) \
11714                     (dst) = ((dst) &\
11715                     ~0x08000000U) | ((uint32_t)(1) << 27)
11716 #define EMAC_REGS__DESIGNCFG_DEBUG6__PBUF_LSO__CLR(dst) \
11717                     (dst) = ((dst) &\
11718                     ~0x08000000U) | ((uint32_t)(0) << 27)
11719 
11720 /* macros for field reserved_31_28 */
11721 #define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_31_28__SHIFT                   28
11722 #define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_31_28__WIDTH                    4
11723 #define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_31_28__MASK           0xf0000000U
11724 #define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_31_28__RESET                    0
11725 #define EMAC_REGS__DESIGNCFG_DEBUG6__RESERVED_31_28__READ(src) \
11726                     (((uint32_t)(src)\
11727                     & 0xf0000000U) >> 28)
11728 #define EMAC_REGS__DESIGNCFG_DEBUG6__TYPE                              uint32_t
11729 #define EMAC_REGS__DESIGNCFG_DEBUG6__READ                           0xffffffffU
11730 
11731 #endif /* __EMAC_REGS__DESIGNCFG_DEBUG6_MACRO__ */
11732 
11733 
11734 /* macros for designcfg_debug6 */
11735 #define INST_DESIGNCFG_DEBUG6__NUM                                            1
11736 
11737 /* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug7 */
11738 #ifndef __EMAC_REGS__DESIGNCFG_DEBUG7_MACRO__
11739 #define __EMAC_REGS__DESIGNCFG_DEBUG7_MACRO__
11740 
11741 /* macros for field tx_pbuf_num_segments_q0 */
11742 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q0__SHIFT           0
11743 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q0__WIDTH           4
11744 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q0__MASK  0x0000000fU
11745 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q0__RESET           0
11746 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q0__READ(src) \
11747                     ((uint32_t)(src)\
11748                     & 0x0000000fU)
11749 
11750 /* macros for field tx_pbuf_num_segments_q1 */
11751 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q1__SHIFT           4
11752 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q1__WIDTH           4
11753 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q1__MASK  0x000000f0U
11754 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q1__RESET           0
11755 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q1__READ(src) \
11756                     (((uint32_t)(src)\
11757                     & 0x000000f0U) >> 4)
11758 
11759 /* macros for field tx_pbuf_num_segments_q2 */
11760 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q2__SHIFT           8
11761 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q2__WIDTH           4
11762 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q2__MASK  0x00000f00U
11763 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q2__RESET           0
11764 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q2__READ(src) \
11765                     (((uint32_t)(src)\
11766                     & 0x00000f00U) >> 8)
11767 
11768 /* macros for field tx_pbuf_num_segments_q3 */
11769 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q3__SHIFT          12
11770 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q3__WIDTH           4
11771 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q3__MASK  0x0000f000U
11772 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q3__RESET           0
11773 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q3__READ(src) \
11774                     (((uint32_t)(src)\
11775                     & 0x0000f000U) >> 12)
11776 
11777 /* macros for field tx_pbuf_num_segments_q4 */
11778 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q4__SHIFT          16
11779 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q4__WIDTH           4
11780 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q4__MASK  0x000f0000U
11781 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q4__RESET           0
11782 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q4__READ(src) \
11783                     (((uint32_t)(src)\
11784                     & 0x000f0000U) >> 16)
11785 
11786 /* macros for field tx_pbuf_num_segments_q5 */
11787 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q5__SHIFT          20
11788 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q5__WIDTH           4
11789 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q5__MASK  0x00f00000U
11790 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q5__RESET           0
11791 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q5__READ(src) \
11792                     (((uint32_t)(src)\
11793                     & 0x00f00000U) >> 20)
11794 
11795 /* macros for field tx_pbuf_num_segments_q6 */
11796 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q6__SHIFT          24
11797 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q6__WIDTH           4
11798 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q6__MASK  0x0f000000U
11799 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q6__RESET           0
11800 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q6__READ(src) \
11801                     (((uint32_t)(src)\
11802                     & 0x0f000000U) >> 24)
11803 
11804 /* macros for field tx_pbuf_num_segments_q7 */
11805 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q7__SHIFT          28
11806 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q7__WIDTH           4
11807 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q7__MASK  0xf0000000U
11808 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q7__RESET           0
11809 #define EMAC_REGS__DESIGNCFG_DEBUG7__TX_PBUF_NUM_SEGMENTS_Q7__READ(src) \
11810                     (((uint32_t)(src)\
11811                     & 0xf0000000U) >> 28)
11812 #define EMAC_REGS__DESIGNCFG_DEBUG7__TYPE                              uint32_t
11813 #define EMAC_REGS__DESIGNCFG_DEBUG7__READ                           0xffffffffU
11814 
11815 #endif /* __EMAC_REGS__DESIGNCFG_DEBUG7_MACRO__ */
11816 
11817 
11818 /* macros for designcfg_debug7 */
11819 #define INST_DESIGNCFG_DEBUG7__NUM                                            1
11820 
11821 /* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug8 */
11822 #ifndef __EMAC_REGS__DESIGNCFG_DEBUG8_MACRO__
11823 #define __EMAC_REGS__DESIGNCFG_DEBUG8_MACRO__
11824 
11825 /* macros for field num_scr2_compare_regs */
11826 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__SHIFT             0
11827 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__WIDTH             8
11828 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__MASK    0x000000ffU
11829 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__RESET            32
11830 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_COMPARE_REGS__READ(src) \
11831                     ((uint32_t)(src)\
11832                     & 0x000000ffU)
11833 
11834 /* macros for field num_scr2_ethtype_regs */
11835 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__SHIFT             8
11836 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__WIDTH             8
11837 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__MASK    0x0000ff00U
11838 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__RESET             8
11839 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_SCR2_ETHTYPE_REGS__READ(src) \
11840                     (((uint32_t)(src)\
11841                     & 0x0000ff00U) >> 8)
11842 
11843 /* macros for field num_type2_screeners */
11844 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__SHIFT              16
11845 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__WIDTH               8
11846 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__MASK      0x00ff0000U
11847 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__RESET              16
11848 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE2_SCREENERS__READ(src) \
11849                     (((uint32_t)(src)\
11850                     & 0x00ff0000U) >> 16)
11851 
11852 /* macros for field num_type1_screeners */
11853 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__SHIFT              24
11854 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__WIDTH               8
11855 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__MASK      0xff000000U
11856 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__RESET              16
11857 #define EMAC_REGS__DESIGNCFG_DEBUG8__NUM_TYPE1_SCREENERS__READ(src) \
11858                     (((uint32_t)(src)\
11859                     & 0xff000000U) >> 24)
11860 #define EMAC_REGS__DESIGNCFG_DEBUG8__TYPE                              uint32_t
11861 #define EMAC_REGS__DESIGNCFG_DEBUG8__READ                           0xffffffffU
11862 
11863 #endif /* __EMAC_REGS__DESIGNCFG_DEBUG8_MACRO__ */
11864 
11865 
11866 /* macros for designcfg_debug8 */
11867 #define INST_DESIGNCFG_DEBUG8__NUM                                            1
11868 
11869 /* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug9 */
11870 #ifndef __EMAC_REGS__DESIGNCFG_DEBUG9_MACRO__
11871 #define __EMAC_REGS__DESIGNCFG_DEBUG9_MACRO__
11872 
11873 /* macros for field tx_pbuf_num_segments_q8 */
11874 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q8__SHIFT           0
11875 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q8__WIDTH           4
11876 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q8__MASK  0x0000000fU
11877 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q8__RESET           0
11878 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q8__READ(src) \
11879                     ((uint32_t)(src)\
11880                     & 0x0000000fU)
11881 
11882 /* macros for field tx_pbuf_num_segments_q9 */
11883 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q9__SHIFT           4
11884 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q9__WIDTH           4
11885 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q9__MASK  0x000000f0U
11886 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q9__RESET           0
11887 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q9__READ(src) \
11888                     (((uint32_t)(src)\
11889                     & 0x000000f0U) >> 4)
11890 
11891 /* macros for field tx_pbuf_num_segments_q10 */
11892 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q10__SHIFT          8
11893 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q10__WIDTH          4
11894 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q10__MASK 0x00000f00U
11895 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q10__RESET          0
11896 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q10__READ(src) \
11897                     (((uint32_t)(src)\
11898                     & 0x00000f00U) >> 8)
11899 
11900 /* macros for field tx_pbuf_num_segments_q11 */
11901 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q11__SHIFT         12
11902 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q11__WIDTH          4
11903 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q11__MASK 0x0000f000U
11904 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q11__RESET          0
11905 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q11__READ(src) \
11906                     (((uint32_t)(src)\
11907                     & 0x0000f000U) >> 12)
11908 
11909 /* macros for field tx_pbuf_num_segments_q12 */
11910 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q12__SHIFT         16
11911 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q12__WIDTH          4
11912 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q12__MASK 0x000f0000U
11913 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q12__RESET          0
11914 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q12__READ(src) \
11915                     (((uint32_t)(src)\
11916                     & 0x000f0000U) >> 16)
11917 
11918 /* macros for field tx_pbuf_num_segments_q13 */
11919 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q13__SHIFT         20
11920 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q13__WIDTH          4
11921 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q13__MASK 0x00f00000U
11922 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q13__RESET          0
11923 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q13__READ(src) \
11924                     (((uint32_t)(src)\
11925                     & 0x00f00000U) >> 20)
11926 
11927 /* macros for field tx_pbuf_num_segments_q14 */
11928 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q14__SHIFT         24
11929 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q14__WIDTH          4
11930 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q14__MASK 0x0f000000U
11931 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q14__RESET          0
11932 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q14__READ(src) \
11933                     (((uint32_t)(src)\
11934                     & 0x0f000000U) >> 24)
11935 
11936 /* macros for field tx_pbuf_num_segments_q15 */
11937 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q15__SHIFT         28
11938 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q15__WIDTH          4
11939 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q15__MASK 0xf0000000U
11940 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q15__RESET          0
11941 #define EMAC_REGS__DESIGNCFG_DEBUG9__TX_PBUF_NUM_SEGMENTS_Q15__READ(src) \
11942                     (((uint32_t)(src)\
11943                     & 0xf0000000U) >> 28)
11944 #define EMAC_REGS__DESIGNCFG_DEBUG9__TYPE                              uint32_t
11945 #define EMAC_REGS__DESIGNCFG_DEBUG9__READ                           0xffffffffU
11946 
11947 #endif /* __EMAC_REGS__DESIGNCFG_DEBUG9_MACRO__ */
11948 
11949 
11950 /* macros for designcfg_debug9 */
11951 #define INST_DESIGNCFG_DEBUG9__NUM                                            1
11952 
11953 /* macros for BlueprintGlobalNameSpace::emac_regs::designcfg_debug10 */
11954 #ifndef __EMAC_REGS__DESIGNCFG_DEBUG10_MACRO__
11955 #define __EMAC_REGS__DESIGNCFG_DEBUG10_MACRO__
11956 
11957 /* macros for field axi_rx_descr_wr_buff_bits */
11958 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_WR_BUFF_BITS__SHIFT        0
11959 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_WR_BUFF_BITS__WIDTH        4
11960 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_WR_BUFF_BITS__MASK \
11961                     0x0000000fU
11962 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_WR_BUFF_BITS__RESET        4
11963 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_WR_BUFF_BITS__READ(src) \
11964                     ((uint32_t)(src)\
11965                     & 0x0000000fU)
11966 
11967 /* macros for field axi_tx_descr_wr_buff_bits */
11968 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_WR_BUFF_BITS__SHIFT        4
11969 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_WR_BUFF_BITS__WIDTH        4
11970 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_WR_BUFF_BITS__MASK \
11971                     0x000000f0U
11972 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_WR_BUFF_BITS__RESET        4
11973 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_WR_BUFF_BITS__READ(src) \
11974                     (((uint32_t)(src)\
11975                     & 0x000000f0U) >> 4)
11976 
11977 /* macros for field axi_rx_descr_rd_buff_bits */
11978 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_RD_BUFF_BITS__SHIFT        8
11979 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_RD_BUFF_BITS__WIDTH        4
11980 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_RD_BUFF_BITS__MASK \
11981                     0x00000f00U
11982 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_RD_BUFF_BITS__RESET        4
11983 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_RX_DESCR_RD_BUFF_BITS__READ(src) \
11984                     (((uint32_t)(src)\
11985                     & 0x00000f00U) >> 8)
11986 
11987 /* macros for field axi_tx_descr_rd_buff_bits */
11988 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_RD_BUFF_BITS__SHIFT       12
11989 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_RD_BUFF_BITS__WIDTH        4
11990 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_RD_BUFF_BITS__MASK \
11991                     0x0000f000U
11992 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_RD_BUFF_BITS__RESET        4
11993 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_TX_DESCR_RD_BUFF_BITS__READ(src) \
11994                     (((uint32_t)(src)\
11995                     & 0x0000f000U) >> 12)
11996 
11997 /* macros for field axi_access_pipeline_bits */
11998 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_ACCESS_PIPELINE_BITS__SHIFT        16
11999 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_ACCESS_PIPELINE_BITS__WIDTH         4
12000 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_ACCESS_PIPELINE_BITS__MASK \
12001                     0x000f0000U
12002 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_ACCESS_PIPELINE_BITS__RESET         4
12003 #define EMAC_REGS__DESIGNCFG_DEBUG10__AXI_ACCESS_PIPELINE_BITS__READ(src) \
12004                     (((uint32_t)(src)\
12005                     & 0x000f0000U) >> 16)
12006 
12007 /* macros for field rx_pbuf_data */
12008 #define EMAC_REGS__DESIGNCFG_DEBUG10__RX_PBUF_DATA__SHIFT                    20
12009 #define EMAC_REGS__DESIGNCFG_DEBUG10__RX_PBUF_DATA__WIDTH                     4
12010 #define EMAC_REGS__DESIGNCFG_DEBUG10__RX_PBUF_DATA__MASK            0x00f00000U
12011 #define EMAC_REGS__DESIGNCFG_DEBUG10__RX_PBUF_DATA__RESET                     2
12012 #define EMAC_REGS__DESIGNCFG_DEBUG10__RX_PBUF_DATA__READ(src) \
12013                     (((uint32_t)(src)\
12014                     & 0x00f00000U) >> 20)
12015 
12016 /* macros for field tx_pbuf_data */
12017 #define EMAC_REGS__DESIGNCFG_DEBUG10__TX_PBUF_DATA__SHIFT                    24
12018 #define EMAC_REGS__DESIGNCFG_DEBUG10__TX_PBUF_DATA__WIDTH                     4
12019 #define EMAC_REGS__DESIGNCFG_DEBUG10__TX_PBUF_DATA__MASK            0x0f000000U
12020 #define EMAC_REGS__DESIGNCFG_DEBUG10__TX_PBUF_DATA__RESET                     2
12021 #define EMAC_REGS__DESIGNCFG_DEBUG10__TX_PBUF_DATA__READ(src) \
12022                     (((uint32_t)(src)\
12023                     & 0x0f000000U) >> 24)
12024 
12025 /* macros for field emac_bus_width */
12026 #define EMAC_REGS__DESIGNCFG_DEBUG10__EMAC_BUS_WIDTH__SHIFT                  28
12027 #define EMAC_REGS__DESIGNCFG_DEBUG10__EMAC_BUS_WIDTH__WIDTH                   4
12028 #define EMAC_REGS__DESIGNCFG_DEBUG10__EMAC_BUS_WIDTH__MASK          0xf0000000U
12029 #define EMAC_REGS__DESIGNCFG_DEBUG10__EMAC_BUS_WIDTH__RESET                   2
12030 #define EMAC_REGS__DESIGNCFG_DEBUG10__EMAC_BUS_WIDTH__READ(src) \
12031                     (((uint32_t)(src)\
12032                     & 0xf0000000U) >> 28)
12033 #define EMAC_REGS__DESIGNCFG_DEBUG10__TYPE                             uint32_t
12034 #define EMAC_REGS__DESIGNCFG_DEBUG10__READ                          0xffffffffU
12035 
12036 #endif /* __EMAC_REGS__DESIGNCFG_DEBUG10_MACRO__ */
12037 
12038 
12039 /* macros for designcfg_debug10 */
12040 #define INST_DESIGNCFG_DEBUG10__NUM                                           1
12041 
12042 /* macros for spec_add5_bottom */
12043 #define INST_SPEC_ADD5_BOTTOM__NUM                                            1
12044 
12045 /* macros for spec_add5_top */
12046 #define INST_SPEC_ADD5_TOP__NUM                                               1
12047 
12048 /* macros for spec_add6_bottom */
12049 #define INST_SPEC_ADD6_BOTTOM__NUM                                            1
12050 
12051 /* macros for spec_add6_top */
12052 #define INST_SPEC_ADD6_TOP__NUM                                               1
12053 
12054 /* macros for spec_add7_bottom */
12055 #define INST_SPEC_ADD7_BOTTOM__NUM                                            1
12056 
12057 /* macros for spec_add7_top */
12058 #define INST_SPEC_ADD7_TOP__NUM                                               1
12059 
12060 /* macros for spec_add8_bottom */
12061 #define INST_SPEC_ADD8_BOTTOM__NUM                                            1
12062 
12063 /* macros for spec_add8_top */
12064 #define INST_SPEC_ADD8_TOP__NUM                                               1
12065 
12066 /* macros for spec_add9_bottom */
12067 #define INST_SPEC_ADD9_BOTTOM__NUM                                            1
12068 
12069 /* macros for spec_add9_top */
12070 #define INST_SPEC_ADD9_TOP__NUM                                               1
12071 
12072 /* macros for spec_add10_bottom */
12073 #define INST_SPEC_ADD10_BOTTOM__NUM                                           1
12074 
12075 /* macros for spec_add10_top */
12076 #define INST_SPEC_ADD10_TOP__NUM                                              1
12077 
12078 /* macros for spec_add11_bottom */
12079 #define INST_SPEC_ADD11_BOTTOM__NUM                                           1
12080 
12081 /* macros for spec_add11_top */
12082 #define INST_SPEC_ADD11_TOP__NUM                                              1
12083 
12084 /* macros for spec_add12_bottom */
12085 #define INST_SPEC_ADD12_BOTTOM__NUM                                           1
12086 
12087 /* macros for spec_add12_top */
12088 #define INST_SPEC_ADD12_TOP__NUM                                              1
12089 
12090 /* macros for spec_add13_bottom */
12091 #define INST_SPEC_ADD13_BOTTOM__NUM                                           1
12092 
12093 /* macros for spec_add13_top */
12094 #define INST_SPEC_ADD13_TOP__NUM                                              1
12095 
12096 /* macros for spec_add14_bottom */
12097 #define INST_SPEC_ADD14_BOTTOM__NUM                                           1
12098 
12099 /* macros for spec_add14_top */
12100 #define INST_SPEC_ADD14_TOP__NUM                                              1
12101 
12102 /* macros for spec_add15_bottom */
12103 #define INST_SPEC_ADD15_BOTTOM__NUM                                           1
12104 
12105 /* macros for spec_add15_top */
12106 #define INST_SPEC_ADD15_TOP__NUM                                              1
12107 
12108 /* macros for spec_add16_bottom */
12109 #define INST_SPEC_ADD16_BOTTOM__NUM                                           1
12110 
12111 /* macros for spec_add16_top */
12112 #define INST_SPEC_ADD16_TOP__NUM                                              1
12113 
12114 /* macros for spec_add17_bottom */
12115 #define INST_SPEC_ADD17_BOTTOM__NUM                                           1
12116 
12117 /* macros for spec_add17_top */
12118 #define INST_SPEC_ADD17_TOP__NUM                                              1
12119 
12120 /* macros for spec_add18_bottom */
12121 #define INST_SPEC_ADD18_BOTTOM__NUM                                           1
12122 
12123 /* macros for spec_add18_top */
12124 #define INST_SPEC_ADD18_TOP__NUM                                              1
12125 
12126 /* macros for spec_add19_bottom */
12127 #define INST_SPEC_ADD19_BOTTOM__NUM                                           1
12128 
12129 /* macros for spec_add19_top */
12130 #define INST_SPEC_ADD19_TOP__NUM                                              1
12131 
12132 /* macros for spec_add20_bottom */
12133 #define INST_SPEC_ADD20_BOTTOM__NUM                                           1
12134 
12135 /* macros for spec_add20_top */
12136 #define INST_SPEC_ADD20_TOP__NUM                                              1
12137 
12138 /* macros for spec_add21_bottom */
12139 #define INST_SPEC_ADD21_BOTTOM__NUM                                           1
12140 
12141 /* macros for spec_add21_top */
12142 #define INST_SPEC_ADD21_TOP__NUM                                              1
12143 
12144 /* macros for spec_add22_bottom */
12145 #define INST_SPEC_ADD22_BOTTOM__NUM                                           1
12146 
12147 /* macros for spec_add22_top */
12148 #define INST_SPEC_ADD22_TOP__NUM                                              1
12149 
12150 /* macros for spec_add23_bottom */
12151 #define INST_SPEC_ADD23_BOTTOM__NUM                                           1
12152 
12153 /* macros for spec_add23_top */
12154 #define INST_SPEC_ADD23_TOP__NUM                                              1
12155 
12156 /* macros for spec_add24_bottom */
12157 #define INST_SPEC_ADD24_BOTTOM__NUM                                           1
12158 
12159 /* macros for spec_add24_top */
12160 #define INST_SPEC_ADD24_TOP__NUM                                              1
12161 
12162 /* macros for spec_add25_bottom */
12163 #define INST_SPEC_ADD25_BOTTOM__NUM                                           1
12164 
12165 /* macros for spec_add25_top */
12166 #define INST_SPEC_ADD25_TOP__NUM                                              1
12167 
12168 /* macros for spec_add26_bottom */
12169 #define INST_SPEC_ADD26_BOTTOM__NUM                                           1
12170 
12171 /* macros for spec_add26_top */
12172 #define INST_SPEC_ADD26_TOP__NUM                                              1
12173 
12174 /* macros for spec_add27_bottom */
12175 #define INST_SPEC_ADD27_BOTTOM__NUM                                           1
12176 
12177 /* macros for spec_add27_top */
12178 #define INST_SPEC_ADD27_TOP__NUM                                              1
12179 
12180 /* macros for spec_add28_bottom */
12181 #define INST_SPEC_ADD28_BOTTOM__NUM                                           1
12182 
12183 /* macros for spec_add28_top */
12184 #define INST_SPEC_ADD28_TOP__NUM                                              1
12185 
12186 /* macros for spec_add29_bottom */
12187 #define INST_SPEC_ADD29_BOTTOM__NUM                                           1
12188 
12189 /* macros for spec_add29_top */
12190 #define INST_SPEC_ADD29_TOP__NUM                                              1
12191 
12192 /* macros for spec_add30_bottom */
12193 #define INST_SPEC_ADD30_BOTTOM__NUM                                           1
12194 
12195 /* macros for spec_add30_top */
12196 #define INST_SPEC_ADD30_TOP__NUM                                              1
12197 
12198 /* macros for spec_add31_bottom */
12199 #define INST_SPEC_ADD31_BOTTOM__NUM                                           1
12200 
12201 /* macros for spec_add31_top */
12202 #define INST_SPEC_ADD31_TOP__NUM                                              1
12203 
12204 /* macros for spec_add32_bottom */
12205 #define INST_SPEC_ADD32_BOTTOM__NUM                                           1
12206 
12207 /* macros for spec_add32_top */
12208 #define INST_SPEC_ADD32_TOP__NUM                                              1
12209 
12210 /* macros for spec_add33_bottom */
12211 #define INST_SPEC_ADD33_BOTTOM__NUM                                           1
12212 
12213 /* macros for spec_add33_top */
12214 #define INST_SPEC_ADD33_TOP__NUM                                              1
12215 
12216 /* macros for spec_add34_bottom */
12217 #define INST_SPEC_ADD34_BOTTOM__NUM                                           1
12218 
12219 /* macros for spec_add34_top */
12220 #define INST_SPEC_ADD34_TOP__NUM                                              1
12221 
12222 /* macros for spec_add35_bottom */
12223 #define INST_SPEC_ADD35_BOTTOM__NUM                                           1
12224 
12225 /* macros for spec_add35_top */
12226 #define INST_SPEC_ADD35_TOP__NUM                                              1
12227 
12228 /* macros for spec_add36_bottom */
12229 #define INST_SPEC_ADD36_BOTTOM__NUM                                           1
12230 
12231 /* macros for spec_add36_top */
12232 #define INST_SPEC_ADD36_TOP__NUM                                              1
12233 
12234 /* macros for BlueprintGlobalNameSpace::emac_regs::int_q_status */
12235 #ifndef __EMAC_REGS__INT_Q_STATUS_MACRO__
12236 #define __EMAC_REGS__INT_Q_STATUS_MACRO__
12237 
12238 /* macros for field reserved_0 */
12239 #define EMAC_REGS__INT_Q_STATUS__RESERVED_0__SHIFT                            0
12240 #define EMAC_REGS__INT_Q_STATUS__RESERVED_0__WIDTH                            1
12241 #define EMAC_REGS__INT_Q_STATUS__RESERVED_0__MASK                   0x00000001U
12242 #define EMAC_REGS__INT_Q_STATUS__RESERVED_0__RESET                            0
12243 #define EMAC_REGS__INT_Q_STATUS__RESERVED_0__READ(src) \
12244                     ((uint32_t)(src)\
12245                     & 0x00000001U)
12246 #define EMAC_REGS__INT_Q_STATUS__RESERVED_0__SET(dst) \
12247                     (dst) = ((dst) &\
12248                     ~0x00000001U) | (uint32_t)(1)
12249 #define EMAC_REGS__INT_Q_STATUS__RESERVED_0__CLR(dst) \
12250                     (dst) = ((dst) &\
12251                     ~0x00000001U) | (uint32_t)(0)
12252 
12253 /* macros for field receive_complete */
12254 #define EMAC_REGS__INT_Q_STATUS__RECEIVE_COMPLETE__SHIFT                      1
12255 #define EMAC_REGS__INT_Q_STATUS__RECEIVE_COMPLETE__WIDTH                      1
12256 #define EMAC_REGS__INT_Q_STATUS__RECEIVE_COMPLETE__MASK             0x00000002U
12257 #define EMAC_REGS__INT_Q_STATUS__RECEIVE_COMPLETE__RESET                      0
12258 #define EMAC_REGS__INT_Q_STATUS__RECEIVE_COMPLETE__READ(src) \
12259                     (((uint32_t)(src)\
12260                     & 0x00000002U) >> 1)
12261 #define EMAC_REGS__INT_Q_STATUS__RECEIVE_COMPLETE__SET(dst) \
12262                     (dst) = ((dst) &\
12263                     ~0x00000002U) | ((uint32_t)(1) << 1)
12264 #define EMAC_REGS__INT_Q_STATUS__RECEIVE_COMPLETE__CLR(dst) \
12265                     (dst) = ((dst) &\
12266                     ~0x00000002U) | ((uint32_t)(0) << 1)
12267 
12268 /* macros for field rx_used_bit_read */
12269 #define EMAC_REGS__INT_Q_STATUS__RX_USED_BIT_READ__SHIFT                      2
12270 #define EMAC_REGS__INT_Q_STATUS__RX_USED_BIT_READ__WIDTH                      1
12271 #define EMAC_REGS__INT_Q_STATUS__RX_USED_BIT_READ__MASK             0x00000004U
12272 #define EMAC_REGS__INT_Q_STATUS__RX_USED_BIT_READ__RESET                      0
12273 #define EMAC_REGS__INT_Q_STATUS__RX_USED_BIT_READ__READ(src) \
12274                     (((uint32_t)(src)\
12275                     & 0x00000004U) >> 2)
12276 #define EMAC_REGS__INT_Q_STATUS__RX_USED_BIT_READ__SET(dst) \
12277                     (dst) = ((dst) &\
12278                     ~0x00000004U) | ((uint32_t)(1) << 2)
12279 #define EMAC_REGS__INT_Q_STATUS__RX_USED_BIT_READ__CLR(dst) \
12280                     (dst) = ((dst) &\
12281                     ~0x00000004U) | ((uint32_t)(0) << 2)
12282 
12283 /* macros for field reserved_4_3 */
12284 #define EMAC_REGS__INT_Q_STATUS__RESERVED_4_3__SHIFT                          3
12285 #define EMAC_REGS__INT_Q_STATUS__RESERVED_4_3__WIDTH                          2
12286 #define EMAC_REGS__INT_Q_STATUS__RESERVED_4_3__MASK                 0x00000018U
12287 #define EMAC_REGS__INT_Q_STATUS__RESERVED_4_3__RESET                          0
12288 #define EMAC_REGS__INT_Q_STATUS__RESERVED_4_3__READ(src) \
12289                     (((uint32_t)(src)\
12290                     & 0x00000018U) >> 3)
12291 
12292 /* macros for field retry_limit_exceeded_or_late_collision */
12293 #define EMAC_REGS__INT_Q_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SHIFT \
12294                     5
12295 #define EMAC_REGS__INT_Q_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__WIDTH \
12296                     1
12297 #define EMAC_REGS__INT_Q_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__MASK \
12298                     0x00000020U
12299 #define EMAC_REGS__INT_Q_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__RESET \
12300                     0
12301 #define EMAC_REGS__INT_Q_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__READ(src) \
12302                     (((uint32_t)(src)\
12303                     & 0x00000020U) >> 5)
12304 #define EMAC_REGS__INT_Q_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__SET(dst) \
12305                     (dst) = ((dst) &\
12306                     ~0x00000020U) | ((uint32_t)(1) << 5)
12307 #define EMAC_REGS__INT_Q_STATUS__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION__CLR(dst) \
12308                     (dst) = ((dst) &\
12309                     ~0x00000020U) | ((uint32_t)(0) << 5)
12310 
12311 /* macros for field amba_error */
12312 #define EMAC_REGS__INT_Q_STATUS__AMBA_ERROR__SHIFT                            6
12313 #define EMAC_REGS__INT_Q_STATUS__AMBA_ERROR__WIDTH                            1
12314 #define EMAC_REGS__INT_Q_STATUS__AMBA_ERROR__MASK                   0x00000040U
12315 #define EMAC_REGS__INT_Q_STATUS__AMBA_ERROR__RESET                            0
12316 #define EMAC_REGS__INT_Q_STATUS__AMBA_ERROR__READ(src) \
12317                     (((uint32_t)(src)\
12318                     & 0x00000040U) >> 6)
12319 #define EMAC_REGS__INT_Q_STATUS__AMBA_ERROR__SET(dst) \
12320                     (dst) = ((dst) &\
12321                     ~0x00000040U) | ((uint32_t)(1) << 6)
12322 #define EMAC_REGS__INT_Q_STATUS__AMBA_ERROR__CLR(dst) \
12323                     (dst) = ((dst) &\
12324                     ~0x00000040U) | ((uint32_t)(0) << 6)
12325 
12326 /* macros for field transmit_complete */
12327 #define EMAC_REGS__INT_Q_STATUS__TRANSMIT_COMPLETE__SHIFT                     7
12328 #define EMAC_REGS__INT_Q_STATUS__TRANSMIT_COMPLETE__WIDTH                     1
12329 #define EMAC_REGS__INT_Q_STATUS__TRANSMIT_COMPLETE__MASK            0x00000080U
12330 #define EMAC_REGS__INT_Q_STATUS__TRANSMIT_COMPLETE__RESET                     0
12331 #define EMAC_REGS__INT_Q_STATUS__TRANSMIT_COMPLETE__READ(src) \
12332                     (((uint32_t)(src)\
12333                     & 0x00000080U) >> 7)
12334 #define EMAC_REGS__INT_Q_STATUS__TRANSMIT_COMPLETE__SET(dst) \
12335                     (dst) = ((dst) &\
12336                     ~0x00000080U) | ((uint32_t)(1) << 7)
12337 #define EMAC_REGS__INT_Q_STATUS__TRANSMIT_COMPLETE__CLR(dst) \
12338                     (dst) = ((dst) &\
12339                     ~0x00000080U) | ((uint32_t)(0) << 7)
12340 
12341 /* macros for field reserved_9_8 */
12342 #define EMAC_REGS__INT_Q_STATUS__RESERVED_9_8__SHIFT                          8
12343 #define EMAC_REGS__INT_Q_STATUS__RESERVED_9_8__WIDTH                          2
12344 #define EMAC_REGS__INT_Q_STATUS__RESERVED_9_8__MASK                 0x00000300U
12345 #define EMAC_REGS__INT_Q_STATUS__RESERVED_9_8__RESET                          0
12346 #define EMAC_REGS__INT_Q_STATUS__RESERVED_9_8__READ(src) \
12347                     (((uint32_t)(src)\
12348                     & 0x00000300U) >> 8)
12349 
12350 /* macros for field receive_overrun */
12351 #define EMAC_REGS__INT_Q_STATUS__RECEIVE_OVERRUN__SHIFT                      10
12352 #define EMAC_REGS__INT_Q_STATUS__RECEIVE_OVERRUN__WIDTH                       1
12353 #define EMAC_REGS__INT_Q_STATUS__RECEIVE_OVERRUN__MASK              0x00000400U
12354 #define EMAC_REGS__INT_Q_STATUS__RECEIVE_OVERRUN__RESET                       0
12355 #define EMAC_REGS__INT_Q_STATUS__RECEIVE_OVERRUN__READ(src) \
12356                     (((uint32_t)(src)\
12357                     & 0x00000400U) >> 10)
12358 #define EMAC_REGS__INT_Q_STATUS__RECEIVE_OVERRUN__SET(dst) \
12359                     (dst) = ((dst) &\
12360                     ~0x00000400U) | ((uint32_t)(1) << 10)
12361 #define EMAC_REGS__INT_Q_STATUS__RECEIVE_OVERRUN__CLR(dst) \
12362                     (dst) = ((dst) &\
12363                     ~0x00000400U) | ((uint32_t)(0) << 10)
12364 
12365 /* macros for field resp_not_ok */
12366 #define EMAC_REGS__INT_Q_STATUS__RESP_NOT_OK__SHIFT                          11
12367 #define EMAC_REGS__INT_Q_STATUS__RESP_NOT_OK__WIDTH                           1
12368 #define EMAC_REGS__INT_Q_STATUS__RESP_NOT_OK__MASK                  0x00000800U
12369 #define EMAC_REGS__INT_Q_STATUS__RESP_NOT_OK__RESET                         0b0
12370 #define EMAC_REGS__INT_Q_STATUS__RESP_NOT_OK__READ(src) \
12371                     (((uint32_t)(src)\
12372                     & 0x00000800U) >> 11)
12373 #define EMAC_REGS__INT_Q_STATUS__RESP_NOT_OK__SET(dst) \
12374                     (dst) = ((dst) &\
12375                     ~0x00000800U) | ((uint32_t)(1) << 11)
12376 #define EMAC_REGS__INT_Q_STATUS__RESP_NOT_OK__CLR(dst) \
12377                     (dst) = ((dst) &\
12378                     ~0x00000800U) | ((uint32_t)(0) << 11)
12379 
12380 /* macros for field reserved_31_12 */
12381 #define EMAC_REGS__INT_Q_STATUS__RESERVED_31_12__SHIFT                       12
12382 #define EMAC_REGS__INT_Q_STATUS__RESERVED_31_12__WIDTH                       20
12383 #define EMAC_REGS__INT_Q_STATUS__RESERVED_31_12__MASK               0xfffff000U
12384 #define EMAC_REGS__INT_Q_STATUS__RESERVED_31_12__RESET                        0
12385 #define EMAC_REGS__INT_Q_STATUS__RESERVED_31_12__READ(src) \
12386                     (((uint32_t)(src)\
12387                     & 0xfffff000U) >> 12)
12388 #define EMAC_REGS__INT_Q_STATUS__TYPE                                  uint32_t
12389 #define EMAC_REGS__INT_Q_STATUS__READ                               0xffffffffU
12390 #define EMAC_REGS__INT_Q_STATUS__RCLR                               0x00000ce6U
12391 
12392 #endif /* __EMAC_REGS__INT_Q_STATUS_MACRO__ */
12393 
12394 
12395 /* macros for int_q1_status */
12396 #define INST_INT_Q1_STATUS__NUM                                               1
12397 
12398 /* macros for int_q2_status */
12399 #define INST_INT_Q2_STATUS__NUM                                               1
12400 
12401 /* macros for int_q3_status */
12402 #define INST_INT_Q3_STATUS__NUM                                               1
12403 
12404 /* macros for int_q4_status */
12405 #define INST_INT_Q4_STATUS__NUM                                               1
12406 
12407 /* macros for int_q5_status */
12408 #define INST_INT_Q5_STATUS__NUM                                               1
12409 
12410 /* macros for int_q6_status */
12411 #define INST_INT_Q6_STATUS__NUM                                               1
12412 
12413 /* macros for int_q7_status */
12414 #define INST_INT_Q7_STATUS__NUM                                               1
12415 
12416 /* macros for int_q8_status */
12417 #define INST_INT_Q8_STATUS__NUM                                               1
12418 
12419 /* macros for int_q9_status */
12420 #define INST_INT_Q9_STATUS__NUM                                               1
12421 
12422 /* macros for int_q10_status */
12423 #define INST_INT_Q10_STATUS__NUM                                              1
12424 
12425 /* macros for int_q11_status */
12426 #define INST_INT_Q11_STATUS__NUM                                              1
12427 
12428 /* macros for int_q12_status */
12429 #define INST_INT_Q12_STATUS__NUM                                              1
12430 
12431 /* macros for int_q13_status */
12432 #define INST_INT_Q13_STATUS__NUM                                              1
12433 
12434 /* macros for int_q14_status */
12435 #define INST_INT_Q14_STATUS__NUM                                              1
12436 
12437 /* macros for int_q15_status */
12438 #define INST_INT_Q15_STATUS__NUM                                              1
12439 
12440 /* macros for BlueprintGlobalNameSpace::emac_regs::transmit_qx_ptr */
12441 #ifndef __EMAC_REGS__TRANSMIT_QX_PTR_MACRO__
12442 #define __EMAC_REGS__TRANSMIT_QX_PTR_MACRO__
12443 
12444 /* macros for field dma_tx_dis_q */
12445 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__SHIFT                       0
12446 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__WIDTH                       1
12447 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__MASK              0x00000001U
12448 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__RESET                     0b0
12449 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__READ(src) \
12450                     ((uint32_t)(src)\
12451                     & 0x00000001U)
12452 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__WRITE(src) \
12453                     ((uint32_t)(src)\
12454                     & 0x00000001U)
12455 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__MODIFY(dst, src) \
12456                     (dst) = ((dst) &\
12457                     ~0x00000001U) | ((uint32_t)(src) &\
12458                     0x00000001U)
12459 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__VERIFY(src) \
12460                     (!(((uint32_t)(src)\
12461                     & ~0x00000001U)))
12462 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__SET(dst) \
12463                     (dst) = ((dst) &\
12464                     ~0x00000001U) | (uint32_t)(1)
12465 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_DIS_Q__CLR(dst) \
12466                     (dst) = ((dst) &\
12467                     ~0x00000001U) | (uint32_t)(0)
12468 
12469 /* macros for field reserved_1_1 */
12470 #define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1_1__SHIFT                       1
12471 #define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1_1__WIDTH                       1
12472 #define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1_1__MASK              0x00000002U
12473 #define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1_1__RESET                     0b0
12474 #define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1_1__READ(src) \
12475                     (((uint32_t)(src)\
12476                     & 0x00000002U) >> 1)
12477 #define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1_1__SET(dst) \
12478                     (dst) = ((dst) &\
12479                     ~0x00000002U) | ((uint32_t)(1) << 1)
12480 #define EMAC_REGS__TRANSMIT_QX_PTR__RESERVED_1_1__CLR(dst) \
12481                     (dst) = ((dst) &\
12482                     ~0x00000002U) | ((uint32_t)(0) << 1)
12483 
12484 /* macros for field dma_tx_q_ptr */
12485 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__SHIFT                       2
12486 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__WIDTH                      30
12487 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__MASK              0xfffffffcU
12488 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__RESET                       0
12489 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__READ(src) \
12490                     (((uint32_t)(src)\
12491                     & 0xfffffffcU) >> 2)
12492 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__WRITE(src) \
12493                     (((uint32_t)(src)\
12494                     << 2) & 0xfffffffcU)
12495 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__MODIFY(dst, src) \
12496                     (dst) = ((dst) &\
12497                     ~0xfffffffcU) | (((uint32_t)(src) <<\
12498                     2) & 0xfffffffcU)
12499 #define EMAC_REGS__TRANSMIT_QX_PTR__DMA_TX_Q_PTR__VERIFY(src) \
12500                     (!((((uint32_t)(src)\
12501                     << 2) & ~0xfffffffcU)))
12502 #define EMAC_REGS__TRANSMIT_QX_PTR__TYPE                               uint32_t
12503 #define EMAC_REGS__TRANSMIT_QX_PTR__READ                            0xffffffffU
12504 #define EMAC_REGS__TRANSMIT_QX_PTR__WRITE                           0xffffffffU
12505 
12506 #endif /* __EMAC_REGS__TRANSMIT_QX_PTR_MACRO__ */
12507 
12508 
12509 /* macros for transmit_q1_ptr */
12510 #define INST_TRANSMIT_Q1_PTR__NUM                                             1
12511 
12512 /* macros for transmit_q2_ptr */
12513 #define INST_TRANSMIT_Q2_PTR__NUM                                             1
12514 
12515 /* macros for transmit_q3_ptr */
12516 #define INST_TRANSMIT_Q3_PTR__NUM                                             1
12517 
12518 /* macros for transmit_q4_ptr */
12519 #define INST_TRANSMIT_Q4_PTR__NUM                                             1
12520 
12521 /* macros for transmit_q5_ptr */
12522 #define INST_TRANSMIT_Q5_PTR__NUM                                             1
12523 
12524 /* macros for transmit_q6_ptr */
12525 #define INST_TRANSMIT_Q6_PTR__NUM                                             1
12526 
12527 /* macros for transmit_q7_ptr */
12528 #define INST_TRANSMIT_Q7_PTR__NUM                                             1
12529 
12530 /* macros for transmit_q8_ptr */
12531 #define INST_TRANSMIT_Q8_PTR__NUM                                             1
12532 
12533 /* macros for transmit_q9_ptr */
12534 #define INST_TRANSMIT_Q9_PTR__NUM                                             1
12535 
12536 /* macros for transmit_q10_ptr */
12537 #define INST_TRANSMIT_Q10_PTR__NUM                                            1
12538 
12539 /* macros for transmit_q11_ptr */
12540 #define INST_TRANSMIT_Q11_PTR__NUM                                            1
12541 
12542 /* macros for transmit_q12_ptr */
12543 #define INST_TRANSMIT_Q12_PTR__NUM                                            1
12544 
12545 /* macros for transmit_q13_ptr */
12546 #define INST_TRANSMIT_Q13_PTR__NUM                                            1
12547 
12548 /* macros for transmit_q14_ptr */
12549 #define INST_TRANSMIT_Q14_PTR__NUM                                            1
12550 
12551 /* macros for transmit_q15_ptr */
12552 #define INST_TRANSMIT_Q15_PTR__NUM                                            1
12553 
12554 /* macros for BlueprintGlobalNameSpace::emac_regs::receive_qx_ptr */
12555 #ifndef __EMAC_REGS__RECEIVE_QX_PTR_MACRO__
12556 #define __EMAC_REGS__RECEIVE_QX_PTR_MACRO__
12557 
12558 /* macros for field dma_rx_dis_q */
12559 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__SHIFT                        0
12560 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__WIDTH                        1
12561 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__MASK               0x00000001U
12562 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__RESET                      0b0
12563 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__READ(src) \
12564                     ((uint32_t)(src)\
12565                     & 0x00000001U)
12566 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__WRITE(src) \
12567                     ((uint32_t)(src)\
12568                     & 0x00000001U)
12569 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__MODIFY(dst, src) \
12570                     (dst) = ((dst) &\
12571                     ~0x00000001U) | ((uint32_t)(src) &\
12572                     0x00000001U)
12573 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__VERIFY(src) \
12574                     (!(((uint32_t)(src)\
12575                     & ~0x00000001U)))
12576 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__SET(dst) \
12577                     (dst) = ((dst) &\
12578                     ~0x00000001U) | (uint32_t)(1)
12579 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_DIS_Q__CLR(dst) \
12580                     (dst) = ((dst) &\
12581                     ~0x00000001U) | (uint32_t)(0)
12582 
12583 /* macros for field reserved_1_1 */
12584 #define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1_1__SHIFT                        1
12585 #define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1_1__WIDTH                        1
12586 #define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1_1__MASK               0x00000002U
12587 #define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1_1__RESET                      0b0
12588 #define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1_1__READ(src) \
12589                     (((uint32_t)(src)\
12590                     & 0x00000002U) >> 1)
12591 #define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1_1__SET(dst) \
12592                     (dst) = ((dst) &\
12593                     ~0x00000002U) | ((uint32_t)(1) << 1)
12594 #define EMAC_REGS__RECEIVE_QX_PTR__RESERVED_1_1__CLR(dst) \
12595                     (dst) = ((dst) &\
12596                     ~0x00000002U) | ((uint32_t)(0) << 1)
12597 
12598 /* macros for field dma_rx_q_ptr */
12599 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__SHIFT                        2
12600 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__WIDTH                       30
12601 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__MASK               0xfffffffcU
12602 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__RESET                        0
12603 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__READ(src) \
12604                     (((uint32_t)(src)\
12605                     & 0xfffffffcU) >> 2)
12606 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__WRITE(src) \
12607                     (((uint32_t)(src)\
12608                     << 2) & 0xfffffffcU)
12609 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__MODIFY(dst, src) \
12610                     (dst) = ((dst) &\
12611                     ~0xfffffffcU) | (((uint32_t)(src) <<\
12612                     2) & 0xfffffffcU)
12613 #define EMAC_REGS__RECEIVE_QX_PTR__DMA_RX_Q_PTR__VERIFY(src) \
12614                     (!((((uint32_t)(src)\
12615                     << 2) & ~0xfffffffcU)))
12616 #define EMAC_REGS__RECEIVE_QX_PTR__TYPE                                uint32_t
12617 #define EMAC_REGS__RECEIVE_QX_PTR__READ                             0xffffffffU
12618 #define EMAC_REGS__RECEIVE_QX_PTR__WRITE                            0xffffffffU
12619 
12620 #endif /* __EMAC_REGS__RECEIVE_QX_PTR_MACRO__ */
12621 
12622 
12623 /* macros for receive_q1_ptr */
12624 #define INST_RECEIVE_Q1_PTR__NUM                                              1
12625 
12626 /* macros for receive_q2_ptr */
12627 #define INST_RECEIVE_Q2_PTR__NUM                                              1
12628 
12629 /* macros for receive_q3_ptr */
12630 #define INST_RECEIVE_Q3_PTR__NUM                                              1
12631 
12632 /* macros for receive_q4_ptr */
12633 #define INST_RECEIVE_Q4_PTR__NUM                                              1
12634 
12635 /* macros for receive_q5_ptr */
12636 #define INST_RECEIVE_Q5_PTR__NUM                                              1
12637 
12638 /* macros for receive_q6_ptr */
12639 #define INST_RECEIVE_Q6_PTR__NUM                                              1
12640 
12641 /* macros for receive_q7_ptr */
12642 #define INST_RECEIVE_Q7_PTR__NUM                                              1
12643 
12644 /* macros for BlueprintGlobalNameSpace::emac_regs::dma_rxbuf_size_q */
12645 #ifndef __EMAC_REGS__DMA_RXBUF_SIZE_Q_MACRO__
12646 #define __EMAC_REGS__DMA_RXBUF_SIZE_Q_MACRO__
12647 
12648 /* macros for field dma_rx_q_buf_size */
12649 #define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__SHIFT                 0
12650 #define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__WIDTH                 8
12651 #define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__MASK        0x000000ffU
12652 #define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__RESET                 2
12653 #define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__READ(src) \
12654                     ((uint32_t)(src)\
12655                     & 0x000000ffU)
12656 #define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__WRITE(src) \
12657                     ((uint32_t)(src)\
12658                     & 0x000000ffU)
12659 #define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__MODIFY(dst, src) \
12660                     (dst) = ((dst) &\
12661                     ~0x000000ffU) | ((uint32_t)(src) &\
12662                     0x000000ffU)
12663 #define EMAC_REGS__DMA_RXBUF_SIZE_Q__DMA_RX_Q_BUF_SIZE__VERIFY(src) \
12664                     (!(((uint32_t)(src)\
12665                     & ~0x000000ffU)))
12666 
12667 /* macros for field reserved_31_8 */
12668 #define EMAC_REGS__DMA_RXBUF_SIZE_Q__RESERVED_31_8__SHIFT                     8
12669 #define EMAC_REGS__DMA_RXBUF_SIZE_Q__RESERVED_31_8__WIDTH                    24
12670 #define EMAC_REGS__DMA_RXBUF_SIZE_Q__RESERVED_31_8__MASK            0xffffff00U
12671 #define EMAC_REGS__DMA_RXBUF_SIZE_Q__RESERVED_31_8__RESET                     0
12672 #define EMAC_REGS__DMA_RXBUF_SIZE_Q__RESERVED_31_8__READ(src) \
12673                     (((uint32_t)(src)\
12674                     & 0xffffff00U) >> 8)
12675 #define EMAC_REGS__DMA_RXBUF_SIZE_Q__TYPE                              uint32_t
12676 #define EMAC_REGS__DMA_RXBUF_SIZE_Q__READ                           0xffffffffU
12677 #define EMAC_REGS__DMA_RXBUF_SIZE_Q__WRITE                          0xffffffffU
12678 
12679 #endif /* __EMAC_REGS__DMA_RXBUF_SIZE_Q_MACRO__ */
12680 
12681 
12682 /* macros for dma_rxbuf_size_q1 */
12683 #define INST_DMA_RXBUF_SIZE_Q1__NUM                                           1
12684 
12685 /* macros for dma_rxbuf_size_q2 */
12686 #define INST_DMA_RXBUF_SIZE_Q2__NUM                                           1
12687 
12688 /* macros for dma_rxbuf_size_q3 */
12689 #define INST_DMA_RXBUF_SIZE_Q3__NUM                                           1
12690 
12691 /* macros for dma_rxbuf_size_q4 */
12692 #define INST_DMA_RXBUF_SIZE_Q4__NUM                                           1
12693 
12694 /* macros for dma_rxbuf_size_q5 */
12695 #define INST_DMA_RXBUF_SIZE_Q5__NUM                                           1
12696 
12697 /* macros for dma_rxbuf_size_q6 */
12698 #define INST_DMA_RXBUF_SIZE_Q6__NUM                                           1
12699 
12700 /* macros for dma_rxbuf_size_q7 */
12701 #define INST_DMA_RXBUF_SIZE_Q7__NUM                                           1
12702 
12703 /* macros for BlueprintGlobalNameSpace::emac_regs::cbs_control */
12704 #ifndef __EMAC_REGS__CBS_CONTROL_MACRO__
12705 #define __EMAC_REGS__CBS_CONTROL_MACRO__
12706 
12707 /* macros for field cbs_enable_queue_a */
12708 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__SHIFT                     0
12709 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__WIDTH                     1
12710 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__MASK            0x00000001U
12711 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__RESET                     0
12712 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__READ(src) \
12713                     ((uint32_t)(src)\
12714                     & 0x00000001U)
12715 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__WRITE(src) \
12716                     ((uint32_t)(src)\
12717                     & 0x00000001U)
12718 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__MODIFY(dst, src) \
12719                     (dst) = ((dst) &\
12720                     ~0x00000001U) | ((uint32_t)(src) &\
12721                     0x00000001U)
12722 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__VERIFY(src) \
12723                     (!(((uint32_t)(src)\
12724                     & ~0x00000001U)))
12725 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__SET(dst) \
12726                     (dst) = ((dst) &\
12727                     ~0x00000001U) | (uint32_t)(1)
12728 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_A__CLR(dst) \
12729                     (dst) = ((dst) &\
12730                     ~0x00000001U) | (uint32_t)(0)
12731 
12732 /* macros for field cbs_enable_queue_b */
12733 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__SHIFT                     1
12734 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__WIDTH                     1
12735 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__MASK            0x00000002U
12736 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__RESET                     0
12737 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__READ(src) \
12738                     (((uint32_t)(src)\
12739                     & 0x00000002U) >> 1)
12740 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__WRITE(src) \
12741                     (((uint32_t)(src)\
12742                     << 1) & 0x00000002U)
12743 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__MODIFY(dst, src) \
12744                     (dst) = ((dst) &\
12745                     ~0x00000002U) | (((uint32_t)(src) <<\
12746                     1) & 0x00000002U)
12747 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__VERIFY(src) \
12748                     (!((((uint32_t)(src)\
12749                     << 1) & ~0x00000002U)))
12750 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__SET(dst) \
12751                     (dst) = ((dst) &\
12752                     ~0x00000002U) | ((uint32_t)(1) << 1)
12753 #define EMAC_REGS__CBS_CONTROL__CBS_ENABLE_QUEUE_B__CLR(dst) \
12754                     (dst) = ((dst) &\
12755                     ~0x00000002U) | ((uint32_t)(0) << 1)
12756 
12757 /* macros for field reserved_31_2 */
12758 #define EMAC_REGS__CBS_CONTROL__RESERVED_31_2__SHIFT                          2
12759 #define EMAC_REGS__CBS_CONTROL__RESERVED_31_2__WIDTH                         30
12760 #define EMAC_REGS__CBS_CONTROL__RESERVED_31_2__MASK                 0xfffffffcU
12761 #define EMAC_REGS__CBS_CONTROL__RESERVED_31_2__RESET                          0
12762 #define EMAC_REGS__CBS_CONTROL__RESERVED_31_2__READ(src) \
12763                     (((uint32_t)(src)\
12764                     & 0xfffffffcU) >> 2)
12765 #define EMAC_REGS__CBS_CONTROL__TYPE                                   uint32_t
12766 #define EMAC_REGS__CBS_CONTROL__READ                                0xffffffffU
12767 #define EMAC_REGS__CBS_CONTROL__WRITE                               0xffffffffU
12768 
12769 #endif /* __EMAC_REGS__CBS_CONTROL_MACRO__ */
12770 
12771 
12772 /* macros for cbs_control */
12773 #define INST_CBS_CONTROL__NUM                                                 1
12774 
12775 /* macros for BlueprintGlobalNameSpace::emac_regs::cbs_idleslope_q_a */
12776 #ifndef __EMAC_REGS__CBS_IDLESLOPE_Q_A_MACRO__
12777 #define __EMAC_REGS__CBS_IDLESLOPE_Q_A_MACRO__
12778 
12779 /* macros for field idleslope_a */
12780 #define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__SHIFT                      0
12781 #define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__WIDTH                     32
12782 #define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__MASK             0xffffffffU
12783 #define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__RESET                      0
12784 #define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__READ(src) \
12785                     ((uint32_t)(src)\
12786                     & 0xffffffffU)
12787 #define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__WRITE(src) \
12788                     ((uint32_t)(src)\
12789                     & 0xffffffffU)
12790 #define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__MODIFY(dst, src) \
12791                     (dst) = ((dst) &\
12792                     ~0xffffffffU) | ((uint32_t)(src) &\
12793                     0xffffffffU)
12794 #define EMAC_REGS__CBS_IDLESLOPE_Q_A__IDLESLOPE_A__VERIFY(src) \
12795                     (!(((uint32_t)(src)\
12796                     & ~0xffffffffU)))
12797 #define EMAC_REGS__CBS_IDLESLOPE_Q_A__TYPE                             uint32_t
12798 #define EMAC_REGS__CBS_IDLESLOPE_Q_A__READ                          0xffffffffU
12799 #define EMAC_REGS__CBS_IDLESLOPE_Q_A__WRITE                         0xffffffffU
12800 
12801 #endif /* __EMAC_REGS__CBS_IDLESLOPE_Q_A_MACRO__ */
12802 
12803 
12804 /* macros for cbs_idleslope_q_a */
12805 #define INST_CBS_IDLESLOPE_Q_A__NUM                                           1
12806 
12807 /* macros for BlueprintGlobalNameSpace::emac_regs::cbs_idleslope_q_b */
12808 #ifndef __EMAC_REGS__CBS_IDLESLOPE_Q_B_MACRO__
12809 #define __EMAC_REGS__CBS_IDLESLOPE_Q_B_MACRO__
12810 
12811 /* macros for field idleslope_b */
12812 #define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__SHIFT                      0
12813 #define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__WIDTH                     32
12814 #define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__MASK             0xffffffffU
12815 #define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__RESET                      0
12816 #define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__READ(src) \
12817                     ((uint32_t)(src)\
12818                     & 0xffffffffU)
12819 #define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__WRITE(src) \
12820                     ((uint32_t)(src)\
12821                     & 0xffffffffU)
12822 #define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__MODIFY(dst, src) \
12823                     (dst) = ((dst) &\
12824                     ~0xffffffffU) | ((uint32_t)(src) &\
12825                     0xffffffffU)
12826 #define EMAC_REGS__CBS_IDLESLOPE_Q_B__IDLESLOPE_B__VERIFY(src) \
12827                     (!(((uint32_t)(src)\
12828                     & ~0xffffffffU)))
12829 #define EMAC_REGS__CBS_IDLESLOPE_Q_B__TYPE                             uint32_t
12830 #define EMAC_REGS__CBS_IDLESLOPE_Q_B__READ                          0xffffffffU
12831 #define EMAC_REGS__CBS_IDLESLOPE_Q_B__WRITE                         0xffffffffU
12832 
12833 #endif /* __EMAC_REGS__CBS_IDLESLOPE_Q_B_MACRO__ */
12834 
12835 
12836 /* macros for cbs_idleslope_q_b */
12837 #define INST_CBS_IDLESLOPE_Q_B__NUM                                           1
12838 
12839 /* macros for BlueprintGlobalNameSpace::emac_regs::upper_tx_q_base_addr */
12840 #ifndef __EMAC_REGS__UPPER_TX_Q_BASE_ADDR_MACRO__
12841 #define __EMAC_REGS__UPPER_TX_Q_BASE_ADDR_MACRO__
12842 
12843 /* macros for field upper_tx_q_base_addr */
12844 #define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__SHIFT          0
12845 #define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__WIDTH         32
12846 #define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__MASK 0xffffffffU
12847 #define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__RESET          0
12848 #define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__READ(src) \
12849                     ((uint32_t)(src)\
12850                     & 0xffffffffU)
12851 #define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__WRITE(src) \
12852                     ((uint32_t)(src)\
12853                     & 0xffffffffU)
12854 #define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__MODIFY(dst, src) \
12855                     (dst) = ((dst) &\
12856                     ~0xffffffffU) | ((uint32_t)(src) &\
12857                     0xffffffffU)
12858 #define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__UPPER_TX_Q_BASE_ADDR__VERIFY(src) \
12859                     (!(((uint32_t)(src)\
12860                     & ~0xffffffffU)))
12861 #define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__TYPE                          uint32_t
12862 #define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__READ                       0xffffffffU
12863 #define EMAC_REGS__UPPER_TX_Q_BASE_ADDR__WRITE                      0xffffffffU
12864 
12865 #endif /* __EMAC_REGS__UPPER_TX_Q_BASE_ADDR_MACRO__ */
12866 
12867 
12868 /* macros for upper_tx_q_base_addr */
12869 #define INST_UPPER_TX_Q_BASE_ADDR__NUM                                        1
12870 
12871 /* macros for BlueprintGlobalNameSpace::emac_regs::tx_bd_control */
12872 #ifndef __EMAC_REGS__TX_BD_CONTROL_MACRO__
12873 #define __EMAC_REGS__TX_BD_CONTROL_MACRO__
12874 
12875 /* macros for field reserved_3_0 */
12876 #define EMAC_REGS__TX_BD_CONTROL__RESERVED_3_0__SHIFT                         0
12877 #define EMAC_REGS__TX_BD_CONTROL__RESERVED_3_0__WIDTH                         4
12878 #define EMAC_REGS__TX_BD_CONTROL__RESERVED_3_0__MASK                0x0000000fU
12879 #define EMAC_REGS__TX_BD_CONTROL__RESERVED_3_0__RESET                         0
12880 #define EMAC_REGS__TX_BD_CONTROL__RESERVED_3_0__READ(src) \
12881                     ((uint32_t)(src)\
12882                     & 0x0000000fU)
12883 
12884 /* macros for field tx_bd_ts_mode */
12885 #define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__SHIFT                        4
12886 #define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__WIDTH                        2
12887 #define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__MASK               0x00000030U
12888 #define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__RESET                        0
12889 #define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__READ(src) \
12890                     (((uint32_t)(src)\
12891                     & 0x00000030U) >> 4)
12892 #define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__WRITE(src) \
12893                     (((uint32_t)(src)\
12894                     << 4) & 0x00000030U)
12895 #define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__MODIFY(dst, src) \
12896                     (dst) = ((dst) &\
12897                     ~0x00000030U) | (((uint32_t)(src) <<\
12898                     4) & 0x00000030U)
12899 #define EMAC_REGS__TX_BD_CONTROL__TX_BD_TS_MODE__VERIFY(src) \
12900                     (!((((uint32_t)(src)\
12901                     << 4) & ~0x00000030U)))
12902 
12903 /* macros for field reserved_31_6 */
12904 #define EMAC_REGS__TX_BD_CONTROL__RESERVED_31_6__SHIFT                        6
12905 #define EMAC_REGS__TX_BD_CONTROL__RESERVED_31_6__WIDTH                       26
12906 #define EMAC_REGS__TX_BD_CONTROL__RESERVED_31_6__MASK               0xffffffc0U
12907 #define EMAC_REGS__TX_BD_CONTROL__RESERVED_31_6__RESET                        0
12908 #define EMAC_REGS__TX_BD_CONTROL__RESERVED_31_6__READ(src) \
12909                     (((uint32_t)(src)\
12910                     & 0xffffffc0U) >> 6)
12911 #define EMAC_REGS__TX_BD_CONTROL__TYPE                                 uint32_t
12912 #define EMAC_REGS__TX_BD_CONTROL__READ                              0xffffffffU
12913 #define EMAC_REGS__TX_BD_CONTROL__WRITE                             0xffffffffU
12914 
12915 #endif /* __EMAC_REGS__TX_BD_CONTROL_MACRO__ */
12916 
12917 
12918 /* macros for tx_bd_control */
12919 #define INST_TX_BD_CONTROL__NUM                                               1
12920 
12921 /* macros for BlueprintGlobalNameSpace::emac_regs::rx_bd_control */
12922 #ifndef __EMAC_REGS__RX_BD_CONTROL_MACRO__
12923 #define __EMAC_REGS__RX_BD_CONTROL_MACRO__
12924 
12925 /* macros for field reserved_3_0 */
12926 #define EMAC_REGS__RX_BD_CONTROL__RESERVED_3_0__SHIFT                         0
12927 #define EMAC_REGS__RX_BD_CONTROL__RESERVED_3_0__WIDTH                         4
12928 #define EMAC_REGS__RX_BD_CONTROL__RESERVED_3_0__MASK                0x0000000fU
12929 #define EMAC_REGS__RX_BD_CONTROL__RESERVED_3_0__RESET                         0
12930 #define EMAC_REGS__RX_BD_CONTROL__RESERVED_3_0__READ(src) \
12931                     ((uint32_t)(src)\
12932                     & 0x0000000fU)
12933 
12934 /* macros for field rx_bd_ts_mode */
12935 #define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__SHIFT                        4
12936 #define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__WIDTH                        2
12937 #define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__MASK               0x00000030U
12938 #define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__RESET                        0
12939 #define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__READ(src) \
12940                     (((uint32_t)(src)\
12941                     & 0x00000030U) >> 4)
12942 #define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__WRITE(src) \
12943                     (((uint32_t)(src)\
12944                     << 4) & 0x00000030U)
12945 #define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__MODIFY(dst, src) \
12946                     (dst) = ((dst) &\
12947                     ~0x00000030U) | (((uint32_t)(src) <<\
12948                     4) & 0x00000030U)
12949 #define EMAC_REGS__RX_BD_CONTROL__RX_BD_TS_MODE__VERIFY(src) \
12950                     (!((((uint32_t)(src)\
12951                     << 4) & ~0x00000030U)))
12952 
12953 /* macros for field reserved_31_6 */
12954 #define EMAC_REGS__RX_BD_CONTROL__RESERVED_31_6__SHIFT                        6
12955 #define EMAC_REGS__RX_BD_CONTROL__RESERVED_31_6__WIDTH                       26
12956 #define EMAC_REGS__RX_BD_CONTROL__RESERVED_31_6__MASK               0xffffffc0U
12957 #define EMAC_REGS__RX_BD_CONTROL__RESERVED_31_6__RESET                        0
12958 #define EMAC_REGS__RX_BD_CONTROL__RESERVED_31_6__READ(src) \
12959                     (((uint32_t)(src)\
12960                     & 0xffffffc0U) >> 6)
12961 #define EMAC_REGS__RX_BD_CONTROL__TYPE                                 uint32_t
12962 #define EMAC_REGS__RX_BD_CONTROL__READ                              0xffffffffU
12963 #define EMAC_REGS__RX_BD_CONTROL__WRITE                             0xffffffffU
12964 
12965 #endif /* __EMAC_REGS__RX_BD_CONTROL_MACRO__ */
12966 
12967 
12968 /* macros for rx_bd_control */
12969 #define INST_RX_BD_CONTROL__NUM                                               1
12970 
12971 /* macros for BlueprintGlobalNameSpace::emac_regs::upper_rx_q_base_addr */
12972 #ifndef __EMAC_REGS__UPPER_RX_Q_BASE_ADDR_MACRO__
12973 #define __EMAC_REGS__UPPER_RX_Q_BASE_ADDR_MACRO__
12974 
12975 /* macros for field upper_rx_q_base_addr */
12976 #define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__SHIFT          0
12977 #define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__WIDTH         32
12978 #define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__MASK 0xffffffffU
12979 #define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__RESET          0
12980 #define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__READ(src) \
12981                     ((uint32_t)(src)\
12982                     & 0xffffffffU)
12983 #define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__WRITE(src) \
12984                     ((uint32_t)(src)\
12985                     & 0xffffffffU)
12986 #define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__MODIFY(dst, src) \
12987                     (dst) = ((dst) &\
12988                     ~0xffffffffU) | ((uint32_t)(src) &\
12989                     0xffffffffU)
12990 #define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__UPPER_RX_Q_BASE_ADDR__VERIFY(src) \
12991                     (!(((uint32_t)(src)\
12992                     & ~0xffffffffU)))
12993 #define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__TYPE                          uint32_t
12994 #define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__READ                       0xffffffffU
12995 #define EMAC_REGS__UPPER_RX_Q_BASE_ADDR__WRITE                      0xffffffffU
12996 
12997 #endif /* __EMAC_REGS__UPPER_RX_Q_BASE_ADDR_MACRO__ */
12998 
12999 
13000 /* macros for upper_rx_q_base_addr */
13001 #define INST_UPPER_RX_Q_BASE_ADDR__NUM                                        1
13002 
13003 /* macros for BlueprintGlobalNameSpace::emac_regs::screening_type_1_register */
13004 #ifndef __EMAC_REGS__SCREENING_TYPE_1_REGISTER_MACRO__
13005 #define __EMAC_REGS__SCREENING_TYPE_1_REGISTER_MACRO__
13006 
13007 /* macros for field queue_number */
13008 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__SHIFT             0
13009 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__WIDTH             4
13010 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__MASK    0x0000000fU
13011 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__RESET             0
13012 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__READ(src) \
13013                     ((uint32_t)(src)\
13014                     & 0x0000000fU)
13015 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__WRITE(src) \
13016                     ((uint32_t)(src)\
13017                     & 0x0000000fU)
13018 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__MODIFY(dst, src) \
13019                     (dst) = ((dst) &\
13020                     ~0x0000000fU) | ((uint32_t)(src) &\
13021                     0x0000000fU)
13022 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__QUEUE_NUMBER__VERIFY(src) \
13023                     (!(((uint32_t)(src)\
13024                     & ~0x0000000fU)))
13025 
13026 /* macros for field dstc_match */
13027 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__SHIFT               4
13028 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__WIDTH               8
13029 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__MASK      0x00000ff0U
13030 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__RESET               0
13031 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__READ(src) \
13032                     (((uint32_t)(src)\
13033                     & 0x00000ff0U) >> 4)
13034 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__WRITE(src) \
13035                     (((uint32_t)(src)\
13036                     << 4) & 0x00000ff0U)
13037 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__MODIFY(dst, src) \
13038                     (dst) = ((dst) &\
13039                     ~0x00000ff0U) | (((uint32_t)(src) <<\
13040                     4) & 0x00000ff0U)
13041 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_MATCH__VERIFY(src) \
13042                     (!((((uint32_t)(src)\
13043                     << 4) & ~0x00000ff0U)))
13044 
13045 /* macros for field udp_port_match */
13046 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__SHIFT          12
13047 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__WIDTH          16
13048 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__MASK  0x0ffff000U
13049 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__RESET           0
13050 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__READ(src) \
13051                     (((uint32_t)(src)\
13052                     & 0x0ffff000U) >> 12)
13053 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__WRITE(src) \
13054                     (((uint32_t)(src)\
13055                     << 12) & 0x0ffff000U)
13056 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__MODIFY(dst, src) \
13057                     (dst) = ((dst) &\
13058                     ~0x0ffff000U) | (((uint32_t)(src) <<\
13059                     12) & 0x0ffff000U)
13060 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH__VERIFY(src) \
13061                     (!((((uint32_t)(src)\
13062                     << 12) & ~0x0ffff000U)))
13063 
13064 /* macros for field dstc_enable */
13065 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__SHIFT             28
13066 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__WIDTH              1
13067 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__MASK     0x10000000U
13068 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__RESET              0
13069 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__READ(src) \
13070                     (((uint32_t)(src)\
13071                     & 0x10000000U) >> 28)
13072 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__WRITE(src) \
13073                     (((uint32_t)(src)\
13074                     << 28) & 0x10000000U)
13075 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__MODIFY(dst, src) \
13076                     (dst) = ((dst) &\
13077                     ~0x10000000U) | (((uint32_t)(src) <<\
13078                     28) & 0x10000000U)
13079 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__VERIFY(src) \
13080                     (!((((uint32_t)(src)\
13081                     << 28) & ~0x10000000U)))
13082 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__SET(dst) \
13083                     (dst) = ((dst) &\
13084                     ~0x10000000U) | ((uint32_t)(1) << 28)
13085 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__DSTC_ENABLE__CLR(dst) \
13086                     (dst) = ((dst) &\
13087                     ~0x10000000U) | ((uint32_t)(0) << 28)
13088 
13089 /* macros for field udp_port_match_enable */
13090 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__SHIFT   29
13091 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__WIDTH    1
13092 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__MASK \
13093                     0x20000000U
13094 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__RESET    0
13095 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__READ(src) \
13096                     (((uint32_t)(src)\
13097                     & 0x20000000U) >> 29)
13098 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__WRITE(src) \
13099                     (((uint32_t)(src)\
13100                     << 29) & 0x20000000U)
13101 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__MODIFY(dst, src) \
13102                     (dst) = ((dst) &\
13103                     ~0x20000000U) | (((uint32_t)(src) <<\
13104                     29) & 0x20000000U)
13105 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__VERIFY(src) \
13106                     (!((((uint32_t)(src)\
13107                     << 29) & ~0x20000000U)))
13108 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__SET(dst) \
13109                     (dst) = ((dst) &\
13110                     ~0x20000000U) | ((uint32_t)(1) << 29)
13111 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__UDP_PORT_MATCH_ENABLE__CLR(dst) \
13112                     (dst) = ((dst) &\
13113                     ~0x20000000U) | ((uint32_t)(0) << 29)
13114 
13115 /* macros for field reserved_31_30 */
13116 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31_30__SHIFT          30
13117 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31_30__WIDTH           2
13118 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31_30__MASK  0xc0000000U
13119 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31_30__RESET           0
13120 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__RESERVED_31_30__READ(src) \
13121                     (((uint32_t)(src)\
13122                     & 0xc0000000U) >> 30)
13123 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__TYPE                     uint32_t
13124 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__READ                  0xffffffffU
13125 #define EMAC_REGS__SCREENING_TYPE_1_REGISTER__WRITE                 0xffffffffU
13126 
13127 #endif /* __EMAC_REGS__SCREENING_TYPE_1_REGISTER_MACRO__ */
13128 
13129 
13130 /* macros for screening_type_1_register_0 */
13131 #define INST_SCREENING_TYPE_1_REGISTER_0__NUM                                 1
13132 
13133 /* macros for screening_type_1_register_1 */
13134 #define INST_SCREENING_TYPE_1_REGISTER_1__NUM                                 1
13135 
13136 /* macros for screening_type_1_register_2 */
13137 #define INST_SCREENING_TYPE_1_REGISTER_2__NUM                                 1
13138 
13139 /* macros for screening_type_1_register_3 */
13140 #define INST_SCREENING_TYPE_1_REGISTER_3__NUM                                 1
13141 
13142 /* macros for screening_type_1_register_4 */
13143 #define INST_SCREENING_TYPE_1_REGISTER_4__NUM                                 1
13144 
13145 /* macros for screening_type_1_register_5 */
13146 #define INST_SCREENING_TYPE_1_REGISTER_5__NUM                                 1
13147 
13148 /* macros for screening_type_1_register_6 */
13149 #define INST_SCREENING_TYPE_1_REGISTER_6__NUM                                 1
13150 
13151 /* macros for screening_type_1_register_7 */
13152 #define INST_SCREENING_TYPE_1_REGISTER_7__NUM                                 1
13153 
13154 /* macros for screening_type_1_register_8 */
13155 #define INST_SCREENING_TYPE_1_REGISTER_8__NUM                                 1
13156 
13157 /* macros for screening_type_1_register_9 */
13158 #define INST_SCREENING_TYPE_1_REGISTER_9__NUM                                 1
13159 
13160 /* macros for screening_type_1_register_10 */
13161 #define INST_SCREENING_TYPE_1_REGISTER_10__NUM                                1
13162 
13163 /* macros for screening_type_1_register_11 */
13164 #define INST_SCREENING_TYPE_1_REGISTER_11__NUM                                1
13165 
13166 /* macros for screening_type_1_register_12 */
13167 #define INST_SCREENING_TYPE_1_REGISTER_12__NUM                                1
13168 
13169 /* macros for screening_type_1_register_13 */
13170 #define INST_SCREENING_TYPE_1_REGISTER_13__NUM                                1
13171 
13172 /* macros for screening_type_1_register_14 */
13173 #define INST_SCREENING_TYPE_1_REGISTER_14__NUM                                1
13174 
13175 /* macros for screening_type_1_register_15 */
13176 #define INST_SCREENING_TYPE_1_REGISTER_15__NUM                                1
13177 
13178 /* macros for BlueprintGlobalNameSpace::emac_regs::screening_type_2_register */
13179 #ifndef __EMAC_REGS__SCREENING_TYPE_2_REGISTER_MACRO__
13180 #define __EMAC_REGS__SCREENING_TYPE_2_REGISTER_MACRO__
13181 
13182 /* macros for field queue_number */
13183 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__SHIFT             0
13184 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__WIDTH             4
13185 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__MASK    0x0000000fU
13186 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__RESET             0
13187 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__READ(src) \
13188                     ((uint32_t)(src)\
13189                     & 0x0000000fU)
13190 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__WRITE(src) \
13191                     ((uint32_t)(src)\
13192                     & 0x0000000fU)
13193 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__MODIFY(dst, src) \
13194                     (dst) = ((dst) &\
13195                     ~0x0000000fU) | ((uint32_t)(src) &\
13196                     0x0000000fU)
13197 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__QUEUE_NUMBER__VERIFY(src) \
13198                     (!(((uint32_t)(src)\
13199                     & ~0x0000000fU)))
13200 
13201 /* macros for field vlan_priority */
13202 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__SHIFT            4
13203 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__WIDTH            3
13204 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__MASK   0x00000070U
13205 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__RESET            0
13206 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__READ(src) \
13207                     (((uint32_t)(src)\
13208                     & 0x00000070U) >> 4)
13209 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__WRITE(src) \
13210                     (((uint32_t)(src)\
13211                     << 4) & 0x00000070U)
13212 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__MODIFY(dst, src) \
13213                     (dst) = ((dst) &\
13214                     ~0x00000070U) | (((uint32_t)(src) <<\
13215                     4) & 0x00000070U)
13216 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_PRIORITY__VERIFY(src) \
13217                     (!((((uint32_t)(src)\
13218                     << 4) & ~0x00000070U)))
13219 
13220 /* macros for field reserved_7 */
13221 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__SHIFT               7
13222 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__WIDTH               1
13223 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__MASK      0x00000080U
13224 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__RESET               0
13225 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__READ(src) \
13226                     (((uint32_t)(src)\
13227                     & 0x00000080U) >> 7)
13228 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__WRITE(src) \
13229                     (((uint32_t)(src)\
13230                     << 7) & 0x00000080U)
13231 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__MODIFY(dst, src) \
13232                     (dst) = ((dst) &\
13233                     ~0x00000080U) | (((uint32_t)(src) <<\
13234                     7) & 0x00000080U)
13235 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__VERIFY(src) \
13236                     (!((((uint32_t)(src)\
13237                     << 7) & ~0x00000080U)))
13238 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__SET(dst) \
13239                     (dst) = ((dst) &\
13240                     ~0x00000080U) | ((uint32_t)(1) << 7)
13241 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_7__CLR(dst) \
13242                     (dst) = ((dst) &\
13243                     ~0x00000080U) | ((uint32_t)(0) << 7)
13244 
13245 /* macros for field vlan_enable */
13246 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__SHIFT              8
13247 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__WIDTH              1
13248 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__MASK     0x00000100U
13249 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__RESET              0
13250 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__READ(src) \
13251                     (((uint32_t)(src)\
13252                     & 0x00000100U) >> 8)
13253 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__WRITE(src) \
13254                     (((uint32_t)(src)\
13255                     << 8) & 0x00000100U)
13256 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__MODIFY(dst, src) \
13257                     (dst) = ((dst) &\
13258                     ~0x00000100U) | (((uint32_t)(src) <<\
13259                     8) & 0x00000100U)
13260 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__VERIFY(src) \
13261                     (!((((uint32_t)(src)\
13262                     << 8) & ~0x00000100U)))
13263 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__SET(dst) \
13264                     (dst) = ((dst) &\
13265                     ~0x00000100U) | ((uint32_t)(1) << 8)
13266 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__VLAN_ENABLE__CLR(dst) \
13267                     (dst) = ((dst) &\
13268                     ~0x00000100U) | ((uint32_t)(0) << 8)
13269 
13270 /* macros for field index */
13271 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__SHIFT                    9
13272 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__WIDTH                    3
13273 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__MASK           0x00000e00U
13274 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__RESET                    0
13275 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__READ(src) \
13276                     (((uint32_t)(src)\
13277                     & 0x00000e00U) >> 9)
13278 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__WRITE(src) \
13279                     (((uint32_t)(src)\
13280                     << 9) & 0x00000e00U)
13281 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__MODIFY(dst, src) \
13282                     (dst) = ((dst) &\
13283                     ~0x00000e00U) | (((uint32_t)(src) <<\
13284                     9) & 0x00000e00U)
13285 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__INDEX__VERIFY(src) \
13286                     (!((((uint32_t)(src)\
13287                     << 9) & ~0x00000e00U)))
13288 
13289 /* macros for field ethertype_enable */
13290 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__SHIFT        12
13291 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__WIDTH         1
13292 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__MASK \
13293                     0x00001000U
13294 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__RESET         0
13295 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__READ(src) \
13296                     (((uint32_t)(src)\
13297                     & 0x00001000U) >> 12)
13298 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__WRITE(src) \
13299                     (((uint32_t)(src)\
13300                     << 12) & 0x00001000U)
13301 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__MODIFY(dst, src) \
13302                     (dst) = ((dst) &\
13303                     ~0x00001000U) | (((uint32_t)(src) <<\
13304                     12) & 0x00001000U)
13305 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__VERIFY(src) \
13306                     (!((((uint32_t)(src)\
13307                     << 12) & ~0x00001000U)))
13308 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__SET(dst) \
13309                     (dst) = ((dst) &\
13310                     ~0x00001000U) | ((uint32_t)(1) << 12)
13311 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__ETHERTYPE_ENABLE__CLR(dst) \
13312                     (dst) = ((dst) &\
13313                     ~0x00001000U) | ((uint32_t)(0) << 12)
13314 
13315 /* macros for field compare_a */
13316 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__SHIFT               13
13317 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__WIDTH                5
13318 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__MASK       0x0003e000U
13319 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__RESET                0
13320 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__READ(src) \
13321                     (((uint32_t)(src)\
13322                     & 0x0003e000U) >> 13)
13323 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__WRITE(src) \
13324                     (((uint32_t)(src)\
13325                     << 13) & 0x0003e000U)
13326 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__MODIFY(dst, src) \
13327                     (dst) = ((dst) &\
13328                     ~0x0003e000U) | (((uint32_t)(src) <<\
13329                     13) & 0x0003e000U)
13330 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A__VERIFY(src) \
13331                     (!((((uint32_t)(src)\
13332                     << 13) & ~0x0003e000U)))
13333 
13334 /* macros for field compare_a_enable */
13335 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__SHIFT        18
13336 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__WIDTH         1
13337 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__MASK \
13338                     0x00040000U
13339 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__RESET         0
13340 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__READ(src) \
13341                     (((uint32_t)(src)\
13342                     & 0x00040000U) >> 18)
13343 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__WRITE(src) \
13344                     (((uint32_t)(src)\
13345                     << 18) & 0x00040000U)
13346 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__MODIFY(dst, src) \
13347                     (dst) = ((dst) &\
13348                     ~0x00040000U) | (((uint32_t)(src) <<\
13349                     18) & 0x00040000U)
13350 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__VERIFY(src) \
13351                     (!((((uint32_t)(src)\
13352                     << 18) & ~0x00040000U)))
13353 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__SET(dst) \
13354                     (dst) = ((dst) &\
13355                     ~0x00040000U) | ((uint32_t)(1) << 18)
13356 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_A_ENABLE__CLR(dst) \
13357                     (dst) = ((dst) &\
13358                     ~0x00040000U) | ((uint32_t)(0) << 18)
13359 
13360 /* macros for field compare_b */
13361 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__SHIFT               19
13362 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__WIDTH                5
13363 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__MASK       0x00f80000U
13364 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__RESET                0
13365 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__READ(src) \
13366                     (((uint32_t)(src)\
13367                     & 0x00f80000U) >> 19)
13368 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__WRITE(src) \
13369                     (((uint32_t)(src)\
13370                     << 19) & 0x00f80000U)
13371 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__MODIFY(dst, src) \
13372                     (dst) = ((dst) &\
13373                     ~0x00f80000U) | (((uint32_t)(src) <<\
13374                     19) & 0x00f80000U)
13375 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B__VERIFY(src) \
13376                     (!((((uint32_t)(src)\
13377                     << 19) & ~0x00f80000U)))
13378 
13379 /* macros for field compare_b_enable */
13380 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__SHIFT        24
13381 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__WIDTH         1
13382 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__MASK \
13383                     0x01000000U
13384 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__RESET         0
13385 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__READ(src) \
13386                     (((uint32_t)(src)\
13387                     & 0x01000000U) >> 24)
13388 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__WRITE(src) \
13389                     (((uint32_t)(src)\
13390                     << 24) & 0x01000000U)
13391 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__MODIFY(dst, src) \
13392                     (dst) = ((dst) &\
13393                     ~0x01000000U) | (((uint32_t)(src) <<\
13394                     24) & 0x01000000U)
13395 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__VERIFY(src) \
13396                     (!((((uint32_t)(src)\
13397                     << 24) & ~0x01000000U)))
13398 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__SET(dst) \
13399                     (dst) = ((dst) &\
13400                     ~0x01000000U) | ((uint32_t)(1) << 24)
13401 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_B_ENABLE__CLR(dst) \
13402                     (dst) = ((dst) &\
13403                     ~0x01000000U) | ((uint32_t)(0) << 24)
13404 
13405 /* macros for field compare_c */
13406 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__SHIFT               25
13407 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__WIDTH                5
13408 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__MASK       0x3e000000U
13409 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__RESET                0
13410 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__READ(src) \
13411                     (((uint32_t)(src)\
13412                     & 0x3e000000U) >> 25)
13413 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__WRITE(src) \
13414                     (((uint32_t)(src)\
13415                     << 25) & 0x3e000000U)
13416 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__MODIFY(dst, src) \
13417                     (dst) = ((dst) &\
13418                     ~0x3e000000U) | (((uint32_t)(src) <<\
13419                     25) & 0x3e000000U)
13420 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C__VERIFY(src) \
13421                     (!((((uint32_t)(src)\
13422                     << 25) & ~0x3e000000U)))
13423 
13424 /* macros for field compare_c_enable */
13425 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__SHIFT        30
13426 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__WIDTH         1
13427 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__MASK \
13428                     0x40000000U
13429 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__RESET         0
13430 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__READ(src) \
13431                     (((uint32_t)(src)\
13432                     & 0x40000000U) >> 30)
13433 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__WRITE(src) \
13434                     (((uint32_t)(src)\
13435                     << 30) & 0x40000000U)
13436 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__MODIFY(dst, src) \
13437                     (dst) = ((dst) &\
13438                     ~0x40000000U) | (((uint32_t)(src) <<\
13439                     30) & 0x40000000U)
13440 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__VERIFY(src) \
13441                     (!((((uint32_t)(src)\
13442                     << 30) & ~0x40000000U)))
13443 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__SET(dst) \
13444                     (dst) = ((dst) &\
13445                     ~0x40000000U) | ((uint32_t)(1) << 30)
13446 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__COMPARE_C_ENABLE__CLR(dst) \
13447                     (dst) = ((dst) &\
13448                     ~0x40000000U) | ((uint32_t)(0) << 30)
13449 
13450 /* macros for field reserved_31 */
13451 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_31__SHIFT             31
13452 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_31__WIDTH              1
13453 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_31__MASK     0x80000000U
13454 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_31__RESET              0
13455 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_31__READ(src) \
13456                     (((uint32_t)(src)\
13457                     & 0x80000000U) >> 31)
13458 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_31__SET(dst) \
13459                     (dst) = ((dst) &\
13460                     ~0x80000000U) | ((uint32_t)(1) << 31)
13461 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__RESERVED_31__CLR(dst) \
13462                     (dst) = ((dst) &\
13463                     ~0x80000000U) | ((uint32_t)(0) << 31)
13464 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__TYPE                     uint32_t
13465 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__READ                  0xffffffffU
13466 #define EMAC_REGS__SCREENING_TYPE_2_REGISTER__WRITE                 0xffffffffU
13467 
13468 #endif /* __EMAC_REGS__SCREENING_TYPE_2_REGISTER_MACRO__ */
13469 
13470 
13471 /* macros for screening_type_2_register_0 */
13472 #define INST_SCREENING_TYPE_2_REGISTER_0__NUM                                 1
13473 
13474 /* macros for screening_type_2_register_1 */
13475 #define INST_SCREENING_TYPE_2_REGISTER_1__NUM                                 1
13476 
13477 /* macros for screening_type_2_register_2 */
13478 #define INST_SCREENING_TYPE_2_REGISTER_2__NUM                                 1
13479 
13480 /* macros for screening_type_2_register_3 */
13481 #define INST_SCREENING_TYPE_2_REGISTER_3__NUM                                 1
13482 
13483 /* macros for screening_type_2_register_4 */
13484 #define INST_SCREENING_TYPE_2_REGISTER_4__NUM                                 1
13485 
13486 /* macros for screening_type_2_register_5 */
13487 #define INST_SCREENING_TYPE_2_REGISTER_5__NUM                                 1
13488 
13489 /* macros for screening_type_2_register_6 */
13490 #define INST_SCREENING_TYPE_2_REGISTER_6__NUM                                 1
13491 
13492 /* macros for screening_type_2_register_7 */
13493 #define INST_SCREENING_TYPE_2_REGISTER_7__NUM                                 1
13494 
13495 /* macros for screening_type_2_register_8 */
13496 #define INST_SCREENING_TYPE_2_REGISTER_8__NUM                                 1
13497 
13498 /* macros for screening_type_2_register_9 */
13499 #define INST_SCREENING_TYPE_2_REGISTER_9__NUM                                 1
13500 
13501 /* macros for screening_type_2_register_10 */
13502 #define INST_SCREENING_TYPE_2_REGISTER_10__NUM                                1
13503 
13504 /* macros for screening_type_2_register_11 */
13505 #define INST_SCREENING_TYPE_2_REGISTER_11__NUM                                1
13506 
13507 /* macros for screening_type_2_register_12 */
13508 #define INST_SCREENING_TYPE_2_REGISTER_12__NUM                                1
13509 
13510 /* macros for screening_type_2_register_13 */
13511 #define INST_SCREENING_TYPE_2_REGISTER_13__NUM                                1
13512 
13513 /* macros for screening_type_2_register_14 */
13514 #define INST_SCREENING_TYPE_2_REGISTER_14__NUM                                1
13515 
13516 /* macros for screening_type_2_register_15 */
13517 #define INST_SCREENING_TYPE_2_REGISTER_15__NUM                                1
13518 
13519 /* macros for BlueprintGlobalNameSpace::emac_regs::tx_sched_ctrl */
13520 #ifndef __EMAC_REGS__TX_SCHED_CTRL_MACRO__
13521 #define __EMAC_REGS__TX_SCHED_CTRL_MACRO__
13522 
13523 /* macros for field tx_sched_q1 */
13524 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__SHIFT                          0
13525 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__WIDTH                          2
13526 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__MASK                 0x00000003U
13527 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__RESET                          0
13528 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__READ(src) \
13529                     ((uint32_t)(src)\
13530                     & 0x00000003U)
13531 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__WRITE(src) \
13532                     ((uint32_t)(src)\
13533                     & 0x00000003U)
13534 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__MODIFY(dst, src) \
13535                     (dst) = ((dst) &\
13536                     ~0x00000003U) | ((uint32_t)(src) &\
13537                     0x00000003U)
13538 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q1__VERIFY(src) \
13539                     (!(((uint32_t)(src)\
13540                     & ~0x00000003U)))
13541 
13542 /* macros for field tx_sched_q2 */
13543 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__SHIFT                          2
13544 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__WIDTH                          2
13545 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__MASK                 0x0000000cU
13546 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__RESET                          0
13547 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__READ(src) \
13548                     (((uint32_t)(src)\
13549                     & 0x0000000cU) >> 2)
13550 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__WRITE(src) \
13551                     (((uint32_t)(src)\
13552                     << 2) & 0x0000000cU)
13553 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__MODIFY(dst, src) \
13554                     (dst) = ((dst) &\
13555                     ~0x0000000cU) | (((uint32_t)(src) <<\
13556                     2) & 0x0000000cU)
13557 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q2__VERIFY(src) \
13558                     (!((((uint32_t)(src)\
13559                     << 2) & ~0x0000000cU)))
13560 
13561 /* macros for field tx_sched_q3 */
13562 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__SHIFT                          4
13563 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__WIDTH                          2
13564 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__MASK                 0x00000030U
13565 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__RESET                          0
13566 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__READ(src) \
13567                     (((uint32_t)(src)\
13568                     & 0x00000030U) >> 4)
13569 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__WRITE(src) \
13570                     (((uint32_t)(src)\
13571                     << 4) & 0x00000030U)
13572 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__MODIFY(dst, src) \
13573                     (dst) = ((dst) &\
13574                     ~0x00000030U) | (((uint32_t)(src) <<\
13575                     4) & 0x00000030U)
13576 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q3__VERIFY(src) \
13577                     (!((((uint32_t)(src)\
13578                     << 4) & ~0x00000030U)))
13579 
13580 /* macros for field tx_sched_q4 */
13581 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__SHIFT                          6
13582 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__WIDTH                          2
13583 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__MASK                 0x000000c0U
13584 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__RESET                          0
13585 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__READ(src) \
13586                     (((uint32_t)(src)\
13587                     & 0x000000c0U) >> 6)
13588 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__WRITE(src) \
13589                     (((uint32_t)(src)\
13590                     << 6) & 0x000000c0U)
13591 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__MODIFY(dst, src) \
13592                     (dst) = ((dst) &\
13593                     ~0x000000c0U) | (((uint32_t)(src) <<\
13594                     6) & 0x000000c0U)
13595 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q4__VERIFY(src) \
13596                     (!((((uint32_t)(src)\
13597                     << 6) & ~0x000000c0U)))
13598 
13599 /* macros for field tx_sched_q5 */
13600 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__SHIFT                          8
13601 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__WIDTH                          2
13602 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__MASK                 0x00000300U
13603 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__RESET                          0
13604 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__READ(src) \
13605                     (((uint32_t)(src)\
13606                     & 0x00000300U) >> 8)
13607 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__WRITE(src) \
13608                     (((uint32_t)(src)\
13609                     << 8) & 0x00000300U)
13610 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__MODIFY(dst, src) \
13611                     (dst) = ((dst) &\
13612                     ~0x00000300U) | (((uint32_t)(src) <<\
13613                     8) & 0x00000300U)
13614 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q5__VERIFY(src) \
13615                     (!((((uint32_t)(src)\
13616                     << 8) & ~0x00000300U)))
13617 
13618 /* macros for field tx_sched_q6 */
13619 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__SHIFT                         10
13620 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__WIDTH                          2
13621 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__MASK                 0x00000c00U
13622 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__RESET                          0
13623 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__READ(src) \
13624                     (((uint32_t)(src)\
13625                     & 0x00000c00U) >> 10)
13626 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__WRITE(src) \
13627                     (((uint32_t)(src)\
13628                     << 10) & 0x00000c00U)
13629 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__MODIFY(dst, src) \
13630                     (dst) = ((dst) &\
13631                     ~0x00000c00U) | (((uint32_t)(src) <<\
13632                     10) & 0x00000c00U)
13633 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q6__VERIFY(src) \
13634                     (!((((uint32_t)(src)\
13635                     << 10) & ~0x00000c00U)))
13636 
13637 /* macros for field tx_sched_q7 */
13638 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__SHIFT                         12
13639 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__WIDTH                          2
13640 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__MASK                 0x00003000U
13641 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__RESET                          0
13642 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__READ(src) \
13643                     (((uint32_t)(src)\
13644                     & 0x00003000U) >> 12)
13645 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__WRITE(src) \
13646                     (((uint32_t)(src)\
13647                     << 12) & 0x00003000U)
13648 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__MODIFY(dst, src) \
13649                     (dst) = ((dst) &\
13650                     ~0x00003000U) | (((uint32_t)(src) <<\
13651                     12) & 0x00003000U)
13652 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q7__VERIFY(src) \
13653                     (!((((uint32_t)(src)\
13654                     << 12) & ~0x00003000U)))
13655 
13656 /* macros for field tx_sched_q8 */
13657 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__SHIFT                         14
13658 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__WIDTH                          2
13659 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__MASK                 0x0000c000U
13660 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__RESET                          0
13661 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__READ(src) \
13662                     (((uint32_t)(src)\
13663                     & 0x0000c000U) >> 14)
13664 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__WRITE(src) \
13665                     (((uint32_t)(src)\
13666                     << 14) & 0x0000c000U)
13667 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__MODIFY(dst, src) \
13668                     (dst) = ((dst) &\
13669                     ~0x0000c000U) | (((uint32_t)(src) <<\
13670                     14) & 0x0000c000U)
13671 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q8__VERIFY(src) \
13672                     (!((((uint32_t)(src)\
13673                     << 14) & ~0x0000c000U)))
13674 
13675 /* macros for field tx_sched_q9 */
13676 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__SHIFT                         16
13677 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__WIDTH                          2
13678 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__MASK                 0x00030000U
13679 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__RESET                          0
13680 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__READ(src) \
13681                     (((uint32_t)(src)\
13682                     & 0x00030000U) >> 16)
13683 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__WRITE(src) \
13684                     (((uint32_t)(src)\
13685                     << 16) & 0x00030000U)
13686 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__MODIFY(dst, src) \
13687                     (dst) = ((dst) &\
13688                     ~0x00030000U) | (((uint32_t)(src) <<\
13689                     16) & 0x00030000U)
13690 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q9__VERIFY(src) \
13691                     (!((((uint32_t)(src)\
13692                     << 16) & ~0x00030000U)))
13693 
13694 /* macros for field tx_sched_q10 */
13695 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__SHIFT                        18
13696 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__WIDTH                         2
13697 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__MASK                0x000c0000U
13698 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__RESET                         0
13699 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__READ(src) \
13700                     (((uint32_t)(src)\
13701                     & 0x000c0000U) >> 18)
13702 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__WRITE(src) \
13703                     (((uint32_t)(src)\
13704                     << 18) & 0x000c0000U)
13705 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__MODIFY(dst, src) \
13706                     (dst) = ((dst) &\
13707                     ~0x000c0000U) | (((uint32_t)(src) <<\
13708                     18) & 0x000c0000U)
13709 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q10__VERIFY(src) \
13710                     (!((((uint32_t)(src)\
13711                     << 18) & ~0x000c0000U)))
13712 
13713 /* macros for field tx_sched_q11 */
13714 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__SHIFT                        20
13715 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__WIDTH                         2
13716 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__MASK                0x00300000U
13717 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__RESET                         0
13718 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__READ(src) \
13719                     (((uint32_t)(src)\
13720                     & 0x00300000U) >> 20)
13721 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__WRITE(src) \
13722                     (((uint32_t)(src)\
13723                     << 20) & 0x00300000U)
13724 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__MODIFY(dst, src) \
13725                     (dst) = ((dst) &\
13726                     ~0x00300000U) | (((uint32_t)(src) <<\
13727                     20) & 0x00300000U)
13728 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q11__VERIFY(src) \
13729                     (!((((uint32_t)(src)\
13730                     << 20) & ~0x00300000U)))
13731 
13732 /* macros for field tx_sched_q12 */
13733 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__SHIFT                        22
13734 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__WIDTH                         2
13735 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__MASK                0x00c00000U
13736 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__RESET                         0
13737 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__READ(src) \
13738                     (((uint32_t)(src)\
13739                     & 0x00c00000U) >> 22)
13740 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__WRITE(src) \
13741                     (((uint32_t)(src)\
13742                     << 22) & 0x00c00000U)
13743 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__MODIFY(dst, src) \
13744                     (dst) = ((dst) &\
13745                     ~0x00c00000U) | (((uint32_t)(src) <<\
13746                     22) & 0x00c00000U)
13747 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q12__VERIFY(src) \
13748                     (!((((uint32_t)(src)\
13749                     << 22) & ~0x00c00000U)))
13750 
13751 /* macros for field tx_sched_q13 */
13752 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__SHIFT                        24
13753 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__WIDTH                         2
13754 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__MASK                0x03000000U
13755 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__RESET                         0
13756 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__READ(src) \
13757                     (((uint32_t)(src)\
13758                     & 0x03000000U) >> 24)
13759 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__WRITE(src) \
13760                     (((uint32_t)(src)\
13761                     << 24) & 0x03000000U)
13762 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__MODIFY(dst, src) \
13763                     (dst) = ((dst) &\
13764                     ~0x03000000U) | (((uint32_t)(src) <<\
13765                     24) & 0x03000000U)
13766 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q13__VERIFY(src) \
13767                     (!((((uint32_t)(src)\
13768                     << 24) & ~0x03000000U)))
13769 
13770 /* macros for field tx_sched_q14 */
13771 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__SHIFT                        26
13772 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__WIDTH                         2
13773 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__MASK                0x0c000000U
13774 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__RESET                         0
13775 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__READ(src) \
13776                     (((uint32_t)(src)\
13777                     & 0x0c000000U) >> 26)
13778 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__WRITE(src) \
13779                     (((uint32_t)(src)\
13780                     << 26) & 0x0c000000U)
13781 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__MODIFY(dst, src) \
13782                     (dst) = ((dst) &\
13783                     ~0x0c000000U) | (((uint32_t)(src) <<\
13784                     26) & 0x0c000000U)
13785 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q14__VERIFY(src) \
13786                     (!((((uint32_t)(src)\
13787                     << 26) & ~0x0c000000U)))
13788 
13789 /* macros for field tx_sched_q15 */
13790 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__SHIFT                        28
13791 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__WIDTH                         2
13792 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__MASK                0x30000000U
13793 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__RESET                         0
13794 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__READ(src) \
13795                     (((uint32_t)(src)\
13796                     & 0x30000000U) >> 28)
13797 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__WRITE(src) \
13798                     (((uint32_t)(src)\
13799                     << 28) & 0x30000000U)
13800 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__MODIFY(dst, src) \
13801                     (dst) = ((dst) &\
13802                     ~0x30000000U) | (((uint32_t)(src) <<\
13803                     28) & 0x30000000U)
13804 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q15__VERIFY(src) \
13805                     (!((((uint32_t)(src)\
13806                     << 28) & ~0x30000000U)))
13807 
13808 /* macros for field tx_sched_q16 */
13809 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q16__SHIFT                        30
13810 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q16__WIDTH                         2
13811 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q16__MASK                0xc0000000U
13812 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q16__RESET                         0
13813 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q16__READ(src) \
13814                     (((uint32_t)(src)\
13815                     & 0xc0000000U) >> 30)
13816 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q16__WRITE(src) \
13817                     (((uint32_t)(src)\
13818                     << 30) & 0xc0000000U)
13819 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q16__MODIFY(dst, src) \
13820                     (dst) = ((dst) &\
13821                     ~0xc0000000U) | (((uint32_t)(src) <<\
13822                     30) & 0xc0000000U)
13823 #define EMAC_REGS__TX_SCHED_CTRL__TX_SCHED_Q16__VERIFY(src) \
13824                     (!((((uint32_t)(src)\
13825                     << 30) & ~0xc0000000U)))
13826 #define EMAC_REGS__TX_SCHED_CTRL__TYPE                                 uint32_t
13827 #define EMAC_REGS__TX_SCHED_CTRL__READ                              0xffffffffU
13828 #define EMAC_REGS__TX_SCHED_CTRL__WRITE                             0xffffffffU
13829 
13830 #endif /* __EMAC_REGS__TX_SCHED_CTRL_MACRO__ */
13831 
13832 
13833 /* macros for tx_sched_ctrl */
13834 #define INST_TX_SCHED_CTRL__NUM                                               1
13835 
13836 /* macros for BlueprintGlobalNameSpace::emac_regs::bw_rate_limit_q0to3 */
13837 #ifndef __EMAC_REGS__BW_RATE_LIMIT_Q0TO3_MACRO__
13838 #define __EMAC_REGS__BW_RATE_LIMIT_Q0TO3_MACRO__
13839 
13840 /* macros for field dwrr_ets_weight_q0 */
13841 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__SHIFT             0
13842 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__WIDTH             8
13843 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__MASK    0x000000ffU
13844 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__RESET             0
13845 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__READ(src) \
13846                     ((uint32_t)(src)\
13847                     & 0x000000ffU)
13848 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__WRITE(src) \
13849                     ((uint32_t)(src)\
13850                     & 0x000000ffU)
13851 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__MODIFY(dst, src) \
13852                     (dst) = ((dst) &\
13853                     ~0x000000ffU) | ((uint32_t)(src) &\
13854                     0x000000ffU)
13855 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q0__VERIFY(src) \
13856                     (!(((uint32_t)(src)\
13857                     & ~0x000000ffU)))
13858 
13859 /* macros for field dwrr_ets_weight_q1 */
13860 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__SHIFT             8
13861 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__WIDTH             8
13862 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__MASK    0x0000ff00U
13863 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__RESET             0
13864 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__READ(src) \
13865                     (((uint32_t)(src)\
13866                     & 0x0000ff00U) >> 8)
13867 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__WRITE(src) \
13868                     (((uint32_t)(src)\
13869                     << 8) & 0x0000ff00U)
13870 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__MODIFY(dst, src) \
13871                     (dst) = ((dst) &\
13872                     ~0x0000ff00U) | (((uint32_t)(src) <<\
13873                     8) & 0x0000ff00U)
13874 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q1__VERIFY(src) \
13875                     (!((((uint32_t)(src)\
13876                     << 8) & ~0x0000ff00U)))
13877 
13878 /* macros for field dwrr_ets_weight_q2 */
13879 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__SHIFT            16
13880 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__WIDTH             8
13881 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__MASK    0x00ff0000U
13882 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__RESET             0
13883 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__READ(src) \
13884                     (((uint32_t)(src)\
13885                     & 0x00ff0000U) >> 16)
13886 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__WRITE(src) \
13887                     (((uint32_t)(src)\
13888                     << 16) & 0x00ff0000U)
13889 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__MODIFY(dst, src) \
13890                     (dst) = ((dst) &\
13891                     ~0x00ff0000U) | (((uint32_t)(src) <<\
13892                     16) & 0x00ff0000U)
13893 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q2__VERIFY(src) \
13894                     (!((((uint32_t)(src)\
13895                     << 16) & ~0x00ff0000U)))
13896 
13897 /* macros for field dwrr_ets_weight_q3 */
13898 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__SHIFT            24
13899 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__WIDTH             8
13900 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__MASK    0xff000000U
13901 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__RESET             0
13902 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__READ(src) \
13903                     (((uint32_t)(src)\
13904                     & 0xff000000U) >> 24)
13905 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__WRITE(src) \
13906                     (((uint32_t)(src)\
13907                     << 24) & 0xff000000U)
13908 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__MODIFY(dst, src) \
13909                     (dst) = ((dst) &\
13910                     ~0xff000000U) | (((uint32_t)(src) <<\
13911                     24) & 0xff000000U)
13912 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__DWRR_ETS_WEIGHT_Q3__VERIFY(src) \
13913                     (!((((uint32_t)(src)\
13914                     << 24) & ~0xff000000U)))
13915 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__TYPE                           uint32_t
13916 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__READ                        0xffffffffU
13917 #define EMAC_REGS__BW_RATE_LIMIT_Q0TO3__WRITE                       0xffffffffU
13918 
13919 #endif /* __EMAC_REGS__BW_RATE_LIMIT_Q0TO3_MACRO__ */
13920 
13921 
13922 /* macros for bw_rate_limit_q0to3 */
13923 #define INST_BW_RATE_LIMIT_Q0TO3__NUM                                         1
13924 
13925 /* macros for BlueprintGlobalNameSpace::emac_regs::bw_rate_limit_q4to7 */
13926 #ifndef __EMAC_REGS__BW_RATE_LIMIT_Q4TO7_MACRO__
13927 #define __EMAC_REGS__BW_RATE_LIMIT_Q4TO7_MACRO__
13928 
13929 /* macros for field dwrr_ets_weight_q4 */
13930 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__SHIFT             0
13931 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__WIDTH             8
13932 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__MASK    0x000000ffU
13933 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__RESET             0
13934 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__READ(src) \
13935                     ((uint32_t)(src)\
13936                     & 0x000000ffU)
13937 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__WRITE(src) \
13938                     ((uint32_t)(src)\
13939                     & 0x000000ffU)
13940 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__MODIFY(dst, src) \
13941                     (dst) = ((dst) &\
13942                     ~0x000000ffU) | ((uint32_t)(src) &\
13943                     0x000000ffU)
13944 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q4__VERIFY(src) \
13945                     (!(((uint32_t)(src)\
13946                     & ~0x000000ffU)))
13947 
13948 /* macros for field dwrr_ets_weight_q5 */
13949 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__SHIFT             8
13950 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__WIDTH             8
13951 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__MASK    0x0000ff00U
13952 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__RESET             0
13953 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__READ(src) \
13954                     (((uint32_t)(src)\
13955                     & 0x0000ff00U) >> 8)
13956 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__WRITE(src) \
13957                     (((uint32_t)(src)\
13958                     << 8) & 0x0000ff00U)
13959 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__MODIFY(dst, src) \
13960                     (dst) = ((dst) &\
13961                     ~0x0000ff00U) | (((uint32_t)(src) <<\
13962                     8) & 0x0000ff00U)
13963 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q5__VERIFY(src) \
13964                     (!((((uint32_t)(src)\
13965                     << 8) & ~0x0000ff00U)))
13966 
13967 /* macros for field dwrr_ets_weight_q6 */
13968 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__SHIFT            16
13969 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__WIDTH             8
13970 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__MASK    0x00ff0000U
13971 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__RESET             0
13972 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__READ(src) \
13973                     (((uint32_t)(src)\
13974                     & 0x00ff0000U) >> 16)
13975 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__WRITE(src) \
13976                     (((uint32_t)(src)\
13977                     << 16) & 0x00ff0000U)
13978 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__MODIFY(dst, src) \
13979                     (dst) = ((dst) &\
13980                     ~0x00ff0000U) | (((uint32_t)(src) <<\
13981                     16) & 0x00ff0000U)
13982 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q6__VERIFY(src) \
13983                     (!((((uint32_t)(src)\
13984                     << 16) & ~0x00ff0000U)))
13985 
13986 /* macros for field dwrr_ets_weight_q7 */
13987 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__SHIFT            24
13988 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__WIDTH             8
13989 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__MASK    0xff000000U
13990 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__RESET             0
13991 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__READ(src) \
13992                     (((uint32_t)(src)\
13993                     & 0xff000000U) >> 24)
13994 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__WRITE(src) \
13995                     (((uint32_t)(src)\
13996                     << 24) & 0xff000000U)
13997 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__MODIFY(dst, src) \
13998                     (dst) = ((dst) &\
13999                     ~0xff000000U) | (((uint32_t)(src) <<\
14000                     24) & 0xff000000U)
14001 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__DWRR_ETS_WEIGHT_Q7__VERIFY(src) \
14002                     (!((((uint32_t)(src)\
14003                     << 24) & ~0xff000000U)))
14004 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__TYPE                           uint32_t
14005 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__READ                        0xffffffffU
14006 #define EMAC_REGS__BW_RATE_LIMIT_Q4TO7__WRITE                       0xffffffffU
14007 
14008 #endif /* __EMAC_REGS__BW_RATE_LIMIT_Q4TO7_MACRO__ */
14009 
14010 
14011 /* macros for bw_rate_limit_q4to7 */
14012 #define INST_BW_RATE_LIMIT_Q4TO7__NUM                                         1
14013 
14014 /* macros for BlueprintGlobalNameSpace::emac_regs::bw_rate_limit_q8to11 */
14015 #ifndef __EMAC_REGS__BW_RATE_LIMIT_Q8TO11_MACRO__
14016 #define __EMAC_REGS__BW_RATE_LIMIT_Q8TO11_MACRO__
14017 
14018 /* macros for field dwrr_ets_weight_q8 */
14019 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__SHIFT            0
14020 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__WIDTH            8
14021 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__MASK   0x000000ffU
14022 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__RESET            0
14023 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__READ(src) \
14024                     ((uint32_t)(src)\
14025                     & 0x000000ffU)
14026 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__WRITE(src) \
14027                     ((uint32_t)(src)\
14028                     & 0x000000ffU)
14029 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__MODIFY(dst, src) \
14030                     (dst) = ((dst) &\
14031                     ~0x000000ffU) | ((uint32_t)(src) &\
14032                     0x000000ffU)
14033 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q8__VERIFY(src) \
14034                     (!(((uint32_t)(src)\
14035                     & ~0x000000ffU)))
14036 
14037 /* macros for field dwrr_ets_weight_q9 */
14038 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__SHIFT            8
14039 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__WIDTH            8
14040 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__MASK   0x0000ff00U
14041 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__RESET            0
14042 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__READ(src) \
14043                     (((uint32_t)(src)\
14044                     & 0x0000ff00U) >> 8)
14045 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__WRITE(src) \
14046                     (((uint32_t)(src)\
14047                     << 8) & 0x0000ff00U)
14048 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__MODIFY(dst, src) \
14049                     (dst) = ((dst) &\
14050                     ~0x0000ff00U) | (((uint32_t)(src) <<\
14051                     8) & 0x0000ff00U)
14052 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q9__VERIFY(src) \
14053                     (!((((uint32_t)(src)\
14054                     << 8) & ~0x0000ff00U)))
14055 
14056 /* macros for field dwrr_ets_weight_q10 */
14057 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__SHIFT          16
14058 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__WIDTH           8
14059 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__MASK  0x00ff0000U
14060 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__RESET           0
14061 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__READ(src) \
14062                     (((uint32_t)(src)\
14063                     & 0x00ff0000U) >> 16)
14064 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__WRITE(src) \
14065                     (((uint32_t)(src)\
14066                     << 16) & 0x00ff0000U)
14067 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__MODIFY(dst, src) \
14068                     (dst) = ((dst) &\
14069                     ~0x00ff0000U) | (((uint32_t)(src) <<\
14070                     16) & 0x00ff0000U)
14071 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q10__VERIFY(src) \
14072                     (!((((uint32_t)(src)\
14073                     << 16) & ~0x00ff0000U)))
14074 
14075 /* macros for field dwrr_ets_weight_q11 */
14076 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__SHIFT          24
14077 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__WIDTH           8
14078 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__MASK  0xff000000U
14079 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__RESET           0
14080 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__READ(src) \
14081                     (((uint32_t)(src)\
14082                     & 0xff000000U) >> 24)
14083 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__WRITE(src) \
14084                     (((uint32_t)(src)\
14085                     << 24) & 0xff000000U)
14086 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__MODIFY(dst, src) \
14087                     (dst) = ((dst) &\
14088                     ~0xff000000U) | (((uint32_t)(src) <<\
14089                     24) & 0xff000000U)
14090 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__DWRR_ETS_WEIGHT_Q11__VERIFY(src) \
14091                     (!((((uint32_t)(src)\
14092                     << 24) & ~0xff000000U)))
14093 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__TYPE                          uint32_t
14094 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__READ                       0xffffffffU
14095 #define EMAC_REGS__BW_RATE_LIMIT_Q8TO11__WRITE                      0xffffffffU
14096 
14097 #endif /* __EMAC_REGS__BW_RATE_LIMIT_Q8TO11_MACRO__ */
14098 
14099 
14100 /* macros for bw_rate_limit_q8to11 */
14101 #define INST_BW_RATE_LIMIT_Q8TO11__NUM                                        1
14102 
14103 /* macros for BlueprintGlobalNameSpace::emac_regs::bw_rate_limit_q12to15 */
14104 #ifndef __EMAC_REGS__BW_RATE_LIMIT_Q12TO15_MACRO__
14105 #define __EMAC_REGS__BW_RATE_LIMIT_Q12TO15_MACRO__
14106 
14107 /* macros for field dwrr_ets_weight_q12 */
14108 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__SHIFT          0
14109 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__WIDTH          8
14110 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__MASK 0x000000ffU
14111 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__RESET          0
14112 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__READ(src) \
14113                     ((uint32_t)(src)\
14114                     & 0x000000ffU)
14115 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__WRITE(src) \
14116                     ((uint32_t)(src)\
14117                     & 0x000000ffU)
14118 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__MODIFY(dst, src) \
14119                     (dst) = ((dst) &\
14120                     ~0x000000ffU) | ((uint32_t)(src) &\
14121                     0x000000ffU)
14122 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q12__VERIFY(src) \
14123                     (!(((uint32_t)(src)\
14124                     & ~0x000000ffU)))
14125 
14126 /* macros for field dwrr_ets_weight_q13 */
14127 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__SHIFT          8
14128 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__WIDTH          8
14129 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__MASK 0x0000ff00U
14130 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__RESET          0
14131 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__READ(src) \
14132                     (((uint32_t)(src)\
14133                     & 0x0000ff00U) >> 8)
14134 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__WRITE(src) \
14135                     (((uint32_t)(src)\
14136                     << 8) & 0x0000ff00U)
14137 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__MODIFY(dst, src) \
14138                     (dst) = ((dst) &\
14139                     ~0x0000ff00U) | (((uint32_t)(src) <<\
14140                     8) & 0x0000ff00U)
14141 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q13__VERIFY(src) \
14142                     (!((((uint32_t)(src)\
14143                     << 8) & ~0x0000ff00U)))
14144 
14145 /* macros for field dwrr_ets_weight_q14 */
14146 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__SHIFT         16
14147 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__WIDTH          8
14148 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__MASK 0x00ff0000U
14149 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__RESET          0
14150 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__READ(src) \
14151                     (((uint32_t)(src)\
14152                     & 0x00ff0000U) >> 16)
14153 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__WRITE(src) \
14154                     (((uint32_t)(src)\
14155                     << 16) & 0x00ff0000U)
14156 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__MODIFY(dst, src) \
14157                     (dst) = ((dst) &\
14158                     ~0x00ff0000U) | (((uint32_t)(src) <<\
14159                     16) & 0x00ff0000U)
14160 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q14__VERIFY(src) \
14161                     (!((((uint32_t)(src)\
14162                     << 16) & ~0x00ff0000U)))
14163 
14164 /* macros for field dwrr_ets_weight_q15 */
14165 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__SHIFT         24
14166 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__WIDTH          8
14167 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__MASK 0xff000000U
14168 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__RESET          0
14169 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__READ(src) \
14170                     (((uint32_t)(src)\
14171                     & 0xff000000U) >> 24)
14172 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__WRITE(src) \
14173                     (((uint32_t)(src)\
14174                     << 24) & 0xff000000U)
14175 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__MODIFY(dst, src) \
14176                     (dst) = ((dst) &\
14177                     ~0xff000000U) | (((uint32_t)(src) <<\
14178                     24) & 0xff000000U)
14179 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__DWRR_ETS_WEIGHT_Q15__VERIFY(src) \
14180                     (!((((uint32_t)(src)\
14181                     << 24) & ~0xff000000U)))
14182 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__TYPE                         uint32_t
14183 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__READ                      0xffffffffU
14184 #define EMAC_REGS__BW_RATE_LIMIT_Q12TO15__WRITE                     0xffffffffU
14185 
14186 #endif /* __EMAC_REGS__BW_RATE_LIMIT_Q12TO15_MACRO__ */
14187 
14188 
14189 /* macros for bw_rate_limit_q12to15 */
14190 #define INST_BW_RATE_LIMIT_Q12TO15__NUM                                       1
14191 
14192 /* macros for BlueprintGlobalNameSpace::emac_regs::tx_q_seg_alloc_q0to7 */
14193 #ifndef __EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7_MACRO__
14194 #define __EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7_MACRO__
14195 
14196 /* macros for field segment_alloc_q0 */
14197 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q0__SHIFT              0
14198 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q0__WIDTH              3
14199 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q0__MASK     0x00000007U
14200 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q0__RESET              0
14201 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q0__READ(src) \
14202                     ((uint32_t)(src)\
14203                     & 0x00000007U)
14204 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q0__WRITE(src) \
14205                     ((uint32_t)(src)\
14206                     & 0x00000007U)
14207 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q0__MODIFY(dst, src) \
14208                     (dst) = ((dst) &\
14209                     ~0x00000007U) | ((uint32_t)(src) &\
14210                     0x00000007U)
14211 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q0__VERIFY(src) \
14212                     (!(((uint32_t)(src)\
14213                     & ~0x00000007U)))
14214 
14215 /* macros for field reserved_3_3 */
14216 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_3_3__SHIFT                  3
14217 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_3_3__WIDTH                  1
14218 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_3_3__MASK         0x00000008U
14219 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_3_3__RESET                  0
14220 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_3_3__READ(src) \
14221                     (((uint32_t)(src)\
14222                     & 0x00000008U) >> 3)
14223 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_3_3__SET(dst) \
14224                     (dst) = ((dst) &\
14225                     ~0x00000008U) | ((uint32_t)(1) << 3)
14226 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_3_3__CLR(dst) \
14227                     (dst) = ((dst) &\
14228                     ~0x00000008U) | ((uint32_t)(0) << 3)
14229 
14230 /* macros for field segment_alloc_q1 */
14231 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q1__SHIFT              4
14232 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q1__WIDTH              3
14233 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q1__MASK     0x00000070U
14234 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q1__RESET              0
14235 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q1__READ(src) \
14236                     (((uint32_t)(src)\
14237                     & 0x00000070U) >> 4)
14238 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q1__WRITE(src) \
14239                     (((uint32_t)(src)\
14240                     << 4) & 0x00000070U)
14241 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q1__MODIFY(dst, src) \
14242                     (dst) = ((dst) &\
14243                     ~0x00000070U) | (((uint32_t)(src) <<\
14244                     4) & 0x00000070U)
14245 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q1__VERIFY(src) \
14246                     (!((((uint32_t)(src)\
14247                     << 4) & ~0x00000070U)))
14248 
14249 /* macros for field reserved_7_7 */
14250 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_7_7__SHIFT                  7
14251 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_7_7__WIDTH                  1
14252 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_7_7__MASK         0x00000080U
14253 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_7_7__RESET                  0
14254 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_7_7__READ(src) \
14255                     (((uint32_t)(src)\
14256                     & 0x00000080U) >> 7)
14257 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_7_7__SET(dst) \
14258                     (dst) = ((dst) &\
14259                     ~0x00000080U) | ((uint32_t)(1) << 7)
14260 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_7_7__CLR(dst) \
14261                     (dst) = ((dst) &\
14262                     ~0x00000080U) | ((uint32_t)(0) << 7)
14263 
14264 /* macros for field segment_alloc_q2 */
14265 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q2__SHIFT              8
14266 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q2__WIDTH              3
14267 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q2__MASK     0x00000700U
14268 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q2__RESET              0
14269 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q2__READ(src) \
14270                     (((uint32_t)(src)\
14271                     & 0x00000700U) >> 8)
14272 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q2__WRITE(src) \
14273                     (((uint32_t)(src)\
14274                     << 8) & 0x00000700U)
14275 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q2__MODIFY(dst, src) \
14276                     (dst) = ((dst) &\
14277                     ~0x00000700U) | (((uint32_t)(src) <<\
14278                     8) & 0x00000700U)
14279 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q2__VERIFY(src) \
14280                     (!((((uint32_t)(src)\
14281                     << 8) & ~0x00000700U)))
14282 
14283 /* macros for field reserved_11_11 */
14284 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_11_11__SHIFT               11
14285 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_11_11__WIDTH                1
14286 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_11_11__MASK       0x00000800U
14287 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_11_11__RESET                0
14288 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_11_11__READ(src) \
14289                     (((uint32_t)(src)\
14290                     & 0x00000800U) >> 11)
14291 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_11_11__SET(dst) \
14292                     (dst) = ((dst) &\
14293                     ~0x00000800U) | ((uint32_t)(1) << 11)
14294 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_11_11__CLR(dst) \
14295                     (dst) = ((dst) &\
14296                     ~0x00000800U) | ((uint32_t)(0) << 11)
14297 
14298 /* macros for field segment_alloc_q3 */
14299 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q3__SHIFT             12
14300 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q3__WIDTH              3
14301 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q3__MASK     0x00007000U
14302 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q3__RESET              0
14303 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q3__READ(src) \
14304                     (((uint32_t)(src)\
14305                     & 0x00007000U) >> 12)
14306 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q3__WRITE(src) \
14307                     (((uint32_t)(src)\
14308                     << 12) & 0x00007000U)
14309 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q3__MODIFY(dst, src) \
14310                     (dst) = ((dst) &\
14311                     ~0x00007000U) | (((uint32_t)(src) <<\
14312                     12) & 0x00007000U)
14313 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q3__VERIFY(src) \
14314                     (!((((uint32_t)(src)\
14315                     << 12) & ~0x00007000U)))
14316 
14317 /* macros for field reserved_15_15 */
14318 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_15_15__SHIFT               15
14319 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_15_15__WIDTH                1
14320 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_15_15__MASK       0x00008000U
14321 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_15_15__RESET                0
14322 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_15_15__READ(src) \
14323                     (((uint32_t)(src)\
14324                     & 0x00008000U) >> 15)
14325 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_15_15__SET(dst) \
14326                     (dst) = ((dst) &\
14327                     ~0x00008000U) | ((uint32_t)(1) << 15)
14328 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_15_15__CLR(dst) \
14329                     (dst) = ((dst) &\
14330                     ~0x00008000U) | ((uint32_t)(0) << 15)
14331 
14332 /* macros for field segment_alloc_q4 */
14333 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q4__SHIFT             16
14334 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q4__WIDTH              3
14335 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q4__MASK     0x00070000U
14336 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q4__RESET              0
14337 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q4__READ(src) \
14338                     (((uint32_t)(src)\
14339                     & 0x00070000U) >> 16)
14340 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q4__WRITE(src) \
14341                     (((uint32_t)(src)\
14342                     << 16) & 0x00070000U)
14343 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q4__MODIFY(dst, src) \
14344                     (dst) = ((dst) &\
14345                     ~0x00070000U) | (((uint32_t)(src) <<\
14346                     16) & 0x00070000U)
14347 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q4__VERIFY(src) \
14348                     (!((((uint32_t)(src)\
14349                     << 16) & ~0x00070000U)))
14350 
14351 /* macros for field reserved_19_19 */
14352 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_19_19__SHIFT               19
14353 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_19_19__WIDTH                1
14354 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_19_19__MASK       0x00080000U
14355 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_19_19__RESET                0
14356 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_19_19__READ(src) \
14357                     (((uint32_t)(src)\
14358                     & 0x00080000U) >> 19)
14359 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_19_19__SET(dst) \
14360                     (dst) = ((dst) &\
14361                     ~0x00080000U) | ((uint32_t)(1) << 19)
14362 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_19_19__CLR(dst) \
14363                     (dst) = ((dst) &\
14364                     ~0x00080000U) | ((uint32_t)(0) << 19)
14365 
14366 /* macros for field segment_alloc_q5 */
14367 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q5__SHIFT             20
14368 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q5__WIDTH              3
14369 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q5__MASK     0x00700000U
14370 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q5__RESET              0
14371 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q5__READ(src) \
14372                     (((uint32_t)(src)\
14373                     & 0x00700000U) >> 20)
14374 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q5__WRITE(src) \
14375                     (((uint32_t)(src)\
14376                     << 20) & 0x00700000U)
14377 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q5__MODIFY(dst, src) \
14378                     (dst) = ((dst) &\
14379                     ~0x00700000U) | (((uint32_t)(src) <<\
14380                     20) & 0x00700000U)
14381 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q5__VERIFY(src) \
14382                     (!((((uint32_t)(src)\
14383                     << 20) & ~0x00700000U)))
14384 
14385 /* macros for field reserved_23_23 */
14386 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_23_23__SHIFT               23
14387 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_23_23__WIDTH                1
14388 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_23_23__MASK       0x00800000U
14389 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_23_23__RESET                0
14390 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_23_23__READ(src) \
14391                     (((uint32_t)(src)\
14392                     & 0x00800000U) >> 23)
14393 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_23_23__SET(dst) \
14394                     (dst) = ((dst) &\
14395                     ~0x00800000U) | ((uint32_t)(1) << 23)
14396 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_23_23__CLR(dst) \
14397                     (dst) = ((dst) &\
14398                     ~0x00800000U) | ((uint32_t)(0) << 23)
14399 
14400 /* macros for field segment_alloc_q6 */
14401 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q6__SHIFT             24
14402 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q6__WIDTH              3
14403 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q6__MASK     0x07000000U
14404 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q6__RESET              0
14405 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q6__READ(src) \
14406                     (((uint32_t)(src)\
14407                     & 0x07000000U) >> 24)
14408 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q6__WRITE(src) \
14409                     (((uint32_t)(src)\
14410                     << 24) & 0x07000000U)
14411 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q6__MODIFY(dst, src) \
14412                     (dst) = ((dst) &\
14413                     ~0x07000000U) | (((uint32_t)(src) <<\
14414                     24) & 0x07000000U)
14415 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q6__VERIFY(src) \
14416                     (!((((uint32_t)(src)\
14417                     << 24) & ~0x07000000U)))
14418 
14419 /* macros for field reserved_27_27 */
14420 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_27_27__SHIFT               27
14421 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_27_27__WIDTH                1
14422 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_27_27__MASK       0x08000000U
14423 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_27_27__RESET                0
14424 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_27_27__READ(src) \
14425                     (((uint32_t)(src)\
14426                     & 0x08000000U) >> 27)
14427 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_27_27__SET(dst) \
14428                     (dst) = ((dst) &\
14429                     ~0x08000000U) | ((uint32_t)(1) << 27)
14430 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_27_27__CLR(dst) \
14431                     (dst) = ((dst) &\
14432                     ~0x08000000U) | ((uint32_t)(0) << 27)
14433 
14434 /* macros for field segment_alloc_q7 */
14435 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q7__SHIFT             28
14436 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q7__WIDTH              3
14437 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q7__MASK     0x70000000U
14438 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q7__RESET              0
14439 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q7__READ(src) \
14440                     (((uint32_t)(src)\
14441                     & 0x70000000U) >> 28)
14442 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q7__WRITE(src) \
14443                     (((uint32_t)(src)\
14444                     << 28) & 0x70000000U)
14445 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q7__MODIFY(dst, src) \
14446                     (dst) = ((dst) &\
14447                     ~0x70000000U) | (((uint32_t)(src) <<\
14448                     28) & 0x70000000U)
14449 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__SEGMENT_ALLOC_Q7__VERIFY(src) \
14450                     (!((((uint32_t)(src)\
14451                     << 28) & ~0x70000000U)))
14452 
14453 /* macros for field reserved_31_31 */
14454 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_31_31__SHIFT               31
14455 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_31_31__WIDTH                1
14456 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_31_31__MASK       0x80000000U
14457 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_31_31__RESET                0
14458 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_31_31__READ(src) \
14459                     (((uint32_t)(src)\
14460                     & 0x80000000U) >> 31)
14461 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_31_31__SET(dst) \
14462                     (dst) = ((dst) &\
14463                     ~0x80000000U) | ((uint32_t)(1) << 31)
14464 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__RESERVED_31_31__CLR(dst) \
14465                     (dst) = ((dst) &\
14466                     ~0x80000000U) | ((uint32_t)(0) << 31)
14467 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__TYPE                          uint32_t
14468 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__READ                       0xffffffffU
14469 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7__WRITE                      0xffffffffU
14470 
14471 #endif /* __EMAC_REGS__TX_Q_SEG_ALLOC_Q0TO7_MACRO__ */
14472 
14473 
14474 /* macros for tx_q_seg_alloc_q0to7 */
14475 #define INST_TX_Q_SEG_ALLOC_Q0TO7__NUM                                        1
14476 
14477 /* macros for BlueprintGlobalNameSpace::emac_regs::tx_q_seg_alloc_q8to15 */
14478 #ifndef __EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15_MACRO__
14479 #define __EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15_MACRO__
14480 
14481 /* macros for field segment_alloc_q8 */
14482 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q8__SHIFT             0
14483 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q8__WIDTH             3
14484 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q8__MASK    0x00000007U
14485 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q8__RESET             0
14486 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q8__READ(src) \
14487                     ((uint32_t)(src)\
14488                     & 0x00000007U)
14489 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q8__WRITE(src) \
14490                     ((uint32_t)(src)\
14491                     & 0x00000007U)
14492 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q8__MODIFY(dst, src) \
14493                     (dst) = ((dst) &\
14494                     ~0x00000007U) | ((uint32_t)(src) &\
14495                     0x00000007U)
14496 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q8__VERIFY(src) \
14497                     (!(((uint32_t)(src)\
14498                     & ~0x00000007U)))
14499 
14500 /* macros for field reserved_3_3 */
14501 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_3_3__SHIFT                 3
14502 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_3_3__WIDTH                 1
14503 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_3_3__MASK        0x00000008U
14504 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_3_3__RESET                 0
14505 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_3_3__READ(src) \
14506                     (((uint32_t)(src)\
14507                     & 0x00000008U) >> 3)
14508 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_3_3__SET(dst) \
14509                     (dst) = ((dst) &\
14510                     ~0x00000008U) | ((uint32_t)(1) << 3)
14511 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_3_3__CLR(dst) \
14512                     (dst) = ((dst) &\
14513                     ~0x00000008U) | ((uint32_t)(0) << 3)
14514 
14515 /* macros for field segment_alloc_q9 */
14516 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q9__SHIFT             4
14517 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q9__WIDTH             3
14518 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q9__MASK    0x00000070U
14519 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q9__RESET             0
14520 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q9__READ(src) \
14521                     (((uint32_t)(src)\
14522                     & 0x00000070U) >> 4)
14523 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q9__WRITE(src) \
14524                     (((uint32_t)(src)\
14525                     << 4) & 0x00000070U)
14526 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q9__MODIFY(dst, src) \
14527                     (dst) = ((dst) &\
14528                     ~0x00000070U) | (((uint32_t)(src) <<\
14529                     4) & 0x00000070U)
14530 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q9__VERIFY(src) \
14531                     (!((((uint32_t)(src)\
14532                     << 4) & ~0x00000070U)))
14533 
14534 /* macros for field reserved_7_7 */
14535 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_7_7__SHIFT                 7
14536 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_7_7__WIDTH                 1
14537 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_7_7__MASK        0x00000080U
14538 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_7_7__RESET                 0
14539 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_7_7__READ(src) \
14540                     (((uint32_t)(src)\
14541                     & 0x00000080U) >> 7)
14542 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_7_7__SET(dst) \
14543                     (dst) = ((dst) &\
14544                     ~0x00000080U) | ((uint32_t)(1) << 7)
14545 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_7_7__CLR(dst) \
14546                     (dst) = ((dst) &\
14547                     ~0x00000080U) | ((uint32_t)(0) << 7)
14548 
14549 /* macros for field segment_alloc_q10 */
14550 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q10__SHIFT            8
14551 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q10__WIDTH            3
14552 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q10__MASK   0x00000700U
14553 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q10__RESET            0
14554 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q10__READ(src) \
14555                     (((uint32_t)(src)\
14556                     & 0x00000700U) >> 8)
14557 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q10__WRITE(src) \
14558                     (((uint32_t)(src)\
14559                     << 8) & 0x00000700U)
14560 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q10__MODIFY(dst, src) \
14561                     (dst) = ((dst) &\
14562                     ~0x00000700U) | (((uint32_t)(src) <<\
14563                     8) & 0x00000700U)
14564 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q10__VERIFY(src) \
14565                     (!((((uint32_t)(src)\
14566                     << 8) & ~0x00000700U)))
14567 
14568 /* macros for field reserved_11_11 */
14569 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_11_11__SHIFT              11
14570 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_11_11__WIDTH               1
14571 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_11_11__MASK      0x00000800U
14572 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_11_11__RESET               0
14573 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_11_11__READ(src) \
14574                     (((uint32_t)(src)\
14575                     & 0x00000800U) >> 11)
14576 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_11_11__SET(dst) \
14577                     (dst) = ((dst) &\
14578                     ~0x00000800U) | ((uint32_t)(1) << 11)
14579 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_11_11__CLR(dst) \
14580                     (dst) = ((dst) &\
14581                     ~0x00000800U) | ((uint32_t)(0) << 11)
14582 
14583 /* macros for field segment_alloc_q11 */
14584 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q11__SHIFT           12
14585 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q11__WIDTH            3
14586 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q11__MASK   0x00007000U
14587 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q11__RESET            0
14588 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q11__READ(src) \
14589                     (((uint32_t)(src)\
14590                     & 0x00007000U) >> 12)
14591 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q11__WRITE(src) \
14592                     (((uint32_t)(src)\
14593                     << 12) & 0x00007000U)
14594 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q11__MODIFY(dst, src) \
14595                     (dst) = ((dst) &\
14596                     ~0x00007000U) | (((uint32_t)(src) <<\
14597                     12) & 0x00007000U)
14598 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q11__VERIFY(src) \
14599                     (!((((uint32_t)(src)\
14600                     << 12) & ~0x00007000U)))
14601 
14602 /* macros for field reserved_15_15 */
14603 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_15_15__SHIFT              15
14604 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_15_15__WIDTH               1
14605 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_15_15__MASK      0x00008000U
14606 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_15_15__RESET               0
14607 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_15_15__READ(src) \
14608                     (((uint32_t)(src)\
14609                     & 0x00008000U) >> 15)
14610 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_15_15__SET(dst) \
14611                     (dst) = ((dst) &\
14612                     ~0x00008000U) | ((uint32_t)(1) << 15)
14613 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_15_15__CLR(dst) \
14614                     (dst) = ((dst) &\
14615                     ~0x00008000U) | ((uint32_t)(0) << 15)
14616 
14617 /* macros for field segment_alloc_q12 */
14618 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q12__SHIFT           16
14619 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q12__WIDTH            3
14620 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q12__MASK   0x00070000U
14621 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q12__RESET            0
14622 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q12__READ(src) \
14623                     (((uint32_t)(src)\
14624                     & 0x00070000U) >> 16)
14625 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q12__WRITE(src) \
14626                     (((uint32_t)(src)\
14627                     << 16) & 0x00070000U)
14628 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q12__MODIFY(dst, src) \
14629                     (dst) = ((dst) &\
14630                     ~0x00070000U) | (((uint32_t)(src) <<\
14631                     16) & 0x00070000U)
14632 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q12__VERIFY(src) \
14633                     (!((((uint32_t)(src)\
14634                     << 16) & ~0x00070000U)))
14635 
14636 /* macros for field reserved_19_19 */
14637 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_19_19__SHIFT              19
14638 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_19_19__WIDTH               1
14639 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_19_19__MASK      0x00080000U
14640 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_19_19__RESET               0
14641 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_19_19__READ(src) \
14642                     (((uint32_t)(src)\
14643                     & 0x00080000U) >> 19)
14644 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_19_19__SET(dst) \
14645                     (dst) = ((dst) &\
14646                     ~0x00080000U) | ((uint32_t)(1) << 19)
14647 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_19_19__CLR(dst) \
14648                     (dst) = ((dst) &\
14649                     ~0x00080000U) | ((uint32_t)(0) << 19)
14650 
14651 /* macros for field segment_alloc_q13 */
14652 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q13__SHIFT           20
14653 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q13__WIDTH            3
14654 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q13__MASK   0x00700000U
14655 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q13__RESET            0
14656 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q13__READ(src) \
14657                     (((uint32_t)(src)\
14658                     & 0x00700000U) >> 20)
14659 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q13__WRITE(src) \
14660                     (((uint32_t)(src)\
14661                     << 20) & 0x00700000U)
14662 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q13__MODIFY(dst, src) \
14663                     (dst) = ((dst) &\
14664                     ~0x00700000U) | (((uint32_t)(src) <<\
14665                     20) & 0x00700000U)
14666 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q13__VERIFY(src) \
14667                     (!((((uint32_t)(src)\
14668                     << 20) & ~0x00700000U)))
14669 
14670 /* macros for field reserved_23_23 */
14671 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_23_23__SHIFT              23
14672 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_23_23__WIDTH               1
14673 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_23_23__MASK      0x00800000U
14674 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_23_23__RESET               0
14675 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_23_23__READ(src) \
14676                     (((uint32_t)(src)\
14677                     & 0x00800000U) >> 23)
14678 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_23_23__SET(dst) \
14679                     (dst) = ((dst) &\
14680                     ~0x00800000U) | ((uint32_t)(1) << 23)
14681 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_23_23__CLR(dst) \
14682                     (dst) = ((dst) &\
14683                     ~0x00800000U) | ((uint32_t)(0) << 23)
14684 
14685 /* macros for field segment_alloc_q14 */
14686 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q14__SHIFT           24
14687 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q14__WIDTH            3
14688 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q14__MASK   0x07000000U
14689 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q14__RESET            0
14690 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q14__READ(src) \
14691                     (((uint32_t)(src)\
14692                     & 0x07000000U) >> 24)
14693 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q14__WRITE(src) \
14694                     (((uint32_t)(src)\
14695                     << 24) & 0x07000000U)
14696 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q14__MODIFY(dst, src) \
14697                     (dst) = ((dst) &\
14698                     ~0x07000000U) | (((uint32_t)(src) <<\
14699                     24) & 0x07000000U)
14700 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q14__VERIFY(src) \
14701                     (!((((uint32_t)(src)\
14702                     << 24) & ~0x07000000U)))
14703 
14704 /* macros for field reserved_27_27 */
14705 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_27_27__SHIFT              27
14706 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_27_27__WIDTH               1
14707 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_27_27__MASK      0x08000000U
14708 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_27_27__RESET               0
14709 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_27_27__READ(src) \
14710                     (((uint32_t)(src)\
14711                     & 0x08000000U) >> 27)
14712 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_27_27__SET(dst) \
14713                     (dst) = ((dst) &\
14714                     ~0x08000000U) | ((uint32_t)(1) << 27)
14715 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_27_27__CLR(dst) \
14716                     (dst) = ((dst) &\
14717                     ~0x08000000U) | ((uint32_t)(0) << 27)
14718 
14719 /* macros for field segment_alloc_q15 */
14720 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q15__SHIFT           28
14721 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q15__WIDTH            3
14722 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q15__MASK   0x70000000U
14723 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q15__RESET            0
14724 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q15__READ(src) \
14725                     (((uint32_t)(src)\
14726                     & 0x70000000U) >> 28)
14727 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q15__WRITE(src) \
14728                     (((uint32_t)(src)\
14729                     << 28) & 0x70000000U)
14730 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q15__MODIFY(dst, src) \
14731                     (dst) = ((dst) &\
14732                     ~0x70000000U) | (((uint32_t)(src) <<\
14733                     28) & 0x70000000U)
14734 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__SEGMENT_ALLOC_Q15__VERIFY(src) \
14735                     (!((((uint32_t)(src)\
14736                     << 28) & ~0x70000000U)))
14737 
14738 /* macros for field reserved_31_31 */
14739 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_31_31__SHIFT              31
14740 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_31_31__WIDTH               1
14741 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_31_31__MASK      0x80000000U
14742 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_31_31__RESET               0
14743 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_31_31__READ(src) \
14744                     (((uint32_t)(src)\
14745                     & 0x80000000U) >> 31)
14746 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_31_31__SET(dst) \
14747                     (dst) = ((dst) &\
14748                     ~0x80000000U) | ((uint32_t)(1) << 31)
14749 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__RESERVED_31_31__CLR(dst) \
14750                     (dst) = ((dst) &\
14751                     ~0x80000000U) | ((uint32_t)(0) << 31)
14752 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__TYPE                         uint32_t
14753 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__READ                      0xffffffffU
14754 #define EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15__WRITE                     0xffffffffU
14755 
14756 #endif /* __EMAC_REGS__TX_Q_SEG_ALLOC_Q8TO15_MACRO__ */
14757 
14758 
14759 /* macros for tx_q_seg_alloc_q8to15 */
14760 #define INST_TX_Q_SEG_ALLOC_Q8TO15__NUM                                       1
14761 
14762 /* macros for receive_q8_ptr */
14763 #define INST_RECEIVE_Q8_PTR__NUM                                              1
14764 
14765 /* macros for receive_q9_ptr */
14766 #define INST_RECEIVE_Q9_PTR__NUM                                              1
14767 
14768 /* macros for receive_q10_ptr */
14769 #define INST_RECEIVE_Q10_PTR__NUM                                             1
14770 
14771 /* macros for receive_q11_ptr */
14772 #define INST_RECEIVE_Q11_PTR__NUM                                             1
14773 
14774 /* macros for receive_q12_ptr */
14775 #define INST_RECEIVE_Q12_PTR__NUM                                             1
14776 
14777 /* macros for receive_q13_ptr */
14778 #define INST_RECEIVE_Q13_PTR__NUM                                             1
14779 
14780 /* macros for receive_q14_ptr */
14781 #define INST_RECEIVE_Q14_PTR__NUM                                             1
14782 
14783 /* macros for receive_q15_ptr */
14784 #define INST_RECEIVE_Q15_PTR__NUM                                             1
14785 
14786 /* macros for dma_rxbuf_size_q8 */
14787 #define INST_DMA_RXBUF_SIZE_Q8__NUM                                           1
14788 
14789 /* macros for dma_rxbuf_size_q9 */
14790 #define INST_DMA_RXBUF_SIZE_Q9__NUM                                           1
14791 
14792 /* macros for dma_rxbuf_size_q10 */
14793 #define INST_DMA_RXBUF_SIZE_Q10__NUM                                          1
14794 
14795 /* macros for dma_rxbuf_size_q11 */
14796 #define INST_DMA_RXBUF_SIZE_Q11__NUM                                          1
14797 
14798 /* macros for dma_rxbuf_size_q12 */
14799 #define INST_DMA_RXBUF_SIZE_Q12__NUM                                          1
14800 
14801 /* macros for dma_rxbuf_size_q13 */
14802 #define INST_DMA_RXBUF_SIZE_Q13__NUM                                          1
14803 
14804 /* macros for dma_rxbuf_size_q14 */
14805 #define INST_DMA_RXBUF_SIZE_Q14__NUM                                          1
14806 
14807 /* macros for dma_rxbuf_size_q15 */
14808 #define INST_DMA_RXBUF_SIZE_Q15__NUM                                          1
14809 
14810 /* macros for BlueprintGlobalNameSpace::emac_regs::int_q_enable */
14811 #ifndef __EMAC_REGS__INT_Q_ENABLE_MACRO__
14812 #define __EMAC_REGS__INT_Q_ENABLE_MACRO__
14813 
14814 /* macros for field reserved_0 */
14815 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__SHIFT                            0
14816 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__WIDTH                            1
14817 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__MASK                   0x00000001U
14818 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__RESET                            0
14819 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__READ(src) \
14820                     ((uint32_t)(src)\
14821                     & 0x00000001U)
14822 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__SET(dst) \
14823                     (dst) = ((dst) &\
14824                     ~0x00000001U) | (uint32_t)(1)
14825 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_0__CLR(dst) \
14826                     (dst) = ((dst) &\
14827                     ~0x00000001U) | (uint32_t)(0)
14828 
14829 /* macros for field enable_receive_complete_interrupt */
14830 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__SHIFT     1
14831 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__WIDTH     1
14832 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__MASK \
14833                     0x00000002U
14834 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__RESET     0
14835 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__WRITE(src) \
14836                     (((uint32_t)(src)\
14837                     << 1) & 0x00000002U)
14838 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__MODIFY(dst, src) \
14839                     (dst) = ((dst) &\
14840                     ~0x00000002U) | (((uint32_t)(src) <<\
14841                     1) & 0x00000002U)
14842 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__VERIFY(src) \
14843                     (!((((uint32_t)(src)\
14844                     << 1) & ~0x00000002U)))
14845 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__SET(dst) \
14846                     (dst) = ((dst) &\
14847                     ~0x00000002U) | ((uint32_t)(1) << 1)
14848 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RECEIVE_COMPLETE_INTERRUPT__CLR(dst) \
14849                     (dst) = ((dst) &\
14850                     ~0x00000002U) | ((uint32_t)(0) << 1)
14851 
14852 /* macros for field enable_rx_used_bit_read_interrupt */
14853 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__SHIFT     2
14854 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__WIDTH     1
14855 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__MASK \
14856                     0x00000004U
14857 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__RESET     0
14858 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__WRITE(src) \
14859                     (((uint32_t)(src)\
14860                     << 2) & 0x00000004U)
14861 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \
14862                     (dst) = ((dst) &\
14863                     ~0x00000004U) | (((uint32_t)(src) <<\
14864                     2) & 0x00000004U)
14865 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__VERIFY(src) \
14866                     (!((((uint32_t)(src)\
14867                     << 2) & ~0x00000004U)))
14868 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__SET(dst) \
14869                     (dst) = ((dst) &\
14870                     ~0x00000004U) | ((uint32_t)(1) << 2)
14871 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RX_USED_BIT_READ_INTERRUPT__CLR(dst) \
14872                     (dst) = ((dst) &\
14873                     ~0x00000004U) | ((uint32_t)(0) << 2)
14874 
14875 /* macros for field reserved_4_3 */
14876 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_4_3__SHIFT                          3
14877 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_4_3__WIDTH                          2
14878 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_4_3__MASK                 0x00000018U
14879 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_4_3__RESET                          0
14880 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_4_3__READ(src) \
14881                     (((uint32_t)(src)\
14882                     & 0x00000018U) >> 3)
14883 
14884 /* macros for field enable_retry_limit_exceeded_or_late_collision_interrupt */
14885 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SHIFT \
14886                     5
14887 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WIDTH \
14888                     1
14889 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MASK \
14890                     0x00000020U
14891 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__RESET \
14892                     0
14893 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WRITE(src) \
14894                     (((uint32_t)(src)\
14895                     << 5) & 0x00000020U)
14896 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MODIFY(dst, src) \
14897                     (dst) = ((dst) &\
14898                     ~0x00000020U) | (((uint32_t)(src) <<\
14899                     5) & 0x00000020U)
14900 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__VERIFY(src) \
14901                     (!((((uint32_t)(src)\
14902                     << 5) & ~0x00000020U)))
14903 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SET(dst) \
14904                     (dst) = ((dst) &\
14905                     ~0x00000020U) | ((uint32_t)(1) << 5)
14906 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__CLR(dst) \
14907                     (dst) = ((dst) &\
14908                     ~0x00000020U) | ((uint32_t)(0) << 5)
14909 
14910 /* macros for field enable_transmit_frame_corruption_due_to_amba_error_interrupt */
14911 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SHIFT \
14912                     6
14913 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WIDTH \
14914                     1
14915 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MASK \
14916                     0x00000040U
14917 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__RESET \
14918                     0
14919 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WRITE(src) \
14920                     (((uint32_t)(src)\
14921                     << 6) & 0x00000040U)
14922 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MODIFY(dst, src) \
14923                     (dst) = ((dst) &\
14924                     ~0x00000040U) | (((uint32_t)(src) <<\
14925                     6) & 0x00000040U)
14926 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__VERIFY(src) \
14927                     (!((((uint32_t)(src)\
14928                     << 6) & ~0x00000040U)))
14929 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SET(dst) \
14930                     (dst) = ((dst) &\
14931                     ~0x00000040U) | ((uint32_t)(1) << 6)
14932 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__CLR(dst) \
14933                     (dst) = ((dst) &\
14934                     ~0x00000040U) | ((uint32_t)(0) << 6)
14935 
14936 /* macros for field enable_transmit_complete_interrupt */
14937 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__SHIFT    7
14938 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__WIDTH    1
14939 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__MASK \
14940                     0x00000080U
14941 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__RESET    0
14942 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__WRITE(src) \
14943                     (((uint32_t)(src)\
14944                     << 7) & 0x00000080U)
14945 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__MODIFY(dst, src) \
14946                     (dst) = ((dst) &\
14947                     ~0x00000080U) | (((uint32_t)(src) <<\
14948                     7) & 0x00000080U)
14949 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__VERIFY(src) \
14950                     (!((((uint32_t)(src)\
14951                     << 7) & ~0x00000080U)))
14952 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__SET(dst) \
14953                     (dst) = ((dst) &\
14954                     ~0x00000080U) | ((uint32_t)(1) << 7)
14955 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_TRANSMIT_COMPLETE_INTERRUPT__CLR(dst) \
14956                     (dst) = ((dst) &\
14957                     ~0x00000080U) | ((uint32_t)(0) << 7)
14958 
14959 /* macros for field reserved_10_8 */
14960 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_10_8__SHIFT                         8
14961 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_10_8__WIDTH                         3
14962 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_10_8__MASK                0x00000700U
14963 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_10_8__RESET                         0
14964 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_10_8__READ(src) \
14965                     (((uint32_t)(src)\
14966                     & 0x00000700U) >> 8)
14967 
14968 /* macros for field enable_resp_not_ok_interrupt */
14969 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__SHIFT         11
14970 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__WIDTH          1
14971 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__MASK 0x00000800U
14972 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__RESET          0
14973 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__WRITE(src) \
14974                     (((uint32_t)(src)\
14975                     << 11) & 0x00000800U)
14976 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__MODIFY(dst, src) \
14977                     (dst) = ((dst) &\
14978                     ~0x00000800U) | (((uint32_t)(src) <<\
14979                     11) & 0x00000800U)
14980 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__VERIFY(src) \
14981                     (!((((uint32_t)(src)\
14982                     << 11) & ~0x00000800U)))
14983 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__SET(dst) \
14984                     (dst) = ((dst) &\
14985                     ~0x00000800U) | ((uint32_t)(1) << 11)
14986 #define EMAC_REGS__INT_Q_ENABLE__ENABLE_RESP_NOT_OK_INTERRUPT__CLR(dst) \
14987                     (dst) = ((dst) &\
14988                     ~0x00000800U) | ((uint32_t)(0) << 11)
14989 
14990 /* macros for field reserved_31_12 */
14991 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_31_12__SHIFT                       12
14992 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_31_12__WIDTH                       20
14993 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_31_12__MASK               0xfffff000U
14994 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_31_12__RESET                        0
14995 #define EMAC_REGS__INT_Q_ENABLE__RESERVED_31_12__READ(src) \
14996                     (((uint32_t)(src)\
14997                     & 0xfffff000U) >> 12)
14998 #define EMAC_REGS__INT_Q_ENABLE__TYPE                                  uint32_t
14999 #define EMAC_REGS__INT_Q_ENABLE__READ                               0xfffff719U
15000 #define EMAC_REGS__INT_Q_ENABLE__WRITE                              0xfffff719U
15001 
15002 #endif /* __EMAC_REGS__INT_Q_ENABLE_MACRO__ */
15003 
15004 
15005 /* macros for int_q1_enable */
15006 #define INST_INT_Q1_ENABLE__NUM                                               1
15007 
15008 /* macros for int_q2_enable */
15009 #define INST_INT_Q2_ENABLE__NUM                                               1
15010 
15011 /* macros for int_q3_enable */
15012 #define INST_INT_Q3_ENABLE__NUM                                               1
15013 
15014 /* macros for int_q4_enable */
15015 #define INST_INT_Q4_ENABLE__NUM                                               1
15016 
15017 /* macros for int_q5_enable */
15018 #define INST_INT_Q5_ENABLE__NUM                                               1
15019 
15020 /* macros for int_q6_enable */
15021 #define INST_INT_Q6_ENABLE__NUM                                               1
15022 
15023 /* macros for int_q7_enable */
15024 #define INST_INT_Q7_ENABLE__NUM                                               1
15025 
15026 /* macros for BlueprintGlobalNameSpace::emac_regs::int_q_disable */
15027 #ifndef __EMAC_REGS__INT_Q_DISABLE_MACRO__
15028 #define __EMAC_REGS__INT_Q_DISABLE_MACRO__
15029 
15030 /* macros for field reserved_0 */
15031 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__SHIFT                           0
15032 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__WIDTH                           1
15033 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__MASK                  0x00000001U
15034 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__RESET                           0
15035 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__READ(src) \
15036                     ((uint32_t)(src)\
15037                     & 0x00000001U)
15038 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__SET(dst) \
15039                     (dst) = ((dst) &\
15040                     ~0x00000001U) | (uint32_t)(1)
15041 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_0__CLR(dst) \
15042                     (dst) = ((dst) &\
15043                     ~0x00000001U) | (uint32_t)(0)
15044 
15045 /* macros for field disable_receive_complete_interrupt */
15046 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__SHIFT   1
15047 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__WIDTH   1
15048 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__MASK \
15049                     0x00000002U
15050 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__RESET   0
15051 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__WRITE(src) \
15052                     (((uint32_t)(src)\
15053                     << 1) & 0x00000002U)
15054 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__MODIFY(dst, src) \
15055                     (dst) = ((dst) &\
15056                     ~0x00000002U) | (((uint32_t)(src) <<\
15057                     1) & 0x00000002U)
15058 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__VERIFY(src) \
15059                     (!((((uint32_t)(src)\
15060                     << 1) & ~0x00000002U)))
15061 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__SET(dst) \
15062                     (dst) = ((dst) &\
15063                     ~0x00000002U) | ((uint32_t)(1) << 1)
15064 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RECEIVE_COMPLETE_INTERRUPT__CLR(dst) \
15065                     (dst) = ((dst) &\
15066                     ~0x00000002U) | ((uint32_t)(0) << 1)
15067 
15068 /* macros for field disable_rx_used_bit_read_interrupt */
15069 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__SHIFT   2
15070 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__WIDTH   1
15071 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__MASK \
15072                     0x00000004U
15073 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__RESET   0
15074 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__WRITE(src) \
15075                     (((uint32_t)(src)\
15076                     << 2) & 0x00000004U)
15077 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__MODIFY(dst, src) \
15078                     (dst) = ((dst) &\
15079                     ~0x00000004U) | (((uint32_t)(src) <<\
15080                     2) & 0x00000004U)
15081 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__VERIFY(src) \
15082                     (!((((uint32_t)(src)\
15083                     << 2) & ~0x00000004U)))
15084 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__SET(dst) \
15085                     (dst) = ((dst) &\
15086                     ~0x00000004U) | ((uint32_t)(1) << 2)
15087 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RX_USED_BIT_READ_INTERRUPT__CLR(dst) \
15088                     (dst) = ((dst) &\
15089                     ~0x00000004U) | ((uint32_t)(0) << 2)
15090 
15091 /* macros for field reserved_4_3 */
15092 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_4_3__SHIFT                         3
15093 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_4_3__WIDTH                         2
15094 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_4_3__MASK                0x00000018U
15095 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_4_3__RESET                         0
15096 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_4_3__READ(src) \
15097                     (((uint32_t)(src)\
15098                     & 0x00000018U) >> 3)
15099 
15100 /* macros for field disable_retry_limit_exceeded_or_late_collision_interrupt */
15101 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SHIFT \
15102                     5
15103 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WIDTH \
15104                     1
15105 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MASK \
15106                     0x00000020U
15107 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__RESET \
15108                     0
15109 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__WRITE(src) \
15110                     (((uint32_t)(src)\
15111                     << 5) & 0x00000020U)
15112 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__MODIFY(dst, src) \
15113                     (dst) = ((dst) &\
15114                     ~0x00000020U) | (((uint32_t)(src) <<\
15115                     5) & 0x00000020U)
15116 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__VERIFY(src) \
15117                     (!((((uint32_t)(src)\
15118                     << 5) & ~0x00000020U)))
15119 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__SET(dst) \
15120                     (dst) = ((dst) &\
15121                     ~0x00000020U) | ((uint32_t)(1) << 5)
15122 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT__CLR(dst) \
15123                     (dst) = ((dst) &\
15124                     ~0x00000020U) | ((uint32_t)(0) << 5)
15125 
15126 /* macros for field disable_transmit_frame_corruption_due_to_amba_error_interrupt */
15127 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SHIFT \
15128                     6
15129 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WIDTH \
15130                     1
15131 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MASK \
15132                     0x00000040U
15133 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__RESET \
15134                     0
15135 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__WRITE(src) \
15136                     (((uint32_t)(src)\
15137                     << 6) & 0x00000040U)
15138 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__MODIFY(dst, src) \
15139                     (dst) = ((dst) &\
15140                     ~0x00000040U) | (((uint32_t)(src) <<\
15141                     6) & 0x00000040U)
15142 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__VERIFY(src) \
15143                     (!((((uint32_t)(src)\
15144                     << 6) & ~0x00000040U)))
15145 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__SET(dst) \
15146                     (dst) = ((dst) &\
15147                     ~0x00000040U) | ((uint32_t)(1) << 6)
15148 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT__CLR(dst) \
15149                     (dst) = ((dst) &\
15150                     ~0x00000040U) | ((uint32_t)(0) << 6)
15151 
15152 /* macros for field disable_transmit_complete_interrupt */
15153 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__SHIFT  7
15154 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__WIDTH  1
15155 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__MASK \
15156                     0x00000080U
15157 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__RESET  0
15158 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__WRITE(src) \
15159                     (((uint32_t)(src)\
15160                     << 7) & 0x00000080U)
15161 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__MODIFY(dst, src) \
15162                     (dst) = ((dst) &\
15163                     ~0x00000080U) | (((uint32_t)(src) <<\
15164                     7) & 0x00000080U)
15165 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__VERIFY(src) \
15166                     (!((((uint32_t)(src)\
15167                     << 7) & ~0x00000080U)))
15168 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__SET(dst) \
15169                     (dst) = ((dst) &\
15170                     ~0x00000080U) | ((uint32_t)(1) << 7)
15171 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_TRANSMIT_COMPLETE_INTERRUPT__CLR(dst) \
15172                     (dst) = ((dst) &\
15173                     ~0x00000080U) | ((uint32_t)(0) << 7)
15174 
15175 /* macros for field reserved_10_8 */
15176 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_10_8__SHIFT                        8
15177 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_10_8__WIDTH                        3
15178 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_10_8__MASK               0x00000700U
15179 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_10_8__RESET                        0
15180 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_10_8__READ(src) \
15181                     (((uint32_t)(src)\
15182                     & 0x00000700U) >> 8)
15183 
15184 /* macros for field disable_resp_not_ok_interrupt */
15185 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__SHIFT       11
15186 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__WIDTH        1
15187 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__MASK \
15188                     0x00000800U
15189 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__RESET        0
15190 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__WRITE(src) \
15191                     (((uint32_t)(src)\
15192                     << 11) & 0x00000800U)
15193 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__MODIFY(dst, src) \
15194                     (dst) = ((dst) &\
15195                     ~0x00000800U) | (((uint32_t)(src) <<\
15196                     11) & 0x00000800U)
15197 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__VERIFY(src) \
15198                     (!((((uint32_t)(src)\
15199                     << 11) & ~0x00000800U)))
15200 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__SET(dst) \
15201                     (dst) = ((dst) &\
15202                     ~0x00000800U) | ((uint32_t)(1) << 11)
15203 #define EMAC_REGS__INT_Q_DISABLE__DISABLE_RESP_NOT_OK_INTERRUPT__CLR(dst) \
15204                     (dst) = ((dst) &\
15205                     ~0x00000800U) | ((uint32_t)(0) << 11)
15206 
15207 /* macros for field reserved_31_12 */
15208 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_31_12__SHIFT                      12
15209 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_31_12__WIDTH                      20
15210 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_31_12__MASK              0xfffff000U
15211 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_31_12__RESET                       0
15212 #define EMAC_REGS__INT_Q_DISABLE__RESERVED_31_12__READ(src) \
15213                     (((uint32_t)(src)\
15214                     & 0xfffff000U) >> 12)
15215 #define EMAC_REGS__INT_Q_DISABLE__TYPE                                 uint32_t
15216 #define EMAC_REGS__INT_Q_DISABLE__READ                              0xfffff719U
15217 #define EMAC_REGS__INT_Q_DISABLE__WRITE                             0xfffff719U
15218 
15219 #endif /* __EMAC_REGS__INT_Q_DISABLE_MACRO__ */
15220 
15221 
15222 /* macros for int_q1_disable */
15223 #define INST_INT_Q1_DISABLE__NUM                                              1
15224 
15225 /* macros for int_q2_disable */
15226 #define INST_INT_Q2_DISABLE__NUM                                              1
15227 
15228 /* macros for int_q3_disable */
15229 #define INST_INT_Q3_DISABLE__NUM                                              1
15230 
15231 /* macros for int_q4_disable */
15232 #define INST_INT_Q4_DISABLE__NUM                                              1
15233 
15234 /* macros for int_q5_disable */
15235 #define INST_INT_Q5_DISABLE__NUM                                              1
15236 
15237 /* macros for int_q6_disable */
15238 #define INST_INT_Q6_DISABLE__NUM                                              1
15239 
15240 /* macros for int_q7_disable */
15241 #define INST_INT_Q7_DISABLE__NUM                                              1
15242 
15243 /* macros for BlueprintGlobalNameSpace::emac_regs::int_q_mask */
15244 #ifndef __EMAC_REGS__INT_Q_MASK_MACRO__
15245 #define __EMAC_REGS__INT_Q_MASK_MACRO__
15246 
15247 /* macros for field reserved_0 */
15248 #define EMAC_REGS__INT_Q_MASK__RESERVED_0__SHIFT                              0
15249 #define EMAC_REGS__INT_Q_MASK__RESERVED_0__WIDTH                              1
15250 #define EMAC_REGS__INT_Q_MASK__RESERVED_0__MASK                     0x00000001U
15251 #define EMAC_REGS__INT_Q_MASK__RESERVED_0__RESET                              0
15252 #define EMAC_REGS__INT_Q_MASK__RESERVED_0__READ(src) \
15253                     ((uint32_t)(src)\
15254                     & 0x00000001U)
15255 #define EMAC_REGS__INT_Q_MASK__RESERVED_0__SET(dst) \
15256                     (dst) = ((dst) &\
15257                     ~0x00000001U) | (uint32_t)(1)
15258 #define EMAC_REGS__INT_Q_MASK__RESERVED_0__CLR(dst) \
15259                     (dst) = ((dst) &\
15260                     ~0x00000001U) | (uint32_t)(0)
15261 
15262 /* macros for field receive_complete_interrupt_mask */
15263 #define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__SHIFT         1
15264 #define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__WIDTH         1
15265 #define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__MASK \
15266                     0x00000002U
15267 #define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__RESET         1
15268 #define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__READ(src) \
15269                     (((uint32_t)(src)\
15270                     & 0x00000002U) >> 1)
15271 #define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__SET(dst) \
15272                     (dst) = ((dst) &\
15273                     ~0x00000002U) | ((uint32_t)(1) << 1)
15274 #define EMAC_REGS__INT_Q_MASK__RECEIVE_COMPLETE_INTERRUPT_MASK__CLR(dst) \
15275                     (dst) = ((dst) &\
15276                     ~0x00000002U) | ((uint32_t)(0) << 1)
15277 
15278 /* macros for field rx_used_interrupt_mask */
15279 #define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__SHIFT                  2
15280 #define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__WIDTH                  1
15281 #define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__MASK         0x00000004U
15282 #define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__RESET                  1
15283 #define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__READ(src) \
15284                     (((uint32_t)(src)\
15285                     & 0x00000004U) >> 2)
15286 #define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__SET(dst) \
15287                     (dst) = ((dst) &\
15288                     ~0x00000004U) | ((uint32_t)(1) << 2)
15289 #define EMAC_REGS__INT_Q_MASK__RX_USED_INTERRUPT_MASK__CLR(dst) \
15290                     (dst) = ((dst) &\
15291                     ~0x00000004U) | ((uint32_t)(0) << 2)
15292 
15293 /* macros for field reserved_4_3 */
15294 #define EMAC_REGS__INT_Q_MASK__RESERVED_4_3__SHIFT                            3
15295 #define EMAC_REGS__INT_Q_MASK__RESERVED_4_3__WIDTH                            2
15296 #define EMAC_REGS__INT_Q_MASK__RESERVED_4_3__MASK                   0x00000018U
15297 #define EMAC_REGS__INT_Q_MASK__RESERVED_4_3__RESET                            0
15298 #define EMAC_REGS__INT_Q_MASK__RESERVED_4_3__READ(src) \
15299                     (((uint32_t)(src)\
15300                     & 0x00000018U) >> 3)
15301 
15302 /* macros for field retry_limit_exceeded_or_late_collision_interrupt_mask */
15303 #define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__SHIFT \
15304                     5
15305 #define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__WIDTH \
15306                     1
15307 #define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__MASK \
15308                     0x00000020U
15309 #define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__RESET \
15310                     1
15311 #define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__READ(src) \
15312                     (((uint32_t)(src)\
15313                     & 0x00000020U) >> 5)
15314 #define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__SET(dst) \
15315                     (dst) = ((dst) &\
15316                     ~0x00000020U) | ((uint32_t)(1) << 5)
15317 #define EMAC_REGS__INT_Q_MASK__RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK__CLR(dst) \
15318                     (dst) = ((dst) &\
15319                     ~0x00000020U) | ((uint32_t)(0) << 5)
15320 
15321 /* macros for field amba_error_interrupt_mask */
15322 #define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__SHIFT               6
15323 #define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__WIDTH               1
15324 #define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__MASK      0x00000040U
15325 #define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__RESET               1
15326 #define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__READ(src) \
15327                     (((uint32_t)(src)\
15328                     & 0x00000040U) >> 6)
15329 #define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__SET(dst) \
15330                     (dst) = ((dst) &\
15331                     ~0x00000040U) | ((uint32_t)(1) << 6)
15332 #define EMAC_REGS__INT_Q_MASK__AMBA_ERROR_INTERRUPT_MASK__CLR(dst) \
15333                     (dst) = ((dst) &\
15334                     ~0x00000040U) | ((uint32_t)(0) << 6)
15335 
15336 /* macros for field transmit_complete_interrupt_mask */
15337 #define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__SHIFT        7
15338 #define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__WIDTH        1
15339 #define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__MASK \
15340                     0x00000080U
15341 #define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__RESET        1
15342 #define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__READ(src) \
15343                     (((uint32_t)(src)\
15344                     & 0x00000080U) >> 7)
15345 #define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__SET(dst) \
15346                     (dst) = ((dst) &\
15347                     ~0x00000080U) | ((uint32_t)(1) << 7)
15348 #define EMAC_REGS__INT_Q_MASK__TRANSMIT_COMPLETE_INTERRUPT_MASK__CLR(dst) \
15349                     (dst) = ((dst) &\
15350                     ~0x00000080U) | ((uint32_t)(0) << 7)
15351 
15352 /* macros for field reserved_10_8 */
15353 #define EMAC_REGS__INT_Q_MASK__RESERVED_10_8__SHIFT                           8
15354 #define EMAC_REGS__INT_Q_MASK__RESERVED_10_8__WIDTH                           3
15355 #define EMAC_REGS__INT_Q_MASK__RESERVED_10_8__MASK                  0x00000700U
15356 #define EMAC_REGS__INT_Q_MASK__RESERVED_10_8__RESET                           0
15357 #define EMAC_REGS__INT_Q_MASK__RESERVED_10_8__READ(src) \
15358                     (((uint32_t)(src)\
15359                     & 0x00000700U) >> 8)
15360 
15361 /* macros for field resp_not_ok_interrupt_mask */
15362 #define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__SHIFT             11
15363 #define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__WIDTH              1
15364 #define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__MASK     0x00000800U
15365 #define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__RESET              1
15366 #define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__READ(src) \
15367                     (((uint32_t)(src)\
15368                     & 0x00000800U) >> 11)
15369 #define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__SET(dst) \
15370                     (dst) = ((dst) &\
15371                     ~0x00000800U) | ((uint32_t)(1) << 11)
15372 #define EMAC_REGS__INT_Q_MASK__RESP_NOT_OK_INTERRUPT_MASK__CLR(dst) \
15373                     (dst) = ((dst) &\
15374                     ~0x00000800U) | ((uint32_t)(0) << 11)
15375 
15376 /* macros for field reserved_31_12 */
15377 #define EMAC_REGS__INT_Q_MASK__RESERVED_31_12__SHIFT                         12
15378 #define EMAC_REGS__INT_Q_MASK__RESERVED_31_12__WIDTH                         20
15379 #define EMAC_REGS__INT_Q_MASK__RESERVED_31_12__MASK                 0xfffff000U
15380 #define EMAC_REGS__INT_Q_MASK__RESERVED_31_12__RESET                          0
15381 #define EMAC_REGS__INT_Q_MASK__RESERVED_31_12__READ(src) \
15382                     (((uint32_t)(src)\
15383                     & 0xfffff000U) >> 12)
15384 #define EMAC_REGS__INT_Q_MASK__TYPE                                    uint32_t
15385 #define EMAC_REGS__INT_Q_MASK__READ                                 0xffffffffU
15386 
15387 #endif /* __EMAC_REGS__INT_Q_MASK_MACRO__ */
15388 
15389 
15390 /* macros for int_q1_mask */
15391 #define INST_INT_Q1_MASK__NUM                                                 1
15392 
15393 /* macros for int_q2_mask */
15394 #define INST_INT_Q2_MASK__NUM                                                 1
15395 
15396 /* macros for int_q3_mask */
15397 #define INST_INT_Q3_MASK__NUM                                                 1
15398 
15399 /* macros for int_q4_mask */
15400 #define INST_INT_Q4_MASK__NUM                                                 1
15401 
15402 /* macros for int_q5_mask */
15403 #define INST_INT_Q5_MASK__NUM                                                 1
15404 
15405 /* macros for int_q6_mask */
15406 #define INST_INT_Q6_MASK__NUM                                                 1
15407 
15408 /* macros for int_q7_mask */
15409 #define INST_INT_Q7_MASK__NUM                                                 1
15410 
15411 /* macros for int_q8_enable */
15412 #define INST_INT_Q8_ENABLE__NUM                                               1
15413 
15414 /* macros for int_q9_enable */
15415 #define INST_INT_Q9_ENABLE__NUM                                               1
15416 
15417 /* macros for int_q10_enable */
15418 #define INST_INT_Q10_ENABLE__NUM                                              1
15419 
15420 /* macros for int_q11_enable */
15421 #define INST_INT_Q11_ENABLE__NUM                                              1
15422 
15423 /* macros for int_q12_enable */
15424 #define INST_INT_Q12_ENABLE__NUM                                              1
15425 
15426 /* macros for int_q13_enable */
15427 #define INST_INT_Q13_ENABLE__NUM                                              1
15428 
15429 /* macros for int_q14_enable */
15430 #define INST_INT_Q14_ENABLE__NUM                                              1
15431 
15432 /* macros for int_q15_enable */
15433 #define INST_INT_Q15_ENABLE__NUM                                              1
15434 
15435 /* macros for int_q8_disable */
15436 #define INST_INT_Q8_DISABLE__NUM                                              1
15437 
15438 /* macros for int_q9_disable */
15439 #define INST_INT_Q9_DISABLE__NUM                                              1
15440 
15441 /* macros for int_q10_disable */
15442 #define INST_INT_Q10_DISABLE__NUM                                             1
15443 
15444 /* macros for int_q11_disable */
15445 #define INST_INT_Q11_DISABLE__NUM                                             1
15446 
15447 /* macros for int_q12_disable */
15448 #define INST_INT_Q12_DISABLE__NUM                                             1
15449 
15450 /* macros for int_q13_disable */
15451 #define INST_INT_Q13_DISABLE__NUM                                             1
15452 
15453 /* macros for int_q14_disable */
15454 #define INST_INT_Q14_DISABLE__NUM                                             1
15455 
15456 /* macros for int_q15_disable */
15457 #define INST_INT_Q15_DISABLE__NUM                                             1
15458 
15459 /* macros for int_q8_mask */
15460 #define INST_INT_Q8_MASK__NUM                                                 1
15461 
15462 /* macros for int_q9_mask */
15463 #define INST_INT_Q9_MASK__NUM                                                 1
15464 
15465 /* macros for int_q10_mask */
15466 #define INST_INT_Q10_MASK__NUM                                                1
15467 
15468 /* macros for int_q11_mask */
15469 #define INST_INT_Q11_MASK__NUM                                                1
15470 
15471 /* macros for int_q12_mask */
15472 #define INST_INT_Q12_MASK__NUM                                                1
15473 
15474 /* macros for int_q13_mask */
15475 #define INST_INT_Q13_MASK__NUM                                                1
15476 
15477 /* macros for int_q14_mask */
15478 #define INST_INT_Q14_MASK__NUM                                                1
15479 
15480 /* macros for int_q15_mask */
15481 #define INST_INT_Q15_MASK__NUM                                                1
15482 
15483 /* macros for BlueprintGlobalNameSpace::emac_regs::screening_type_2_ethertype_reg */
15484 #ifndef __EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG_MACRO__
15485 #define __EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG_MACRO__
15486 
15487 /* macros for field compare_value */
15488 #define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__SHIFT       0
15489 #define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__WIDTH      16
15490 #define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__MASK \
15491                     0x0000ffffU
15492 #define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__RESET       0
15493 #define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__READ(src) \
15494                     ((uint32_t)(src)\
15495                     & 0x0000ffffU)
15496 #define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__WRITE(src) \
15497                     ((uint32_t)(src)\
15498                     & 0x0000ffffU)
15499 #define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__MODIFY(dst, src) \
15500                     (dst) = ((dst) &\
15501                     ~0x0000ffffU) | ((uint32_t)(src) &\
15502                     0x0000ffffU)
15503 #define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__COMPARE_VALUE__VERIFY(src) \
15504                     (!(((uint32_t)(src)\
15505                     & ~0x0000ffffU)))
15506 
15507 /* macros for field reserved_31_16 */
15508 #define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__RESERVED_31_16__SHIFT     16
15509 #define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__RESERVED_31_16__WIDTH     16
15510 #define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__RESERVED_31_16__MASK \
15511                     0xffff0000U
15512 #define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__RESERVED_31_16__RESET      0
15513 #define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__RESERVED_31_16__READ(src) \
15514                     (((uint32_t)(src)\
15515                     & 0xffff0000U) >> 16)
15516 #define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__TYPE                uint32_t
15517 #define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__READ             0xffffffffU
15518 #define EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG__WRITE            0xffffffffU
15519 
15520 #endif /* __EMAC_REGS__SCREENING_TYPE_2_ETHERTYPE_REG_MACRO__ */
15521 
15522 
15523 /* macros for screening_type_2_ethertype_reg_0 */
15524 #define INST_SCREENING_TYPE_2_ETHERTYPE_REG_0__NUM                            1
15525 
15526 /* macros for screening_type_2_ethertype_reg_1 */
15527 #define INST_SCREENING_TYPE_2_ETHERTYPE_REG_1__NUM                            1
15528 
15529 /* macros for screening_type_2_ethertype_reg_2 */
15530 #define INST_SCREENING_TYPE_2_ETHERTYPE_REG_2__NUM                            1
15531 
15532 /* macros for screening_type_2_ethertype_reg_3 */
15533 #define INST_SCREENING_TYPE_2_ETHERTYPE_REG_3__NUM                            1
15534 
15535 /* macros for screening_type_2_ethertype_reg_4 */
15536 #define INST_SCREENING_TYPE_2_ETHERTYPE_REG_4__NUM                            1
15537 
15538 /* macros for screening_type_2_ethertype_reg_5 */
15539 #define INST_SCREENING_TYPE_2_ETHERTYPE_REG_5__NUM                            1
15540 
15541 /* macros for screening_type_2_ethertype_reg_6 */
15542 #define INST_SCREENING_TYPE_2_ETHERTYPE_REG_6__NUM                            1
15543 
15544 /* macros for screening_type_2_ethertype_reg_7 */
15545 #define INST_SCREENING_TYPE_2_ETHERTYPE_REG_7__NUM                            1
15546 
15547 /* macros for BlueprintGlobalNameSpace::emac_regs::type2_compare_word_0 */
15548 #ifndef __EMAC_REGS__TYPE2_COMPARE_WORD_0_MACRO__
15549 #define __EMAC_REGS__TYPE2_COMPARE_WORD_0_MACRO__
15550 
15551 /* macros for field mask_value */
15552 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__SHIFT                    0
15553 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__WIDTH                   16
15554 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__MASK           0x0000ffffU
15555 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__RESET                    0
15556 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__READ(src) \
15557                     ((uint32_t)(src)\
15558                     & 0x0000ffffU)
15559 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__WRITE(src) \
15560                     ((uint32_t)(src)\
15561                     & 0x0000ffffU)
15562 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__MODIFY(dst, src) \
15563                     (dst) = ((dst) &\
15564                     ~0x0000ffffU) | ((uint32_t)(src) &\
15565                     0x0000ffffU)
15566 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__MASK_VALUE__VERIFY(src) \
15567                     (!(((uint32_t)(src)\
15568                     & ~0x0000ffffU)))
15569 
15570 /* macros for field compare_value */
15571 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__SHIFT                16
15572 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__WIDTH                16
15573 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__MASK        0xffff0000U
15574 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__RESET                 0
15575 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__READ(src) \
15576                     (((uint32_t)(src)\
15577                     & 0xffff0000U) >> 16)
15578 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__WRITE(src) \
15579                     (((uint32_t)(src)\
15580                     << 16) & 0xffff0000U)
15581 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__MODIFY(dst, src) \
15582                     (dst) = ((dst) &\
15583                     ~0xffff0000U) | (((uint32_t)(src) <<\
15584                     16) & 0xffff0000U)
15585 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__COMPARE_VALUE__VERIFY(src) \
15586                     (!((((uint32_t)(src)\
15587                     << 16) & ~0xffff0000U)))
15588 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__TYPE                          uint32_t
15589 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__READ                       0xffffffffU
15590 #define EMAC_REGS__TYPE2_COMPARE_WORD_0__WRITE                      0xffffffffU
15591 
15592 #endif /* __EMAC_REGS__TYPE2_COMPARE_WORD_0_MACRO__ */
15593 
15594 
15595 /* macros for type2_compare_0_word_0 */
15596 #define INST_TYPE2_COMPARE_0_WORD_0__NUM                                      1
15597 
15598 /* macros for BlueprintGlobalNameSpace::emac_regs::type2_compare_word_1 */
15599 #ifndef __EMAC_REGS__TYPE2_COMPARE_WORD_1_MACRO__
15600 #define __EMAC_REGS__TYPE2_COMPARE_WORD_1_MACRO__
15601 
15602 /* macros for field offset_value */
15603 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__SHIFT                  0
15604 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__WIDTH                  7
15605 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__MASK         0x0000007fU
15606 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__RESET                  0
15607 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__READ(src) \
15608                     ((uint32_t)(src)\
15609                     & 0x0000007fU)
15610 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__WRITE(src) \
15611                     ((uint32_t)(src)\
15612                     & 0x0000007fU)
15613 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__MODIFY(dst, src) \
15614                     (dst) = ((dst) &\
15615                     ~0x0000007fU) | ((uint32_t)(src) &\
15616                     0x0000007fU)
15617 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__OFFSET_VALUE__VERIFY(src) \
15618                     (!(((uint32_t)(src)\
15619                     & ~0x0000007fU)))
15620 
15621 /* macros for field compare_offset */
15622 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__SHIFT                7
15623 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__WIDTH                2
15624 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__MASK       0x00000180U
15625 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__RESET                0
15626 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__READ(src) \
15627                     (((uint32_t)(src)\
15628                     & 0x00000180U) >> 7)
15629 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__WRITE(src) \
15630                     (((uint32_t)(src)\
15631                     << 7) & 0x00000180U)
15632 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__MODIFY(dst, src) \
15633                     (dst) = ((dst) &\
15634                     ~0x00000180U) | (((uint32_t)(src) <<\
15635                     7) & 0x00000180U)
15636 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__COMPARE_OFFSET__VERIFY(src) \
15637                     (!((((uint32_t)(src)\
15638                     << 7) & ~0x00000180U)))
15639 
15640 /* macros for field disable_mask */
15641 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__SHIFT                  9
15642 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__WIDTH                  1
15643 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__MASK         0x00000200U
15644 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__RESET                  0
15645 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__READ(src) \
15646                     (((uint32_t)(src)\
15647                     & 0x00000200U) >> 9)
15648 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__WRITE(src) \
15649                     (((uint32_t)(src)\
15650                     << 9) & 0x00000200U)
15651 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__MODIFY(dst, src) \
15652                     (dst) = ((dst) &\
15653                     ~0x00000200U) | (((uint32_t)(src) <<\
15654                     9) & 0x00000200U)
15655 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__VERIFY(src) \
15656                     (!((((uint32_t)(src)\
15657                     << 9) & ~0x00000200U)))
15658 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__SET(dst) \
15659                     (dst) = ((dst) &\
15660                     ~0x00000200U) | ((uint32_t)(1) << 9)
15661 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__DISABLE_MASK__CLR(dst) \
15662                     (dst) = ((dst) &\
15663                     ~0x00000200U) | ((uint32_t)(0) << 9)
15664 
15665 /* macros for field reserved_31_10 */
15666 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__RESERVED_31_10__SHIFT               10
15667 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__RESERVED_31_10__WIDTH               22
15668 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__RESERVED_31_10__MASK       0xfffffc00U
15669 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__RESERVED_31_10__RESET                0
15670 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__RESERVED_31_10__READ(src) \
15671                     (((uint32_t)(src)\
15672                     & 0xfffffc00U) >> 10)
15673 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__TYPE                          uint32_t
15674 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__READ                       0xffffffffU
15675 #define EMAC_REGS__TYPE2_COMPARE_WORD_1__WRITE                      0xffffffffU
15676 
15677 #endif /* __EMAC_REGS__TYPE2_COMPARE_WORD_1_MACRO__ */
15678 
15679 
15680 /* macros for type2_compare_0_word_1 */
15681 #define INST_TYPE2_COMPARE_0_WORD_1__NUM                                      1
15682 
15683 /* macros for type2_compare_1_word_0 */
15684 #define INST_TYPE2_COMPARE_1_WORD_0__NUM                                      1
15685 
15686 /* macros for type2_compare_1_word_1 */
15687 #define INST_TYPE2_COMPARE_1_WORD_1__NUM                                      1
15688 
15689 /* macros for type2_compare_2_word_0 */
15690 #define INST_TYPE2_COMPARE_2_WORD_0__NUM                                      1
15691 
15692 /* macros for type2_compare_2_word_1 */
15693 #define INST_TYPE2_COMPARE_2_WORD_1__NUM                                      1
15694 
15695 /* macros for type2_compare_3_word_0 */
15696 #define INST_TYPE2_COMPARE_3_WORD_0__NUM                                      1
15697 
15698 /* macros for type2_compare_3_word_1 */
15699 #define INST_TYPE2_COMPARE_3_WORD_1__NUM                                      1
15700 
15701 /* macros for type2_compare_4_word_0 */
15702 #define INST_TYPE2_COMPARE_4_WORD_0__NUM                                      1
15703 
15704 /* macros for type2_compare_4_word_1 */
15705 #define INST_TYPE2_COMPARE_4_WORD_1__NUM                                      1
15706 
15707 /* macros for type2_compare_5_word_0 */
15708 #define INST_TYPE2_COMPARE_5_WORD_0__NUM                                      1
15709 
15710 /* macros for type2_compare_5_word_1 */
15711 #define INST_TYPE2_COMPARE_5_WORD_1__NUM                                      1
15712 
15713 /* macros for type2_compare_6_word_0 */
15714 #define INST_TYPE2_COMPARE_6_WORD_0__NUM                                      1
15715 
15716 /* macros for type2_compare_6_word_1 */
15717 #define INST_TYPE2_COMPARE_6_WORD_1__NUM                                      1
15718 
15719 /* macros for type2_compare_7_word_0 */
15720 #define INST_TYPE2_COMPARE_7_WORD_0__NUM                                      1
15721 
15722 /* macros for type2_compare_7_word_1 */
15723 #define INST_TYPE2_COMPARE_7_WORD_1__NUM                                      1
15724 
15725 /* macros for type2_compare_8_word_0 */
15726 #define INST_TYPE2_COMPARE_8_WORD_0__NUM                                      1
15727 
15728 /* macros for type2_compare_8_word_1 */
15729 #define INST_TYPE2_COMPARE_8_WORD_1__NUM                                      1
15730 
15731 /* macros for type2_compare_9_word_0 */
15732 #define INST_TYPE2_COMPARE_9_WORD_0__NUM                                      1
15733 
15734 /* macros for type2_compare_9_word_1 */
15735 #define INST_TYPE2_COMPARE_9_WORD_1__NUM                                      1
15736 
15737 /* macros for type2_compare_10_word_0 */
15738 #define INST_TYPE2_COMPARE_10_WORD_0__NUM                                     1
15739 
15740 /* macros for type2_compare_10_word_1 */
15741 #define INST_TYPE2_COMPARE_10_WORD_1__NUM                                     1
15742 
15743 /* macros for type2_compare_11_word_0 */
15744 #define INST_TYPE2_COMPARE_11_WORD_0__NUM                                     1
15745 
15746 /* macros for type2_compare_11_word_1 */
15747 #define INST_TYPE2_COMPARE_11_WORD_1__NUM                                     1
15748 
15749 /* macros for type2_compare_12_word_0 */
15750 #define INST_TYPE2_COMPARE_12_WORD_0__NUM                                     1
15751 
15752 /* macros for type2_compare_12_word_1 */
15753 #define INST_TYPE2_COMPARE_12_WORD_1__NUM                                     1
15754 
15755 /* macros for type2_compare_13_word_0 */
15756 #define INST_TYPE2_COMPARE_13_WORD_0__NUM                                     1
15757 
15758 /* macros for type2_compare_13_word_1 */
15759 #define INST_TYPE2_COMPARE_13_WORD_1__NUM                                     1
15760 
15761 /* macros for type2_compare_14_word_0 */
15762 #define INST_TYPE2_COMPARE_14_WORD_0__NUM                                     1
15763 
15764 /* macros for type2_compare_14_word_1 */
15765 #define INST_TYPE2_COMPARE_14_WORD_1__NUM                                     1
15766 
15767 /* macros for type2_compare_15_word_0 */
15768 #define INST_TYPE2_COMPARE_15_WORD_0__NUM                                     1
15769 
15770 /* macros for type2_compare_15_word_1 */
15771 #define INST_TYPE2_COMPARE_15_WORD_1__NUM                                     1
15772 
15773 /* macros for type2_compare_16_word_0 */
15774 #define INST_TYPE2_COMPARE_16_WORD_0__NUM                                     1
15775 
15776 /* macros for type2_compare_16_word_1 */
15777 #define INST_TYPE2_COMPARE_16_WORD_1__NUM                                     1
15778 
15779 /* macros for type2_compare_17_word_0 */
15780 #define INST_TYPE2_COMPARE_17_WORD_0__NUM                                     1
15781 
15782 /* macros for type2_compare_17_word_1 */
15783 #define INST_TYPE2_COMPARE_17_WORD_1__NUM                                     1
15784 
15785 /* macros for type2_compare_18_word_0 */
15786 #define INST_TYPE2_COMPARE_18_WORD_0__NUM                                     1
15787 
15788 /* macros for type2_compare_18_word_1 */
15789 #define INST_TYPE2_COMPARE_18_WORD_1__NUM                                     1
15790 
15791 /* macros for type2_compare_19_word_0 */
15792 #define INST_TYPE2_COMPARE_19_WORD_0__NUM                                     1
15793 
15794 /* macros for type2_compare_19_word_1 */
15795 #define INST_TYPE2_COMPARE_19_WORD_1__NUM                                     1
15796 
15797 /* macros for type2_compare_20_word_0 */
15798 #define INST_TYPE2_COMPARE_20_WORD_0__NUM                                     1
15799 
15800 /* macros for type2_compare_20_word_1 */
15801 #define INST_TYPE2_COMPARE_20_WORD_1__NUM                                     1
15802 
15803 /* macros for type2_compare_21_word_0 */
15804 #define INST_TYPE2_COMPARE_21_WORD_0__NUM                                     1
15805 
15806 /* macros for type2_compare_21_word_1 */
15807 #define INST_TYPE2_COMPARE_21_WORD_1__NUM                                     1
15808 
15809 /* macros for type2_compare_22_word_0 */
15810 #define INST_TYPE2_COMPARE_22_WORD_0__NUM                                     1
15811 
15812 /* macros for type2_compare_22_word_1 */
15813 #define INST_TYPE2_COMPARE_22_WORD_1__NUM                                     1
15814 
15815 /* macros for type2_compare_23_word_0 */
15816 #define INST_TYPE2_COMPARE_23_WORD_0__NUM                                     1
15817 
15818 /* macros for type2_compare_23_word_1 */
15819 #define INST_TYPE2_COMPARE_23_WORD_1__NUM                                     1
15820 
15821 /* macros for type2_compare_24_word_0 */
15822 #define INST_TYPE2_COMPARE_24_WORD_0__NUM                                     1
15823 
15824 /* macros for type2_compare_24_word_1 */
15825 #define INST_TYPE2_COMPARE_24_WORD_1__NUM                                     1
15826 
15827 /* macros for type2_compare_25_word_0 */
15828 #define INST_TYPE2_COMPARE_25_WORD_0__NUM                                     1
15829 
15830 /* macros for type2_compare_25_word_1 */
15831 #define INST_TYPE2_COMPARE_25_WORD_1__NUM                                     1
15832 
15833 /* macros for type2_compare_26_word_0 */
15834 #define INST_TYPE2_COMPARE_26_WORD_0__NUM                                     1
15835 
15836 /* macros for type2_compare_26_word_1 */
15837 #define INST_TYPE2_COMPARE_26_WORD_1__NUM                                     1
15838 
15839 /* macros for type2_compare_27_word_0 */
15840 #define INST_TYPE2_COMPARE_27_WORD_0__NUM                                     1
15841 
15842 /* macros for type2_compare_27_word_1 */
15843 #define INST_TYPE2_COMPARE_27_WORD_1__NUM                                     1
15844 
15845 /* macros for type2_compare_28_word_0 */
15846 #define INST_TYPE2_COMPARE_28_WORD_0__NUM                                     1
15847 
15848 /* macros for type2_compare_28_word_1 */
15849 #define INST_TYPE2_COMPARE_28_WORD_1__NUM                                     1
15850 
15851 /* macros for type2_compare_29_word_0 */
15852 #define INST_TYPE2_COMPARE_29_WORD_0__NUM                                     1
15853 
15854 /* macros for type2_compare_29_word_1 */
15855 #define INST_TYPE2_COMPARE_29_WORD_1__NUM                                     1
15856 
15857 /* macros for type2_compare_30_word_0 */
15858 #define INST_TYPE2_COMPARE_30_WORD_0__NUM                                     1
15859 
15860 /* macros for type2_compare_30_word_1 */
15861 #define INST_TYPE2_COMPARE_30_WORD_1__NUM                                     1
15862 
15863 /* macros for type2_compare_31_word_0 */
15864 #define INST_TYPE2_COMPARE_31_WORD_0__NUM                                     1
15865 
15866 /* macros for type2_compare_31_word_1 */
15867 #define INST_TYPE2_COMPARE_31_WORD_1__NUM                                     1
15868 
15869 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_start_time_q8 */
15870 #ifndef __EMAC_REGS__ENST_START_TIME_Q8_MACRO__
15871 #define __EMAC_REGS__ENST_START_TIME_Q8_MACRO__
15872 
15873 /* macros for field start_time_nsec */
15874 #define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__SHIFT                 0
15875 #define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__WIDTH                30
15876 #define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__MASK        0x3fffffffU
15877 #define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__RESET                 0
15878 #define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__READ(src) \
15879                     ((uint32_t)(src)\
15880                     & 0x3fffffffU)
15881 #define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__WRITE(src) \
15882                     ((uint32_t)(src)\
15883                     & 0x3fffffffU)
15884 #define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__MODIFY(dst, src) \
15885                     (dst) = ((dst) &\
15886                     ~0x3fffffffU) | ((uint32_t)(src) &\
15887                     0x3fffffffU)
15888 #define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_NSEC__VERIFY(src) \
15889                     (!(((uint32_t)(src)\
15890                     & ~0x3fffffffU)))
15891 
15892 /* macros for field start_time_sec */
15893 #define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__SHIFT                 30
15894 #define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__WIDTH                  2
15895 #define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__MASK         0xc0000000U
15896 #define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__RESET                  0
15897 #define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__READ(src) \
15898                     (((uint32_t)(src)\
15899                     & 0xc0000000U) >> 30)
15900 #define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__WRITE(src) \
15901                     (((uint32_t)(src)\
15902                     << 30) & 0xc0000000U)
15903 #define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__MODIFY(dst, src) \
15904                     (dst) = ((dst) &\
15905                     ~0xc0000000U) | (((uint32_t)(src) <<\
15906                     30) & 0xc0000000U)
15907 #define EMAC_REGS__ENST_START_TIME_Q8__START_TIME_SEC__VERIFY(src) \
15908                     (!((((uint32_t)(src)\
15909                     << 30) & ~0xc0000000U)))
15910 #define EMAC_REGS__ENST_START_TIME_Q8__TYPE                            uint32_t
15911 #define EMAC_REGS__ENST_START_TIME_Q8__READ                         0xffffffffU
15912 #define EMAC_REGS__ENST_START_TIME_Q8__WRITE                        0xffffffffU
15913 
15914 #endif /* __EMAC_REGS__ENST_START_TIME_Q8_MACRO__ */
15915 
15916 
15917 /* macros for enst_start_time_q8 */
15918 #define INST_ENST_START_TIME_Q8__NUM                                          1
15919 
15920 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_start_time_q9 */
15921 #ifndef __EMAC_REGS__ENST_START_TIME_Q9_MACRO__
15922 #define __EMAC_REGS__ENST_START_TIME_Q9_MACRO__
15923 
15924 /* macros for field start_time_nsec */
15925 #define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__SHIFT                 0
15926 #define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__WIDTH                30
15927 #define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__MASK        0x3fffffffU
15928 #define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__RESET                 0
15929 #define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__READ(src) \
15930                     ((uint32_t)(src)\
15931                     & 0x3fffffffU)
15932 #define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__WRITE(src) \
15933                     ((uint32_t)(src)\
15934                     & 0x3fffffffU)
15935 #define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__MODIFY(dst, src) \
15936                     (dst) = ((dst) &\
15937                     ~0x3fffffffU) | ((uint32_t)(src) &\
15938                     0x3fffffffU)
15939 #define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_NSEC__VERIFY(src) \
15940                     (!(((uint32_t)(src)\
15941                     & ~0x3fffffffU)))
15942 
15943 /* macros for field start_time_sec */
15944 #define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__SHIFT                 30
15945 #define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__WIDTH                  2
15946 #define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__MASK         0xc0000000U
15947 #define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__RESET                  0
15948 #define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__READ(src) \
15949                     (((uint32_t)(src)\
15950                     & 0xc0000000U) >> 30)
15951 #define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__WRITE(src) \
15952                     (((uint32_t)(src)\
15953                     << 30) & 0xc0000000U)
15954 #define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__MODIFY(dst, src) \
15955                     (dst) = ((dst) &\
15956                     ~0xc0000000U) | (((uint32_t)(src) <<\
15957                     30) & 0xc0000000U)
15958 #define EMAC_REGS__ENST_START_TIME_Q9__START_TIME_SEC__VERIFY(src) \
15959                     (!((((uint32_t)(src)\
15960                     << 30) & ~0xc0000000U)))
15961 #define EMAC_REGS__ENST_START_TIME_Q9__TYPE                            uint32_t
15962 #define EMAC_REGS__ENST_START_TIME_Q9__READ                         0xffffffffU
15963 #define EMAC_REGS__ENST_START_TIME_Q9__WRITE                        0xffffffffU
15964 
15965 #endif /* __EMAC_REGS__ENST_START_TIME_Q9_MACRO__ */
15966 
15967 
15968 /* macros for enst_start_time_q9 */
15969 #define INST_ENST_START_TIME_Q9__NUM                                          1
15970 
15971 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_start_time_q10 */
15972 #ifndef __EMAC_REGS__ENST_START_TIME_Q10_MACRO__
15973 #define __EMAC_REGS__ENST_START_TIME_Q10_MACRO__
15974 
15975 /* macros for field start_time_nsec */
15976 #define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__SHIFT                0
15977 #define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__WIDTH               30
15978 #define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__MASK       0x3fffffffU
15979 #define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__RESET                0
15980 #define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__READ(src) \
15981                     ((uint32_t)(src)\
15982                     & 0x3fffffffU)
15983 #define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__WRITE(src) \
15984                     ((uint32_t)(src)\
15985                     & 0x3fffffffU)
15986 #define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__MODIFY(dst, src) \
15987                     (dst) = ((dst) &\
15988                     ~0x3fffffffU) | ((uint32_t)(src) &\
15989                     0x3fffffffU)
15990 #define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_NSEC__VERIFY(src) \
15991                     (!(((uint32_t)(src)\
15992                     & ~0x3fffffffU)))
15993 
15994 /* macros for field start_time_sec */
15995 #define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__SHIFT                30
15996 #define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__WIDTH                 2
15997 #define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__MASK        0xc0000000U
15998 #define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__RESET                 0
15999 #define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__READ(src) \
16000                     (((uint32_t)(src)\
16001                     & 0xc0000000U) >> 30)
16002 #define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__WRITE(src) \
16003                     (((uint32_t)(src)\
16004                     << 30) & 0xc0000000U)
16005 #define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__MODIFY(dst, src) \
16006                     (dst) = ((dst) &\
16007                     ~0xc0000000U) | (((uint32_t)(src) <<\
16008                     30) & 0xc0000000U)
16009 #define EMAC_REGS__ENST_START_TIME_Q10__START_TIME_SEC__VERIFY(src) \
16010                     (!((((uint32_t)(src)\
16011                     << 30) & ~0xc0000000U)))
16012 #define EMAC_REGS__ENST_START_TIME_Q10__TYPE                           uint32_t
16013 #define EMAC_REGS__ENST_START_TIME_Q10__READ                        0xffffffffU
16014 #define EMAC_REGS__ENST_START_TIME_Q10__WRITE                       0xffffffffU
16015 
16016 #endif /* __EMAC_REGS__ENST_START_TIME_Q10_MACRO__ */
16017 
16018 
16019 /* macros for enst_start_time_q10 */
16020 #define INST_ENST_START_TIME_Q10__NUM                                         1
16021 
16022 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_start_time_q11 */
16023 #ifndef __EMAC_REGS__ENST_START_TIME_Q11_MACRO__
16024 #define __EMAC_REGS__ENST_START_TIME_Q11_MACRO__
16025 
16026 /* macros for field start_time_nsec */
16027 #define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__SHIFT                0
16028 #define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__WIDTH               30
16029 #define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__MASK       0x3fffffffU
16030 #define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__RESET                0
16031 #define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__READ(src) \
16032                     ((uint32_t)(src)\
16033                     & 0x3fffffffU)
16034 #define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__WRITE(src) \
16035                     ((uint32_t)(src)\
16036                     & 0x3fffffffU)
16037 #define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__MODIFY(dst, src) \
16038                     (dst) = ((dst) &\
16039                     ~0x3fffffffU) | ((uint32_t)(src) &\
16040                     0x3fffffffU)
16041 #define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_NSEC__VERIFY(src) \
16042                     (!(((uint32_t)(src)\
16043                     & ~0x3fffffffU)))
16044 
16045 /* macros for field start_time_sec */
16046 #define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__SHIFT                30
16047 #define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__WIDTH                 2
16048 #define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__MASK        0xc0000000U
16049 #define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__RESET                 0
16050 #define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__READ(src) \
16051                     (((uint32_t)(src)\
16052                     & 0xc0000000U) >> 30)
16053 #define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__WRITE(src) \
16054                     (((uint32_t)(src)\
16055                     << 30) & 0xc0000000U)
16056 #define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__MODIFY(dst, src) \
16057                     (dst) = ((dst) &\
16058                     ~0xc0000000U) | (((uint32_t)(src) <<\
16059                     30) & 0xc0000000U)
16060 #define EMAC_REGS__ENST_START_TIME_Q11__START_TIME_SEC__VERIFY(src) \
16061                     (!((((uint32_t)(src)\
16062                     << 30) & ~0xc0000000U)))
16063 #define EMAC_REGS__ENST_START_TIME_Q11__TYPE                           uint32_t
16064 #define EMAC_REGS__ENST_START_TIME_Q11__READ                        0xffffffffU
16065 #define EMAC_REGS__ENST_START_TIME_Q11__WRITE                       0xffffffffU
16066 
16067 #endif /* __EMAC_REGS__ENST_START_TIME_Q11_MACRO__ */
16068 
16069 
16070 /* macros for enst_start_time_q11 */
16071 #define INST_ENST_START_TIME_Q11__NUM                                         1
16072 
16073 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_start_time_q12 */
16074 #ifndef __EMAC_REGS__ENST_START_TIME_Q12_MACRO__
16075 #define __EMAC_REGS__ENST_START_TIME_Q12_MACRO__
16076 
16077 /* macros for field start_time_nsec */
16078 #define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__SHIFT                0
16079 #define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__WIDTH               30
16080 #define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__MASK       0x3fffffffU
16081 #define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__RESET                0
16082 #define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__READ(src) \
16083                     ((uint32_t)(src)\
16084                     & 0x3fffffffU)
16085 #define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__WRITE(src) \
16086                     ((uint32_t)(src)\
16087                     & 0x3fffffffU)
16088 #define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__MODIFY(dst, src) \
16089                     (dst) = ((dst) &\
16090                     ~0x3fffffffU) | ((uint32_t)(src) &\
16091                     0x3fffffffU)
16092 #define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_NSEC__VERIFY(src) \
16093                     (!(((uint32_t)(src)\
16094                     & ~0x3fffffffU)))
16095 
16096 /* macros for field start_time_sec */
16097 #define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__SHIFT                30
16098 #define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__WIDTH                 2
16099 #define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__MASK        0xc0000000U
16100 #define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__RESET                 0
16101 #define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__READ(src) \
16102                     (((uint32_t)(src)\
16103                     & 0xc0000000U) >> 30)
16104 #define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__WRITE(src) \
16105                     (((uint32_t)(src)\
16106                     << 30) & 0xc0000000U)
16107 #define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__MODIFY(dst, src) \
16108                     (dst) = ((dst) &\
16109                     ~0xc0000000U) | (((uint32_t)(src) <<\
16110                     30) & 0xc0000000U)
16111 #define EMAC_REGS__ENST_START_TIME_Q12__START_TIME_SEC__VERIFY(src) \
16112                     (!((((uint32_t)(src)\
16113                     << 30) & ~0xc0000000U)))
16114 #define EMAC_REGS__ENST_START_TIME_Q12__TYPE                           uint32_t
16115 #define EMAC_REGS__ENST_START_TIME_Q12__READ                        0xffffffffU
16116 #define EMAC_REGS__ENST_START_TIME_Q12__WRITE                       0xffffffffU
16117 
16118 #endif /* __EMAC_REGS__ENST_START_TIME_Q12_MACRO__ */
16119 
16120 
16121 /* macros for enst_start_time_q12 */
16122 #define INST_ENST_START_TIME_Q12__NUM                                         1
16123 
16124 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_start_time_q13 */
16125 #ifndef __EMAC_REGS__ENST_START_TIME_Q13_MACRO__
16126 #define __EMAC_REGS__ENST_START_TIME_Q13_MACRO__
16127 
16128 /* macros for field start_time_nsec */
16129 #define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__SHIFT                0
16130 #define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__WIDTH               30
16131 #define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__MASK       0x3fffffffU
16132 #define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__RESET                0
16133 #define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__READ(src) \
16134                     ((uint32_t)(src)\
16135                     & 0x3fffffffU)
16136 #define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__WRITE(src) \
16137                     ((uint32_t)(src)\
16138                     & 0x3fffffffU)
16139 #define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__MODIFY(dst, src) \
16140                     (dst) = ((dst) &\
16141                     ~0x3fffffffU) | ((uint32_t)(src) &\
16142                     0x3fffffffU)
16143 #define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_NSEC__VERIFY(src) \
16144                     (!(((uint32_t)(src)\
16145                     & ~0x3fffffffU)))
16146 
16147 /* macros for field start_time_sec */
16148 #define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__SHIFT                30
16149 #define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__WIDTH                 2
16150 #define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__MASK        0xc0000000U
16151 #define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__RESET                 0
16152 #define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__READ(src) \
16153                     (((uint32_t)(src)\
16154                     & 0xc0000000U) >> 30)
16155 #define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__WRITE(src) \
16156                     (((uint32_t)(src)\
16157                     << 30) & 0xc0000000U)
16158 #define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__MODIFY(dst, src) \
16159                     (dst) = ((dst) &\
16160                     ~0xc0000000U) | (((uint32_t)(src) <<\
16161                     30) & 0xc0000000U)
16162 #define EMAC_REGS__ENST_START_TIME_Q13__START_TIME_SEC__VERIFY(src) \
16163                     (!((((uint32_t)(src)\
16164                     << 30) & ~0xc0000000U)))
16165 #define EMAC_REGS__ENST_START_TIME_Q13__TYPE                           uint32_t
16166 #define EMAC_REGS__ENST_START_TIME_Q13__READ                        0xffffffffU
16167 #define EMAC_REGS__ENST_START_TIME_Q13__WRITE                       0xffffffffU
16168 
16169 #endif /* __EMAC_REGS__ENST_START_TIME_Q13_MACRO__ */
16170 
16171 
16172 /* macros for enst_start_time_q13 */
16173 #define INST_ENST_START_TIME_Q13__NUM                                         1
16174 
16175 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_start_time_q14 */
16176 #ifndef __EMAC_REGS__ENST_START_TIME_Q14_MACRO__
16177 #define __EMAC_REGS__ENST_START_TIME_Q14_MACRO__
16178 
16179 /* macros for field start_time_nsec */
16180 #define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__SHIFT                0
16181 #define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__WIDTH               30
16182 #define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__MASK       0x3fffffffU
16183 #define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__RESET                0
16184 #define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__READ(src) \
16185                     ((uint32_t)(src)\
16186                     & 0x3fffffffU)
16187 #define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__WRITE(src) \
16188                     ((uint32_t)(src)\
16189                     & 0x3fffffffU)
16190 #define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__MODIFY(dst, src) \
16191                     (dst) = ((dst) &\
16192                     ~0x3fffffffU) | ((uint32_t)(src) &\
16193                     0x3fffffffU)
16194 #define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_NSEC__VERIFY(src) \
16195                     (!(((uint32_t)(src)\
16196                     & ~0x3fffffffU)))
16197 
16198 /* macros for field start_time_sec */
16199 #define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__SHIFT                30
16200 #define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__WIDTH                 2
16201 #define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__MASK        0xc0000000U
16202 #define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__RESET                 0
16203 #define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__READ(src) \
16204                     (((uint32_t)(src)\
16205                     & 0xc0000000U) >> 30)
16206 #define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__WRITE(src) \
16207                     (((uint32_t)(src)\
16208                     << 30) & 0xc0000000U)
16209 #define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__MODIFY(dst, src) \
16210                     (dst) = ((dst) &\
16211                     ~0xc0000000U) | (((uint32_t)(src) <<\
16212                     30) & 0xc0000000U)
16213 #define EMAC_REGS__ENST_START_TIME_Q14__START_TIME_SEC__VERIFY(src) \
16214                     (!((((uint32_t)(src)\
16215                     << 30) & ~0xc0000000U)))
16216 #define EMAC_REGS__ENST_START_TIME_Q14__TYPE                           uint32_t
16217 #define EMAC_REGS__ENST_START_TIME_Q14__READ                        0xffffffffU
16218 #define EMAC_REGS__ENST_START_TIME_Q14__WRITE                       0xffffffffU
16219 
16220 #endif /* __EMAC_REGS__ENST_START_TIME_Q14_MACRO__ */
16221 
16222 
16223 /* macros for enst_start_time_q14 */
16224 #define INST_ENST_START_TIME_Q14__NUM                                         1
16225 
16226 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_start_time_q15 */
16227 #ifndef __EMAC_REGS__ENST_START_TIME_Q15_MACRO__
16228 #define __EMAC_REGS__ENST_START_TIME_Q15_MACRO__
16229 
16230 /* macros for field start_time_nsec */
16231 #define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__SHIFT                0
16232 #define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__WIDTH               30
16233 #define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__MASK       0x3fffffffU
16234 #define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__RESET                0
16235 #define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__READ(src) \
16236                     ((uint32_t)(src)\
16237                     & 0x3fffffffU)
16238 #define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__WRITE(src) \
16239                     ((uint32_t)(src)\
16240                     & 0x3fffffffU)
16241 #define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__MODIFY(dst, src) \
16242                     (dst) = ((dst) &\
16243                     ~0x3fffffffU) | ((uint32_t)(src) &\
16244                     0x3fffffffU)
16245 #define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_NSEC__VERIFY(src) \
16246                     (!(((uint32_t)(src)\
16247                     & ~0x3fffffffU)))
16248 
16249 /* macros for field start_time_sec */
16250 #define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__SHIFT                30
16251 #define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__WIDTH                 2
16252 #define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__MASK        0xc0000000U
16253 #define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__RESET                 0
16254 #define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__READ(src) \
16255                     (((uint32_t)(src)\
16256                     & 0xc0000000U) >> 30)
16257 #define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__WRITE(src) \
16258                     (((uint32_t)(src)\
16259                     << 30) & 0xc0000000U)
16260 #define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__MODIFY(dst, src) \
16261                     (dst) = ((dst) &\
16262                     ~0xc0000000U) | (((uint32_t)(src) <<\
16263                     30) & 0xc0000000U)
16264 #define EMAC_REGS__ENST_START_TIME_Q15__START_TIME_SEC__VERIFY(src) \
16265                     (!((((uint32_t)(src)\
16266                     << 30) & ~0xc0000000U)))
16267 #define EMAC_REGS__ENST_START_TIME_Q15__TYPE                           uint32_t
16268 #define EMAC_REGS__ENST_START_TIME_Q15__READ                        0xffffffffU
16269 #define EMAC_REGS__ENST_START_TIME_Q15__WRITE                       0xffffffffU
16270 
16271 #endif /* __EMAC_REGS__ENST_START_TIME_Q15_MACRO__ */
16272 
16273 
16274 /* macros for enst_start_time_q15 */
16275 #define INST_ENST_START_TIME_Q15__NUM                                         1
16276 
16277 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_on_time_q8 */
16278 #ifndef __EMAC_REGS__ENST_ON_TIME_Q8_MACRO__
16279 #define __EMAC_REGS__ENST_ON_TIME_Q8_MACRO__
16280 
16281 /* macros for field on_time */
16282 #define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__SHIFT                            0
16283 #define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__WIDTH                           17
16284 #define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__MASK                   0x0001ffffU
16285 #define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__RESET                      0x1FFFF
16286 #define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__READ(src) \
16287                     ((uint32_t)(src)\
16288                     & 0x0001ffffU)
16289 #define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__WRITE(src) \
16290                     ((uint32_t)(src)\
16291                     & 0x0001ffffU)
16292 #define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__MODIFY(dst, src) \
16293                     (dst) = ((dst) &\
16294                     ~0x0001ffffU) | ((uint32_t)(src) &\
16295                     0x0001ffffU)
16296 #define EMAC_REGS__ENST_ON_TIME_Q8__ON_TIME__VERIFY(src) \
16297                     (!(((uint32_t)(src)\
16298                     & ~0x0001ffffU)))
16299 
16300 /* macros for field reserved_31_17 */
16301 #define EMAC_REGS__ENST_ON_TIME_Q8__RESERVED_31_17__SHIFT                    17
16302 #define EMAC_REGS__ENST_ON_TIME_Q8__RESERVED_31_17__WIDTH                    15
16303 #define EMAC_REGS__ENST_ON_TIME_Q8__RESERVED_31_17__MASK            0xfffe0000U
16304 #define EMAC_REGS__ENST_ON_TIME_Q8__RESERVED_31_17__RESET                     0
16305 #define EMAC_REGS__ENST_ON_TIME_Q8__RESERVED_31_17__READ(src) \
16306                     (((uint32_t)(src)\
16307                     & 0xfffe0000U) >> 17)
16308 #define EMAC_REGS__ENST_ON_TIME_Q8__TYPE                               uint32_t
16309 #define EMAC_REGS__ENST_ON_TIME_Q8__READ                            0xffffffffU
16310 #define EMAC_REGS__ENST_ON_TIME_Q8__WRITE                           0xffffffffU
16311 
16312 #endif /* __EMAC_REGS__ENST_ON_TIME_Q8_MACRO__ */
16313 
16314 
16315 /* macros for enst_on_time_q8 */
16316 #define INST_ENST_ON_TIME_Q8__NUM                                             1
16317 
16318 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_on_time_q9 */
16319 #ifndef __EMAC_REGS__ENST_ON_TIME_Q9_MACRO__
16320 #define __EMAC_REGS__ENST_ON_TIME_Q9_MACRO__
16321 
16322 /* macros for field on_time */
16323 #define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__SHIFT                            0
16324 #define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__WIDTH                           17
16325 #define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__MASK                   0x0001ffffU
16326 #define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__RESET                      0x1FFFF
16327 #define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__READ(src) \
16328                     ((uint32_t)(src)\
16329                     & 0x0001ffffU)
16330 #define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__WRITE(src) \
16331                     ((uint32_t)(src)\
16332                     & 0x0001ffffU)
16333 #define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__MODIFY(dst, src) \
16334                     (dst) = ((dst) &\
16335                     ~0x0001ffffU) | ((uint32_t)(src) &\
16336                     0x0001ffffU)
16337 #define EMAC_REGS__ENST_ON_TIME_Q9__ON_TIME__VERIFY(src) \
16338                     (!(((uint32_t)(src)\
16339                     & ~0x0001ffffU)))
16340 
16341 /* macros for field reserved_31_17 */
16342 #define EMAC_REGS__ENST_ON_TIME_Q9__RESERVED_31_17__SHIFT                    17
16343 #define EMAC_REGS__ENST_ON_TIME_Q9__RESERVED_31_17__WIDTH                    15
16344 #define EMAC_REGS__ENST_ON_TIME_Q9__RESERVED_31_17__MASK            0xfffe0000U
16345 #define EMAC_REGS__ENST_ON_TIME_Q9__RESERVED_31_17__RESET                     0
16346 #define EMAC_REGS__ENST_ON_TIME_Q9__RESERVED_31_17__READ(src) \
16347                     (((uint32_t)(src)\
16348                     & 0xfffe0000U) >> 17)
16349 #define EMAC_REGS__ENST_ON_TIME_Q9__TYPE                               uint32_t
16350 #define EMAC_REGS__ENST_ON_TIME_Q9__READ                            0xffffffffU
16351 #define EMAC_REGS__ENST_ON_TIME_Q9__WRITE                           0xffffffffU
16352 
16353 #endif /* __EMAC_REGS__ENST_ON_TIME_Q9_MACRO__ */
16354 
16355 
16356 /* macros for enst_on_time_q9 */
16357 #define INST_ENST_ON_TIME_Q9__NUM                                             1
16358 
16359 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_on_time_q10 */
16360 #ifndef __EMAC_REGS__ENST_ON_TIME_Q10_MACRO__
16361 #define __EMAC_REGS__ENST_ON_TIME_Q10_MACRO__
16362 
16363 /* macros for field on_time */
16364 #define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__SHIFT                           0
16365 #define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__WIDTH                          17
16366 #define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__MASK                  0x0001ffffU
16367 #define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__RESET                     0x1FFFF
16368 #define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__READ(src) \
16369                     ((uint32_t)(src)\
16370                     & 0x0001ffffU)
16371 #define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__WRITE(src) \
16372                     ((uint32_t)(src)\
16373                     & 0x0001ffffU)
16374 #define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__MODIFY(dst, src) \
16375                     (dst) = ((dst) &\
16376                     ~0x0001ffffU) | ((uint32_t)(src) &\
16377                     0x0001ffffU)
16378 #define EMAC_REGS__ENST_ON_TIME_Q10__ON_TIME__VERIFY(src) \
16379                     (!(((uint32_t)(src)\
16380                     & ~0x0001ffffU)))
16381 
16382 /* macros for field reserved_31_17 */
16383 #define EMAC_REGS__ENST_ON_TIME_Q10__RESERVED_31_17__SHIFT                   17
16384 #define EMAC_REGS__ENST_ON_TIME_Q10__RESERVED_31_17__WIDTH                   15
16385 #define EMAC_REGS__ENST_ON_TIME_Q10__RESERVED_31_17__MASK           0xfffe0000U
16386 #define EMAC_REGS__ENST_ON_TIME_Q10__RESERVED_31_17__RESET                    0
16387 #define EMAC_REGS__ENST_ON_TIME_Q10__RESERVED_31_17__READ(src) \
16388                     (((uint32_t)(src)\
16389                     & 0xfffe0000U) >> 17)
16390 #define EMAC_REGS__ENST_ON_TIME_Q10__TYPE                              uint32_t
16391 #define EMAC_REGS__ENST_ON_TIME_Q10__READ                           0xffffffffU
16392 #define EMAC_REGS__ENST_ON_TIME_Q10__WRITE                          0xffffffffU
16393 
16394 #endif /* __EMAC_REGS__ENST_ON_TIME_Q10_MACRO__ */
16395 
16396 
16397 /* macros for enst_on_time_q10 */
16398 #define INST_ENST_ON_TIME_Q10__NUM                                            1
16399 
16400 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_on_time_q11 */
16401 #ifndef __EMAC_REGS__ENST_ON_TIME_Q11_MACRO__
16402 #define __EMAC_REGS__ENST_ON_TIME_Q11_MACRO__
16403 
16404 /* macros for field on_time */
16405 #define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__SHIFT                           0
16406 #define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__WIDTH                          17
16407 #define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__MASK                  0x0001ffffU
16408 #define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__RESET                     0x1FFFF
16409 #define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__READ(src) \
16410                     ((uint32_t)(src)\
16411                     & 0x0001ffffU)
16412 #define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__WRITE(src) \
16413                     ((uint32_t)(src)\
16414                     & 0x0001ffffU)
16415 #define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__MODIFY(dst, src) \
16416                     (dst) = ((dst) &\
16417                     ~0x0001ffffU) | ((uint32_t)(src) &\
16418                     0x0001ffffU)
16419 #define EMAC_REGS__ENST_ON_TIME_Q11__ON_TIME__VERIFY(src) \
16420                     (!(((uint32_t)(src)\
16421                     & ~0x0001ffffU)))
16422 
16423 /* macros for field reserved_31_17 */
16424 #define EMAC_REGS__ENST_ON_TIME_Q11__RESERVED_31_17__SHIFT                   17
16425 #define EMAC_REGS__ENST_ON_TIME_Q11__RESERVED_31_17__WIDTH                   15
16426 #define EMAC_REGS__ENST_ON_TIME_Q11__RESERVED_31_17__MASK           0xfffe0000U
16427 #define EMAC_REGS__ENST_ON_TIME_Q11__RESERVED_31_17__RESET                    0
16428 #define EMAC_REGS__ENST_ON_TIME_Q11__RESERVED_31_17__READ(src) \
16429                     (((uint32_t)(src)\
16430                     & 0xfffe0000U) >> 17)
16431 #define EMAC_REGS__ENST_ON_TIME_Q11__TYPE                              uint32_t
16432 #define EMAC_REGS__ENST_ON_TIME_Q11__READ                           0xffffffffU
16433 #define EMAC_REGS__ENST_ON_TIME_Q11__WRITE                          0xffffffffU
16434 
16435 #endif /* __EMAC_REGS__ENST_ON_TIME_Q11_MACRO__ */
16436 
16437 
16438 /* macros for enst_on_time_q11 */
16439 #define INST_ENST_ON_TIME_Q11__NUM                                            1
16440 
16441 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_on_time_q12 */
16442 #ifndef __EMAC_REGS__ENST_ON_TIME_Q12_MACRO__
16443 #define __EMAC_REGS__ENST_ON_TIME_Q12_MACRO__
16444 
16445 /* macros for field on_time */
16446 #define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__SHIFT                           0
16447 #define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__WIDTH                          17
16448 #define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__MASK                  0x0001ffffU
16449 #define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__RESET                     0x1FFFF
16450 #define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__READ(src) \
16451                     ((uint32_t)(src)\
16452                     & 0x0001ffffU)
16453 #define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__WRITE(src) \
16454                     ((uint32_t)(src)\
16455                     & 0x0001ffffU)
16456 #define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__MODIFY(dst, src) \
16457                     (dst) = ((dst) &\
16458                     ~0x0001ffffU) | ((uint32_t)(src) &\
16459                     0x0001ffffU)
16460 #define EMAC_REGS__ENST_ON_TIME_Q12__ON_TIME__VERIFY(src) \
16461                     (!(((uint32_t)(src)\
16462                     & ~0x0001ffffU)))
16463 
16464 /* macros for field reserved_31_17 */
16465 #define EMAC_REGS__ENST_ON_TIME_Q12__RESERVED_31_17__SHIFT                   17
16466 #define EMAC_REGS__ENST_ON_TIME_Q12__RESERVED_31_17__WIDTH                   15
16467 #define EMAC_REGS__ENST_ON_TIME_Q12__RESERVED_31_17__MASK           0xfffe0000U
16468 #define EMAC_REGS__ENST_ON_TIME_Q12__RESERVED_31_17__RESET                    0
16469 #define EMAC_REGS__ENST_ON_TIME_Q12__RESERVED_31_17__READ(src) \
16470                     (((uint32_t)(src)\
16471                     & 0xfffe0000U) >> 17)
16472 #define EMAC_REGS__ENST_ON_TIME_Q12__TYPE                              uint32_t
16473 #define EMAC_REGS__ENST_ON_TIME_Q12__READ                           0xffffffffU
16474 #define EMAC_REGS__ENST_ON_TIME_Q12__WRITE                          0xffffffffU
16475 
16476 #endif /* __EMAC_REGS__ENST_ON_TIME_Q12_MACRO__ */
16477 
16478 
16479 /* macros for enst_on_time_q12 */
16480 #define INST_ENST_ON_TIME_Q12__NUM                                            1
16481 
16482 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_on_time_q13 */
16483 #ifndef __EMAC_REGS__ENST_ON_TIME_Q13_MACRO__
16484 #define __EMAC_REGS__ENST_ON_TIME_Q13_MACRO__
16485 
16486 /* macros for field on_time */
16487 #define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__SHIFT                           0
16488 #define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__WIDTH                          17
16489 #define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__MASK                  0x0001ffffU
16490 #define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__RESET                     0x1FFFF
16491 #define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__READ(src) \
16492                     ((uint32_t)(src)\
16493                     & 0x0001ffffU)
16494 #define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__WRITE(src) \
16495                     ((uint32_t)(src)\
16496                     & 0x0001ffffU)
16497 #define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__MODIFY(dst, src) \
16498                     (dst) = ((dst) &\
16499                     ~0x0001ffffU) | ((uint32_t)(src) &\
16500                     0x0001ffffU)
16501 #define EMAC_REGS__ENST_ON_TIME_Q13__ON_TIME__VERIFY(src) \
16502                     (!(((uint32_t)(src)\
16503                     & ~0x0001ffffU)))
16504 
16505 /* macros for field reserved_31_17 */
16506 #define EMAC_REGS__ENST_ON_TIME_Q13__RESERVED_31_17__SHIFT                   17
16507 #define EMAC_REGS__ENST_ON_TIME_Q13__RESERVED_31_17__WIDTH                   15
16508 #define EMAC_REGS__ENST_ON_TIME_Q13__RESERVED_31_17__MASK           0xfffe0000U
16509 #define EMAC_REGS__ENST_ON_TIME_Q13__RESERVED_31_17__RESET                    0
16510 #define EMAC_REGS__ENST_ON_TIME_Q13__RESERVED_31_17__READ(src) \
16511                     (((uint32_t)(src)\
16512                     & 0xfffe0000U) >> 17)
16513 #define EMAC_REGS__ENST_ON_TIME_Q13__TYPE                              uint32_t
16514 #define EMAC_REGS__ENST_ON_TIME_Q13__READ                           0xffffffffU
16515 #define EMAC_REGS__ENST_ON_TIME_Q13__WRITE                          0xffffffffU
16516 
16517 #endif /* __EMAC_REGS__ENST_ON_TIME_Q13_MACRO__ */
16518 
16519 
16520 /* macros for enst_on_time_q13 */
16521 #define INST_ENST_ON_TIME_Q13__NUM                                            1
16522 
16523 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_on_time_q14 */
16524 #ifndef __EMAC_REGS__ENST_ON_TIME_Q14_MACRO__
16525 #define __EMAC_REGS__ENST_ON_TIME_Q14_MACRO__
16526 
16527 /* macros for field on_time */
16528 #define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__SHIFT                           0
16529 #define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__WIDTH                          17
16530 #define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__MASK                  0x0001ffffU
16531 #define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__RESET                     0x1FFFF
16532 #define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__READ(src) \
16533                     ((uint32_t)(src)\
16534                     & 0x0001ffffU)
16535 #define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__WRITE(src) \
16536                     ((uint32_t)(src)\
16537                     & 0x0001ffffU)
16538 #define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__MODIFY(dst, src) \
16539                     (dst) = ((dst) &\
16540                     ~0x0001ffffU) | ((uint32_t)(src) &\
16541                     0x0001ffffU)
16542 #define EMAC_REGS__ENST_ON_TIME_Q14__ON_TIME__VERIFY(src) \
16543                     (!(((uint32_t)(src)\
16544                     & ~0x0001ffffU)))
16545 
16546 /* macros for field reserved_31_17 */
16547 #define EMAC_REGS__ENST_ON_TIME_Q14__RESERVED_31_17__SHIFT                   17
16548 #define EMAC_REGS__ENST_ON_TIME_Q14__RESERVED_31_17__WIDTH                   15
16549 #define EMAC_REGS__ENST_ON_TIME_Q14__RESERVED_31_17__MASK           0xfffe0000U
16550 #define EMAC_REGS__ENST_ON_TIME_Q14__RESERVED_31_17__RESET                    0
16551 #define EMAC_REGS__ENST_ON_TIME_Q14__RESERVED_31_17__READ(src) \
16552                     (((uint32_t)(src)\
16553                     & 0xfffe0000U) >> 17)
16554 #define EMAC_REGS__ENST_ON_TIME_Q14__TYPE                              uint32_t
16555 #define EMAC_REGS__ENST_ON_TIME_Q14__READ                           0xffffffffU
16556 #define EMAC_REGS__ENST_ON_TIME_Q14__WRITE                          0xffffffffU
16557 
16558 #endif /* __EMAC_REGS__ENST_ON_TIME_Q14_MACRO__ */
16559 
16560 
16561 /* macros for enst_on_time_q14 */
16562 #define INST_ENST_ON_TIME_Q14__NUM                                            1
16563 
16564 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_on_time_q15 */
16565 #ifndef __EMAC_REGS__ENST_ON_TIME_Q15_MACRO__
16566 #define __EMAC_REGS__ENST_ON_TIME_Q15_MACRO__
16567 
16568 /* macros for field on_time */
16569 #define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__SHIFT                           0
16570 #define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__WIDTH                          17
16571 #define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__MASK                  0x0001ffffU
16572 #define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__RESET                     0x1FFFF
16573 #define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__READ(src) \
16574                     ((uint32_t)(src)\
16575                     & 0x0001ffffU)
16576 #define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__WRITE(src) \
16577                     ((uint32_t)(src)\
16578                     & 0x0001ffffU)
16579 #define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__MODIFY(dst, src) \
16580                     (dst) = ((dst) &\
16581                     ~0x0001ffffU) | ((uint32_t)(src) &\
16582                     0x0001ffffU)
16583 #define EMAC_REGS__ENST_ON_TIME_Q15__ON_TIME__VERIFY(src) \
16584                     (!(((uint32_t)(src)\
16585                     & ~0x0001ffffU)))
16586 
16587 /* macros for field reserved_31_17 */
16588 #define EMAC_REGS__ENST_ON_TIME_Q15__RESERVED_31_17__SHIFT                   17
16589 #define EMAC_REGS__ENST_ON_TIME_Q15__RESERVED_31_17__WIDTH                   15
16590 #define EMAC_REGS__ENST_ON_TIME_Q15__RESERVED_31_17__MASK           0xfffe0000U
16591 #define EMAC_REGS__ENST_ON_TIME_Q15__RESERVED_31_17__RESET                    0
16592 #define EMAC_REGS__ENST_ON_TIME_Q15__RESERVED_31_17__READ(src) \
16593                     (((uint32_t)(src)\
16594                     & 0xfffe0000U) >> 17)
16595 #define EMAC_REGS__ENST_ON_TIME_Q15__TYPE                              uint32_t
16596 #define EMAC_REGS__ENST_ON_TIME_Q15__READ                           0xffffffffU
16597 #define EMAC_REGS__ENST_ON_TIME_Q15__WRITE                          0xffffffffU
16598 
16599 #endif /* __EMAC_REGS__ENST_ON_TIME_Q15_MACRO__ */
16600 
16601 
16602 /* macros for enst_on_time_q15 */
16603 #define INST_ENST_ON_TIME_Q15__NUM                                            1
16604 
16605 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_off_time_q8 */
16606 #ifndef __EMAC_REGS__ENST_OFF_TIME_Q8_MACRO__
16607 #define __EMAC_REGS__ENST_OFF_TIME_Q8_MACRO__
16608 
16609 /* macros for field off_time */
16610 #define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__SHIFT                          0
16611 #define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__WIDTH                         17
16612 #define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__MASK                 0x0001ffffU
16613 #define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__RESET                          0
16614 #define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__READ(src) \
16615                     ((uint32_t)(src)\
16616                     & 0x0001ffffU)
16617 #define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__WRITE(src) \
16618                     ((uint32_t)(src)\
16619                     & 0x0001ffffU)
16620 #define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__MODIFY(dst, src) \
16621                     (dst) = ((dst) &\
16622                     ~0x0001ffffU) | ((uint32_t)(src) &\
16623                     0x0001ffffU)
16624 #define EMAC_REGS__ENST_OFF_TIME_Q8__OFF_TIME__VERIFY(src) \
16625                     (!(((uint32_t)(src)\
16626                     & ~0x0001ffffU)))
16627 
16628 /* macros for field reserved_31_17 */
16629 #define EMAC_REGS__ENST_OFF_TIME_Q8__RESERVED_31_17__SHIFT                   17
16630 #define EMAC_REGS__ENST_OFF_TIME_Q8__RESERVED_31_17__WIDTH                   15
16631 #define EMAC_REGS__ENST_OFF_TIME_Q8__RESERVED_31_17__MASK           0xfffe0000U
16632 #define EMAC_REGS__ENST_OFF_TIME_Q8__RESERVED_31_17__RESET                    0
16633 #define EMAC_REGS__ENST_OFF_TIME_Q8__RESERVED_31_17__READ(src) \
16634                     (((uint32_t)(src)\
16635                     & 0xfffe0000U) >> 17)
16636 #define EMAC_REGS__ENST_OFF_TIME_Q8__TYPE                              uint32_t
16637 #define EMAC_REGS__ENST_OFF_TIME_Q8__READ                           0xffffffffU
16638 #define EMAC_REGS__ENST_OFF_TIME_Q8__WRITE                          0xffffffffU
16639 
16640 #endif /* __EMAC_REGS__ENST_OFF_TIME_Q8_MACRO__ */
16641 
16642 
16643 /* macros for enst_off_time_q8 */
16644 #define INST_ENST_OFF_TIME_Q8__NUM                                            1
16645 
16646 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_off_time_q9 */
16647 #ifndef __EMAC_REGS__ENST_OFF_TIME_Q9_MACRO__
16648 #define __EMAC_REGS__ENST_OFF_TIME_Q9_MACRO__
16649 
16650 /* macros for field off_time */
16651 #define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__SHIFT                          0
16652 #define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__WIDTH                         17
16653 #define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__MASK                 0x0001ffffU
16654 #define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__RESET                          0
16655 #define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__READ(src) \
16656                     ((uint32_t)(src)\
16657                     & 0x0001ffffU)
16658 #define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__WRITE(src) \
16659                     ((uint32_t)(src)\
16660                     & 0x0001ffffU)
16661 #define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__MODIFY(dst, src) \
16662                     (dst) = ((dst) &\
16663                     ~0x0001ffffU) | ((uint32_t)(src) &\
16664                     0x0001ffffU)
16665 #define EMAC_REGS__ENST_OFF_TIME_Q9__OFF_TIME__VERIFY(src) \
16666                     (!(((uint32_t)(src)\
16667                     & ~0x0001ffffU)))
16668 
16669 /* macros for field reserved_31_17 */
16670 #define EMAC_REGS__ENST_OFF_TIME_Q9__RESERVED_31_17__SHIFT                   17
16671 #define EMAC_REGS__ENST_OFF_TIME_Q9__RESERVED_31_17__WIDTH                   15
16672 #define EMAC_REGS__ENST_OFF_TIME_Q9__RESERVED_31_17__MASK           0xfffe0000U
16673 #define EMAC_REGS__ENST_OFF_TIME_Q9__RESERVED_31_17__RESET                    0
16674 #define EMAC_REGS__ENST_OFF_TIME_Q9__RESERVED_31_17__READ(src) \
16675                     (((uint32_t)(src)\
16676                     & 0xfffe0000U) >> 17)
16677 #define EMAC_REGS__ENST_OFF_TIME_Q9__TYPE                              uint32_t
16678 #define EMAC_REGS__ENST_OFF_TIME_Q9__READ                           0xffffffffU
16679 #define EMAC_REGS__ENST_OFF_TIME_Q9__WRITE                          0xffffffffU
16680 
16681 #endif /* __EMAC_REGS__ENST_OFF_TIME_Q9_MACRO__ */
16682 
16683 
16684 /* macros for enst_off_time_q9 */
16685 #define INST_ENST_OFF_TIME_Q9__NUM                                            1
16686 
16687 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_off_time_q10 */
16688 #ifndef __EMAC_REGS__ENST_OFF_TIME_Q10_MACRO__
16689 #define __EMAC_REGS__ENST_OFF_TIME_Q10_MACRO__
16690 
16691 /* macros for field off_time */
16692 #define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__SHIFT                         0
16693 #define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__WIDTH                        17
16694 #define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__MASK                0x0001ffffU
16695 #define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__RESET                         0
16696 #define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__READ(src) \
16697                     ((uint32_t)(src)\
16698                     & 0x0001ffffU)
16699 #define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__WRITE(src) \
16700                     ((uint32_t)(src)\
16701                     & 0x0001ffffU)
16702 #define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__MODIFY(dst, src) \
16703                     (dst) = ((dst) &\
16704                     ~0x0001ffffU) | ((uint32_t)(src) &\
16705                     0x0001ffffU)
16706 #define EMAC_REGS__ENST_OFF_TIME_Q10__OFF_TIME__VERIFY(src) \
16707                     (!(((uint32_t)(src)\
16708                     & ~0x0001ffffU)))
16709 
16710 /* macros for field reserved_31_17 */
16711 #define EMAC_REGS__ENST_OFF_TIME_Q10__RESERVED_31_17__SHIFT                  17
16712 #define EMAC_REGS__ENST_OFF_TIME_Q10__RESERVED_31_17__WIDTH                  15
16713 #define EMAC_REGS__ENST_OFF_TIME_Q10__RESERVED_31_17__MASK          0xfffe0000U
16714 #define EMAC_REGS__ENST_OFF_TIME_Q10__RESERVED_31_17__RESET                   0
16715 #define EMAC_REGS__ENST_OFF_TIME_Q10__RESERVED_31_17__READ(src) \
16716                     (((uint32_t)(src)\
16717                     & 0xfffe0000U) >> 17)
16718 #define EMAC_REGS__ENST_OFF_TIME_Q10__TYPE                             uint32_t
16719 #define EMAC_REGS__ENST_OFF_TIME_Q10__READ                          0xffffffffU
16720 #define EMAC_REGS__ENST_OFF_TIME_Q10__WRITE                         0xffffffffU
16721 
16722 #endif /* __EMAC_REGS__ENST_OFF_TIME_Q10_MACRO__ */
16723 
16724 
16725 /* macros for enst_off_time_q10 */
16726 #define INST_ENST_OFF_TIME_Q10__NUM                                           1
16727 
16728 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_off_time_q11 */
16729 #ifndef __EMAC_REGS__ENST_OFF_TIME_Q11_MACRO__
16730 #define __EMAC_REGS__ENST_OFF_TIME_Q11_MACRO__
16731 
16732 /* macros for field off_time */
16733 #define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__SHIFT                         0
16734 #define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__WIDTH                        17
16735 #define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__MASK                0x0001ffffU
16736 #define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__RESET                         0
16737 #define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__READ(src) \
16738                     ((uint32_t)(src)\
16739                     & 0x0001ffffU)
16740 #define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__WRITE(src) \
16741                     ((uint32_t)(src)\
16742                     & 0x0001ffffU)
16743 #define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__MODIFY(dst, src) \
16744                     (dst) = ((dst) &\
16745                     ~0x0001ffffU) | ((uint32_t)(src) &\
16746                     0x0001ffffU)
16747 #define EMAC_REGS__ENST_OFF_TIME_Q11__OFF_TIME__VERIFY(src) \
16748                     (!(((uint32_t)(src)\
16749                     & ~0x0001ffffU)))
16750 
16751 /* macros for field reserved_31_17 */
16752 #define EMAC_REGS__ENST_OFF_TIME_Q11__RESERVED_31_17__SHIFT                  17
16753 #define EMAC_REGS__ENST_OFF_TIME_Q11__RESERVED_31_17__WIDTH                  15
16754 #define EMAC_REGS__ENST_OFF_TIME_Q11__RESERVED_31_17__MASK          0xfffe0000U
16755 #define EMAC_REGS__ENST_OFF_TIME_Q11__RESERVED_31_17__RESET                   0
16756 #define EMAC_REGS__ENST_OFF_TIME_Q11__RESERVED_31_17__READ(src) \
16757                     (((uint32_t)(src)\
16758                     & 0xfffe0000U) >> 17)
16759 #define EMAC_REGS__ENST_OFF_TIME_Q11__TYPE                             uint32_t
16760 #define EMAC_REGS__ENST_OFF_TIME_Q11__READ                          0xffffffffU
16761 #define EMAC_REGS__ENST_OFF_TIME_Q11__WRITE                         0xffffffffU
16762 
16763 #endif /* __EMAC_REGS__ENST_OFF_TIME_Q11_MACRO__ */
16764 
16765 
16766 /* macros for enst_off_time_q11 */
16767 #define INST_ENST_OFF_TIME_Q11__NUM                                           1
16768 
16769 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_off_time_q12 */
16770 #ifndef __EMAC_REGS__ENST_OFF_TIME_Q12_MACRO__
16771 #define __EMAC_REGS__ENST_OFF_TIME_Q12_MACRO__
16772 
16773 /* macros for field off_time */
16774 #define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__SHIFT                         0
16775 #define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__WIDTH                        17
16776 #define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__MASK                0x0001ffffU
16777 #define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__RESET                         0
16778 #define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__READ(src) \
16779                     ((uint32_t)(src)\
16780                     & 0x0001ffffU)
16781 #define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__WRITE(src) \
16782                     ((uint32_t)(src)\
16783                     & 0x0001ffffU)
16784 #define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__MODIFY(dst, src) \
16785                     (dst) = ((dst) &\
16786                     ~0x0001ffffU) | ((uint32_t)(src) &\
16787                     0x0001ffffU)
16788 #define EMAC_REGS__ENST_OFF_TIME_Q12__OFF_TIME__VERIFY(src) \
16789                     (!(((uint32_t)(src)\
16790                     & ~0x0001ffffU)))
16791 
16792 /* macros for field reserved_31_17 */
16793 #define EMAC_REGS__ENST_OFF_TIME_Q12__RESERVED_31_17__SHIFT                  17
16794 #define EMAC_REGS__ENST_OFF_TIME_Q12__RESERVED_31_17__WIDTH                  15
16795 #define EMAC_REGS__ENST_OFF_TIME_Q12__RESERVED_31_17__MASK          0xfffe0000U
16796 #define EMAC_REGS__ENST_OFF_TIME_Q12__RESERVED_31_17__RESET                   0
16797 #define EMAC_REGS__ENST_OFF_TIME_Q12__RESERVED_31_17__READ(src) \
16798                     (((uint32_t)(src)\
16799                     & 0xfffe0000U) >> 17)
16800 #define EMAC_REGS__ENST_OFF_TIME_Q12__TYPE                             uint32_t
16801 #define EMAC_REGS__ENST_OFF_TIME_Q12__READ                          0xffffffffU
16802 #define EMAC_REGS__ENST_OFF_TIME_Q12__WRITE                         0xffffffffU
16803 
16804 #endif /* __EMAC_REGS__ENST_OFF_TIME_Q12_MACRO__ */
16805 
16806 
16807 /* macros for enst_off_time_q12 */
16808 #define INST_ENST_OFF_TIME_Q12__NUM                                           1
16809 
16810 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_off_time_q13 */
16811 #ifndef __EMAC_REGS__ENST_OFF_TIME_Q13_MACRO__
16812 #define __EMAC_REGS__ENST_OFF_TIME_Q13_MACRO__
16813 
16814 /* macros for field off_time */
16815 #define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__SHIFT                         0
16816 #define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__WIDTH                        17
16817 #define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__MASK                0x0001ffffU
16818 #define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__RESET                         0
16819 #define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__READ(src) \
16820                     ((uint32_t)(src)\
16821                     & 0x0001ffffU)
16822 #define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__WRITE(src) \
16823                     ((uint32_t)(src)\
16824                     & 0x0001ffffU)
16825 #define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__MODIFY(dst, src) \
16826                     (dst) = ((dst) &\
16827                     ~0x0001ffffU) | ((uint32_t)(src) &\
16828                     0x0001ffffU)
16829 #define EMAC_REGS__ENST_OFF_TIME_Q13__OFF_TIME__VERIFY(src) \
16830                     (!(((uint32_t)(src)\
16831                     & ~0x0001ffffU)))
16832 
16833 /* macros for field reserved_31_17 */
16834 #define EMAC_REGS__ENST_OFF_TIME_Q13__RESERVED_31_17__SHIFT                  17
16835 #define EMAC_REGS__ENST_OFF_TIME_Q13__RESERVED_31_17__WIDTH                  15
16836 #define EMAC_REGS__ENST_OFF_TIME_Q13__RESERVED_31_17__MASK          0xfffe0000U
16837 #define EMAC_REGS__ENST_OFF_TIME_Q13__RESERVED_31_17__RESET                   0
16838 #define EMAC_REGS__ENST_OFF_TIME_Q13__RESERVED_31_17__READ(src) \
16839                     (((uint32_t)(src)\
16840                     & 0xfffe0000U) >> 17)
16841 #define EMAC_REGS__ENST_OFF_TIME_Q13__TYPE                             uint32_t
16842 #define EMAC_REGS__ENST_OFF_TIME_Q13__READ                          0xffffffffU
16843 #define EMAC_REGS__ENST_OFF_TIME_Q13__WRITE                         0xffffffffU
16844 
16845 #endif /* __EMAC_REGS__ENST_OFF_TIME_Q13_MACRO__ */
16846 
16847 
16848 /* macros for enst_off_time_q13 */
16849 #define INST_ENST_OFF_TIME_Q13__NUM                                           1
16850 
16851 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_off_time_q14 */
16852 #ifndef __EMAC_REGS__ENST_OFF_TIME_Q14_MACRO__
16853 #define __EMAC_REGS__ENST_OFF_TIME_Q14_MACRO__
16854 
16855 /* macros for field off_time */
16856 #define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__SHIFT                         0
16857 #define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__WIDTH                        17
16858 #define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__MASK                0x0001ffffU
16859 #define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__RESET                         0
16860 #define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__READ(src) \
16861                     ((uint32_t)(src)\
16862                     & 0x0001ffffU)
16863 #define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__WRITE(src) \
16864                     ((uint32_t)(src)\
16865                     & 0x0001ffffU)
16866 #define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__MODIFY(dst, src) \
16867                     (dst) = ((dst) &\
16868                     ~0x0001ffffU) | ((uint32_t)(src) &\
16869                     0x0001ffffU)
16870 #define EMAC_REGS__ENST_OFF_TIME_Q14__OFF_TIME__VERIFY(src) \
16871                     (!(((uint32_t)(src)\
16872                     & ~0x0001ffffU)))
16873 
16874 /* macros for field reserved_31_17 */
16875 #define EMAC_REGS__ENST_OFF_TIME_Q14__RESERVED_31_17__SHIFT                  17
16876 #define EMAC_REGS__ENST_OFF_TIME_Q14__RESERVED_31_17__WIDTH                  15
16877 #define EMAC_REGS__ENST_OFF_TIME_Q14__RESERVED_31_17__MASK          0xfffe0000U
16878 #define EMAC_REGS__ENST_OFF_TIME_Q14__RESERVED_31_17__RESET                   0
16879 #define EMAC_REGS__ENST_OFF_TIME_Q14__RESERVED_31_17__READ(src) \
16880                     (((uint32_t)(src)\
16881                     & 0xfffe0000U) >> 17)
16882 #define EMAC_REGS__ENST_OFF_TIME_Q14__TYPE                             uint32_t
16883 #define EMAC_REGS__ENST_OFF_TIME_Q14__READ                          0xffffffffU
16884 #define EMAC_REGS__ENST_OFF_TIME_Q14__WRITE                         0xffffffffU
16885 
16886 #endif /* __EMAC_REGS__ENST_OFF_TIME_Q14_MACRO__ */
16887 
16888 
16889 /* macros for enst_off_time_q14 */
16890 #define INST_ENST_OFF_TIME_Q14__NUM                                           1
16891 
16892 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_off_time_q15 */
16893 #ifndef __EMAC_REGS__ENST_OFF_TIME_Q15_MACRO__
16894 #define __EMAC_REGS__ENST_OFF_TIME_Q15_MACRO__
16895 
16896 /* macros for field off_time */
16897 #define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__SHIFT                         0
16898 #define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__WIDTH                        17
16899 #define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__MASK                0x0001ffffU
16900 #define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__RESET                         0
16901 #define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__READ(src) \
16902                     ((uint32_t)(src)\
16903                     & 0x0001ffffU)
16904 #define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__WRITE(src) \
16905                     ((uint32_t)(src)\
16906                     & 0x0001ffffU)
16907 #define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__MODIFY(dst, src) \
16908                     (dst) = ((dst) &\
16909                     ~0x0001ffffU) | ((uint32_t)(src) &\
16910                     0x0001ffffU)
16911 #define EMAC_REGS__ENST_OFF_TIME_Q15__OFF_TIME__VERIFY(src) \
16912                     (!(((uint32_t)(src)\
16913                     & ~0x0001ffffU)))
16914 
16915 /* macros for field reserved_31_17 */
16916 #define EMAC_REGS__ENST_OFF_TIME_Q15__RESERVED_31_17__SHIFT                  17
16917 #define EMAC_REGS__ENST_OFF_TIME_Q15__RESERVED_31_17__WIDTH                  15
16918 #define EMAC_REGS__ENST_OFF_TIME_Q15__RESERVED_31_17__MASK          0xfffe0000U
16919 #define EMAC_REGS__ENST_OFF_TIME_Q15__RESERVED_31_17__RESET                   0
16920 #define EMAC_REGS__ENST_OFF_TIME_Q15__RESERVED_31_17__READ(src) \
16921                     (((uint32_t)(src)\
16922                     & 0xfffe0000U) >> 17)
16923 #define EMAC_REGS__ENST_OFF_TIME_Q15__TYPE                             uint32_t
16924 #define EMAC_REGS__ENST_OFF_TIME_Q15__READ                          0xffffffffU
16925 #define EMAC_REGS__ENST_OFF_TIME_Q15__WRITE                         0xffffffffU
16926 
16927 #endif /* __EMAC_REGS__ENST_OFF_TIME_Q15_MACRO__ */
16928 
16929 
16930 /* macros for enst_off_time_q15 */
16931 #define INST_ENST_OFF_TIME_Q15__NUM                                           1
16932 
16933 /* macros for BlueprintGlobalNameSpace::emac_regs::enst_control */
16934 #ifndef __EMAC_REGS__ENST_CONTROL_MACRO__
16935 #define __EMAC_REGS__ENST_CONTROL_MACRO__
16936 
16937 /* macros for field enst_enable_q8 */
16938 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__SHIFT                        0
16939 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__WIDTH                        1
16940 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__MASK               0x00000001U
16941 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__RESET                        0
16942 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__READ(src) \
16943                     ((uint32_t)(src)\
16944                     & 0x00000001U)
16945 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__WRITE(src) \
16946                     ((uint32_t)(src)\
16947                     & 0x00000001U)
16948 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__MODIFY(dst, src) \
16949                     (dst) = ((dst) &\
16950                     ~0x00000001U) | ((uint32_t)(src) &\
16951                     0x00000001U)
16952 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__VERIFY(src) \
16953                     (!(((uint32_t)(src)\
16954                     & ~0x00000001U)))
16955 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__SET(dst) \
16956                     (dst) = ((dst) &\
16957                     ~0x00000001U) | (uint32_t)(1)
16958 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q8__CLR(dst) \
16959                     (dst) = ((dst) &\
16960                     ~0x00000001U) | (uint32_t)(0)
16961 
16962 /* macros for field enst_enable_q9 */
16963 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__SHIFT                        1
16964 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__WIDTH                        1
16965 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__MASK               0x00000002U
16966 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__RESET                        0
16967 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__READ(src) \
16968                     (((uint32_t)(src)\
16969                     & 0x00000002U) >> 1)
16970 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__WRITE(src) \
16971                     (((uint32_t)(src)\
16972                     << 1) & 0x00000002U)
16973 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__MODIFY(dst, src) \
16974                     (dst) = ((dst) &\
16975                     ~0x00000002U) | (((uint32_t)(src) <<\
16976                     1) & 0x00000002U)
16977 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__VERIFY(src) \
16978                     (!((((uint32_t)(src)\
16979                     << 1) & ~0x00000002U)))
16980 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__SET(dst) \
16981                     (dst) = ((dst) &\
16982                     ~0x00000002U) | ((uint32_t)(1) << 1)
16983 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q9__CLR(dst) \
16984                     (dst) = ((dst) &\
16985                     ~0x00000002U) | ((uint32_t)(0) << 1)
16986 
16987 /* macros for field enst_enable_q10 */
16988 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__SHIFT                       2
16989 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__WIDTH                       1
16990 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__MASK              0x00000004U
16991 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__RESET                       0
16992 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__READ(src) \
16993                     (((uint32_t)(src)\
16994                     & 0x00000004U) >> 2)
16995 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__WRITE(src) \
16996                     (((uint32_t)(src)\
16997                     << 2) & 0x00000004U)
16998 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__MODIFY(dst, src) \
16999                     (dst) = ((dst) &\
17000                     ~0x00000004U) | (((uint32_t)(src) <<\
17001                     2) & 0x00000004U)
17002 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__VERIFY(src) \
17003                     (!((((uint32_t)(src)\
17004                     << 2) & ~0x00000004U)))
17005 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__SET(dst) \
17006                     (dst) = ((dst) &\
17007                     ~0x00000004U) | ((uint32_t)(1) << 2)
17008 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q10__CLR(dst) \
17009                     (dst) = ((dst) &\
17010                     ~0x00000004U) | ((uint32_t)(0) << 2)
17011 
17012 /* macros for field enst_enable_q11 */
17013 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__SHIFT                       3
17014 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__WIDTH                       1
17015 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__MASK              0x00000008U
17016 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__RESET                       0
17017 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__READ(src) \
17018                     (((uint32_t)(src)\
17019                     & 0x00000008U) >> 3)
17020 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__WRITE(src) \
17021                     (((uint32_t)(src)\
17022                     << 3) & 0x00000008U)
17023 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__MODIFY(dst, src) \
17024                     (dst) = ((dst) &\
17025                     ~0x00000008U) | (((uint32_t)(src) <<\
17026                     3) & 0x00000008U)
17027 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__VERIFY(src) \
17028                     (!((((uint32_t)(src)\
17029                     << 3) & ~0x00000008U)))
17030 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__SET(dst) \
17031                     (dst) = ((dst) &\
17032                     ~0x00000008U) | ((uint32_t)(1) << 3)
17033 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q11__CLR(dst) \
17034                     (dst) = ((dst) &\
17035                     ~0x00000008U) | ((uint32_t)(0) << 3)
17036 
17037 /* macros for field enst_enable_q12 */
17038 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__SHIFT                       4
17039 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__WIDTH                       1
17040 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__MASK              0x00000010U
17041 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__RESET                       0
17042 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__READ(src) \
17043                     (((uint32_t)(src)\
17044                     & 0x00000010U) >> 4)
17045 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__WRITE(src) \
17046                     (((uint32_t)(src)\
17047                     << 4) & 0x00000010U)
17048 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__MODIFY(dst, src) \
17049                     (dst) = ((dst) &\
17050                     ~0x00000010U) | (((uint32_t)(src) <<\
17051                     4) & 0x00000010U)
17052 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__VERIFY(src) \
17053                     (!((((uint32_t)(src)\
17054                     << 4) & ~0x00000010U)))
17055 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__SET(dst) \
17056                     (dst) = ((dst) &\
17057                     ~0x00000010U) | ((uint32_t)(1) << 4)
17058 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q12__CLR(dst) \
17059                     (dst) = ((dst) &\
17060                     ~0x00000010U) | ((uint32_t)(0) << 4)
17061 
17062 /* macros for field enst_enable_q13 */
17063 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__SHIFT                       5
17064 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__WIDTH                       1
17065 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__MASK              0x00000020U
17066 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__RESET                       0
17067 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__READ(src) \
17068                     (((uint32_t)(src)\
17069                     & 0x00000020U) >> 5)
17070 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__WRITE(src) \
17071                     (((uint32_t)(src)\
17072                     << 5) & 0x00000020U)
17073 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__MODIFY(dst, src) \
17074                     (dst) = ((dst) &\
17075                     ~0x00000020U) | (((uint32_t)(src) <<\
17076                     5) & 0x00000020U)
17077 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__VERIFY(src) \
17078                     (!((((uint32_t)(src)\
17079                     << 5) & ~0x00000020U)))
17080 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__SET(dst) \
17081                     (dst) = ((dst) &\
17082                     ~0x00000020U) | ((uint32_t)(1) << 5)
17083 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q13__CLR(dst) \
17084                     (dst) = ((dst) &\
17085                     ~0x00000020U) | ((uint32_t)(0) << 5)
17086 
17087 /* macros for field enst_enable_q14 */
17088 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__SHIFT                       6
17089 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__WIDTH                       1
17090 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__MASK              0x00000040U
17091 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__RESET                       0
17092 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__READ(src) \
17093                     (((uint32_t)(src)\
17094                     & 0x00000040U) >> 6)
17095 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__WRITE(src) \
17096                     (((uint32_t)(src)\
17097                     << 6) & 0x00000040U)
17098 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__MODIFY(dst, src) \
17099                     (dst) = ((dst) &\
17100                     ~0x00000040U) | (((uint32_t)(src) <<\
17101                     6) & 0x00000040U)
17102 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__VERIFY(src) \
17103                     (!((((uint32_t)(src)\
17104                     << 6) & ~0x00000040U)))
17105 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__SET(dst) \
17106                     (dst) = ((dst) &\
17107                     ~0x00000040U) | ((uint32_t)(1) << 6)
17108 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q14__CLR(dst) \
17109                     (dst) = ((dst) &\
17110                     ~0x00000040U) | ((uint32_t)(0) << 6)
17111 
17112 /* macros for field enst_enable_q15 */
17113 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__SHIFT                       7
17114 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__WIDTH                       1
17115 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__MASK              0x00000080U
17116 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__RESET                       0
17117 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__READ(src) \
17118                     (((uint32_t)(src)\
17119                     & 0x00000080U) >> 7)
17120 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__WRITE(src) \
17121                     (((uint32_t)(src)\
17122                     << 7) & 0x00000080U)
17123 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__MODIFY(dst, src) \
17124                     (dst) = ((dst) &\
17125                     ~0x00000080U) | (((uint32_t)(src) <<\
17126                     7) & 0x00000080U)
17127 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__VERIFY(src) \
17128                     (!((((uint32_t)(src)\
17129                     << 7) & ~0x00000080U)))
17130 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__SET(dst) \
17131                     (dst) = ((dst) &\
17132                     ~0x00000080U) | ((uint32_t)(1) << 7)
17133 #define EMAC_REGS__ENST_CONTROL__ENST_ENABLE_Q15__CLR(dst) \
17134                     (dst) = ((dst) &\
17135                     ~0x00000080U) | ((uint32_t)(0) << 7)
17136 
17137 /* macros for field reserved_15_8 */
17138 #define EMAC_REGS__ENST_CONTROL__RESERVED_15_8__SHIFT                         8
17139 #define EMAC_REGS__ENST_CONTROL__RESERVED_15_8__WIDTH                         8
17140 #define EMAC_REGS__ENST_CONTROL__RESERVED_15_8__MASK                0x0000ff00U
17141 #define EMAC_REGS__ENST_CONTROL__RESERVED_15_8__RESET                         0
17142 #define EMAC_REGS__ENST_CONTROL__RESERVED_15_8__READ(src) \
17143                     (((uint32_t)(src)\
17144                     & 0x0000ff00U) >> 8)
17145 
17146 /* macros for field enst_disable_q8 */
17147 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__SHIFT                      16
17148 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__WIDTH                       1
17149 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__MASK              0x00010000U
17150 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__RESET                       0
17151 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__WRITE(src) \
17152                     (((uint32_t)(src)\
17153                     << 16) & 0x00010000U)
17154 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__MODIFY(dst, src) \
17155                     (dst) = ((dst) &\
17156                     ~0x00010000U) | (((uint32_t)(src) <<\
17157                     16) & 0x00010000U)
17158 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__VERIFY(src) \
17159                     (!((((uint32_t)(src)\
17160                     << 16) & ~0x00010000U)))
17161 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__SET(dst) \
17162                     (dst) = ((dst) &\
17163                     ~0x00010000U) | ((uint32_t)(1) << 16)
17164 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q8__CLR(dst) \
17165                     (dst) = ((dst) &\
17166                     ~0x00010000U) | ((uint32_t)(0) << 16)
17167 
17168 /* macros for field enst_disable_q9 */
17169 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__SHIFT                      17
17170 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__WIDTH                       1
17171 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__MASK              0x00020000U
17172 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__RESET                       0
17173 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__WRITE(src) \
17174                     (((uint32_t)(src)\
17175                     << 17) & 0x00020000U)
17176 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__MODIFY(dst, src) \
17177                     (dst) = ((dst) &\
17178                     ~0x00020000U) | (((uint32_t)(src) <<\
17179                     17) & 0x00020000U)
17180 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__VERIFY(src) \
17181                     (!((((uint32_t)(src)\
17182                     << 17) & ~0x00020000U)))
17183 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__SET(dst) \
17184                     (dst) = ((dst) &\
17185                     ~0x00020000U) | ((uint32_t)(1) << 17)
17186 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q9__CLR(dst) \
17187                     (dst) = ((dst) &\
17188                     ~0x00020000U) | ((uint32_t)(0) << 17)
17189 
17190 /* macros for field enst_disable_q10 */
17191 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__SHIFT                     18
17192 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__WIDTH                      1
17193 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__MASK             0x00040000U
17194 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__RESET                      0
17195 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__WRITE(src) \
17196                     (((uint32_t)(src)\
17197                     << 18) & 0x00040000U)
17198 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__MODIFY(dst, src) \
17199                     (dst) = ((dst) &\
17200                     ~0x00040000U) | (((uint32_t)(src) <<\
17201                     18) & 0x00040000U)
17202 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__VERIFY(src) \
17203                     (!((((uint32_t)(src)\
17204                     << 18) & ~0x00040000U)))
17205 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__SET(dst) \
17206                     (dst) = ((dst) &\
17207                     ~0x00040000U) | ((uint32_t)(1) << 18)
17208 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q10__CLR(dst) \
17209                     (dst) = ((dst) &\
17210                     ~0x00040000U) | ((uint32_t)(0) << 18)
17211 
17212 /* macros for field enst_disable_q11 */
17213 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__SHIFT                     19
17214 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__WIDTH                      1
17215 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__MASK             0x00080000U
17216 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__RESET                      0
17217 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__WRITE(src) \
17218                     (((uint32_t)(src)\
17219                     << 19) & 0x00080000U)
17220 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__MODIFY(dst, src) \
17221                     (dst) = ((dst) &\
17222                     ~0x00080000U) | (((uint32_t)(src) <<\
17223                     19) & 0x00080000U)
17224 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__VERIFY(src) \
17225                     (!((((uint32_t)(src)\
17226                     << 19) & ~0x00080000U)))
17227 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__SET(dst) \
17228                     (dst) = ((dst) &\
17229                     ~0x00080000U) | ((uint32_t)(1) << 19)
17230 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q11__CLR(dst) \
17231                     (dst) = ((dst) &\
17232                     ~0x00080000U) | ((uint32_t)(0) << 19)
17233 
17234 /* macros for field enst_disable_q12 */
17235 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__SHIFT                     20
17236 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__WIDTH                      1
17237 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__MASK             0x00100000U
17238 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__RESET                      0
17239 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__WRITE(src) \
17240                     (((uint32_t)(src)\
17241                     << 20) & 0x00100000U)
17242 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__MODIFY(dst, src) \
17243                     (dst) = ((dst) &\
17244                     ~0x00100000U) | (((uint32_t)(src) <<\
17245                     20) & 0x00100000U)
17246 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__VERIFY(src) \
17247                     (!((((uint32_t)(src)\
17248                     << 20) & ~0x00100000U)))
17249 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__SET(dst) \
17250                     (dst) = ((dst) &\
17251                     ~0x00100000U) | ((uint32_t)(1) << 20)
17252 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q12__CLR(dst) \
17253                     (dst) = ((dst) &\
17254                     ~0x00100000U) | ((uint32_t)(0) << 20)
17255 
17256 /* macros for field enst_disable_q13 */
17257 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__SHIFT                     21
17258 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__WIDTH                      1
17259 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__MASK             0x00200000U
17260 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__RESET                      0
17261 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__WRITE(src) \
17262                     (((uint32_t)(src)\
17263                     << 21) & 0x00200000U)
17264 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__MODIFY(dst, src) \
17265                     (dst) = ((dst) &\
17266                     ~0x00200000U) | (((uint32_t)(src) <<\
17267                     21) & 0x00200000U)
17268 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__VERIFY(src) \
17269                     (!((((uint32_t)(src)\
17270                     << 21) & ~0x00200000U)))
17271 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__SET(dst) \
17272                     (dst) = ((dst) &\
17273                     ~0x00200000U) | ((uint32_t)(1) << 21)
17274 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q13__CLR(dst) \
17275                     (dst) = ((dst) &\
17276                     ~0x00200000U) | ((uint32_t)(0) << 21)
17277 
17278 /* macros for field enst_disable_q14 */
17279 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__SHIFT                     22
17280 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__WIDTH                      1
17281 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__MASK             0x00400000U
17282 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__RESET                      0
17283 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__WRITE(src) \
17284                     (((uint32_t)(src)\
17285                     << 22) & 0x00400000U)
17286 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__MODIFY(dst, src) \
17287                     (dst) = ((dst) &\
17288                     ~0x00400000U) | (((uint32_t)(src) <<\
17289                     22) & 0x00400000U)
17290 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__VERIFY(src) \
17291                     (!((((uint32_t)(src)\
17292                     << 22) & ~0x00400000U)))
17293 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__SET(dst) \
17294                     (dst) = ((dst) &\
17295                     ~0x00400000U) | ((uint32_t)(1) << 22)
17296 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q14__CLR(dst) \
17297                     (dst) = ((dst) &\
17298                     ~0x00400000U) | ((uint32_t)(0) << 22)
17299 
17300 /* macros for field enst_disable_q15 */
17301 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__SHIFT                     23
17302 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__WIDTH                      1
17303 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__MASK             0x00800000U
17304 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__RESET                      0
17305 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__WRITE(src) \
17306                     (((uint32_t)(src)\
17307                     << 23) & 0x00800000U)
17308 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__MODIFY(dst, src) \
17309                     (dst) = ((dst) &\
17310                     ~0x00800000U) | (((uint32_t)(src) <<\
17311                     23) & 0x00800000U)
17312 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__VERIFY(src) \
17313                     (!((((uint32_t)(src)\
17314                     << 23) & ~0x00800000U)))
17315 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__SET(dst) \
17316                     (dst) = ((dst) &\
17317                     ~0x00800000U) | ((uint32_t)(1) << 23)
17318 #define EMAC_REGS__ENST_CONTROL__ENST_DISABLE_Q15__CLR(dst) \
17319                     (dst) = ((dst) &\
17320                     ~0x00800000U) | ((uint32_t)(0) << 23)
17321 
17322 /* macros for field reserved_31_24 */
17323 #define EMAC_REGS__ENST_CONTROL__RESERVED_31_24__SHIFT                       24
17324 #define EMAC_REGS__ENST_CONTROL__RESERVED_31_24__WIDTH                        8
17325 #define EMAC_REGS__ENST_CONTROL__RESERVED_31_24__MASK               0xff000000U
17326 #define EMAC_REGS__ENST_CONTROL__RESERVED_31_24__RESET                        0
17327 #define EMAC_REGS__ENST_CONTROL__RESERVED_31_24__READ(src) \
17328                     (((uint32_t)(src)\
17329                     & 0xff000000U) >> 24)
17330 #define EMAC_REGS__ENST_CONTROL__TYPE                                  uint32_t
17331 #define EMAC_REGS__ENST_CONTROL__READ                               0xff00ffffU
17332 #define EMAC_REGS__ENST_CONTROL__WRITE                              0xff00ffffU
17333 
17334 #endif /* __EMAC_REGS__ENST_CONTROL_MACRO__ */
17335 
17336 
17337 /* macros for enst_control */
17338 #define INST_ENST_CONTROL__NUM                                                1
17339 
17340 #endif /* __REG_EMAC_REGS_MACRO_H__ */
17341