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Searched refs:HSIOM_AMUX_SPLIT_CTL (Results 1 – 5 of 5) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/source/
Dcy_lpcomp.c666 …HSIOM_AMUX_SPLIT_CTL(3U) = _CLR_SET_FLD32U(HSIOM_AMUX_SPLIT_CTL(3U), CY_HSIOM_AMUX_SPLIT_CTL_SWITC… in Cy_LPComp_SetInputs()
672 …HSIOM_AMUX_SPLIT_CTL(3U) = _CLR_SET_FLD32U(HSIOM_AMUX_SPLIT_CTL(3U), CY_HSIOM_AMUX_SPLIT_CTL_SWITC… in Cy_LPComp_SetInputs()
687 …HSIOM_AMUX_SPLIT_CTL(3U) = _CLR_SET_FLD32U(HSIOM_AMUX_SPLIT_CTL(3U), CY_HSIOM_AMUX_SPLIT_CTL_SWITC… in Cy_LPComp_SetInputs()
693 …HSIOM_AMUX_SPLIT_CTL(3U) = _CLR_SET_FLD32U(HSIOM_AMUX_SPLIT_CTL(3U), CY_HSIOM_AMUX_SPLIT_CTL_SWITC… in Cy_LPComp_SetInputs()
Dcy_gpio.c711 tmpReg = HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXB_SPLITTER_MASK; in Cy_GPIO_SetAmuxSplit()
712 … HSIOM_AMUX_SPLIT_CTL(switchCtrl) = tmpReg | ((uint32_t) amuxConnect & GPIO_AMUXA_SPLITTER_MASK); in Cy_GPIO_SetAmuxSplit()
716 tmpReg = HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXA_SPLITTER_MASK; in Cy_GPIO_SetAmuxSplit()
717 HSIOM_AMUX_SPLIT_CTL(switchCtrl) = in Cy_GPIO_SetAmuxSplit()
761 retVal = HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXA_SPLITTER_MASK; in Cy_GPIO_GetAmuxSplit()
765 retVal = ((uint32_t) ((HSIOM_AMUX_SPLIT_CTL(switchCtrl) & GPIO_AMUXB_SPLITTER_MASK) in Cy_GPIO_GetAmuxSplit()
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h921 #define HSIOM_AMUX_SPLIT_CTL(switchCtrl) (((HSIOM_V1_Type *) CY_HSIOM_BASE)->AMUX_SPLIT_CTL[swit… macro
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h1561 #define HSIOM_AMUX_SPLIT_CTL(switchCtrl) (((HSIOM_Type *)HSIOM_BASE)->AMUX_SPLIT_CTL[switchCtrl]) macro
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h467 #define HSIOM_AMUX_SPLIT_CTL(switchCtrl) (((HSIOM_Type *)HSIOM_BASE)->AMUX_SPLIT_CTL[switchCtrl]) macro