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Searched refs:ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE3_Pos (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_eth.h1772 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE3_Pos 3UL macro
Dcyip_eth_v2.h1772 #define ETH_DESIGNCFG_DEBUG6_DMA_PRIORITY_QUEUE3_Pos 3UL macro