1 /***************************************************************************//** 2 * \file cyip_dmac.h 3 * 4 * \brief 5 * DMAC IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_DMAC_H_ 28 #define _CYIP_DMAC_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * DMAC 34 *******************************************************************************/ 35 36 #define DMAC_CH_SECTION_SIZE 0x00000100UL 37 #define DMAC_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief DMA controller channel (DMAC_CH) 41 */ 42 typedef struct { 43 __IOM uint32_t CTL; /*!< 0x00000000 Channel control */ 44 __IM uint32_t RESERVED[3]; 45 __IM uint32_t IDX; /*!< 0x00000010 Channel current indices */ 46 __IM uint32_t SRC; /*!< 0x00000014 Channel current source address */ 47 __IM uint32_t DST; /*!< 0x00000018 Channel current destination address */ 48 __IM uint32_t RESERVED1; 49 __IOM uint32_t CURR; /*!< 0x00000020 Channel current descriptor pointer */ 50 __IM uint32_t RESERVED2; 51 __IOM uint32_t TR_CMD; /*!< 0x00000028 Channle software trigger */ 52 __IM uint32_t RESERVED3[5]; 53 __IM uint32_t DESCR_STATUS; /*!< 0x00000040 Channel descriptor status */ 54 __IM uint32_t RESERVED4[7]; 55 __IM uint32_t DESCR_CTL; /*!< 0x00000060 Channel descriptor control */ 56 __IM uint32_t DESCR_SRC; /*!< 0x00000064 Channel descriptor source */ 57 __IM uint32_t DESCR_DST; /*!< 0x00000068 Channel descriptor destination */ 58 __IM uint32_t DESCR_X_SIZE; /*!< 0x0000006C Channel descriptor X size */ 59 __IM uint32_t DESCR_X_INCR; /*!< 0x00000070 Channel descriptor X increment */ 60 __IM uint32_t DESCR_Y_SIZE; /*!< 0x00000074 Channel descriptor Y size */ 61 __IM uint32_t DESCR_Y_INCR; /*!< 0x00000078 Channel descriptor Y increment */ 62 __IM uint32_t DESCR_NEXT; /*!< 0x0000007C Channel descriptor next pointer */ 63 __IOM uint32_t INTR; /*!< 0x00000080 Interrupt */ 64 __IOM uint32_t INTR_SET; /*!< 0x00000084 Interrupt set */ 65 __IOM uint32_t INTR_MASK; /*!< 0x00000088 Interrupt mask */ 66 __IM uint32_t INTR_MASKED; /*!< 0x0000008C Interrupt masked */ 67 __IM uint32_t RESERVED5[28]; 68 } DMAC_CH_Type; /*!< Size = 256 (0x100) */ 69 70 /** 71 * \brief DMAC (DMAC) 72 */ 73 typedef struct { 74 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 75 __IM uint32_t RESERVED; 76 __IM uint32_t ACTIVE; /*!< 0x00000008 Active channels */ 77 __IM uint32_t RESERVED1[1021]; 78 DMAC_CH_Type CH[8]; /*!< 0x00001000 DMA controller channel */ 79 } DMAC_Type; /*!< Size = 6144 (0x1800) */ 80 81 82 /* DMAC_CH.CTL */ 83 #define DMAC_CH_CTL_P_Pos 0UL 84 #define DMAC_CH_CTL_P_Msk 0x1UL 85 #define DMAC_CH_CTL_NS_Pos 1UL 86 #define DMAC_CH_CTL_NS_Msk 0x2UL 87 #define DMAC_CH_CTL_B_Pos 2UL 88 #define DMAC_CH_CTL_B_Msk 0x4UL 89 #define DMAC_CH_CTL_PC_Pos 4UL 90 #define DMAC_CH_CTL_PC_Msk 0xF0UL 91 #define DMAC_CH_CTL_PRIO_Pos 8UL 92 #define DMAC_CH_CTL_PRIO_Msk 0x300UL 93 #define DMAC_CH_CTL_ENABLED_Pos 31UL 94 #define DMAC_CH_CTL_ENABLED_Msk 0x80000000UL 95 /* DMAC_CH.IDX */ 96 #define DMAC_CH_IDX_X_Pos 0UL 97 #define DMAC_CH_IDX_X_Msk 0xFFFFUL 98 #define DMAC_CH_IDX_Y_Pos 16UL 99 #define DMAC_CH_IDX_Y_Msk 0xFFFF0000UL 100 /* DMAC_CH.SRC */ 101 #define DMAC_CH_SRC_ADDR_Pos 0UL 102 #define DMAC_CH_SRC_ADDR_Msk 0xFFFFFFFFUL 103 /* DMAC_CH.DST */ 104 #define DMAC_CH_DST_ADDR_Pos 0UL 105 #define DMAC_CH_DST_ADDR_Msk 0xFFFFFFFFUL 106 /* DMAC_CH.CURR */ 107 #define DMAC_CH_CURR_PTR_Pos 2UL 108 #define DMAC_CH_CURR_PTR_Msk 0xFFFFFFFCUL 109 /* DMAC_CH.TR_CMD */ 110 #define DMAC_CH_TR_CMD_ACTIVATE_Pos 0UL 111 #define DMAC_CH_TR_CMD_ACTIVATE_Msk 0x1UL 112 /* DMAC_CH.DESCR_STATUS */ 113 #define DMAC_CH_DESCR_STATUS_VALID_Pos 31UL 114 #define DMAC_CH_DESCR_STATUS_VALID_Msk 0x80000000UL 115 /* DMAC_CH.DESCR_CTL */ 116 #define DMAC_CH_DESCR_CTL_WAIT_FOR_DEACT_Pos 0UL 117 #define DMAC_CH_DESCR_CTL_WAIT_FOR_DEACT_Msk 0x3UL 118 #define DMAC_CH_DESCR_CTL_INTR_TYPE_Pos 2UL 119 #define DMAC_CH_DESCR_CTL_INTR_TYPE_Msk 0xCUL 120 #define DMAC_CH_DESCR_CTL_TR_OUT_TYPE_Pos 4UL 121 #define DMAC_CH_DESCR_CTL_TR_OUT_TYPE_Msk 0x30UL 122 #define DMAC_CH_DESCR_CTL_TR_IN_TYPE_Pos 6UL 123 #define DMAC_CH_DESCR_CTL_TR_IN_TYPE_Msk 0xC0UL 124 #define DMAC_CH_DESCR_CTL_DATA_PREFETCH_Pos 8UL 125 #define DMAC_CH_DESCR_CTL_DATA_PREFETCH_Msk 0x100UL 126 #define DMAC_CH_DESCR_CTL_DATA_SIZE_Pos 16UL 127 #define DMAC_CH_DESCR_CTL_DATA_SIZE_Msk 0x30000UL 128 #define DMAC_CH_DESCR_CTL_CH_DISABLE_Pos 24UL 129 #define DMAC_CH_DESCR_CTL_CH_DISABLE_Msk 0x1000000UL 130 #define DMAC_CH_DESCR_CTL_SRC_TRANSFER_SIZE_Pos 26UL 131 #define DMAC_CH_DESCR_CTL_SRC_TRANSFER_SIZE_Msk 0x4000000UL 132 #define DMAC_CH_DESCR_CTL_DST_TRANSFER_SIZE_Pos 27UL 133 #define DMAC_CH_DESCR_CTL_DST_TRANSFER_SIZE_Msk 0x8000000UL 134 #define DMAC_CH_DESCR_CTL_DESCR_TYPE_Pos 28UL 135 #define DMAC_CH_DESCR_CTL_DESCR_TYPE_Msk 0x70000000UL 136 /* DMAC_CH.DESCR_SRC */ 137 #define DMAC_CH_DESCR_SRC_ADDR_Pos 0UL 138 #define DMAC_CH_DESCR_SRC_ADDR_Msk 0xFFFFFFFFUL 139 /* DMAC_CH.DESCR_DST */ 140 #define DMAC_CH_DESCR_DST_ADDR_Pos 0UL 141 #define DMAC_CH_DESCR_DST_ADDR_Msk 0xFFFFFFFFUL 142 /* DMAC_CH.DESCR_X_SIZE */ 143 #define DMAC_CH_DESCR_X_SIZE_X_COUNT_Pos 0UL 144 #define DMAC_CH_DESCR_X_SIZE_X_COUNT_Msk 0xFFFFUL 145 /* DMAC_CH.DESCR_X_INCR */ 146 #define DMAC_CH_DESCR_X_INCR_SRC_X_Pos 0UL 147 #define DMAC_CH_DESCR_X_INCR_SRC_X_Msk 0xFFFFUL 148 #define DMAC_CH_DESCR_X_INCR_DST_X_Pos 16UL 149 #define DMAC_CH_DESCR_X_INCR_DST_X_Msk 0xFFFF0000UL 150 /* DMAC_CH.DESCR_Y_SIZE */ 151 #define DMAC_CH_DESCR_Y_SIZE_Y_COUNT_Pos 0UL 152 #define DMAC_CH_DESCR_Y_SIZE_Y_COUNT_Msk 0xFFFFUL 153 /* DMAC_CH.DESCR_Y_INCR */ 154 #define DMAC_CH_DESCR_Y_INCR_SRC_Y_Pos 0UL 155 #define DMAC_CH_DESCR_Y_INCR_SRC_Y_Msk 0xFFFFUL 156 #define DMAC_CH_DESCR_Y_INCR_DST_Y_Pos 16UL 157 #define DMAC_CH_DESCR_Y_INCR_DST_Y_Msk 0xFFFF0000UL 158 /* DMAC_CH.DESCR_NEXT */ 159 #define DMAC_CH_DESCR_NEXT_PTR_Pos 2UL 160 #define DMAC_CH_DESCR_NEXT_PTR_Msk 0xFFFFFFFCUL 161 /* DMAC_CH.INTR */ 162 #define DMAC_CH_INTR_COMPLETION_Pos 0UL 163 #define DMAC_CH_INTR_COMPLETION_Msk 0x1UL 164 #define DMAC_CH_INTR_SRC_BUS_ERROR_Pos 1UL 165 #define DMAC_CH_INTR_SRC_BUS_ERROR_Msk 0x2UL 166 #define DMAC_CH_INTR_DST_BUS_ERROR_Pos 2UL 167 #define DMAC_CH_INTR_DST_BUS_ERROR_Msk 0x4UL 168 #define DMAC_CH_INTR_SRC_MISAL_Pos 3UL 169 #define DMAC_CH_INTR_SRC_MISAL_Msk 0x8UL 170 #define DMAC_CH_INTR_DST_MISAL_Pos 4UL 171 #define DMAC_CH_INTR_DST_MISAL_Msk 0x10UL 172 #define DMAC_CH_INTR_CURR_PTR_NULL_Pos 5UL 173 #define DMAC_CH_INTR_CURR_PTR_NULL_Msk 0x20UL 174 #define DMAC_CH_INTR_ACTIVE_CH_DISABLED_Pos 6UL 175 #define DMAC_CH_INTR_ACTIVE_CH_DISABLED_Msk 0x40UL 176 #define DMAC_CH_INTR_DESCR_BUS_ERROR_Pos 7UL 177 #define DMAC_CH_INTR_DESCR_BUS_ERROR_Msk 0x80UL 178 /* DMAC_CH.INTR_SET */ 179 #define DMAC_CH_INTR_SET_COMPLETION_Pos 0UL 180 #define DMAC_CH_INTR_SET_COMPLETION_Msk 0x1UL 181 #define DMAC_CH_INTR_SET_SRC_BUS_ERROR_Pos 1UL 182 #define DMAC_CH_INTR_SET_SRC_BUS_ERROR_Msk 0x2UL 183 #define DMAC_CH_INTR_SET_DST_BUS_ERROR_Pos 2UL 184 #define DMAC_CH_INTR_SET_DST_BUS_ERROR_Msk 0x4UL 185 #define DMAC_CH_INTR_SET_SRC_MISAL_Pos 3UL 186 #define DMAC_CH_INTR_SET_SRC_MISAL_Msk 0x8UL 187 #define DMAC_CH_INTR_SET_DST_MISAL_Pos 4UL 188 #define DMAC_CH_INTR_SET_DST_MISAL_Msk 0x10UL 189 #define DMAC_CH_INTR_SET_CURR_PTR_NULL_Pos 5UL 190 #define DMAC_CH_INTR_SET_CURR_PTR_NULL_Msk 0x20UL 191 #define DMAC_CH_INTR_SET_ACTIVE_CH_DISABLED_Pos 6UL 192 #define DMAC_CH_INTR_SET_ACTIVE_CH_DISABLED_Msk 0x40UL 193 #define DMAC_CH_INTR_SET_DESCR_BUS_ERROR_Pos 7UL 194 #define DMAC_CH_INTR_SET_DESCR_BUS_ERROR_Msk 0x80UL 195 /* DMAC_CH.INTR_MASK */ 196 #define DMAC_CH_INTR_MASK_COMPLETION_Pos 0UL 197 #define DMAC_CH_INTR_MASK_COMPLETION_Msk 0x1UL 198 #define DMAC_CH_INTR_MASK_SRC_BUS_ERROR_Pos 1UL 199 #define DMAC_CH_INTR_MASK_SRC_BUS_ERROR_Msk 0x2UL 200 #define DMAC_CH_INTR_MASK_DST_BUS_ERROR_Pos 2UL 201 #define DMAC_CH_INTR_MASK_DST_BUS_ERROR_Msk 0x4UL 202 #define DMAC_CH_INTR_MASK_SRC_MISAL_Pos 3UL 203 #define DMAC_CH_INTR_MASK_SRC_MISAL_Msk 0x8UL 204 #define DMAC_CH_INTR_MASK_DST_MISAL_Pos 4UL 205 #define DMAC_CH_INTR_MASK_DST_MISAL_Msk 0x10UL 206 #define DMAC_CH_INTR_MASK_CURR_PTR_NULL_Pos 5UL 207 #define DMAC_CH_INTR_MASK_CURR_PTR_NULL_Msk 0x20UL 208 #define DMAC_CH_INTR_MASK_ACTIVE_CH_DISABLED_Pos 6UL 209 #define DMAC_CH_INTR_MASK_ACTIVE_CH_DISABLED_Msk 0x40UL 210 #define DMAC_CH_INTR_MASK_DESCR_BUS_ERROR_Pos 7UL 211 #define DMAC_CH_INTR_MASK_DESCR_BUS_ERROR_Msk 0x80UL 212 /* DMAC_CH.INTR_MASKED */ 213 #define DMAC_CH_INTR_MASKED_COMPLETION_Pos 0UL 214 #define DMAC_CH_INTR_MASKED_COMPLETION_Msk 0x1UL 215 #define DMAC_CH_INTR_MASKED_SRC_BUS_ERROR_Pos 1UL 216 #define DMAC_CH_INTR_MASKED_SRC_BUS_ERROR_Msk 0x2UL 217 #define DMAC_CH_INTR_MASKED_DST_BUS_ERROR_Pos 2UL 218 #define DMAC_CH_INTR_MASKED_DST_BUS_ERROR_Msk 0x4UL 219 #define DMAC_CH_INTR_MASKED_SRC_MISAL_Pos 3UL 220 #define DMAC_CH_INTR_MASKED_SRC_MISAL_Msk 0x8UL 221 #define DMAC_CH_INTR_MASKED_DST_MISAL_Pos 4UL 222 #define DMAC_CH_INTR_MASKED_DST_MISAL_Msk 0x10UL 223 #define DMAC_CH_INTR_MASKED_CURR_PTR_NULL_Pos 5UL 224 #define DMAC_CH_INTR_MASKED_CURR_PTR_NULL_Msk 0x20UL 225 #define DMAC_CH_INTR_MASKED_ACTIVE_CH_DISABLED_Pos 6UL 226 #define DMAC_CH_INTR_MASKED_ACTIVE_CH_DISABLED_Msk 0x40UL 227 #define DMAC_CH_INTR_MASKED_DESCR_BUS_ERROR_Pos 7UL 228 #define DMAC_CH_INTR_MASKED_DESCR_BUS_ERROR_Msk 0x80UL 229 230 231 /* DMAC.CTL */ 232 #define DMAC_CTL_ENABLED_Pos 31UL 233 #define DMAC_CTL_ENABLED_Msk 0x80000000UL 234 /* DMAC.ACTIVE */ 235 #define DMAC_ACTIVE_ACTIVE_Pos 0UL 236 #define DMAC_ACTIVE_ACTIVE_Msk 0xFFUL 237 238 239 #endif /* _CYIP_DMAC_H_ */ 240 241 242 /* [] END OF FILE */ 243
