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Searched refs:Cy_SysClk_ClkHfSetDivider (Results 1 – 8 of 8) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/source/
Dcy_syspm_v4.c2095 …(void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_DIVIDE_BY_6);//i.e. 66.66MHz, Assuming 400MHz… in Cy_SysPm_SystemEnterLpToMf()
2166 (void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_DIVIDE_BY_3);//Set to 133.33MHz in Cy_SysPm_SystemEnterLpToMf()
2190 …(void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_DIVIDE_BY_6);//i.e. 66.66MHz, Assuming 400MHz… in Cy_SysPm_SystemEnterMfToLp()
2265 (void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);//Set to 400MHz in Cy_SysPm_SystemEnterMfToLp()
2289 …(void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_DIVIDE_BY_10); //i.e. 40MHz, Assuming 400MHz … in Cy_SysPm_SystemEnterUlpToMf()
2347 (void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_DIVIDE_BY_3);//TBD-Set to 120MHz in Cy_SysPm_SystemEnterUlpToMf()
2368 …(void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_DIVIDE_BY_10); //i.e. 40MHz, Assuming 400MHz … in Cy_SysPm_SystemEnterMfToUlp()
2433 (void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_DIVIDE_BY_8);//Set to 50MHz in Cy_SysPm_SystemEnterMfToUlp()
Dcy_pra_cfg.c293 if (CY_SYSCLK_SUCCESS != Cy_SysClk_ClkHfSetDivider(clkHf, divider)) in Cy_PRA_ClkHfInit()
2805 sysClkStatus = Cy_SysClk_ClkHfSetDivider(CY_PRA_CLKHF_0, devConfig->hf0Divider); in Cy_PRA_SystemConfig()
Dcy_sysclk.c693 cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, cy_en_clkhf_dividers_t divider) in Cy_SysClk_ClkHfSetDivider() function
Dcy_pra.c3146 sysClkStatus = Cy_SysClk_ClkHfSetDivider(CY_PRA_CLKHF_0, CY_SYSCLK_CLKHF_NO_DIVIDE); in Cy_PRA_ClocksReset()
Dcy_sysclk_v2.c893 cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, cy_en_clkhf_dividers_t divider) in Cy_SysClk_ClkHfSetDivider() function
/hal_infineon-3.7.0/mtb-hal-cat1/source/
Dcyhal_usb_dev.c209 Cy_SysClk_ClkHfSetDivider(clock, divider); in _cyhal_usb_dev_set_hf_divider()
260 Cy_SysClk_ClkHfSetDivider(clock, CY_SYSCLK_CLKHF_NO_DIVIDE); in _cyhal_usb_dev_init_pll()
Dcyhal_clock.c2062 cy_rslt_t rslt = (cy_rslt_t)Cy_SysClk_ClkHfSetDivider(clock->channel, new_div); in _cyhal_clock_set_divider_hf()
/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/include/
Dcy_sysclk.h5514 cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, cy_en_clkhf_dividers_t divider);