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Searched refs:CY_SYSCLK_PLL_MIN_REF_DIV (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/source/
Dcy_sysclk.c1743 #define CY_SYSCLK_PLL_MIN_REF_DIV (1UL) macro
1852 for (q = CY_SYSCLK_PLL_MIN_REF_DIV; q <= CY_SYSCLK_PLL_MAX_REF_DIV; q++) in Cy_SysClk_PllConfigure()
1921 …(config->referenceDiv < CY_SYSCLK_PLL_MIN_REF_DIV) || (CY_SYSCLK_PLL_MAX_REF_DIV < config->r… in Cy_SysClk_PllManualConfigure()
Dcy_sysclk_v2.c3206 #define CY_SYSCLK_PLL_MIN_REF_DIV (1UL) macro
3709 for (q = CY_SYSCLK_PLL_MIN_REF_DIV; q <= CY_SYSCLK_PLL_MAX_REF_DIV; q++) in Cy_SysClk_Pll200MConfigure()
3775 …(config->referenceDiv < CY_SYSCLK_PLL_MIN_REF_DIV) || (CY_SYSCLK_PLL_MAX_REF_DIV < config->r… in Cy_SysClk_Pll200MManualConfigure()