Home
last modified time | relevance | path

Searched refs:CY_SYSCLK_DPLL_LP_MAX_OUTPUT_DIV (Results 1 – 1 of 1) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/source/
Dcy_sysclk_v2.c3264 #define CY_SYSCLK_DPLL_LP_MAX_OUTPUT_DIV (16UL) macro
4006 … for (out = CY_SYSCLK_DPLL_LP_MIN_OUTPUT_DIV; out <= CY_SYSCLK_DPLL_LP_MAX_OUTPUT_DIV; out++) in Cy_SysClk_DpllLpConfigure()
4074 …llCfg->outputDiv < CY_SYSCLK_DPLL_LP_MIN_OUTPUT_DIV) || (CY_SYSCLK_DPLL_LP_MAX_OUTPUT_DIV < con… in Cy_SysClk_DpllLpManualConfigure()