Home
last modified time | relevance | path

Searched refs:CY_SYSCLK_CLKHF_NO_DIVIDE (Results 1 – 5 of 5) sorted by relevance

/hal_infineon-3.7.0/mtb-hal-cat1/source/
Dcyhal_usb_dev.c204 …for (cy_en_clkhf_dividers_t divider = CY_SYSCLK_CLKHF_NO_DIVIDE; divider <= CY_SYSCLK_CLKHF_DIVIDE… in _cyhal_usb_dev_set_hf_divider()
260 Cy_SysClk_ClkHfSetDivider(clock, CY_SYSCLK_CLKHF_NO_DIVIDE); in _cyhal_usb_dev_init_pll()
Dcyhal_clock.c1982 new_div = CY_SYSCLK_CLKHF_NO_DIVIDE; in _cyhal_clock_set_divider_hf()
2036 new_div = CY_SYSCLK_CLKHF_NO_DIVIDE; in _cyhal_clock_set_divider_hf()
/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/include/
Dcy_sysclk.h5239 CY_SYSCLK_CLKHF_NO_DIVIDE = 0U, /**< don't divide clkHf */ enumerator
5260 CY_SYSCLK_CLKHF_NO_DIVIDE = 0U, /**< don't divide clkHf */ enumerator
/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/source/
Dcy_syspm_v4.c2265 (void) Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);//Set to 400MHz in Cy_SysPm_SystemEnterMfToLp()
Dcy_pra.c3146 sysClkStatus = Cy_SysClk_ClkHfSetDivider(CY_PRA_CLKHF_0, CY_SYSCLK_CLKHF_NO_DIVIDE); in Cy_PRA_ClocksReset()