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Searched refs:CY_SCB_IS_INTR_VALID (Results 1 – 5 of 5) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/include/
Dcy_scb_common.h822 #define CY_SCB_IS_INTR_VALID(intr, mask) ( 0UL == ((intr) & ((uint32_t) ~(mask))) ) macro
1202 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK)); in Cy_SCB_SetRxInterruptMask()
1277 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK)); in Cy_SCB_ClearRxInterrupt()
1300 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK)); in Cy_SCB_SetRxInterrupt()
1346 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK)); in Cy_SCB_SetTxInterruptMask()
1423 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK)); in Cy_SCB_ClearTxInterrupt()
1446 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK)); in Cy_SCB_SetTxInterrupt()
1492 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK)); in Cy_SCB_SetMasterInterruptMask()
1560 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK)); in Cy_SCB_ClearMasterInterrupt()
1583 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK)); in Cy_SCB_SetMasterInterrupt()
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Dcy_scb_spi.h1096 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_SPI_RX_INTR_MASK)); in Cy_SCB_SPI_ClearRxFifoStatus()
1186 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_SPI_TX_INTR_MASK)); in Cy_SCB_SPI_ClearTxFifoStatus()
1305 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_MASTER_INTR_SPI_DONE)); in Cy_SCB_SPI_ClearSlaveMasterStatus()
1311 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_SLAVE_INTR_SPI_BUS_ERROR)); in Cy_SCB_SPI_ClearSlaveMasterStatus()
Dcy_scb_uart.h1387 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_UART_RX_INTR_MASK)); in Cy_SCB_UART_ClearRxFifoStatus()
1580 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_UART_TX_INTR_MASK)); in Cy_SCB_UART_ClearTxFifoStatus()
/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/source/
Dcy_scb_spi.c88 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->rxFifoIntEnableMask, CY_SCB_SPI_RX_INTR_MASK)); in Cy_SCB_SPI_Init()
89 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->txFifoIntEnableMask, CY_SCB_SPI_TX_INTR_MASK)); in Cy_SCB_SPI_Init()
90 …CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->masterSlaveIntEnableMask, CY_SCB_SPI_MASTER_SLAVE_INTR_M… in Cy_SCB_SPI_Init()
Dcy_scb_uart.c286 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->rxFifoIntEnableMask, CY_SCB_UART_RX_INTR_MASK)); in Cy_SCB_UART_Init()
287 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->txFifoIntEnableMask, CY_SCB_UART_TX_INTR_MASK)); in Cy_SCB_UART_Init()