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Searched refs:CY_PRA_INDX_SRSS_CLK_MF_SELECT (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/include/
Dcy_pra.h395 #define CY_PRA_INDX_SRSS_CLK_MF_SELECT (14U) macro
/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/source/
Dcy_sysclk.c762 CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_CLK_MF_SELECT, SRSS_CLK_MF_SELECT_ENABLE, 1U); in Cy_SysClk_ClkMfEnable()
781 CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_CLK_MF_SELECT, SRSS_CLK_MF_SELECT_ENABLE, 0U); in Cy_SysClk_ClkMfDisable()
796 … CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_CLK_MF_SELECT, SRSS_CLK_MF_SELECT_MFCLK_DIV, divider - 1UL); in Cy_SysClk_ClkMfSetDivider()
Dcy_pra.c143 regIndexToAddr[CY_PRA_INDX_SRSS_CLK_MF_SELECT].addr = &SRSS_CLK_MF_SELECT; in Cy_PRA_Init()