1 /***************************************************************************//** 2 * \file cyip_ctbm_v2.h 3 * 4 * \brief 5 * CTBM IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_CTBM_V2_H_ 28 #define _CYIP_CTBM_V2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * CTBM 34 *******************************************************************************/ 35 36 #define CTBM_V2_SECTION_SIZE 0x00010000UL 37 38 /** 39 * \brief Continuous Time Block Mini (CTBM) 40 */ 41 typedef struct { 42 __IOM uint32_t CTB_CTRL; /*!< 0x00000000 global CTB and power control */ 43 __IOM uint32_t OA_RES0_CTRL; /*!< 0x00000004 Opamp0 and resistor0 control */ 44 __IOM uint32_t OA_RES1_CTRL; /*!< 0x00000008 Opamp1 and resistor1 control */ 45 __IM uint32_t COMP_STAT; /*!< 0x0000000C Comparator status */ 46 __IM uint32_t RESERVED[4]; 47 __IOM uint32_t INTR; /*!< 0x00000020 Interrupt request register */ 48 __IOM uint32_t INTR_SET; /*!< 0x00000024 Interrupt request set register */ 49 __IOM uint32_t INTR_MASK; /*!< 0x00000028 Interrupt request mask */ 50 __IM uint32_t INTR_MASKED; /*!< 0x0000002C Interrupt request masked */ 51 __IM uint32_t RESERVED1[20]; 52 __IOM uint32_t OA0_SW; /*!< 0x00000080 Opamp0 switch control */ 53 __IOM uint32_t OA0_SW_CLEAR; /*!< 0x00000084 Opamp0 switch control clear */ 54 __IOM uint32_t OA1_SW; /*!< 0x00000088 Opamp1 switch control */ 55 __IOM uint32_t OA1_SW_CLEAR; /*!< 0x0000008C Opamp1 switch control clear */ 56 __IM uint32_t RESERVED2[4]; 57 __IOM uint32_t CTD_SW; /*!< 0x000000A0 CTDAC connection switch control */ 58 __IOM uint32_t CTD_SW_CLEAR; /*!< 0x000000A4 CTDAC connection switch control clear */ 59 __IM uint32_t RESERVED3[6]; 60 __IOM uint32_t CTB_SW_DS_CTRL; /*!< 0x000000C0 CTB bus switch control */ 61 __IOM uint32_t CTB_SW_SQ_CTRL; /*!< 0x000000C4 CTB bus switch Sar Sequencer control */ 62 __IM uint32_t CTB_SW_STATUS; /*!< 0x000000C8 CTB bus switch control status */ 63 __IM uint32_t RESERVED4[909]; 64 __IOM uint32_t OA0_OFFSET_TRIM; /*!< 0x00000F00 Opamp0 trim control */ 65 __IOM uint32_t OA0_SLOPE_OFFSET_TRIM; /*!< 0x00000F04 Opamp0 trim control */ 66 __IOM uint32_t OA0_COMP_TRIM; /*!< 0x00000F08 Opamp0 trim control */ 67 __IOM uint32_t OA1_OFFSET_TRIM; /*!< 0x00000F0C Opamp1 trim control */ 68 __IOM uint32_t OA1_SLOPE_OFFSET_TRIM; /*!< 0x00000F10 Opamp1 trim control */ 69 __IOM uint32_t OA1_COMP_TRIM; /*!< 0x00000F14 Opamp1 trim control */ 70 } CTBM_V2_Type; /*!< Size = 3864 (0xF18) */ 71 72 73 /* CTBM.CTB_CTRL */ 74 #define CTBM_V2_CTB_CTRL_DEEPSLEEP_ON_Pos 30UL 75 #define CTBM_V2_CTB_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL 76 #define CTBM_V2_CTB_CTRL_ENABLED_Pos 31UL 77 #define CTBM_V2_CTB_CTRL_ENABLED_Msk 0x80000000UL 78 /* CTBM.OA_RES0_CTRL */ 79 #define CTBM_V2_OA_RES0_CTRL_OA0_PWR_MODE_Pos 0UL 80 #define CTBM_V2_OA_RES0_CTRL_OA0_PWR_MODE_Msk 0x7UL 81 #define CTBM_V2_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Pos 3UL 82 #define CTBM_V2_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Msk 0x8UL 83 #define CTBM_V2_OA_RES0_CTRL_OA0_COMP_EN_Pos 4UL 84 #define CTBM_V2_OA_RES0_CTRL_OA0_COMP_EN_Msk 0x10UL 85 #define CTBM_V2_OA_RES0_CTRL_OA0_HYST_EN_Pos 5UL 86 #define CTBM_V2_OA_RES0_CTRL_OA0_HYST_EN_Msk 0x20UL 87 #define CTBM_V2_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Pos 6UL 88 #define CTBM_V2_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk 0x40UL 89 #define CTBM_V2_OA_RES0_CTRL_OA0_DSI_LEVEL_Pos 7UL 90 #define CTBM_V2_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk 0x80UL 91 #define CTBM_V2_OA_RES0_CTRL_OA0_COMPINT_Pos 8UL 92 #define CTBM_V2_OA_RES0_CTRL_OA0_COMPINT_Msk 0x300UL 93 #define CTBM_V2_OA_RES0_CTRL_OA0_PUMP_EN_Pos 11UL 94 #define CTBM_V2_OA_RES0_CTRL_OA0_PUMP_EN_Msk 0x800UL 95 #define CTBM_V2_OA_RES0_CTRL_OA0_BOOST_EN_Pos 12UL 96 #define CTBM_V2_OA_RES0_CTRL_OA0_BOOST_EN_Msk 0x1000UL 97 /* CTBM.OA_RES1_CTRL */ 98 #define CTBM_V2_OA_RES1_CTRL_OA1_PWR_MODE_Pos 0UL 99 #define CTBM_V2_OA_RES1_CTRL_OA1_PWR_MODE_Msk 0x7UL 100 #define CTBM_V2_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Pos 3UL 101 #define CTBM_V2_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Msk 0x8UL 102 #define CTBM_V2_OA_RES1_CTRL_OA1_COMP_EN_Pos 4UL 103 #define CTBM_V2_OA_RES1_CTRL_OA1_COMP_EN_Msk 0x10UL 104 #define CTBM_V2_OA_RES1_CTRL_OA1_HYST_EN_Pos 5UL 105 #define CTBM_V2_OA_RES1_CTRL_OA1_HYST_EN_Msk 0x20UL 106 #define CTBM_V2_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Pos 6UL 107 #define CTBM_V2_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Msk 0x40UL 108 #define CTBM_V2_OA_RES1_CTRL_OA1_DSI_LEVEL_Pos 7UL 109 #define CTBM_V2_OA_RES1_CTRL_OA1_DSI_LEVEL_Msk 0x80UL 110 #define CTBM_V2_OA_RES1_CTRL_OA1_COMPINT_Pos 8UL 111 #define CTBM_V2_OA_RES1_CTRL_OA1_COMPINT_Msk 0x300UL 112 #define CTBM_V2_OA_RES1_CTRL_OA1_PUMP_EN_Pos 11UL 113 #define CTBM_V2_OA_RES1_CTRL_OA1_PUMP_EN_Msk 0x800UL 114 #define CTBM_V2_OA_RES1_CTRL_OA1_BOOST_EN_Pos 12UL 115 #define CTBM_V2_OA_RES1_CTRL_OA1_BOOST_EN_Msk 0x1000UL 116 /* CTBM.COMP_STAT */ 117 #define CTBM_V2_COMP_STAT_OA0_COMP_Pos 0UL 118 #define CTBM_V2_COMP_STAT_OA0_COMP_Msk 0x1UL 119 #define CTBM_V2_COMP_STAT_OA1_COMP_Pos 16UL 120 #define CTBM_V2_COMP_STAT_OA1_COMP_Msk 0x10000UL 121 /* CTBM.INTR */ 122 #define CTBM_V2_INTR_COMP0_Pos 0UL 123 #define CTBM_V2_INTR_COMP0_Msk 0x1UL 124 #define CTBM_V2_INTR_COMP1_Pos 1UL 125 #define CTBM_V2_INTR_COMP1_Msk 0x2UL 126 /* CTBM.INTR_SET */ 127 #define CTBM_V2_INTR_SET_COMP0_SET_Pos 0UL 128 #define CTBM_V2_INTR_SET_COMP0_SET_Msk 0x1UL 129 #define CTBM_V2_INTR_SET_COMP1_SET_Pos 1UL 130 #define CTBM_V2_INTR_SET_COMP1_SET_Msk 0x2UL 131 /* CTBM.INTR_MASK */ 132 #define CTBM_V2_INTR_MASK_COMP0_MASK_Pos 0UL 133 #define CTBM_V2_INTR_MASK_COMP0_MASK_Msk 0x1UL 134 #define CTBM_V2_INTR_MASK_COMP1_MASK_Pos 1UL 135 #define CTBM_V2_INTR_MASK_COMP1_MASK_Msk 0x2UL 136 /* CTBM.INTR_MASKED */ 137 #define CTBM_V2_INTR_MASKED_COMP0_MASKED_Pos 0UL 138 #define CTBM_V2_INTR_MASKED_COMP0_MASKED_Msk 0x1UL 139 #define CTBM_V2_INTR_MASKED_COMP1_MASKED_Pos 1UL 140 #define CTBM_V2_INTR_MASKED_COMP1_MASKED_Msk 0x2UL 141 /* CTBM.OA0_SW */ 142 #define CTBM_V2_OA0_SW_OA0P_A00_Pos 0UL 143 #define CTBM_V2_OA0_SW_OA0P_A00_Msk 0x1UL 144 #define CTBM_V2_OA0_SW_OA0P_A20_Pos 2UL 145 #define CTBM_V2_OA0_SW_OA0P_A20_Msk 0x4UL 146 #define CTBM_V2_OA0_SW_OA0P_A30_Pos 3UL 147 #define CTBM_V2_OA0_SW_OA0P_A30_Msk 0x8UL 148 #define CTBM_V2_OA0_SW_OA0M_A11_Pos 8UL 149 #define CTBM_V2_OA0_SW_OA0M_A11_Msk 0x100UL 150 #define CTBM_V2_OA0_SW_OA0M_A81_Pos 14UL 151 #define CTBM_V2_OA0_SW_OA0M_A81_Msk 0x4000UL 152 #define CTBM_V2_OA0_SW_OA0O_D51_Pos 18UL 153 #define CTBM_V2_OA0_SW_OA0O_D51_Msk 0x40000UL 154 #define CTBM_V2_OA0_SW_OA0O_D81_Pos 21UL 155 #define CTBM_V2_OA0_SW_OA0O_D81_Msk 0x200000UL 156 /* CTBM.OA0_SW_CLEAR */ 157 #define CTBM_V2_OA0_SW_CLEAR_OA0P_A00_Pos 0UL 158 #define CTBM_V2_OA0_SW_CLEAR_OA0P_A00_Msk 0x1UL 159 #define CTBM_V2_OA0_SW_CLEAR_OA0P_A20_Pos 2UL 160 #define CTBM_V2_OA0_SW_CLEAR_OA0P_A20_Msk 0x4UL 161 #define CTBM_V2_OA0_SW_CLEAR_OA0P_A30_Pos 3UL 162 #define CTBM_V2_OA0_SW_CLEAR_OA0P_A30_Msk 0x8UL 163 #define CTBM_V2_OA0_SW_CLEAR_OA0M_A11_Pos 8UL 164 #define CTBM_V2_OA0_SW_CLEAR_OA0M_A11_Msk 0x100UL 165 #define CTBM_V2_OA0_SW_CLEAR_OA0M_A81_Pos 14UL 166 #define CTBM_V2_OA0_SW_CLEAR_OA0M_A81_Msk 0x4000UL 167 #define CTBM_V2_OA0_SW_CLEAR_OA0O_D51_Pos 18UL 168 #define CTBM_V2_OA0_SW_CLEAR_OA0O_D51_Msk 0x40000UL 169 #define CTBM_V2_OA0_SW_CLEAR_OA0O_D81_Pos 21UL 170 #define CTBM_V2_OA0_SW_CLEAR_OA0O_D81_Msk 0x200000UL 171 /* CTBM.OA1_SW */ 172 #define CTBM_V2_OA1_SW_OA1P_A03_Pos 0UL 173 #define CTBM_V2_OA1_SW_OA1P_A03_Msk 0x1UL 174 #define CTBM_V2_OA1_SW_OA1P_A13_Pos 1UL 175 #define CTBM_V2_OA1_SW_OA1P_A13_Msk 0x2UL 176 #define CTBM_V2_OA1_SW_OA1P_A43_Pos 4UL 177 #define CTBM_V2_OA1_SW_OA1P_A43_Msk 0x10UL 178 #define CTBM_V2_OA1_SW_OA1P_A73_Pos 7UL 179 #define CTBM_V2_OA1_SW_OA1P_A73_Msk 0x80UL 180 #define CTBM_V2_OA1_SW_OA1M_A22_Pos 8UL 181 #define CTBM_V2_OA1_SW_OA1M_A22_Msk 0x100UL 182 #define CTBM_V2_OA1_SW_OA1M_A82_Pos 14UL 183 #define CTBM_V2_OA1_SW_OA1M_A82_Msk 0x4000UL 184 #define CTBM_V2_OA1_SW_OA1O_D52_Pos 18UL 185 #define CTBM_V2_OA1_SW_OA1O_D52_Msk 0x40000UL 186 #define CTBM_V2_OA1_SW_OA1O_D62_Pos 19UL 187 #define CTBM_V2_OA1_SW_OA1O_D62_Msk 0x80000UL 188 #define CTBM_V2_OA1_SW_OA1O_D82_Pos 21UL 189 #define CTBM_V2_OA1_SW_OA1O_D82_Msk 0x200000UL 190 /* CTBM.OA1_SW_CLEAR */ 191 #define CTBM_V2_OA1_SW_CLEAR_OA1P_A03_Pos 0UL 192 #define CTBM_V2_OA1_SW_CLEAR_OA1P_A03_Msk 0x1UL 193 #define CTBM_V2_OA1_SW_CLEAR_OA1P_A13_Pos 1UL 194 #define CTBM_V2_OA1_SW_CLEAR_OA1P_A13_Msk 0x2UL 195 #define CTBM_V2_OA1_SW_CLEAR_OA1P_A43_Pos 4UL 196 #define CTBM_V2_OA1_SW_CLEAR_OA1P_A43_Msk 0x10UL 197 #define CTBM_V2_OA1_SW_CLEAR_OA1P_A73_Pos 7UL 198 #define CTBM_V2_OA1_SW_CLEAR_OA1P_A73_Msk 0x80UL 199 #define CTBM_V2_OA1_SW_CLEAR_OA1M_A22_Pos 8UL 200 #define CTBM_V2_OA1_SW_CLEAR_OA1M_A22_Msk 0x100UL 201 #define CTBM_V2_OA1_SW_CLEAR_OA1M_A82_Pos 14UL 202 #define CTBM_V2_OA1_SW_CLEAR_OA1M_A82_Msk 0x4000UL 203 #define CTBM_V2_OA1_SW_CLEAR_OA1O_D52_Pos 18UL 204 #define CTBM_V2_OA1_SW_CLEAR_OA1O_D52_Msk 0x40000UL 205 #define CTBM_V2_OA1_SW_CLEAR_OA1O_D62_Pos 19UL 206 #define CTBM_V2_OA1_SW_CLEAR_OA1O_D62_Msk 0x80000UL 207 #define CTBM_V2_OA1_SW_CLEAR_OA1O_D82_Pos 21UL 208 #define CTBM_V2_OA1_SW_CLEAR_OA1O_D82_Msk 0x200000UL 209 /* CTBM.CTD_SW */ 210 #define CTBM_V2_CTD_SW_CTDD_CRD_Pos 1UL 211 #define CTBM_V2_CTD_SW_CTDD_CRD_Msk 0x2UL 212 #define CTBM_V2_CTD_SW_CTDS_CRS_Pos 4UL 213 #define CTBM_V2_CTD_SW_CTDS_CRS_Msk 0x10UL 214 #define CTBM_V2_CTD_SW_CTDS_COR_Pos 5UL 215 #define CTBM_V2_CTD_SW_CTDS_COR_Msk 0x20UL 216 #define CTBM_V2_CTD_SW_CTDO_C6H_Pos 8UL 217 #define CTBM_V2_CTD_SW_CTDO_C6H_Msk 0x100UL 218 #define CTBM_V2_CTD_SW_CTDO_COS_Pos 9UL 219 #define CTBM_V2_CTD_SW_CTDO_COS_Msk 0x200UL 220 #define CTBM_V2_CTD_SW_CTDH_COB_Pos 10UL 221 #define CTBM_V2_CTD_SW_CTDH_COB_Msk 0x400UL 222 #define CTBM_V2_CTD_SW_CTDH_CHD_Pos 12UL 223 #define CTBM_V2_CTD_SW_CTDH_CHD_Msk 0x1000UL 224 #define CTBM_V2_CTD_SW_CTDH_CA0_Pos 13UL 225 #define CTBM_V2_CTD_SW_CTDH_CA0_Msk 0x2000UL 226 #define CTBM_V2_CTD_SW_CTDH_CIS_Pos 14UL 227 #define CTBM_V2_CTD_SW_CTDH_CIS_Msk 0x4000UL 228 #define CTBM_V2_CTD_SW_CTDH_ILR_Pos 15UL 229 #define CTBM_V2_CTD_SW_CTDH_ILR_Msk 0x8000UL 230 /* CTBM.CTD_SW_CLEAR */ 231 #define CTBM_V2_CTD_SW_CLEAR_CTDD_CRD_Pos 1UL 232 #define CTBM_V2_CTD_SW_CLEAR_CTDD_CRD_Msk 0x2UL 233 #define CTBM_V2_CTD_SW_CLEAR_CTDS_CRS_Pos 4UL 234 #define CTBM_V2_CTD_SW_CLEAR_CTDS_CRS_Msk 0x10UL 235 #define CTBM_V2_CTD_SW_CLEAR_CTDS_COR_Pos 5UL 236 #define CTBM_V2_CTD_SW_CLEAR_CTDS_COR_Msk 0x20UL 237 #define CTBM_V2_CTD_SW_CLEAR_CTDO_C6H_Pos 8UL 238 #define CTBM_V2_CTD_SW_CLEAR_CTDO_C6H_Msk 0x100UL 239 #define CTBM_V2_CTD_SW_CLEAR_CTDO_COS_Pos 9UL 240 #define CTBM_V2_CTD_SW_CLEAR_CTDO_COS_Msk 0x200UL 241 #define CTBM_V2_CTD_SW_CLEAR_CTDH_COB_Pos 10UL 242 #define CTBM_V2_CTD_SW_CLEAR_CTDH_COB_Msk 0x400UL 243 #define CTBM_V2_CTD_SW_CLEAR_CTDH_CHD_Pos 12UL 244 #define CTBM_V2_CTD_SW_CLEAR_CTDH_CHD_Msk 0x1000UL 245 #define CTBM_V2_CTD_SW_CLEAR_CTDH_CA0_Pos 13UL 246 #define CTBM_V2_CTD_SW_CLEAR_CTDH_CA0_Msk 0x2000UL 247 #define CTBM_V2_CTD_SW_CLEAR_CTDH_CIS_Pos 14UL 248 #define CTBM_V2_CTD_SW_CLEAR_CTDH_CIS_Msk 0x4000UL 249 #define CTBM_V2_CTD_SW_CLEAR_CTDH_ILR_Pos 15UL 250 #define CTBM_V2_CTD_SW_CLEAR_CTDH_ILR_Msk 0x8000UL 251 /* CTBM.CTB_SW_DS_CTRL */ 252 #define CTBM_V2_CTB_SW_DS_CTRL_P2_DS_CTRL23_Pos 10UL 253 #define CTBM_V2_CTB_SW_DS_CTRL_P2_DS_CTRL23_Msk 0x400UL 254 #define CTBM_V2_CTB_SW_DS_CTRL_P3_DS_CTRL23_Pos 11UL 255 #define CTBM_V2_CTB_SW_DS_CTRL_P3_DS_CTRL23_Msk 0x800UL 256 #define CTBM_V2_CTB_SW_DS_CTRL_CTD_COS_DS_CTRL_Pos 31UL 257 #define CTBM_V2_CTB_SW_DS_CTRL_CTD_COS_DS_CTRL_Msk 0x80000000UL 258 /* CTBM.CTB_SW_SQ_CTRL */ 259 #define CTBM_V2_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Pos 10UL 260 #define CTBM_V2_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk 0x400UL 261 #define CTBM_V2_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Pos 11UL 262 #define CTBM_V2_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk 0x800UL 263 /* CTBM.CTB_SW_STATUS */ 264 #define CTBM_V2_CTB_SW_STATUS_OA0O_D51_STAT_Pos 28UL 265 #define CTBM_V2_CTB_SW_STATUS_OA0O_D51_STAT_Msk 0x10000000UL 266 #define CTBM_V2_CTB_SW_STATUS_OA1O_D52_STAT_Pos 29UL 267 #define CTBM_V2_CTB_SW_STATUS_OA1O_D52_STAT_Msk 0x20000000UL 268 #define CTBM_V2_CTB_SW_STATUS_OA1O_D62_STAT_Pos 30UL 269 #define CTBM_V2_CTB_SW_STATUS_OA1O_D62_STAT_Msk 0x40000000UL 270 #define CTBM_V2_CTB_SW_STATUS_CTD_COS_STAT_Pos 31UL 271 #define CTBM_V2_CTB_SW_STATUS_CTD_COS_STAT_Msk 0x80000000UL 272 /* CTBM.OA0_OFFSET_TRIM */ 273 #define CTBM_V2_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Pos 0UL 274 #define CTBM_V2_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Msk 0x3FUL 275 /* CTBM.OA0_SLOPE_OFFSET_TRIM */ 276 #define CTBM_V2_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Pos 0UL 277 #define CTBM_V2_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Msk 0x3FUL 278 /* CTBM.OA0_COMP_TRIM */ 279 #define CTBM_V2_OA0_COMP_TRIM_OA0_COMP_TRIM_Pos 0UL 280 #define CTBM_V2_OA0_COMP_TRIM_OA0_COMP_TRIM_Msk 0x3UL 281 /* CTBM.OA1_OFFSET_TRIM */ 282 #define CTBM_V2_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Pos 0UL 283 #define CTBM_V2_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Msk 0x3FUL 284 /* CTBM.OA1_SLOPE_OFFSET_TRIM */ 285 #define CTBM_V2_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Pos 0UL 286 #define CTBM_V2_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Msk 0x3FUL 287 /* CTBM.OA1_COMP_TRIM */ 288 #define CTBM_V2_OA1_COMP_TRIM_OA1_COMP_TRIM_Pos 0UL 289 #define CTBM_V2_OA1_COMP_TRIM_OA1_COMP_TRIM_Msk 0x3UL 290 291 292 #endif /* _CYIP_CTBM_V2_H_ */ 293 294 295 /* [] END OF FILE */ 296
