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Searched refs:CPUSS_RAMC2_PRESENT (Results 1 – 14 of 14) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device_common.h423 #define CPUSS_RAMC2_PRESENT 0u macro
Dpsoc6_01_config.h1677 #define CPUSS_RAMC2_PRESENT 0u macro
Dpsoc6_03_config.h1328 #define CPUSS_RAMC2_PRESENT 0u macro
Dpsoc6_04_config.h1290 #define CPUSS_RAMC2_PRESENT 0u macro
Dpsoc6_02_config.h1803 #define CPUSS_RAMC2_PRESENT 1u macro
Dcy_device.h446 #define CPUSS_SRAM_COUNT (1u + CPUSS_RAMC1_PRESENT + CPUSS_RAMC2_PRESENT)
/hal_infineon-3.7.0/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM0P/
Dsystem_cm0plus.c228 #if (CPUSS_RAMC2_PRESENT == 1u) in EnableEcc()
/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/source/
Dcy_syspm_v3.c1088 CY_ASSERT_L1( CPUSS_RAMC2_PRESENT ); in Cy_SysPm_SetSRAMMacroPwrMode()
1162 CY_ASSERT_L1( CPUSS_RAMC2_PRESENT ); in Cy_SysPm_SetSRAMPwrMode()
Dcy_syspm.c2107 CY_ASSERT_L1( CPUSS_RAMC2_PRESENT ); in Cy_SysPm_SetSRAMMacroPwrMode()
2188 CY_ASSERT_L1( CPUSS_RAMC2_PRESENT ); in Cy_SysPm_SetSRAMPwrMode()
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcyw20829A0_config.h649 #define CPUSS_RAMC2_PRESENT 0u macro
Dcyw20829B0_config.h652 #define CPUSS_RAMC2_PRESENT 0u macro
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dxmc7100_config.h1954 #define CPUSS_RAMC2_PRESENT 0u macro
Dxmc7200_config.h2536 #define CPUSS_RAMC2_PRESENT 1u macro
Dcy_device.h514 #define CPUSS_SRAM_COUNT (1u + CPUSS_RAMC1_PRESENT + CPUSS_RAMC2_PRESENT)