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Searched refs:CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 (Results 1 – 6 of 6) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dpsoc6_01_config.h1801 #define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u macro
Dpsoc6_03_config.h1527 #define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u macro
Dpsoc6_04_config.h1495 #define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u macro
Dpsoc6_02_config.h2002 #define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u macro
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dxmc7100_config.h2219 #define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u macro
Dxmc7200_config.h2801 #define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u macro