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Searched refs:CPUSS_FAST_0_CLOCK_CTL (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/drivers/source/
Dcy_sysclk_v2.c799 CY_REG32_CLR_SET(CPUSS_FAST_0_CLOCK_CTL, CPUSS_FAST_0_CLOCK_CTL_INT_DIV, intDiv); in Cy_SysClk_ClkFastSrcSetDivider()
800 CY_REG32_CLR_SET(CPUSS_FAST_0_CLOCK_CTL, CPUSS_FAST_0_CLOCK_CTL_FRAC_DIV, fracDiv); in Cy_SysClk_ClkFastSrcSetDivider()
813 … *dividerIntValue = ((uint8_t)_FLD2VAL(CPUSS_FAST_0_CLOCK_CTL_INT_DIV, CPUSS_FAST_0_CLOCK_CTL)); in Cy_SysClk_ClkFastSrcGetDivider()
814 … *dividerFracValue = ((uint8_t)_FLD2VAL(CPUSS_FAST_0_CLOCK_CTL_FRAC_DIV, CPUSS_FAST_0_CLOCK_CTL)); in Cy_SysClk_ClkFastSrcGetDivider()
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h448 #define CPUSS_FAST_0_CLOCK_CTL (((CPUSS_Type*) CPUSS_BASE)->FAST_0_CLOCK_CTL) macro
469 #define CPUSS_FAST_0_CLOCK_CTL (((CPUSS_Type*) CPUSS_BASE)->FAST_0_CLOCK_CTL) macro