1 /***************************************************************************//** 2 * \file cyip_cpuss.h 3 * 4 * \brief 5 * CPUSS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_CPUSS_H_ 28 #define _CYIP_CPUSS_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * CPUSS 34 *******************************************************************************/ 35 36 #define CPUSS_SECTION_SIZE 0x00010000UL 37 38 /** 39 * \brief CPU subsystem (CPUSS) (CPUSS) 40 */ 41 typedef struct { 42 __IM uint32_t IDENTITY; /*!< 0x00000000 Identity */ 43 __IM uint32_t CM7_0_STATUS; /*!< 0x00000004 CM7 0 status */ 44 __IOM uint32_t FAST_0_CLOCK_CTL; /*!< 0x00000008 Fast 0 clock control */ 45 __IOM uint32_t CM7_0_CTL; /*!< 0x0000000C CM7 0 control */ 46 __IM uint32_t RESERVED[60]; 47 __IM uint32_t CM7_0_INT_STATUS[16]; /*!< 0x00000100 CM7 0 interrupt status */ 48 __IM uint32_t RESERVED1[48]; 49 __IOM uint32_t CM7_0_VECTOR_TABLE_BASE; /*!< 0x00000200 CM7 0 vector table base */ 50 __IM uint32_t RESERVED2[15]; 51 __IOM uint32_t CM7_0_NMI_CTL[4]; /*!< 0x00000240 CM7 0 NMI control */ 52 __IM uint32_t RESERVED3[44]; 53 __IOM uint32_t UDB_PWR_CTL; /*!< 0x00000300 UDB power control */ 54 __IOM uint32_t UDB_PWR_DELAY_CTL; /*!< 0x00000304 UDB power control */ 55 __IM uint32_t RESERVED4[6]; 56 __IOM uint32_t TRC_DBG_CLOCK_CTL; /*!< 0x00000320 Trace and debug clock control */ 57 __IM uint32_t RESERVED5[56]; 58 __IM uint32_t CM7_1_STATUS; /*!< 0x00000404 CM7 1status */ 59 __IOM uint32_t FAST_1_CLOCK_CTL; /*!< 0x00000408 Fast 1 clock control */ 60 __IOM uint32_t CM7_1_CTL; /*!< 0x0000040C CM7 1 control */ 61 __IM uint32_t RESERVED6[60]; 62 __IM uint32_t CM7_1_INT_STATUS[16]; /*!< 0x00000500 CM7 1 interrupt status */ 63 __IM uint32_t RESERVED7[48]; 64 __IOM uint32_t CM7_1_VECTOR_TABLE_BASE; /*!< 0x00000600 CM7 1 vector table base */ 65 __IM uint32_t RESERVED8[15]; 66 __IOM uint32_t CM7_1_NMI_CTL[4]; /*!< 0x00000640 CM7 1 NMI control */ 67 __IM uint32_t RESERVED9[620]; 68 __IOM uint32_t CM0_CTL; /*!< 0x00001000 CM0+ control */ 69 __IM uint32_t CM0_STATUS; /*!< 0x00001004 CM0+ status */ 70 __IOM uint32_t SLOW_CLOCK_CTL; /*!< 0x00001008 Slow clock control */ 71 __IOM uint32_t PERI_CLOCK_CTL; /*!< 0x0000100C Peripheral interconnect clock control */ 72 __IOM uint32_t MEM_CLOCK_CTL; /*!< 0x00001010 Memory clock control */ 73 __IM uint32_t RESERVED10[59]; 74 __IM uint32_t CM0_INT0_STATUS; /*!< 0x00001100 CM0+ interrupt 0 status */ 75 __IM uint32_t CM0_INT1_STATUS; /*!< 0x00001104 CM0+ interrupt 1 status */ 76 __IM uint32_t CM0_INT2_STATUS; /*!< 0x00001108 CM0+ interrupt 2 status */ 77 __IM uint32_t CM0_INT3_STATUS; /*!< 0x0000110C CM0+ interrupt 3 status */ 78 __IM uint32_t CM0_INT4_STATUS; /*!< 0x00001110 CM0+ interrupt 4 status */ 79 __IM uint32_t CM0_INT5_STATUS; /*!< 0x00001114 CM0+ interrupt 5 status */ 80 __IM uint32_t CM0_INT6_STATUS; /*!< 0x00001118 CM0+ interrupt 6 status */ 81 __IM uint32_t CM0_INT7_STATUS; /*!< 0x0000111C CM0+ interrupt 7 status */ 82 __IOM uint32_t CM0_VECTOR_TABLE_BASE; /*!< 0x00001120 CM0+ vector table base */ 83 __IM uint32_t RESERVED11[7]; 84 __IOM uint32_t CM0_NMI_CTL[4]; /*!< 0x00001140 CM0+ NMI control */ 85 __IM uint32_t RESERVED12[44]; 86 __IOM uint32_t CM7_0_PWR_CTL; /*!< 0x00001200 CM7 0 power control */ 87 __IOM uint32_t CM7_0_PWR_DELAY_CTL; /*!< 0x00001204 CM7 0 power delay control */ 88 __IM uint32_t RESERVED13[2]; 89 __IOM uint32_t CM7_1_PWR_CTL; /*!< 0x00001210 CM7 1 power control */ 90 __IOM uint32_t CM7_1_PWR_DELAY_CTL; /*!< 0x00001214 CM7 1 power delay control */ 91 __IM uint32_t RESERVED14[58]; 92 __IOM uint32_t RAM0_CTL0; /*!< 0x00001300 RAM 0 control */ 93 __IM uint32_t RAM0_STATUS; /*!< 0x00001304 RAM 0 status */ 94 __IM uint32_t RESERVED15[14]; 95 __IOM uint32_t RAM0_PWR_MACRO_CTL[16]; /*!< 0x00001340 RAM 0 power control */ 96 __IOM uint32_t RAM1_CTL0; /*!< 0x00001380 RAM 1 control */ 97 __IM uint32_t RAM1_STATUS; /*!< 0x00001384 RAM 1 status */ 98 __IOM uint32_t RAM1_PWR_CTL; /*!< 0x00001388 RAM 1 power control */ 99 __IM uint32_t RESERVED16[5]; 100 __IOM uint32_t RAM2_CTL0; /*!< 0x000013A0 RAM 2 control */ 101 __IM uint32_t RAM2_STATUS; /*!< 0x000013A4 RAM 2 status */ 102 __IOM uint32_t RAM2_PWR_CTL; /*!< 0x000013A8 RAM 2 power control */ 103 __IM uint32_t RESERVED17[5]; 104 __IOM uint32_t RAM_PWR_DELAY_CTL; /*!< 0x000013C0 Power up delay used for all SRAM power domains */ 105 __IOM uint32_t ROM_CTL; /*!< 0x000013C4 ROM control */ 106 __IOM uint32_t ECC_CTL; /*!< 0x000013C8 ECC control */ 107 __IM uint32_t RESERVED18[13]; 108 __IM uint32_t PRODUCT_ID; /*!< 0x00001400 Product identifier and version (same as CoreSight RomTables) */ 109 __IM uint32_t RESERVED19[3]; 110 __IM uint32_t DP_STATUS; /*!< 0x00001410 Debug port status */ 111 __IOM uint32_t AP_CTL; /*!< 0x00001414 Access port control */ 112 __IM uint32_t RESERVED20[58]; 113 __IOM uint32_t BUFF_CTL; /*!< 0x00001500 Buffer control */ 114 __IM uint32_t RESERVED21[63]; 115 __IOM uint32_t SYSTICK_CTL; /*!< 0x00001600 SysTick timer control */ 116 __IM uint32_t RESERVED22[64]; 117 __IM uint32_t MBIST_STAT; /*!< 0x00001704 Memory BIST status */ 118 __IM uint32_t RESERVED23[62]; 119 __IOM uint32_t CAL_SUP_SET; /*!< 0x00001800 Calibration support set and read */ 120 __IOM uint32_t CAL_SUP_CLR; /*!< 0x00001804 Calibration support clear and reset */ 121 __IM uint32_t RESERVED24[510]; 122 __IOM uint32_t CM0_PC_CTL; /*!< 0x00002000 CM0+ protection context control */ 123 __IM uint32_t RESERVED25[15]; 124 __IOM uint32_t CM0_PC0_HANDLER; /*!< 0x00002040 CM0+ protection context 0 handler */ 125 __IOM uint32_t CM0_PC1_HANDLER; /*!< 0x00002044 CM0+ protection context 1 handler */ 126 __IOM uint32_t CM0_PC2_HANDLER; /*!< 0x00002048 CM0+ protection context 2 handler */ 127 __IOM uint32_t CM0_PC3_HANDLER; /*!< 0x0000204C CM0+ protection context 3 handler */ 128 __IM uint32_t RESERVED26[29]; 129 __IOM uint32_t PROTECTION; /*!< 0x000020C4 Protection status */ 130 __IM uint32_t RESERVED27[14]; 131 __IOM uint32_t TRIM_ROM_CTL; /*!< 0x00002100 ROM trim control */ 132 __IOM uint32_t TRIM_RAM_CTL; /*!< 0x00002104 RAM trim control for less than 100MHz SRAMs */ 133 __IOM uint32_t TRIM_RAM200_CTL; /*!< 0x00002108 RAM trim control for 100MHz - 200MHz SRAMs */ 134 __IOM uint32_t TRIM_RAM350_CTL; /*!< 0x0000210C RAM trim control for more than 200MHz SRAMs */ 135 __IM uint32_t RESERVED28[6076]; 136 __IOM uint32_t CM0_SYSTEM_INT_CTL[1023]; /*!< 0x00008000 CM0+ system interrupt control */ 137 __IM uint32_t RESERVED29[1025]; 138 __IOM uint32_t CM7_0_SYSTEM_INT_CTL[1023]; /*!< 0x0000A000 CM7 0 system interrupt control */ 139 __IM uint32_t RESERVED30[1025]; 140 __IOM uint32_t CM7_1_SYSTEM_INT_CTL[1023]; /*!< 0x0000C000 CM7 1 system interrupt control */ 141 } CPUSS_Type; /*!< Size = 53244 (0xCFFC) */ 142 143 144 /* CPUSS.IDENTITY */ 145 #define CPUSS_IDENTITY_P_Pos 0UL 146 #define CPUSS_IDENTITY_P_Msk 0x1UL 147 #define CPUSS_IDENTITY_NS_Pos 1UL 148 #define CPUSS_IDENTITY_NS_Msk 0x2UL 149 #define CPUSS_IDENTITY_PC_Pos 4UL 150 #define CPUSS_IDENTITY_PC_Msk 0xF0UL 151 #define CPUSS_IDENTITY_MS_Pos 8UL 152 #define CPUSS_IDENTITY_MS_Msk 0xF00UL 153 /* CPUSS.CM7_0_STATUS */ 154 #define CPUSS_CM7_0_STATUS_SLEEPING_Pos 0UL 155 #define CPUSS_CM7_0_STATUS_SLEEPING_Msk 0x1UL 156 #define CPUSS_CM7_0_STATUS_SLEEPDEEP_Pos 1UL 157 #define CPUSS_CM7_0_STATUS_SLEEPDEEP_Msk 0x2UL 158 #define CPUSS_CM7_0_STATUS_PWR_DONE_Pos 4UL 159 #define CPUSS_CM7_0_STATUS_PWR_DONE_Msk 0x10UL 160 #define CPUSS_CM7_0_STATUS_TCMC_CM7_1_MS_Pos 9UL 161 #define CPUSS_CM7_0_STATUS_TCMC_CM7_1_MS_Msk 0x200UL 162 #define CPUSS_CM7_0_STATUS_TCMC_EXT_MS_2_TO_0_Pos 10UL 163 #define CPUSS_CM7_0_STATUS_TCMC_EXT_MS_2_TO_0_Msk 0x400UL 164 #define CPUSS_CM7_0_STATUS_TCMC_EXT_MS_3_Pos 11UL 165 #define CPUSS_CM7_0_STATUS_TCMC_EXT_MS_3_Msk 0x800UL 166 #define CPUSS_CM7_0_STATUS_TCMC_AHB_MS_Pos 12UL 167 #define CPUSS_CM7_0_STATUS_TCMC_AHB_MS_Msk 0x1000UL 168 /* CPUSS.FAST_0_CLOCK_CTL */ 169 #define CPUSS_FAST_0_CLOCK_CTL_FRAC_DIV_Pos 3UL 170 #define CPUSS_FAST_0_CLOCK_CTL_FRAC_DIV_Msk 0xF8UL 171 #define CPUSS_FAST_0_CLOCK_CTL_INT_DIV_Pos 8UL 172 #define CPUSS_FAST_0_CLOCK_CTL_INT_DIV_Msk 0xFF00UL 173 /* CPUSS.CM7_0_CTL */ 174 #define CPUSS_CM7_0_CTL_PPB_LOCK_Pos 0UL 175 #define CPUSS_CM7_0_CTL_PPB_LOCK_Msk 0xFUL 176 #define CPUSS_CM7_0_CTL_CPU_WAIT_Pos 4UL 177 #define CPUSS_CM7_0_CTL_CPU_WAIT_Msk 0x10UL 178 #define CPUSS_CM7_0_CTL_INIT_TCM_EN_Pos 8UL 179 #define CPUSS_CM7_0_CTL_INIT_TCM_EN_Msk 0x300UL 180 #define CPUSS_CM7_0_CTL_INIT_RMW_EN_Pos 10UL 181 #define CPUSS_CM7_0_CTL_INIT_RMW_EN_Msk 0xC00UL 182 #define CPUSS_CM7_0_CTL_ITCM_ECC_EN_Pos 16UL 183 #define CPUSS_CM7_0_CTL_ITCM_ECC_EN_Msk 0x10000UL 184 #define CPUSS_CM7_0_CTL_ITCM_ECC_INJ_EN_Pos 17UL 185 #define CPUSS_CM7_0_CTL_ITCM_ECC_INJ_EN_Msk 0x20000UL 186 #define CPUSS_CM7_0_CTL_ITCM_READ_WS_Pos 18UL 187 #define CPUSS_CM7_0_CTL_ITCM_READ_WS_Msk 0x40000UL 188 #define CPUSS_CM7_0_CTL_ITCM_ECC_CHECK_DIS_Pos 19UL 189 #define CPUSS_CM7_0_CTL_ITCM_ECC_CHECK_DIS_Msk 0x80000UL 190 #define CPUSS_CM7_0_CTL_DTCM_ECC_EN_Pos 20UL 191 #define CPUSS_CM7_0_CTL_DTCM_ECC_EN_Msk 0x100000UL 192 #define CPUSS_CM7_0_CTL_DTCM_ECC_INJ_EN_Pos 21UL 193 #define CPUSS_CM7_0_CTL_DTCM_ECC_INJ_EN_Msk 0x200000UL 194 #define CPUSS_CM7_0_CTL_DTCM_READ_WS_Pos 22UL 195 #define CPUSS_CM7_0_CTL_DTCM_READ_WS_Msk 0x400000UL 196 #define CPUSS_CM7_0_CTL_TCMC_EN_Pos 23UL 197 #define CPUSS_CM7_0_CTL_TCMC_EN_Msk 0x800000UL 198 #define CPUSS_CM7_0_CTL_IOC_MASK_Pos 24UL 199 #define CPUSS_CM7_0_CTL_IOC_MASK_Msk 0x1000000UL 200 #define CPUSS_CM7_0_CTL_DZC_MASK_Pos 25UL 201 #define CPUSS_CM7_0_CTL_DZC_MASK_Msk 0x2000000UL 202 #define CPUSS_CM7_0_CTL_OFC_MASK_Pos 26UL 203 #define CPUSS_CM7_0_CTL_OFC_MASK_Msk 0x4000000UL 204 #define CPUSS_CM7_0_CTL_UFC_MASK_Pos 27UL 205 #define CPUSS_CM7_0_CTL_UFC_MASK_Msk 0x8000000UL 206 #define CPUSS_CM7_0_CTL_IXC_MASK_Pos 28UL 207 #define CPUSS_CM7_0_CTL_IXC_MASK_Msk 0x10000000UL 208 #define CPUSS_CM7_0_CTL_IDC_MASK_Pos 31UL 209 #define CPUSS_CM7_0_CTL_IDC_MASK_Msk 0x80000000UL 210 /* CPUSS.CM7_0_INT_STATUS */ 211 #define CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_IDX_Pos 0UL 212 #define CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 213 #define CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_VALID_Pos 31UL 214 #define CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 215 /* CPUSS.CM7_0_VECTOR_TABLE_BASE */ 216 #define CPUSS_CM7_0_VECTOR_TABLE_BASE_ADDR25_Pos 7UL 217 #define CPUSS_CM7_0_VECTOR_TABLE_BASE_ADDR25_Msk 0xFFFFFF80UL 218 /* CPUSS.CM7_0_NMI_CTL */ 219 #define CPUSS_CM7_0_NMI_CTL_SYSTEM_INT_IDX_Pos 0UL 220 #define CPUSS_CM7_0_NMI_CTL_SYSTEM_INT_IDX_Msk 0x3FFUL 221 /* CPUSS.UDB_PWR_CTL */ 222 #define CPUSS_UDB_PWR_CTL_PWR_MODE_Pos 0UL 223 #define CPUSS_UDB_PWR_CTL_PWR_MODE_Msk 0x3UL 224 #define CPUSS_UDB_PWR_CTL_VECTKEYSTAT_Pos 16UL 225 #define CPUSS_UDB_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 226 /* CPUSS.UDB_PWR_DELAY_CTL */ 227 #define CPUSS_UDB_PWR_DELAY_CTL_UP_Pos 0UL 228 #define CPUSS_UDB_PWR_DELAY_CTL_UP_Msk 0x3FFUL 229 /* CPUSS.TRC_DBG_CLOCK_CTL */ 230 #define CPUSS_TRC_DBG_CLOCK_CTL_INT_DIV_Pos 8UL 231 #define CPUSS_TRC_DBG_CLOCK_CTL_INT_DIV_Msk 0xFF00UL 232 /* CPUSS.CM7_1_STATUS */ 233 #define CPUSS_CM7_1_STATUS_SLEEPING_Pos 0UL 234 #define CPUSS_CM7_1_STATUS_SLEEPING_Msk 0x1UL 235 #define CPUSS_CM7_1_STATUS_SLEEPDEEP_Pos 1UL 236 #define CPUSS_CM7_1_STATUS_SLEEPDEEP_Msk 0x2UL 237 #define CPUSS_CM7_1_STATUS_PWR_DONE_Pos 4UL 238 #define CPUSS_CM7_1_STATUS_PWR_DONE_Msk 0x10UL 239 #define CPUSS_CM7_1_STATUS_TCMC_CM7_0_MS_Pos 8UL 240 #define CPUSS_CM7_1_STATUS_TCMC_CM7_0_MS_Msk 0x100UL 241 #define CPUSS_CM7_1_STATUS_TCMC_EXT_MS_2_TO_0_Pos 10UL 242 #define CPUSS_CM7_1_STATUS_TCMC_EXT_MS_2_TO_0_Msk 0x400UL 243 #define CPUSS_CM7_1_STATUS_TCMC_EXT_MS_3_Pos 11UL 244 #define CPUSS_CM7_1_STATUS_TCMC_EXT_MS_3_Msk 0x800UL 245 #define CPUSS_CM7_1_STATUS_TCMC_AHB_MS_Pos 12UL 246 #define CPUSS_CM7_1_STATUS_TCMC_AHB_MS_Msk 0x1000UL 247 /* CPUSS.FAST_1_CLOCK_CTL */ 248 #define CPUSS_FAST_1_CLOCK_CTL_FRAC_DIV_Pos 3UL 249 #define CPUSS_FAST_1_CLOCK_CTL_FRAC_DIV_Msk 0xF8UL 250 #define CPUSS_FAST_1_CLOCK_CTL_INT_DIV_Pos 8UL 251 #define CPUSS_FAST_1_CLOCK_CTL_INT_DIV_Msk 0xFF00UL 252 /* CPUSS.CM7_1_CTL */ 253 #define CPUSS_CM7_1_CTL_PPB_LOCK_Pos 0UL 254 #define CPUSS_CM7_1_CTL_PPB_LOCK_Msk 0xFUL 255 #define CPUSS_CM7_1_CTL_CPU_WAIT_Pos 4UL 256 #define CPUSS_CM7_1_CTL_CPU_WAIT_Msk 0x10UL 257 #define CPUSS_CM7_1_CTL_INIT_TCM_EN_Pos 8UL 258 #define CPUSS_CM7_1_CTL_INIT_TCM_EN_Msk 0x300UL 259 #define CPUSS_CM7_1_CTL_INIT_RMW_EN_Pos 10UL 260 #define CPUSS_CM7_1_CTL_INIT_RMW_EN_Msk 0xC00UL 261 #define CPUSS_CM7_1_CTL_ITCM_ECC_EN_Pos 16UL 262 #define CPUSS_CM7_1_CTL_ITCM_ECC_EN_Msk 0x10000UL 263 #define CPUSS_CM7_1_CTL_ITCM_ECC_INJ_EN_Pos 17UL 264 #define CPUSS_CM7_1_CTL_ITCM_ECC_INJ_EN_Msk 0x20000UL 265 #define CPUSS_CM7_1_CTL_ITCM_READ_WS_Pos 18UL 266 #define CPUSS_CM7_1_CTL_ITCM_READ_WS_Msk 0x40000UL 267 #define CPUSS_CM7_1_CTL_ITCM_ECC_CHECK_DIS_Pos 19UL 268 #define CPUSS_CM7_1_CTL_ITCM_ECC_CHECK_DIS_Msk 0x80000UL 269 #define CPUSS_CM7_1_CTL_DTCM_ECC_EN_Pos 20UL 270 #define CPUSS_CM7_1_CTL_DTCM_ECC_EN_Msk 0x100000UL 271 #define CPUSS_CM7_1_CTL_DTCM_ECC_INJ_EN_Pos 21UL 272 #define CPUSS_CM7_1_CTL_DTCM_ECC_INJ_EN_Msk 0x200000UL 273 #define CPUSS_CM7_1_CTL_DTCM_READ_WS_Pos 22UL 274 #define CPUSS_CM7_1_CTL_DTCM_READ_WS_Msk 0x400000UL 275 #define CPUSS_CM7_1_CTL_TCMC_EN_Pos 23UL 276 #define CPUSS_CM7_1_CTL_TCMC_EN_Msk 0x800000UL 277 #define CPUSS_CM7_1_CTL_IOC_MASK_Pos 24UL 278 #define CPUSS_CM7_1_CTL_IOC_MASK_Msk 0x1000000UL 279 #define CPUSS_CM7_1_CTL_DZC_MASK_Pos 25UL 280 #define CPUSS_CM7_1_CTL_DZC_MASK_Msk 0x2000000UL 281 #define CPUSS_CM7_1_CTL_OFC_MASK_Pos 26UL 282 #define CPUSS_CM7_1_CTL_OFC_MASK_Msk 0x4000000UL 283 #define CPUSS_CM7_1_CTL_UFC_MASK_Pos 27UL 284 #define CPUSS_CM7_1_CTL_UFC_MASK_Msk 0x8000000UL 285 #define CPUSS_CM7_1_CTL_IXC_MASK_Pos 28UL 286 #define CPUSS_CM7_1_CTL_IXC_MASK_Msk 0x10000000UL 287 #define CPUSS_CM7_1_CTL_IDC_MASK_Pos 31UL 288 #define CPUSS_CM7_1_CTL_IDC_MASK_Msk 0x80000000UL 289 /* CPUSS.CM7_1_INT_STATUS */ 290 #define CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_IDX_Pos 0UL 291 #define CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 292 #define CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_VALID_Pos 31UL 293 #define CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 294 /* CPUSS.CM7_1_VECTOR_TABLE_BASE */ 295 #define CPUSS_CM7_1_VECTOR_TABLE_BASE_ADDR25_Pos 7UL 296 #define CPUSS_CM7_1_VECTOR_TABLE_BASE_ADDR25_Msk 0xFFFFFF80UL 297 /* CPUSS.CM7_1_NMI_CTL */ 298 #define CPUSS_CM7_1_NMI_CTL_SYSTEM_INT_IDX_Pos 0UL 299 #define CPUSS_CM7_1_NMI_CTL_SYSTEM_INT_IDX_Msk 0x3FFUL 300 /* CPUSS.CM0_CTL */ 301 #define CPUSS_CM0_CTL_SLV_STALL_Pos 0UL 302 #define CPUSS_CM0_CTL_SLV_STALL_Msk 0x1UL 303 #define CPUSS_CM0_CTL_ENABLED_Pos 1UL 304 #define CPUSS_CM0_CTL_ENABLED_Msk 0x2UL 305 #define CPUSS_CM0_CTL_VECTKEYSTAT_Pos 16UL 306 #define CPUSS_CM0_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 307 /* CPUSS.CM0_STATUS */ 308 #define CPUSS_CM0_STATUS_SLEEPING_Pos 0UL 309 #define CPUSS_CM0_STATUS_SLEEPING_Msk 0x1UL 310 #define CPUSS_CM0_STATUS_SLEEPDEEP_Pos 1UL 311 #define CPUSS_CM0_STATUS_SLEEPDEEP_Msk 0x2UL 312 /* CPUSS.SLOW_CLOCK_CTL */ 313 #define CPUSS_SLOW_CLOCK_CTL_INT_DIV_Pos 8UL 314 #define CPUSS_SLOW_CLOCK_CTL_INT_DIV_Msk 0xFF00UL 315 /* CPUSS.PERI_CLOCK_CTL */ 316 #define CPUSS_PERI_CLOCK_CTL_INT_DIV_Pos 8UL 317 #define CPUSS_PERI_CLOCK_CTL_INT_DIV_Msk 0xFF00UL 318 /* CPUSS.MEM_CLOCK_CTL */ 319 #define CPUSS_MEM_CLOCK_CTL_INT_DIV_Pos 8UL 320 #define CPUSS_MEM_CLOCK_CTL_INT_DIV_Msk 0xFF00UL 321 /* CPUSS.CM0_INT0_STATUS */ 322 #define CPUSS_CM0_INT0_STATUS_SYSTEM_INT_IDX_Pos 0UL 323 #define CPUSS_CM0_INT0_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 324 #define CPUSS_CM0_INT0_STATUS_SYSTEM_INT_VALID_Pos 31UL 325 #define CPUSS_CM0_INT0_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 326 /* CPUSS.CM0_INT1_STATUS */ 327 #define CPUSS_CM0_INT1_STATUS_SYSTEM_INT_IDX_Pos 0UL 328 #define CPUSS_CM0_INT1_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 329 #define CPUSS_CM0_INT1_STATUS_SYSTEM_INT_VALID_Pos 31UL 330 #define CPUSS_CM0_INT1_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 331 /* CPUSS.CM0_INT2_STATUS */ 332 #define CPUSS_CM0_INT2_STATUS_SYSTEM_INT_IDX_Pos 0UL 333 #define CPUSS_CM0_INT2_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 334 #define CPUSS_CM0_INT2_STATUS_SYSTEM_INT_VALID_Pos 31UL 335 #define CPUSS_CM0_INT2_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 336 /* CPUSS.CM0_INT3_STATUS */ 337 #define CPUSS_CM0_INT3_STATUS_SYSTEM_INT_IDX_Pos 0UL 338 #define CPUSS_CM0_INT3_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 339 #define CPUSS_CM0_INT3_STATUS_SYSTEM_INT_VALID_Pos 31UL 340 #define CPUSS_CM0_INT3_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 341 /* CPUSS.CM0_INT4_STATUS */ 342 #define CPUSS_CM0_INT4_STATUS_SYSTEM_INT_IDX_Pos 0UL 343 #define CPUSS_CM0_INT4_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 344 #define CPUSS_CM0_INT4_STATUS_SYSTEM_INT_VALID_Pos 31UL 345 #define CPUSS_CM0_INT4_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 346 /* CPUSS.CM0_INT5_STATUS */ 347 #define CPUSS_CM0_INT5_STATUS_SYSTEM_INT_IDX_Pos 0UL 348 #define CPUSS_CM0_INT5_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 349 #define CPUSS_CM0_INT5_STATUS_SYSTEM_INT_VALID_Pos 31UL 350 #define CPUSS_CM0_INT5_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 351 /* CPUSS.CM0_INT6_STATUS */ 352 #define CPUSS_CM0_INT6_STATUS_SYSTEM_INT_IDX_Pos 0UL 353 #define CPUSS_CM0_INT6_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 354 #define CPUSS_CM0_INT6_STATUS_SYSTEM_INT_VALID_Pos 31UL 355 #define CPUSS_CM0_INT6_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 356 /* CPUSS.CM0_INT7_STATUS */ 357 #define CPUSS_CM0_INT7_STATUS_SYSTEM_INT_IDX_Pos 0UL 358 #define CPUSS_CM0_INT7_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 359 #define CPUSS_CM0_INT7_STATUS_SYSTEM_INT_VALID_Pos 31UL 360 #define CPUSS_CM0_INT7_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 361 /* CPUSS.CM0_VECTOR_TABLE_BASE */ 362 #define CPUSS_CM0_VECTOR_TABLE_BASE_ADDR24_Pos 8UL 363 #define CPUSS_CM0_VECTOR_TABLE_BASE_ADDR24_Msk 0xFFFFFF00UL 364 /* CPUSS.CM0_NMI_CTL */ 365 #define CPUSS_CM0_NMI_CTL_SYSTEM_INT_IDX_Pos 0UL 366 #define CPUSS_CM0_NMI_CTL_SYSTEM_INT_IDX_Msk 0x3FFUL 367 /* CPUSS.CM7_0_PWR_CTL */ 368 #define CPUSS_CM7_0_PWR_CTL_PWR_MODE_Pos 0UL 369 #define CPUSS_CM7_0_PWR_CTL_PWR_MODE_Msk 0x3UL 370 #define CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT_Pos 16UL 371 #define CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 372 /* CPUSS.CM7_0_PWR_DELAY_CTL */ 373 #define CPUSS_CM7_0_PWR_DELAY_CTL_UP_Pos 0UL 374 #define CPUSS_CM7_0_PWR_DELAY_CTL_UP_Msk 0x3FFUL 375 /* CPUSS.CM7_1_PWR_CTL */ 376 #define CPUSS_CM7_1_PWR_CTL_PWR_MODE_Pos 0UL 377 #define CPUSS_CM7_1_PWR_CTL_PWR_MODE_Msk 0x3UL 378 #define CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT_Pos 16UL 379 #define CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 380 /* CPUSS.CM7_1_PWR_DELAY_CTL */ 381 #define CPUSS_CM7_1_PWR_DELAY_CTL_UP_Pos 0UL 382 #define CPUSS_CM7_1_PWR_DELAY_CTL_UP_Msk 0x3FFUL 383 /* CPUSS.RAM0_CTL0 */ 384 #define CPUSS_RAM0_CTL0_SLOW_WS_Pos 0UL 385 #define CPUSS_RAM0_CTL0_SLOW_WS_Msk 0x3UL 386 #define CPUSS_RAM0_CTL0_FAST_WS_Pos 8UL 387 #define CPUSS_RAM0_CTL0_FAST_WS_Msk 0x300UL 388 #define CPUSS_RAM0_CTL0_ECC_EN_Pos 16UL 389 #define CPUSS_RAM0_CTL0_ECC_EN_Msk 0x10000UL 390 #define CPUSS_RAM0_CTL0_ECC_AUTO_CORRECT_Pos 17UL 391 #define CPUSS_RAM0_CTL0_ECC_AUTO_CORRECT_Msk 0x20000UL 392 #define CPUSS_RAM0_CTL0_ECC_INJ_EN_Pos 18UL 393 #define CPUSS_RAM0_CTL0_ECC_INJ_EN_Msk 0x40000UL 394 #define CPUSS_RAM0_CTL0_ECC_CHECK_DIS_Pos 19UL 395 #define CPUSS_RAM0_CTL0_ECC_CHECK_DIS_Msk 0x80000UL 396 /* CPUSS.RAM0_STATUS */ 397 #define CPUSS_RAM0_STATUS_WB_EMPTY_Pos 0UL 398 #define CPUSS_RAM0_STATUS_WB_EMPTY_Msk 0x1UL 399 /* CPUSS.RAM0_PWR_MACRO_CTL */ 400 #define CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE_Pos 0UL 401 #define CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE_Msk 0x3UL 402 #define CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Pos 16UL 403 #define CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 404 /* CPUSS.RAM1_CTL0 */ 405 #define CPUSS_RAM1_CTL0_SLOW_WS_Pos 0UL 406 #define CPUSS_RAM1_CTL0_SLOW_WS_Msk 0x3UL 407 #define CPUSS_RAM1_CTL0_FAST_WS_Pos 8UL 408 #define CPUSS_RAM1_CTL0_FAST_WS_Msk 0x300UL 409 #define CPUSS_RAM1_CTL0_ECC_EN_Pos 16UL 410 #define CPUSS_RAM1_CTL0_ECC_EN_Msk 0x10000UL 411 #define CPUSS_RAM1_CTL0_ECC_AUTO_CORRECT_Pos 17UL 412 #define CPUSS_RAM1_CTL0_ECC_AUTO_CORRECT_Msk 0x20000UL 413 #define CPUSS_RAM1_CTL0_ECC_INJ_EN_Pos 18UL 414 #define CPUSS_RAM1_CTL0_ECC_INJ_EN_Msk 0x40000UL 415 #define CPUSS_RAM1_CTL0_ECC_CHECK_DIS_Pos 19UL 416 #define CPUSS_RAM1_CTL0_ECC_CHECK_DIS_Msk 0x80000UL 417 /* CPUSS.RAM1_STATUS */ 418 #define CPUSS_RAM1_STATUS_WB_EMPTY_Pos 0UL 419 #define CPUSS_RAM1_STATUS_WB_EMPTY_Msk 0x1UL 420 /* CPUSS.RAM1_PWR_CTL */ 421 #define CPUSS_RAM1_PWR_CTL_PWR_MODE_Pos 0UL 422 #define CPUSS_RAM1_PWR_CTL_PWR_MODE_Msk 0x3UL 423 #define CPUSS_RAM1_PWR_CTL_VECTKEYSTAT_Pos 16UL 424 #define CPUSS_RAM1_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 425 /* CPUSS.RAM2_CTL0 */ 426 #define CPUSS_RAM2_CTL0_SLOW_WS_Pos 0UL 427 #define CPUSS_RAM2_CTL0_SLOW_WS_Msk 0x3UL 428 #define CPUSS_RAM2_CTL0_FAST_WS_Pos 8UL 429 #define CPUSS_RAM2_CTL0_FAST_WS_Msk 0x300UL 430 #define CPUSS_RAM2_CTL0_ECC_EN_Pos 16UL 431 #define CPUSS_RAM2_CTL0_ECC_EN_Msk 0x10000UL 432 #define CPUSS_RAM2_CTL0_ECC_AUTO_CORRECT_Pos 17UL 433 #define CPUSS_RAM2_CTL0_ECC_AUTO_CORRECT_Msk 0x20000UL 434 #define CPUSS_RAM2_CTL0_ECC_INJ_EN_Pos 18UL 435 #define CPUSS_RAM2_CTL0_ECC_INJ_EN_Msk 0x40000UL 436 #define CPUSS_RAM2_CTL0_ECC_CHECK_DIS_Pos 19UL 437 #define CPUSS_RAM2_CTL0_ECC_CHECK_DIS_Msk 0x80000UL 438 /* CPUSS.RAM2_STATUS */ 439 #define CPUSS_RAM2_STATUS_WB_EMPTY_Pos 0UL 440 #define CPUSS_RAM2_STATUS_WB_EMPTY_Msk 0x1UL 441 /* CPUSS.RAM2_PWR_CTL */ 442 #define CPUSS_RAM2_PWR_CTL_PWR_MODE_Pos 0UL 443 #define CPUSS_RAM2_PWR_CTL_PWR_MODE_Msk 0x3UL 444 #define CPUSS_RAM2_PWR_CTL_VECTKEYSTAT_Pos 16UL 445 #define CPUSS_RAM2_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 446 /* CPUSS.RAM_PWR_DELAY_CTL */ 447 #define CPUSS_RAM_PWR_DELAY_CTL_UP_Pos 0UL 448 #define CPUSS_RAM_PWR_DELAY_CTL_UP_Msk 0x3FFUL 449 /* CPUSS.ROM_CTL */ 450 #define CPUSS_ROM_CTL_SLOW_WS_Pos 0UL 451 #define CPUSS_ROM_CTL_SLOW_WS_Msk 0x3UL 452 #define CPUSS_ROM_CTL_FAST_WS_Pos 8UL 453 #define CPUSS_ROM_CTL_FAST_WS_Msk 0x300UL 454 /* CPUSS.ECC_CTL */ 455 #define CPUSS_ECC_CTL_WORD_ADDR_Pos 0UL 456 #define CPUSS_ECC_CTL_WORD_ADDR_Msk 0xFFFFFFUL 457 #define CPUSS_ECC_CTL_PARITY_Pos 24UL 458 #define CPUSS_ECC_CTL_PARITY_Msk 0xFF000000UL 459 /* CPUSS.PRODUCT_ID */ 460 #define CPUSS_PRODUCT_ID_FAMILY_ID_Pos 0UL 461 #define CPUSS_PRODUCT_ID_FAMILY_ID_Msk 0xFFFUL 462 #define CPUSS_PRODUCT_ID_MAJOR_REV_Pos 16UL 463 #define CPUSS_PRODUCT_ID_MAJOR_REV_Msk 0xF0000UL 464 #define CPUSS_PRODUCT_ID_MINOR_REV_Pos 20UL 465 #define CPUSS_PRODUCT_ID_MINOR_REV_Msk 0xF00000UL 466 /* CPUSS.DP_STATUS */ 467 #define CPUSS_DP_STATUS_SWJ_CONNECTED_Pos 0UL 468 #define CPUSS_DP_STATUS_SWJ_CONNECTED_Msk 0x1UL 469 #define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Pos 1UL 470 #define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Msk 0x2UL 471 #define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Pos 2UL 472 #define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Msk 0x4UL 473 /* CPUSS.AP_CTL */ 474 #define CPUSS_AP_CTL_CM0_ENABLE_Pos 0UL 475 #define CPUSS_AP_CTL_CM0_ENABLE_Msk 0x1UL 476 #define CPUSS_AP_CTL_CM7_ENABLE_Pos 1UL 477 #define CPUSS_AP_CTL_CM7_ENABLE_Msk 0x2UL 478 #define CPUSS_AP_CTL_SYS_ENABLE_Pos 2UL 479 #define CPUSS_AP_CTL_SYS_ENABLE_Msk 0x4UL 480 #define CPUSS_AP_CTL_CM0_DISABLE_Pos 16UL 481 #define CPUSS_AP_CTL_CM0_DISABLE_Msk 0x10000UL 482 #define CPUSS_AP_CTL_CM7_DISABLE_Pos 17UL 483 #define CPUSS_AP_CTL_CM7_DISABLE_Msk 0x20000UL 484 #define CPUSS_AP_CTL_SYS_DISABLE_Pos 18UL 485 #define CPUSS_AP_CTL_SYS_DISABLE_Msk 0x40000UL 486 /* CPUSS.BUFF_CTL */ 487 #define CPUSS_BUFF_CTL_WRITE_BUFF_Pos 0UL 488 #define CPUSS_BUFF_CTL_WRITE_BUFF_Msk 0x1UL 489 /* CPUSS.SYSTICK_CTL */ 490 #define CPUSS_SYSTICK_CTL_TENMS_Pos 0UL 491 #define CPUSS_SYSTICK_CTL_TENMS_Msk 0xFFFFFFUL 492 #define CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Pos 24UL 493 #define CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Msk 0x3000000UL 494 #define CPUSS_SYSTICK_CTL_SKEW_Pos 30UL 495 #define CPUSS_SYSTICK_CTL_SKEW_Msk 0x40000000UL 496 #define CPUSS_SYSTICK_CTL_NOREF_Pos 31UL 497 #define CPUSS_SYSTICK_CTL_NOREF_Msk 0x80000000UL 498 /* CPUSS.MBIST_STAT */ 499 #define CPUSS_MBIST_STAT_SFP_READY_Pos 0UL 500 #define CPUSS_MBIST_STAT_SFP_READY_Msk 0x1UL 501 #define CPUSS_MBIST_STAT_SFP_FAIL_Pos 1UL 502 #define CPUSS_MBIST_STAT_SFP_FAIL_Msk 0x2UL 503 /* CPUSS.CAL_SUP_SET */ 504 #define CPUSS_CAL_SUP_SET_DATA_Pos 0UL 505 #define CPUSS_CAL_SUP_SET_DATA_Msk 0xFFFFFFFFUL 506 /* CPUSS.CAL_SUP_CLR */ 507 #define CPUSS_CAL_SUP_CLR_DATA_Pos 0UL 508 #define CPUSS_CAL_SUP_CLR_DATA_Msk 0xFFFFFFFFUL 509 /* CPUSS.CM0_PC_CTL */ 510 #define CPUSS_CM0_PC_CTL_VALID_Pos 0UL 511 #define CPUSS_CM0_PC_CTL_VALID_Msk 0xFUL 512 /* CPUSS.CM0_PC0_HANDLER */ 513 #define CPUSS_CM0_PC0_HANDLER_ADDR_Pos 0UL 514 #define CPUSS_CM0_PC0_HANDLER_ADDR_Msk 0xFFFFFFFFUL 515 /* CPUSS.CM0_PC1_HANDLER */ 516 #define CPUSS_CM0_PC1_HANDLER_ADDR_Pos 0UL 517 #define CPUSS_CM0_PC1_HANDLER_ADDR_Msk 0xFFFFFFFFUL 518 /* CPUSS.CM0_PC2_HANDLER */ 519 #define CPUSS_CM0_PC2_HANDLER_ADDR_Pos 0UL 520 #define CPUSS_CM0_PC2_HANDLER_ADDR_Msk 0xFFFFFFFFUL 521 /* CPUSS.CM0_PC3_HANDLER */ 522 #define CPUSS_CM0_PC3_HANDLER_ADDR_Pos 0UL 523 #define CPUSS_CM0_PC3_HANDLER_ADDR_Msk 0xFFFFFFFFUL 524 /* CPUSS.PROTECTION */ 525 #define CPUSS_PROTECTION_STATE_Pos 0UL 526 #define CPUSS_PROTECTION_STATE_Msk 0x7UL 527 /* CPUSS.TRIM_ROM_CTL */ 528 #define CPUSS_TRIM_ROM_CTL_TRIM_Pos 0UL 529 #define CPUSS_TRIM_ROM_CTL_TRIM_Msk 0xFFFFFFFFUL 530 /* CPUSS.TRIM_RAM_CTL */ 531 #define CPUSS_TRIM_RAM_CTL_TRIM_Pos 0UL 532 #define CPUSS_TRIM_RAM_CTL_TRIM_Msk 0xFFFFFFFFUL 533 /* CPUSS.TRIM_RAM200_CTL */ 534 #define CPUSS_TRIM_RAM200_CTL_TRIM_Pos 0UL 535 #define CPUSS_TRIM_RAM200_CTL_TRIM_Msk 0xFFFFFFFFUL 536 /* CPUSS.TRIM_RAM350_CTL */ 537 #define CPUSS_TRIM_RAM350_CTL_TRIM_Pos 0UL 538 #define CPUSS_TRIM_RAM350_CTL_TRIM_Msk 0xFFFFFFFFUL 539 /* CPUSS.CM0_SYSTEM_INT_CTL */ 540 #define CPUSS_CM0_SYSTEM_INT_CTL_CM0_CPU_INT_IDX_Pos 0UL 541 #define CPUSS_CM0_SYSTEM_INT_CTL_CM0_CPU_INT_IDX_Msk 0x7UL 542 #define CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Pos 31UL 543 #define CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk 0x80000000UL 544 /* CPUSS.CM7_0_SYSTEM_INT_CTL */ 545 #define CPUSS_CM7_0_SYSTEM_INT_CTL_CPU_INT_IDX_Pos 0UL 546 #define CPUSS_CM7_0_SYSTEM_INT_CTL_CPU_INT_IDX_Msk 0xFUL 547 #define CPUSS_CM7_0_SYSTEM_INT_CTL_CPU_INT_VALID_Pos 31UL 548 #define CPUSS_CM7_0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk 0x80000000UL 549 /* CPUSS.CM7_1_SYSTEM_INT_CTL */ 550 #define CPUSS_CM7_1_SYSTEM_INT_CTL_CPU_INT_IDX_Pos 0UL 551 #define CPUSS_CM7_1_SYSTEM_INT_CTL_CPU_INT_IDX_Msk 0xFUL 552 #define CPUSS_CM7_1_SYSTEM_INT_CTL_CPU_INT_VALID_Pos 31UL 553 #define CPUSS_CM7_1_SYSTEM_INT_CTL_CPU_INT_VALID_Msk 0x80000000UL 554 555 556 #endif /* _CYIP_CPUSS_H_ */ 557 558 559 /* [] END OF FILE */ 560
