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Searched refs:CPUSS_CM7_0_STATUS_PWR_DONE_Msk (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-3.7.0/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM0P/
Dsystem_cm0plus.c455 while((CPUSS->CM7_0_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL) in Cy_SysEnableCM7()
499 while((CPUSS->CM7_0_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL) in Cy_SysDisableCM7()
512 while((CPUSS->CM7_1_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL) in Cy_SysDisableCM7()
564 while((CPUSS->CM7_0_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL) in Cy_SysResetCM7()
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_cpuss.h159 #define CPUSS_CM7_0_STATUS_PWR_DONE_Msk 0x10UL macro