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Searched refs:CPUSS_AP_CTL_SYS_DISABLE_Msk (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/ip/
Dcyip_cpuss.h230 #define CPUSS_AP_CTL_SYS_DISABLE_Msk 0x40000UL macro
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_cpuss.h328 #define CPUSS_AP_CTL_SYS_DISABLE_Msk 0x40000UL macro
/hal_infineon-3.7.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_cpuss.h485 #define CPUSS_AP_CTL_SYS_DISABLE_Msk 0x40000UL macro