1 /***************************************************************************//**
2 * \file cyip_ble.h
3 *
4 * \brief
5 * BLE IP definitions
6 *
7 ********************************************************************************
8 * \copyright
9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 *     http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *******************************************************************************/
26 
27 #ifndef _CYIP_BLE_H_
28 #define _CYIP_BLE_H_
29 
30 #include "cyip_headers.h"
31 
32 /*******************************************************************************
33 *                                     BLE
34 *******************************************************************************/
35 
36 #define BLE_RCB_RCBLL_SECTION_SIZE              0x00000100UL
37 #define BLE_RCB_SECTION_SIZE                    0x00000200UL
38 #define BLE_BLELL_SECTION_SIZE                  0x0001E000UL
39 #define BLE_BLESS_SECTION_SIZE                  0x00001000UL
40 #define BLE_SECTION_SIZE                        0x00020000UL
41 
42 /**
43   * \brief Radio Control Bus (RCB) & Link Layer controller (BLE_RCB_RCBLL)
44   */
45 typedef struct {
46   __IOM uint32_t CTRL;                          /*!< 0x00000000 RCB LL control register. */
47    __IM uint32_t RESERVED[3];
48   __IOM uint32_t INTR;                          /*!< 0x00000010 Master interrupt request register. */
49   __IOM uint32_t INTR_SET;                      /*!< 0x00000014 Master interrupt set request register */
50   __IOM uint32_t INTR_MASK;                     /*!< 0x00000018 Master interrupt mask register. */
51    __IM uint32_t INTR_MASKED;                   /*!< 0x0000001C Master interrupt masked request register */
52   __IOM uint32_t RADIO_REG1_ADDR;               /*!< 0x00000020 Address of Register#1 in Radio  (MDON) */
53   __IOM uint32_t RADIO_REG2_ADDR;               /*!< 0x00000024 Address of Register#2 in Radio  (RSSI) */
54   __IOM uint32_t RADIO_REG3_ADDR;               /*!< 0x00000028 Address of Register#3 in Radio  (ACCL) */
55   __IOM uint32_t RADIO_REG4_ADDR;               /*!< 0x0000002C Address of Register#4 in Radio  (ACCH) */
56   __IOM uint32_t RADIO_REG5_ADDR;               /*!< 0x00000030 Address of Register#5 in Radio  (RSSI ENERGY) */
57    __IM uint32_t RESERVED1[3];
58   __IOM uint32_t CPU_WRITE_REG;                 /*!< 0x00000040 N/A */
59   __IOM uint32_t CPU_READ_REG;                  /*!< 0x00000044 N/A */
60    __IM uint32_t RESERVED2[46];
61 } BLE_RCB_RCBLL_V1_Type;                        /*!< Size = 256 (0x100) */
62 
63 /**
64   * \brief Radio Control Bus (RCB) controller (BLE_RCB)
65   */
66 typedef struct {
67   __IOM uint32_t CTRL;                          /*!< 0x00000000 RCB control register. */
68    __IM uint32_t STATUS;                        /*!< 0x00000004 RCB status register. */
69    __IM uint32_t RESERVED[2];
70   __IOM uint32_t TX_CTRL;                       /*!< 0x00000010 Transmitter control register. */
71   __IOM uint32_t TX_FIFO_CTRL;                  /*!< 0x00000014 Transmitter FIFO control register. */
72    __IM uint32_t TX_FIFO_STATUS;                /*!< 0x00000018 Transmitter FIFO status register. */
73    __OM uint32_t TX_FIFO_WR;                    /*!< 0x0000001C Transmitter FIFO write register. */
74   __IOM uint32_t RX_CTRL;                       /*!< 0x00000020 Receiver control register. */
75   __IOM uint32_t RX_FIFO_CTRL;                  /*!< 0x00000024 Receiver FIFO control register. */
76    __IM uint32_t RX_FIFO_STATUS;                /*!< 0x00000028 Receiver FIFO status register. */
77    __IM uint32_t RX_FIFO_RD;                    /*!< 0x0000002C Receiver FIFO read register. */
78    __IM uint32_t RX_FIFO_RD_SILENT;             /*!< 0x00000030 Receiver FIFO read register. */
79    __IM uint32_t RESERVED1[3];
80   __IOM uint32_t INTR;                          /*!< 0x00000040 Master interrupt request register. */
81   __IOM uint32_t INTR_SET;                      /*!< 0x00000044 Master interrupt set request register */
82   __IOM uint32_t INTR_MASK;                     /*!< 0x00000048 Master interrupt mask register. */
83    __IM uint32_t INTR_MASKED;                   /*!< 0x0000004C Master interrupt masked request register */
84    __IM uint32_t RESERVED2[44];
85         BLE_RCB_RCBLL_V1_Type RCBLL;            /*!< 0x00000100 Radio Control Bus (RCB) & Link Layer controller */
86 } BLE_RCB_V1_Type;                              /*!< Size = 512 (0x200) */
87 
88 /**
89   * \brief Bluetooth Low Energy Link Layer (BLE_BLELL)
90   */
91 typedef struct {
92    __OM uint32_t COMMAND_REGISTER;              /*!< 0x00000000 Instruction Register */
93    __IM uint32_t RESERVED;
94   __IOM uint32_t EVENT_INTR;                    /*!< 0x00000008 Event(Interrupt) status and Clear register */
95    __IM uint32_t RESERVED1;
96   __IOM uint32_t EVENT_ENABLE;                  /*!< 0x00000010 Event indications enable. */
97    __IM uint32_t RESERVED2;
98   __IOM uint32_t ADV_PARAMS;                    /*!< 0x00000018 Advertising parameters register. */
99   __IOM uint32_t ADV_INTERVAL_TIMEOUT;          /*!< 0x0000001C Advertising interval register. */
100   __IOM uint32_t ADV_INTR;                      /*!< 0x00000020 Advertising interrupt status and Clear register */
101    __IM uint32_t ADV_NEXT_INSTANT;              /*!< 0x00000024 Advertising next instant. */
102   __IOM uint32_t SCAN_INTERVAL;                 /*!< 0x00000028 Scan Interval Register */
103   __IOM uint32_t SCAN_WINDOW;                   /*!< 0x0000002C Scan window Register */
104   __IOM uint32_t SCAN_PARAM;                    /*!< 0x00000030 Scanning parameters register */
105    __IM uint32_t RESERVED3;
106   __IOM uint32_t SCAN_INTR;                     /*!< 0x00000038 Scan interrupt status and Clear register */
107    __IM uint32_t SCAN_NEXT_INSTANT;             /*!< 0x0000003C Advertising next instant. */
108   __IOM uint32_t INIT_INTERVAL;                 /*!< 0x00000040 Initiator Interval Register */
109   __IOM uint32_t INIT_WINDOW;                   /*!< 0x00000044 Initiator window Register */
110   __IOM uint32_t INIT_PARAM;                    /*!< 0x00000048 Initiator parameters register */
111    __IM uint32_t RESERVED4;
112   __IOM uint32_t INIT_INTR;                     /*!< 0x00000050 Scan interrupt status and Clear register */
113    __IM uint32_t INIT_NEXT_INSTANT;             /*!< 0x00000054 Initiator next instant. */
114   __IOM uint32_t DEVICE_RAND_ADDR_L;            /*!< 0x00000058 Lower 16 bit random address of the device. */
115   __IOM uint32_t DEVICE_RAND_ADDR_M;            /*!< 0x0000005C Middle 16 bit random address of the device. */
116   __IOM uint32_t DEVICE_RAND_ADDR_H;            /*!< 0x00000060 Higher 16 bit random address of the device. */
117    __IM uint32_t RESERVED5;
118   __IOM uint32_t PEER_ADDR_L;                   /*!< 0x00000068 Lower 16 bit address of the peer device. */
119   __IOM uint32_t PEER_ADDR_M;                   /*!< 0x0000006C Middle 16 bit address of the peer device. */
120   __IOM uint32_t PEER_ADDR_H;                   /*!< 0x00000070 Higher 16 bit address of the peer device. */
121    __IM uint32_t RESERVED6;
122   __IOM uint32_t WL_ADDR_TYPE;                  /*!< 0x00000078 whitelist address type */
123   __IOM uint32_t WL_ENABLE;                     /*!< 0x0000007C whitelist valid entry bit */
124   __IOM uint32_t TRANSMIT_WINDOW_OFFSET;        /*!< 0x00000080 Transmit window offset */
125   __IOM uint32_t TRANSMIT_WINDOW_SIZE;          /*!< 0x00000084 Transmit window size */
126   __IOM uint32_t DATA_CHANNELS_L0;              /*!< 0x00000088 Data channel map 0 (lower word) */
127   __IOM uint32_t DATA_CHANNELS_M0;              /*!< 0x0000008C Data channel map 0 (middle word) */
128   __IOM uint32_t DATA_CHANNELS_H0;              /*!< 0x00000090 Data channel map 0 (upper word) */
129    __IM uint32_t RESERVED7;
130   __IOM uint32_t DATA_CHANNELS_L1;              /*!< 0x00000098 Data channel map 1 (lower word) */
131   __IOM uint32_t DATA_CHANNELS_M1;              /*!< 0x0000009C Data channel map 1 (middle word) */
132   __IOM uint32_t DATA_CHANNELS_H1;              /*!< 0x000000A0 Data channel map 1 (upper word) */
133    __IM uint32_t RESERVED8;
134   __IOM uint32_t CONN_INTR;                     /*!< 0x000000A8 Connection interrupt status and Clear register */
135    __IM uint32_t CONN_STATUS;                   /*!< 0x000000AC Connection channel status */
136   __IOM uint32_t CONN_INDEX;                    /*!< 0x000000B0 Connection Index register */
137    __IM uint32_t RESERVED9;
138   __IOM uint32_t WAKEUP_CONFIG;                 /*!< 0x000000B8 Wakeup configuration */
139    __IM uint32_t RESERVED10;
140   __IOM uint32_t WAKEUP_CONTROL;                /*!< 0x000000C0 Wakeup control */
141   __IOM uint32_t CLOCK_CONFIG;                  /*!< 0x000000C4 Clock control */
142    __IM uint32_t TIM_COUNTER_L;                 /*!< 0x000000C8 Reference Clock */
143   __IOM uint32_t WAKEUP_CONFIG_EXTD;            /*!< 0x000000CC Wakeup configuration extended */
144    __IM uint32_t RESERVED11[2];
145   __IOM uint32_t POC_REG__TIM_CONTROL;          /*!< 0x000000D8 BLE Time Control */
146    __IM uint32_t RESERVED12;
147   __IOM uint32_t ADV_TX_DATA_FIFO;              /*!< 0x000000E0 Advertising data transmit FIFO. Access ADVCH_TX_FIFO. */
148    __IM uint32_t RESERVED13;
149   __IOM uint32_t ADV_SCN_RSP_TX_FIFO;           /*!< 0x000000E8 Advertising scan response data transmit FIFO. Access
150                                                                 ADVCH_TX_FIFO. */
151    __IM uint32_t RESERVED14[3];
152    __IM uint32_t INIT_SCN_ADV_RX_FIFO;          /*!< 0x000000F8 advertising scan response data receive data FIFO. Access
153                                                                 ADVRX_FIFO. */
154    __IM uint32_t RESERVED15;
155   __IOM uint32_t CONN_INTERVAL;                 /*!< 0x00000100 Connection Interval */
156   __IOM uint32_t SUP_TIMEOUT;                   /*!< 0x00000104 Supervision timeout */
157   __IOM uint32_t SLAVE_LATENCY;                 /*!< 0x00000108 Slave Latency */
158   __IOM uint32_t CE_LENGTH;                     /*!< 0x0000010C Connection event length */
159   __IOM uint32_t PDU_ACCESS_ADDR_L_REGISTER;    /*!< 0x00000110 Access address (lower) */
160   __IOM uint32_t PDU_ACCESS_ADDR_H_REGISTER;    /*!< 0x00000114 Access address (upper) */
161   __IOM uint32_t CONN_CE_INSTANT;               /*!< 0x00000118 Connection event instant */
162   __IOM uint32_t CE_CNFG_STS_REGISTER;          /*!< 0x0000011C connection configuration & status register */
163    __IM uint32_t NEXT_CE_INSTANT;               /*!< 0x00000120 Next connection event instant */
164    __IM uint32_t CONN_CE_COUNTER;               /*!< 0x00000124 connection event counter */
165   __IOM uint32_t DATA_LIST_SENT_UPDATE__STATUS; /*!< 0x00000128 data list sent update and status */
166   __IOM uint32_t DATA_LIST_ACK_UPDATE__STATUS;  /*!< 0x0000012C data list ack update and status */
167   __IOM uint32_t CE_CNFG_STS_REGISTER_EXT;      /*!< 0x00000130 connection configuration & status register */
168   __IOM uint32_t CONN_EXT_INTR;                 /*!< 0x00000134 Connection extended interrupt status and Clear register */
169   __IOM uint32_t CONN_EXT_INTR_MASK;            /*!< 0x00000138 Connection Extended Interrupt mask */
170    __IM uint32_t RESERVED16;
171   __IOM uint32_t DATA_MEM_DESCRIPTOR[5];        /*!< 0x00000140 Data buffer descriptor 0 to 4 */
172    __IM uint32_t RESERVED17[3];
173   __IOM uint32_t WINDOW_WIDEN_INTVL;            /*!< 0x00000160 Window widen for interval */
174   __IOM uint32_t WINDOW_WIDEN_WINOFF;           /*!< 0x00000164 Window widen for offset */
175    __IM uint32_t RESERVED18[2];
176   __IOM uint32_t LE_RF_TEST_MODE;               /*!< 0x00000170 Direct Test Mode control */
177    __IM uint32_t DTM_RX_PKT_COUNT;              /*!< 0x00000174 Direct Test Mode receive packet count */
178   __IOM uint32_t LE_RF_TEST_MODE_EXT;           /*!< 0x00000178 Direct Test Mode control */
179    __IM uint32_t RESERVED19[3];
180    __IM uint32_t TXRX_HOP;                      /*!< 0x00000188 Channel Address register */
181    __IM uint32_t RESERVED20;
182   __IOM uint32_t TX_RX_ON_DELAY;                /*!< 0x00000190 Transmit/Receive data delay */
183    __IM uint32_t RESERVED21[5];
184   __IOM uint32_t ADV_ACCADDR_L;                 /*!< 0x000001A8 ADV packet access code low word */
185   __IOM uint32_t ADV_ACCADDR_H;                 /*!< 0x000001AC ADV packet access code high word */
186   __IOM uint32_t ADV_CH_TX_POWER_LVL_LS;        /*!< 0x000001B0 Advertising channel transmit power setting */
187   __IOM uint32_t ADV_CH_TX_POWER_LVL_MS;        /*!< 0x000001B4 Advertising channel transmit power setting extension */
188   __IOM uint32_t CONN_CH_TX_POWER_LVL_LS;       /*!< 0x000001B8 Connection channel transmit power setting */
189   __IOM uint32_t CONN_CH_TX_POWER_LVL_MS;       /*!< 0x000001BC Connection channel transmit power setting extension */
190   __IOM uint32_t DEV_PUB_ADDR_L;                /*!< 0x000001C0 Device public address lower register */
191   __IOM uint32_t DEV_PUB_ADDR_M;                /*!< 0x000001C4 Device public address middle register */
192   __IOM uint32_t DEV_PUB_ADDR_H;                /*!< 0x000001C8 Device public address higher register */
193    __IM uint32_t RESERVED22;
194   __IOM uint32_t OFFSET_TO_FIRST_INSTANT;       /*!< 0x000001D0 Offset to first instant */
195   __IOM uint32_t ADV_CONFIG;                    /*!< 0x000001D4 Advertiser configuration register */
196   __IOM uint32_t SCAN_CONFIG;                   /*!< 0x000001D8 Scan configuration register */
197   __IOM uint32_t INIT_CONFIG;                   /*!< 0x000001DC Initiator configuration register */
198   __IOM uint32_t CONN_CONFIG;                   /*!< 0x000001E0 Connection configuration register */
199    __IM uint32_t RESERVED23;
200   __IOM uint32_t CONN_PARAM1;                   /*!< 0x000001E8 Connection parameter 1 */
201   __IOM uint32_t CONN_PARAM2;                   /*!< 0x000001EC Connection parameter 2 */
202   __IOM uint32_t CONN_INTR_MASK;                /*!< 0x000001F0 Connection Interrupt mask */
203   __IOM uint32_t SLAVE_TIMING_CONTROL;          /*!< 0x000001F4 slave timing control */
204   __IOM uint32_t RECEIVE_TRIG_CTRL;             /*!< 0x000001F8 Receive trigger control */
205    __IM uint32_t RESERVED24;
206    __IM uint32_t LL_DBG_1;                      /*!< 0x00000200 LL debug register 1 */
207    __IM uint32_t LL_DBG_2;                      /*!< 0x00000204 LL debug register 2 */
208    __IM uint32_t LL_DBG_3;                      /*!< 0x00000208 LL debug register 3 */
209    __IM uint32_t LL_DBG_4;                      /*!< 0x0000020C LL debug register 4 */
210    __IM uint32_t LL_DBG_5;                      /*!< 0x00000210 LL debug register 5 */
211    __IM uint32_t LL_DBG_6;                      /*!< 0x00000214 LL debug register 6 */
212    __IM uint32_t LL_DBG_7;                      /*!< 0x00000218 LL debug register 7 */
213    __IM uint32_t LL_DBG_8;                      /*!< 0x0000021C LL debug register 8 */
214    __IM uint32_t LL_DBG_9;                      /*!< 0x00000220 LL debug register 9 */
215    __IM uint32_t LL_DBG_10;                     /*!< 0x00000224 LL debug register 10 */
216    __IM uint32_t RESERVED25[2];
217   __IOM uint32_t PEER_ADDR_INIT_L;              /*!< 0x00000230 Lower 16 bit address of the peer device for INIT. */
218   __IOM uint32_t PEER_ADDR_INIT_M;              /*!< 0x00000234 Middle 16 bit address of the peer device for INIT. */
219   __IOM uint32_t PEER_ADDR_INIT_H;              /*!< 0x00000238 Higher 16 bit address of the peer device for INIT. */
220   __IOM uint32_t PEER_SEC_ADDR_ADV_L;           /*!< 0x0000023C Lower 16 bits of the secondary address of the peer device for
221                                                                 ADV_DIR. */
222   __IOM uint32_t PEER_SEC_ADDR_ADV_M;           /*!< 0x00000240 Middle 16 bits of the secondary address of the peer device for
223                                                                 ADV_DIR. */
224   __IOM uint32_t PEER_SEC_ADDR_ADV_H;           /*!< 0x00000244 Higher 16 bits of the secondary address of the peer device for
225                                                                 ADV_DIR. */
226   __IOM uint32_t INIT_WINDOW_TIMER_CTRL;        /*!< 0x00000248 Initiator Window NI timer control */
227   __IOM uint32_t CONN_CONFIG_EXT;               /*!< 0x0000024C Connection extended configuration register */
228    __IM uint32_t RESERVED26[2];
229   __IOM uint32_t DPLL_CONFIG;                   /*!< 0x00000258 DPLL & CY Correlator configuration register */
230    __IM uint32_t RESERVED27;
231   __IOM uint32_t INIT_NI_VAL;                   /*!< 0x00000260 Initiator Window NI instant */
232    __IM uint32_t INIT_WINDOW_OFFSET;            /*!< 0x00000264 Initiator Window offset captured at conn request */
233    __IM uint32_t INIT_WINDOW_NI_ANCHOR_PT;      /*!< 0x00000268 Initiator Window NI anchor point captured at conn request */
234    __IM uint32_t RESERVED28[78];
235   __IOM uint32_t CONN_UPDATE_NEW_INTERVAL;      /*!< 0x000003A4 Connection update new interval */
236   __IOM uint32_t CONN_UPDATE_NEW_LATENCY;       /*!< 0x000003A8 Connection update new latency */
237   __IOM uint32_t CONN_UPDATE_NEW_SUP_TO;        /*!< 0x000003AC Connection update new supervision timeout */
238   __IOM uint32_t CONN_UPDATE_NEW_SL_INTERVAL;   /*!< 0x000003B0 Connection update new Slave Latency X Conn interval Value */
239    __IM uint32_t RESERVED29[3];
240   __IOM uint32_t CONN_REQ_WORD0;                /*!< 0x000003C0 Connection request address word 0 */
241   __IOM uint32_t CONN_REQ_WORD1;                /*!< 0x000003C4 Connection request address word 1 */
242   __IOM uint32_t CONN_REQ_WORD2;                /*!< 0x000003C8 Connection request address word 2 */
243   __IOM uint32_t CONN_REQ_WORD3;                /*!< 0x000003CC Connection request address word 3 */
244   __IOM uint32_t CONN_REQ_WORD4;                /*!< 0x000003D0 Connection request address word 4 */
245   __IOM uint32_t CONN_REQ_WORD5;                /*!< 0x000003D4 Connection request address word 5 */
246   __IOM uint32_t CONN_REQ_WORD6;                /*!< 0x000003D8 Connection request address word 6 */
247   __IOM uint32_t CONN_REQ_WORD7;                /*!< 0x000003DC Connection request address word 7 */
248   __IOM uint32_t CONN_REQ_WORD8;                /*!< 0x000003E0 Connection request address word 8 */
249   __IOM uint32_t CONN_REQ_WORD9;                /*!< 0x000003E4 Connection request address word 9 */
250   __IOM uint32_t CONN_REQ_WORD10;               /*!< 0x000003E8 Connection request address word 10 */
251   __IOM uint32_t CONN_REQ_WORD11;               /*!< 0x000003EC Connection request address word 11 */
252    __IM uint32_t RESERVED30[389];
253   __IOM uint32_t PDU_RESP_TIMER;                /*!< 0x00000A04 PDU response timer/Generic Timer (MMMS mode) */
254    __IM uint32_t NEXT_RESP_TIMER_EXP;           /*!< 0x00000A08 Next response timeout instant */
255    __IM uint32_t NEXT_SUP_TO;                   /*!< 0x00000A0C Next supervision timeout instant */
256   __IOM uint32_t LLH_FEATURE_CONFIG;            /*!< 0x00000A10 Feature enable */
257   __IOM uint32_t WIN_MIN_STEP_SIZE;             /*!< 0x00000A14 Window minimum step size */
258   __IOM uint32_t SLV_WIN_ADJ;                   /*!< 0x00000A18 Slave window adjustment */
259   __IOM uint32_t SL_CONN_INTERVAL;              /*!< 0x00000A1C Slave Latency X Conn Interval Value */
260   __IOM uint32_t LE_PING_TIMER_ADDR;            /*!< 0x00000A20 LE Ping connection timer address */
261   __IOM uint32_t LE_PING_TIMER_OFFSET;          /*!< 0x00000A24 LE Ping connection timer offset */
262    __IM uint32_t LE_PING_TIMER_NEXT_EXP;        /*!< 0x00000A28 LE Ping timer next expiry instant */
263    __IM uint32_t LE_PING_TIMER_WRAP_COUNT;      /*!< 0x00000A2C LE Ping Timer wrap count */
264    __IM uint32_t RESERVED31[244];
265   __IOM uint32_t TX_EN_EXT_DELAY;               /*!< 0x00000E00 Transmit enable extension delay */
266   __IOM uint32_t TX_RX_SYNTH_DELAY;             /*!< 0x00000E04 Transmit/Receive enable delay */
267   __IOM uint32_t EXT_PA_LNA_DLY_CNFG;           /*!< 0x00000E08 External TX PA and RX LNA delay configuration */
268    __IM uint32_t RESERVED32;
269   __IOM uint32_t LL_CONFIG;                     /*!< 0x00000E10 Link Layer additional configuration */
270    __IM uint32_t RESERVED33[59];
271   __IOM uint32_t LL_CONTROL;                    /*!< 0x00000F00 LL Backward compatibility */
272   __IOM uint32_t DEV_PA_ADDR_L;                 /*!< 0x00000F04 Device Resolvable/Non-Resolvable Private address lower register */
273   __IOM uint32_t DEV_PA_ADDR_M;                 /*!< 0x00000F08 Device Resolvable/Non-Resolvable Private address middle
274                                                                 register */
275   __IOM uint32_t DEV_PA_ADDR_H;                 /*!< 0x00000F0C Device Resolvable/Non-Resolvable Private address higher
276                                                                 register */
277   __IOM uint32_t RSLV_LIST_ENABLE[16];          /*!< 0x00000F10 Resolving list entry control bit */
278    __IM uint32_t RESERVED34[20];
279   __IOM uint32_t WL_CONNECTION_STATUS;          /*!< 0x00000FA0 whitelist valid entry bit */
280    __IM uint32_t RESERVED35[535];
281   __IOM uint32_t CONN_RXMEM_BASE_ADDR_DLE;      /*!< 0x00001800 DLE Connection RX memory base address */
282    __IM uint32_t RESERVED36[1023];
283   __IOM uint32_t CONN_TXMEM_BASE_ADDR_DLE;      /*!< 0x00002800 DLE Connection TX memory base address */
284    __IM uint32_t RESERVED37[16383];
285   __IOM uint32_t CONN_1_PARAM_MEM_BASE_ADDR;    /*!< 0x00012800 Connection Parameter memory base address for connection 1 */
286    __IM uint32_t RESERVED38[31];
287   __IOM uint32_t CONN_2_PARAM_MEM_BASE_ADDR;    /*!< 0x00012880 Connection Parameter memory base address for connection 2 */
288    __IM uint32_t RESERVED39[31];
289   __IOM uint32_t CONN_3_PARAM_MEM_BASE_ADDR;    /*!< 0x00012900 Connection Parameter memory base address for connection 3 */
290    __IM uint32_t RESERVED40[31];
291   __IOM uint32_t CONN_4_PARAM_MEM_BASE_ADDR;    /*!< 0x00012980 Connection Parameter memory base address for connection 4 */
292    __IM uint32_t RESERVED41[1439];
293   __IOM uint32_t NI_TIMER;                      /*!< 0x00014000 Next Instant Timer */
294   __IOM uint32_t US_OFFSET;                     /*!< 0x00014004 Micro-second Offset */
295   __IOM uint32_t NEXT_CONN;                     /*!< 0x00014008 Next Connection */
296   __IOM uint32_t NI_ABORT;                      /*!< 0x0001400C Abort next scheduled connection */
297    __IM uint32_t RESERVED42[4];
298    __IM uint32_t CONN_NI_STATUS;                /*!< 0x00014020 Connection NI Status */
299    __IM uint32_t NEXT_SUP_TO_STATUS;            /*!< 0x00014024 Next Supervision timeout Status */
300    __IM uint32_t MMMS_CONN_STATUS;              /*!< 0x00014028 Connection Status */
301    __IM uint32_t BT_SLOT_CAPT_STATUS;           /*!< 0x0001402C BT Slot Captured Status */
302    __IM uint32_t US_CAPT_STATUS;                /*!< 0x00014030 Micro-second Capture Status */
303    __IM uint32_t US_OFFSET_STATUS;              /*!< 0x00014034 Micro-second Offset Status */
304    __IM uint32_t ACCU_WINDOW_WIDEN_STATUS;      /*!< 0x00014038 Accumulated Window Widen Status */
305    __IM uint32_t EARLY_INTR_STATUS;             /*!< 0x0001403C Status when early interrupt is raised */
306   __IOM uint32_t MMMS_CONFIG;                   /*!< 0x00014040 Multi-Master Multi-Slave Config */
307    __IM uint32_t US_COUNTER;                    /*!< 0x00014044 Running US of the current BT Slot */
308   __IOM uint32_t US_CAPT_PREV;                  /*!< 0x00014048 Previous captured US of the BT Slot */
309    __IM uint32_t EARLY_INTR_NI;                 /*!< 0x0001404C NI at early interrupt */
310    __IM uint32_t RESERVED43[12];
311    __IM uint32_t MMMS_MASTER_CREATE_BT_CAPT;    /*!< 0x00014080 BT slot capture for master connection creation */
312    __IM uint32_t MMMS_SLAVE_CREATE_BT_CAPT;     /*!< 0x00014084 BT slot capture for slave connection creation */
313    __IM uint32_t MMMS_SLAVE_CREATE_US_CAPT;     /*!< 0x00014088 Micro second capture for slave connection creation */
314    __IM uint32_t RESERVED44[29];
315   __IOM uint32_t MMMS_DATA_MEM_DESCRIPTOR[16];  /*!< 0x00014100 Data buffer descriptor 0 to 15 */
316    __IM uint32_t RESERVED45[48];
317   __IOM uint32_t CONN_1_DATA_LIST_SENT;         /*!< 0x00014200 data list sent update and status for connection 1 */
318   __IOM uint32_t CONN_1_DATA_LIST_ACK;          /*!< 0x00014204 data list ack update and status for connection 1 */
319   __IOM uint32_t CONN_1_CE_DATA_LIST_CFG;       /*!< 0x00014208 Connection specific pause resume for connection 1 */
320    __IM uint32_t RESERVED46;
321   __IOM uint32_t CONN_2_DATA_LIST_SENT;         /*!< 0x00014210 data list sent update and status for connection 2 */
322   __IOM uint32_t CONN_2_DATA_LIST_ACK;          /*!< 0x00014214 data list ack update and status for connection 2 */
323   __IOM uint32_t CONN_2_CE_DATA_LIST_CFG;       /*!< 0x00014218 Connection specific pause resume for connection 2 */
324    __IM uint32_t RESERVED47;
325   __IOM uint32_t CONN_3_DATA_LIST_SENT;         /*!< 0x00014220 data list sent update and status for connection 3 */
326   __IOM uint32_t CONN_3_DATA_LIST_ACK;          /*!< 0x00014224 data list ack update and status for connection 3 */
327   __IOM uint32_t CONN_3_CE_DATA_LIST_CFG;       /*!< 0x00014228 Connection specific pause resume for connection 3 */
328    __IM uint32_t RESERVED48;
329   __IOM uint32_t CONN_4_DATA_LIST_SENT;         /*!< 0x00014230 data list sent update and status for connection 4 */
330   __IOM uint32_t CONN_4_DATA_LIST_ACK;          /*!< 0x00014234 data list ack update and status for connection 4 */
331   __IOM uint32_t CONN_4_CE_DATA_LIST_CFG;       /*!< 0x00014238 Connection specific pause resume for connection 4 */
332    __IM uint32_t RESERVED49[113];
333   __IOM uint32_t MMMS_ADVCH_NI_ENABLE;          /*!< 0x00014400 Enable bits for ADV_NI, SCAN_NI and INIT_NI */
334   __IOM uint32_t MMMS_ADVCH_NI_VALID;           /*!< 0x00014404 Next instant valid for ADV, SCAN, INIT */
335   __IOM uint32_t MMMS_ADVCH_NI_ABORT;           /*!< 0x00014408 Abort the next instant of ADV, SCAN, INIT */
336    __IM uint32_t RESERVED50;
337   __IOM uint32_t CONN_PARAM_NEXT_SUP_TO;        /*!< 0x00014410 Register to configure the supervision timeout for next
338                                                                 scheduled connection */
339   __IOM uint32_t CONN_PARAM_ACC_WIN_WIDEN;      /*!< 0x00014414 Register to configure Accumulated window widening for next
340                                                                 scheduled connection */
341    __IM uint32_t RESERVED51[2];
342   __IOM uint32_t HW_LOAD_OFFSET;                /*!< 0x00014420 Register to configure offset from connection anchor point at
343                                                                 which connection parameter memory should be read */
344    __IM uint32_t ADV_RAND;                      /*!< 0x00014424 Random number generated by Hardware for ADV NI calculation */
345    __IM uint32_t MMMS_RX_PKT_CNTR;              /*!< 0x00014428 Packet Counter of packets in RX FIFO in MMMS mode */
346    __IM uint32_t RESERVED52;
347    __IM uint32_t CONN_RX_PKT_CNTR[8];           /*!< 0x00014430 Packet Counter for Individual connection index */
348    __IM uint32_t RESERVED53[236];
349   __IOM uint32_t WHITELIST_BASE_ADDR;           /*!< 0x00014800 Whitelist base address */
350    __IM uint32_t RESERVED54[47];
351   __IOM uint32_t RSLV_LIST_PEER_IDNTT_BASE_ADDR; /*!< 0x000148C0 Resolving list base address for storing Peer Identity address */
352    __IM uint32_t RESERVED55[47];
353   __IOM uint32_t RSLV_LIST_PEER_RPA_BASE_ADDR;  /*!< 0x00014980 Resolving list base address for storing resolved Peer RPA
354                                                                 address */
355    __IM uint32_t RESERVED56[47];
356   __IOM uint32_t RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR; /*!< 0x00014A40 Resolving list base address for storing Resolved received INITA
357                                                                 RPA */
358    __IM uint32_t RESERVED57[47];
359   __IOM uint32_t RSLV_LIST_TX_INIT_RPA_BASE_ADDR; /*!< 0x00014B00 Resolving list base address for storing generated TX INITA RPA */
360    __IM uint32_t RESERVED58[9535];
361 } BLE_BLELL_V1_Type;                            /*!< Size = 122880 (0x1E000) */
362 
363 /**
364   * \brief Bluetooth Low Energy Subsystem Miscellaneous (BLE_BLESS)
365   */
366 typedef struct {
367    __IM uint32_t RESERVED[24];
368   __IOM uint32_t DDFT_CONFIG;                   /*!< 0x00000060 BLESS DDFT configuration register */
369   __IOM uint32_t XTAL_CLK_DIV_CONFIG;           /*!< 0x00000064 Crystal clock divider configuration register */
370   __IOM uint32_t INTR_STAT;                     /*!< 0x00000068 Link Layer interrupt status register */
371   __IOM uint32_t INTR_MASK;                     /*!< 0x0000006C Link Layer interrupt mask register */
372   __IOM uint32_t LL_CLK_EN;                     /*!< 0x00000070 Link Layer primary clock enable */
373   __IOM uint32_t LF_CLK_CTRL;                   /*!< 0x00000074 BLESS LF clock control and BLESS revision ID indicator */
374   __IOM uint32_t EXT_PA_LNA_CTRL;               /*!< 0x00000078 External TX PA and RX LNA control */
375    __IM uint32_t RESERVED1;
376    __IM uint32_t LL_PKT_RSSI_CH_ENERGY;         /*!< 0x00000080 Link Layer Last Received packet RSSI/Channel energy and channel
377                                                                 number */
378    __IM uint32_t BT_CLOCK_CAPT;                 /*!< 0x00000084 BT clock captured on an LL DSM exit */
379    __IM uint32_t RESERVED2[6];
380   __IOM uint32_t MT_CFG;                        /*!< 0x000000A0 MT Configuration Register */
381   __IOM uint32_t MT_DELAY_CFG;                  /*!< 0x000000A4 MT Delay configuration for state transitions */
382   __IOM uint32_t MT_DELAY_CFG2;                 /*!< 0x000000A8 MT Delay configuration for state transitions */
383   __IOM uint32_t MT_DELAY_CFG3;                 /*!< 0x000000AC MT Delay configuration for state transitions */
384   __IOM uint32_t MT_VIO_CTRL;                   /*!< 0x000000B0 MT Configuration Register to control VIO switches */
385    __IM uint32_t MT_STATUS;                     /*!< 0x000000B4 MT Status Register */
386    __IM uint32_t PWR_CTRL_SM_ST;                /*!< 0x000000B8 Link Layer Power Control FSM Status Register */
387    __IM uint32_t RESERVED3;
388   __IOM uint32_t HVLDO_CTRL;                    /*!< 0x000000C0 HVLDO Configuration register */
389   __IOM uint32_t MISC_EN_CTRL;                  /*!< 0x000000C4 Radio Buck and Active regulator enable control */
390    __IM uint32_t RESERVED4[2];
391   __IOM uint32_t EFUSE_CONFIG;                  /*!< 0x000000D0 EFUSE mode configuration register */
392   __IOM uint32_t EFUSE_TIM_CTRL1;               /*!< 0x000000D4 EFUSE timing control register (common for Program and Read
393                                                                 modes) */
394   __IOM uint32_t EFUSE_TIM_CTRL2;               /*!< 0x000000D8 EFUSE timing control Register (for Read) */
395   __IOM uint32_t EFUSE_TIM_CTRL3;               /*!< 0x000000DC EFUSE timing control Register (for Program) */
396    __IM uint32_t EFUSE_RDATA_L;                 /*!< 0x000000E0 EFUSE Lower read data */
397    __IM uint32_t EFUSE_RDATA_H;                 /*!< 0x000000E4 EFUSE higher read data */
398   __IOM uint32_t EFUSE_WDATA_L;                 /*!< 0x000000E8 EFUSE lower write word */
399   __IOM uint32_t EFUSE_WDATA_H;                 /*!< 0x000000EC EFUSE higher write word */
400   __IOM uint32_t DIV_BY_625_CFG;                /*!< 0x000000F0 Divide by 625 for FW Use */
401    __IM uint32_t DIV_BY_625_STS;                /*!< 0x000000F4 Output of divide by 625 divider */
402    __IM uint32_t RESERVED5[2];
403   __IOM uint32_t PACKET_COUNTER0;               /*!< 0x00000100 Packet counter 0 */
404   __IOM uint32_t PACKET_COUNTER2;               /*!< 0x00000104 Packet counter 2 */
405   __IOM uint32_t IV_MASTER0;                    /*!< 0x00000108 Master Initialization Vector 0 */
406   __IOM uint32_t IV_SLAVE0;                     /*!< 0x0000010C Slave Initialization Vector 0 */
407    __OM uint32_t ENC_KEY[4];                    /*!< 0x00000110 Encryption Key register 0-3 */
408   __IOM uint32_t MIC_IN0;                       /*!< 0x00000120 MIC input register */
409    __IM uint32_t MIC_OUT0;                      /*!< 0x00000124 MIC output register */
410   __IOM uint32_t ENC_PARAMS;                    /*!< 0x00000128 Encryption Parameter register */
411   __IOM uint32_t ENC_CONFIG;                    /*!< 0x0000012C Encryption Configuration */
412   __IOM uint32_t ENC_INTR_EN;                   /*!< 0x00000130 Encryption Interrupt enable */
413   __IOM uint32_t ENC_INTR;                      /*!< 0x00000134 Encryption Interrupt status and clear register */
414    __IM uint32_t RESERVED6[2];
415   __IOM uint32_t B1_DATA_REG[4];                /*!< 0x00000140 Programmable B1 Data register (0-3) */
416   __IOM uint32_t ENC_MEM_BASE_ADDR;             /*!< 0x00000150 Encryption memory base address */
417    __IM uint32_t RESERVED7[875];
418   __IOM uint32_t TRIM_LDO_0;                    /*!< 0x00000F00 LDO Trim register 0 */
419   __IOM uint32_t TRIM_LDO_1;                    /*!< 0x00000F04 LDO Trim register 1 */
420   __IOM uint32_t TRIM_LDO_2;                    /*!< 0x00000F08 LDO Trim register 2 */
421   __IOM uint32_t TRIM_LDO_3;                    /*!< 0x00000F0C LDO Trim register 3 */
422   __IOM uint32_t TRIM_MXD[4];                   /*!< 0x00000F10 MXD die Trim registers */
423    __IM uint32_t RESERVED8[4];
424   __IOM uint32_t TRIM_LDO_4;                    /*!< 0x00000F30 LDO Trim register 4 */
425   __IOM uint32_t TRIM_LDO_5;                    /*!< 0x00000F34 LDO Trim register 5 */
426    __IM uint32_t RESERVED9[50];
427 } BLE_BLESS_V1_Type;                            /*!< Size = 4096 (0x1000) */
428 
429 /**
430   * \brief Bluetooth Low Energy Subsystem (BLE)
431   */
432 typedef struct {
433         BLE_RCB_V1_Type RCB;                    /*!< 0x00000000 Radio Control Bus (RCB) controller */
434    __IM uint32_t RESERVED[896];
435         BLE_BLELL_V1_Type BLELL;                /*!< 0x00001000 Bluetooth Low Energy Link Layer */
436         BLE_BLESS_V1_Type BLESS;                /*!< 0x0001F000 Bluetooth Low Energy Subsystem Miscellaneous */
437 } BLE_V1_Type;                                  /*!< Size = 131072 (0x20000) */
438 
439 
440 /* BLE_RCB_RCBLL.CTRL */
441 #define BLE_RCB_RCBLL_CTRL_RCBLL_CTRL_Pos       0UL
442 #define BLE_RCB_RCBLL_CTRL_RCBLL_CTRL_Msk       0x1UL
443 #define BLE_RCB_RCBLL_CTRL_RCBLL_CPU_REQ_Pos    1UL
444 #define BLE_RCB_RCBLL_CTRL_RCBLL_CPU_REQ_Msk    0x2UL
445 #define BLE_RCB_RCBLL_CTRL_CPU_SINGLE_WRITE_Pos 2UL
446 #define BLE_RCB_RCBLL_CTRL_CPU_SINGLE_WRITE_Msk 0x4UL
447 #define BLE_RCB_RCBLL_CTRL_CPU_SINGLE_READ_Pos  3UL
448 #define BLE_RCB_RCBLL_CTRL_CPU_SINGLE_READ_Msk  0x8UL
449 #define BLE_RCB_RCBLL_CTRL_ALLOW_CPU_ACCESS_TX_RX_Pos 4UL
450 #define BLE_RCB_RCBLL_CTRL_ALLOW_CPU_ACCESS_TX_RX_Msk 0x10UL
451 #define BLE_RCB_RCBLL_CTRL_ENABLE_RADIO_BOD_Pos 5UL
452 #define BLE_RCB_RCBLL_CTRL_ENABLE_RADIO_BOD_Msk 0x20UL
453 /* BLE_RCB_RCBLL.INTR */
454 #define BLE_RCB_RCBLL_INTR_RCB_LL_DONE_Pos      0UL
455 #define BLE_RCB_RCBLL_INTR_RCB_LL_DONE_Msk      0x1UL
456 #define BLE_RCB_RCBLL_INTR_SINGLE_WRITE_DONE_Pos 2UL
457 #define BLE_RCB_RCBLL_INTR_SINGLE_WRITE_DONE_Msk 0x4UL
458 #define BLE_RCB_RCBLL_INTR_SINGLE_READ_DONE_Pos 3UL
459 #define BLE_RCB_RCBLL_INTR_SINGLE_READ_DONE_Msk 0x8UL
460 /* BLE_RCB_RCBLL.INTR_SET */
461 #define BLE_RCB_RCBLL_INTR_SET_RCB_LL_DONE_Pos  0UL
462 #define BLE_RCB_RCBLL_INTR_SET_RCB_LL_DONE_Msk  0x1UL
463 #define BLE_RCB_RCBLL_INTR_SET_SINGLE_WRITE_DONE_Pos 2UL
464 #define BLE_RCB_RCBLL_INTR_SET_SINGLE_WRITE_DONE_Msk 0x4UL
465 #define BLE_RCB_RCBLL_INTR_SET_SINGLE_READ_DONE_Pos 3UL
466 #define BLE_RCB_RCBLL_INTR_SET_SINGLE_READ_DONE_Msk 0x8UL
467 /* BLE_RCB_RCBLL.INTR_MASK */
468 #define BLE_RCB_RCBLL_INTR_MASK_RCB_LL_DONE_Pos 0UL
469 #define BLE_RCB_RCBLL_INTR_MASK_RCB_LL_DONE_Msk 0x1UL
470 #define BLE_RCB_RCBLL_INTR_MASK_SINGLE_WRITE_DONE_Pos 2UL
471 #define BLE_RCB_RCBLL_INTR_MASK_SINGLE_WRITE_DONE_Msk 0x4UL
472 #define BLE_RCB_RCBLL_INTR_MASK_SINGLE_READ_DONE_Pos 3UL
473 #define BLE_RCB_RCBLL_INTR_MASK_SINGLE_READ_DONE_Msk 0x8UL
474 /* BLE_RCB_RCBLL.INTR_MASKED */
475 #define BLE_RCB_RCBLL_INTR_MASKED_RCB_LL_DONE_Pos 0UL
476 #define BLE_RCB_RCBLL_INTR_MASKED_RCB_LL_DONE_Msk 0x1UL
477 #define BLE_RCB_RCBLL_INTR_MASKED_SINGLE_WRITE_DONE_Pos 2UL
478 #define BLE_RCB_RCBLL_INTR_MASKED_SINGLE_WRITE_DONE_Msk 0x4UL
479 #define BLE_RCB_RCBLL_INTR_MASKED_SINGLE_READ_DONE_Pos 3UL
480 #define BLE_RCB_RCBLL_INTR_MASKED_SINGLE_READ_DONE_Msk 0x8UL
481 /* BLE_RCB_RCBLL.RADIO_REG1_ADDR */
482 #define BLE_RCB_RCBLL_RADIO_REG1_ADDR_REG_ADDR_Pos 0UL
483 #define BLE_RCB_RCBLL_RADIO_REG1_ADDR_REG_ADDR_Msk 0xFFFFUL
484 /* BLE_RCB_RCBLL.RADIO_REG2_ADDR */
485 #define BLE_RCB_RCBLL_RADIO_REG2_ADDR_REG_ADDR_Pos 0UL
486 #define BLE_RCB_RCBLL_RADIO_REG2_ADDR_REG_ADDR_Msk 0xFFFFUL
487 /* BLE_RCB_RCBLL.RADIO_REG3_ADDR */
488 #define BLE_RCB_RCBLL_RADIO_REG3_ADDR_REG_ADDR_Pos 0UL
489 #define BLE_RCB_RCBLL_RADIO_REG3_ADDR_REG_ADDR_Msk 0xFFFFUL
490 /* BLE_RCB_RCBLL.RADIO_REG4_ADDR */
491 #define BLE_RCB_RCBLL_RADIO_REG4_ADDR_REG_ADDR_Pos 0UL
492 #define BLE_RCB_RCBLL_RADIO_REG4_ADDR_REG_ADDR_Msk 0xFFFFUL
493 /* BLE_RCB_RCBLL.RADIO_REG5_ADDR */
494 #define BLE_RCB_RCBLL_RADIO_REG5_ADDR_REG_ADDR_Pos 0UL
495 #define BLE_RCB_RCBLL_RADIO_REG5_ADDR_REG_ADDR_Msk 0xFFFFUL
496 /* BLE_RCB_RCBLL.CPU_WRITE_REG */
497 #define BLE_RCB_RCBLL_CPU_WRITE_REG_ADDR_Pos    0UL
498 #define BLE_RCB_RCBLL_CPU_WRITE_REG_ADDR_Msk    0xFFFFUL
499 #define BLE_RCB_RCBLL_CPU_WRITE_REG_WRITE_DATA_Pos 16UL
500 #define BLE_RCB_RCBLL_CPU_WRITE_REG_WRITE_DATA_Msk 0xFFFF0000UL
501 /* BLE_RCB_RCBLL.CPU_READ_REG */
502 #define BLE_RCB_RCBLL_CPU_READ_REG_ADDR_Pos     0UL
503 #define BLE_RCB_RCBLL_CPU_READ_REG_ADDR_Msk     0xFFFFUL
504 #define BLE_RCB_RCBLL_CPU_READ_REG_READ_DATA_Pos 16UL
505 #define BLE_RCB_RCBLL_CPU_READ_REG_READ_DATA_Msk 0xFFFF0000UL
506 
507 
508 /* BLE_RCB.CTRL */
509 #define BLE_RCB_CTRL_TX_CLK_EDGE_Pos            1UL
510 #define BLE_RCB_CTRL_TX_CLK_EDGE_Msk            0x2UL
511 #define BLE_RCB_CTRL_RX_CLK_EDGE_Pos            2UL
512 #define BLE_RCB_CTRL_RX_CLK_EDGE_Msk            0x4UL
513 #define BLE_RCB_CTRL_RX_CLK_SRC_Pos             3UL
514 #define BLE_RCB_CTRL_RX_CLK_SRC_Msk             0x8UL
515 #define BLE_RCB_CTRL_SCLK_CONTINUOUS_Pos        4UL
516 #define BLE_RCB_CTRL_SCLK_CONTINUOUS_Msk        0x10UL
517 #define BLE_RCB_CTRL_SSEL_POLARITY_Pos          5UL
518 #define BLE_RCB_CTRL_SSEL_POLARITY_Msk          0x20UL
519 #define BLE_RCB_CTRL_LEAD_Pos                   8UL
520 #define BLE_RCB_CTRL_LEAD_Msk                   0x300UL
521 #define BLE_RCB_CTRL_LAG_Pos                    10UL
522 #define BLE_RCB_CTRL_LAG_Msk                    0xC00UL
523 #define BLE_RCB_CTRL_DIV_ENABLED_Pos            12UL
524 #define BLE_RCB_CTRL_DIV_ENABLED_Msk            0x1000UL
525 #define BLE_RCB_CTRL_DIV_Pos                    13UL
526 #define BLE_RCB_CTRL_DIV_Msk                    0x7E000UL
527 #define BLE_RCB_CTRL_ADDR_WIDTH_Pos             19UL
528 #define BLE_RCB_CTRL_ADDR_WIDTH_Msk             0x780000UL
529 #define BLE_RCB_CTRL_DATA_WIDTH_Pos             23UL
530 #define BLE_RCB_CTRL_DATA_WIDTH_Msk             0x800000UL
531 #define BLE_RCB_CTRL_ENABLED_Pos                31UL
532 #define BLE_RCB_CTRL_ENABLED_Msk                0x80000000UL
533 /* BLE_RCB.STATUS */
534 #define BLE_RCB_STATUS_BUS_BUSY_Pos             0UL
535 #define BLE_RCB_STATUS_BUS_BUSY_Msk             0x1UL
536 /* BLE_RCB.TX_CTRL */
537 #define BLE_RCB_TX_CTRL_MSB_FIRST_Pos           0UL
538 #define BLE_RCB_TX_CTRL_MSB_FIRST_Msk           0x1UL
539 #define BLE_RCB_TX_CTRL_FIFO_RECONFIG_Pos       1UL
540 #define BLE_RCB_TX_CTRL_FIFO_RECONFIG_Msk       0x2UL
541 #define BLE_RCB_TX_CTRL_TX_ENTRIES_Pos          2UL
542 #define BLE_RCB_TX_CTRL_TX_ENTRIES_Msk          0x7CUL
543 /* BLE_RCB.TX_FIFO_CTRL */
544 #define BLE_RCB_TX_FIFO_CTRL_TX_TRIGGER_LEVEL_Pos 0UL
545 #define BLE_RCB_TX_FIFO_CTRL_TX_TRIGGER_LEVEL_Msk 0x1FUL
546 #define BLE_RCB_TX_FIFO_CTRL_CLEAR_Pos          16UL
547 #define BLE_RCB_TX_FIFO_CTRL_CLEAR_Msk          0x10000UL
548 /* BLE_RCB.TX_FIFO_STATUS */
549 #define BLE_RCB_TX_FIFO_STATUS_USED_Pos         0UL
550 #define BLE_RCB_TX_FIFO_STATUS_USED_Msk         0x1FUL
551 #define BLE_RCB_TX_FIFO_STATUS_SR_VALID_Pos     15UL
552 #define BLE_RCB_TX_FIFO_STATUS_SR_VALID_Msk     0x8000UL
553 #define BLE_RCB_TX_FIFO_STATUS_RD_PTR_Pos       16UL
554 #define BLE_RCB_TX_FIFO_STATUS_RD_PTR_Msk       0xF0000UL
555 #define BLE_RCB_TX_FIFO_STATUS_WR_PTR_Pos       24UL
556 #define BLE_RCB_TX_FIFO_STATUS_WR_PTR_Msk       0xF000000UL
557 /* BLE_RCB.TX_FIFO_WR */
558 #define BLE_RCB_TX_FIFO_WR_DATA_Pos             0UL
559 #define BLE_RCB_TX_FIFO_WR_DATA_Msk             0xFFFFFFFFUL
560 /* BLE_RCB.RX_CTRL */
561 #define BLE_RCB_RX_CTRL_MSB_FIRST_Pos           0UL
562 #define BLE_RCB_RX_CTRL_MSB_FIRST_Msk           0x1UL
563 /* BLE_RCB.RX_FIFO_CTRL */
564 #define BLE_RCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Pos  0UL
565 #define BLE_RCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Msk  0xFUL
566 #define BLE_RCB_RX_FIFO_CTRL_CLEAR_Pos          16UL
567 #define BLE_RCB_RX_FIFO_CTRL_CLEAR_Msk          0x10000UL
568 /* BLE_RCB.RX_FIFO_STATUS */
569 #define BLE_RCB_RX_FIFO_STATUS_USED_Pos         0UL
570 #define BLE_RCB_RX_FIFO_STATUS_USED_Msk         0x1FUL
571 #define BLE_RCB_RX_FIFO_STATUS_SR_VALID_Pos     15UL
572 #define BLE_RCB_RX_FIFO_STATUS_SR_VALID_Msk     0x8000UL
573 #define BLE_RCB_RX_FIFO_STATUS_RD_PTR_Pos       16UL
574 #define BLE_RCB_RX_FIFO_STATUS_RD_PTR_Msk       0xF0000UL
575 #define BLE_RCB_RX_FIFO_STATUS_WR_PTR_Pos       24UL
576 #define BLE_RCB_RX_FIFO_STATUS_WR_PTR_Msk       0xF000000UL
577 /* BLE_RCB.RX_FIFO_RD */
578 #define BLE_RCB_RX_FIFO_RD_DATA_Pos             0UL
579 #define BLE_RCB_RX_FIFO_RD_DATA_Msk             0xFFFFFFFFUL
580 /* BLE_RCB.RX_FIFO_RD_SILENT */
581 #define BLE_RCB_RX_FIFO_RD_SILENT_DATA_Pos      0UL
582 #define BLE_RCB_RX_FIFO_RD_SILENT_DATA_Msk      0xFFFFFFFFUL
583 /* BLE_RCB.INTR */
584 #define BLE_RCB_INTR_RCB_DONE_Pos               0UL
585 #define BLE_RCB_INTR_RCB_DONE_Msk               0x1UL
586 #define BLE_RCB_INTR_TX_FIFO_TRIGGER_Pos        8UL
587 #define BLE_RCB_INTR_TX_FIFO_TRIGGER_Msk        0x100UL
588 #define BLE_RCB_INTR_TX_FIFO_NOT_FULL_Pos       9UL
589 #define BLE_RCB_INTR_TX_FIFO_NOT_FULL_Msk       0x200UL
590 #define BLE_RCB_INTR_TX_FIFO_EMPTY_Pos          10UL
591 #define BLE_RCB_INTR_TX_FIFO_EMPTY_Msk          0x400UL
592 #define BLE_RCB_INTR_TX_FIFO_OVERFLOW_Pos       11UL
593 #define BLE_RCB_INTR_TX_FIFO_OVERFLOW_Msk       0x800UL
594 #define BLE_RCB_INTR_TX_FIFO_UNDERFLOW_Pos      12UL
595 #define BLE_RCB_INTR_TX_FIFO_UNDERFLOW_Msk      0x1000UL
596 #define BLE_RCB_INTR_RX_FIFO_TRIGGER_Pos        16UL
597 #define BLE_RCB_INTR_RX_FIFO_TRIGGER_Msk        0x10000UL
598 #define BLE_RCB_INTR_RX_FIFO_NOT_EMPTY_Pos      17UL
599 #define BLE_RCB_INTR_RX_FIFO_NOT_EMPTY_Msk      0x20000UL
600 #define BLE_RCB_INTR_RX_FIFO_FULL_Pos           18UL
601 #define BLE_RCB_INTR_RX_FIFO_FULL_Msk           0x40000UL
602 #define BLE_RCB_INTR_RX_FIFO_OVERFLOW_Pos       19UL
603 #define BLE_RCB_INTR_RX_FIFO_OVERFLOW_Msk       0x80000UL
604 #define BLE_RCB_INTR_RX_FIFO_UNDERFLOW_Pos      20UL
605 #define BLE_RCB_INTR_RX_FIFO_UNDERFLOW_Msk      0x100000UL
606 /* BLE_RCB.INTR_SET */
607 #define BLE_RCB_INTR_SET_RCB_DONE_Pos           0UL
608 #define BLE_RCB_INTR_SET_RCB_DONE_Msk           0x1UL
609 #define BLE_RCB_INTR_SET_TX_FIFO_TRIGGER_Pos    8UL
610 #define BLE_RCB_INTR_SET_TX_FIFO_TRIGGER_Msk    0x100UL
611 #define BLE_RCB_INTR_SET_TX_FIFO_NOT_FULL_Pos   9UL
612 #define BLE_RCB_INTR_SET_TX_FIFO_NOT_FULL_Msk   0x200UL
613 #define BLE_RCB_INTR_SET_TX_FIFO_EMPTY_Pos      10UL
614 #define BLE_RCB_INTR_SET_TX_FIFO_EMPTY_Msk      0x400UL
615 #define BLE_RCB_INTR_SET_TX_FIFO_OVERFLOW_Pos   11UL
616 #define BLE_RCB_INTR_SET_TX_FIFO_OVERFLOW_Msk   0x800UL
617 #define BLE_RCB_INTR_SET_TX_FIFO_UNDERFLOW_Pos  12UL
618 #define BLE_RCB_INTR_SET_TX_FIFO_UNDERFLOW_Msk  0x1000UL
619 #define BLE_RCB_INTR_SET_RX_FIFO_TRIGGER_Pos    16UL
620 #define BLE_RCB_INTR_SET_RX_FIFO_TRIGGER_Msk    0x10000UL
621 #define BLE_RCB_INTR_SET_RX_FIFO_NOT_EMPTY_Pos  17UL
622 #define BLE_RCB_INTR_SET_RX_FIFO_NOT_EMPTY_Msk  0x20000UL
623 #define BLE_RCB_INTR_SET_RX_FIFO_FULL_Pos       18UL
624 #define BLE_RCB_INTR_SET_RX_FIFO_FULL_Msk       0x40000UL
625 #define BLE_RCB_INTR_SET_RX_FIFO_OVERFLOW_Pos   19UL
626 #define BLE_RCB_INTR_SET_RX_FIFO_OVERFLOW_Msk   0x80000UL
627 #define BLE_RCB_INTR_SET_RX_FIFO_UNDERFLOW_Pos  20UL
628 #define BLE_RCB_INTR_SET_RX_FIFO_UNDERFLOW_Msk  0x100000UL
629 /* BLE_RCB.INTR_MASK */
630 #define BLE_RCB_INTR_MASK_RCB_DONE_Pos          0UL
631 #define BLE_RCB_INTR_MASK_RCB_DONE_Msk          0x1UL
632 #define BLE_RCB_INTR_MASK_TX_FIFO_TRIGGER_Pos   8UL
633 #define BLE_RCB_INTR_MASK_TX_FIFO_TRIGGER_Msk   0x100UL
634 #define BLE_RCB_INTR_MASK_TX_FIFO_NOT_FULL_Pos  9UL
635 #define BLE_RCB_INTR_MASK_TX_FIFO_NOT_FULL_Msk  0x200UL
636 #define BLE_RCB_INTR_MASK_TX_FIFO_EMPTY_Pos     10UL
637 #define BLE_RCB_INTR_MASK_TX_FIFO_EMPTY_Msk     0x400UL
638 #define BLE_RCB_INTR_MASK_TX_FIFO_OVERFLOW_Pos  11UL
639 #define BLE_RCB_INTR_MASK_TX_FIFO_OVERFLOW_Msk  0x800UL
640 #define BLE_RCB_INTR_MASK_TX_FIFO_UNDERFLOW_Pos 12UL
641 #define BLE_RCB_INTR_MASK_TX_FIFO_UNDERFLOW_Msk 0x1000UL
642 #define BLE_RCB_INTR_MASK_RX_FIFO_TRIGGER_Pos   16UL
643 #define BLE_RCB_INTR_MASK_RX_FIFO_TRIGGER_Msk   0x10000UL
644 #define BLE_RCB_INTR_MASK_RX_FIFO_NOT_EMPTY_Pos 17UL
645 #define BLE_RCB_INTR_MASK_RX_FIFO_NOT_EMPTY_Msk 0x20000UL
646 #define BLE_RCB_INTR_MASK_RX_FIFO_FULL_Pos      18UL
647 #define BLE_RCB_INTR_MASK_RX_FIFO_FULL_Msk      0x40000UL
648 #define BLE_RCB_INTR_MASK_RX_FIFO_OVERFLOW_Pos  19UL
649 #define BLE_RCB_INTR_MASK_RX_FIFO_OVERFLOW_Msk  0x80000UL
650 #define BLE_RCB_INTR_MASK_RX_FIFO_UNDERFLOW_Pos 20UL
651 #define BLE_RCB_INTR_MASK_RX_FIFO_UNDERFLOW_Msk 0x100000UL
652 /* BLE_RCB.INTR_MASKED */
653 #define BLE_RCB_INTR_MASKED_RCB_DONE_Pos        0UL
654 #define BLE_RCB_INTR_MASKED_RCB_DONE_Msk        0x1UL
655 #define BLE_RCB_INTR_MASKED_TX_FIFO_TRIGGER_Pos 8UL
656 #define BLE_RCB_INTR_MASKED_TX_FIFO_TRIGGER_Msk 0x100UL
657 #define BLE_RCB_INTR_MASKED_TX_FIFO_NOT_FULL_Pos 9UL
658 #define BLE_RCB_INTR_MASKED_TX_FIFO_NOT_FULL_Msk 0x200UL
659 #define BLE_RCB_INTR_MASKED_TX_FIFO_EMPTY_Pos   10UL
660 #define BLE_RCB_INTR_MASKED_TX_FIFO_EMPTY_Msk   0x400UL
661 #define BLE_RCB_INTR_MASKED_TX_FIFO_OVERFLOW_Pos 11UL
662 #define BLE_RCB_INTR_MASKED_TX_FIFO_OVERFLOW_Msk 0x800UL
663 #define BLE_RCB_INTR_MASKED_TX_FIFO_UNDERFLOW_Pos 12UL
664 #define BLE_RCB_INTR_MASKED_TX_FIFO_UNDERFLOW_Msk 0x1000UL
665 #define BLE_RCB_INTR_MASKED_RX_FIFO_TRIGGER_Pos 16UL
666 #define BLE_RCB_INTR_MASKED_RX_FIFO_TRIGGER_Msk 0x10000UL
667 #define BLE_RCB_INTR_MASKED_RX_FIFO_NOT_EMPTY_Pos 17UL
668 #define BLE_RCB_INTR_MASKED_RX_FIFO_NOT_EMPTY_Msk 0x20000UL
669 #define BLE_RCB_INTR_MASKED_RX_FIFO_FULL_Pos    18UL
670 #define BLE_RCB_INTR_MASKED_RX_FIFO_FULL_Msk    0x40000UL
671 #define BLE_RCB_INTR_MASKED_RX_FIFO_OVERFLOW_Pos 19UL
672 #define BLE_RCB_INTR_MASKED_RX_FIFO_OVERFLOW_Msk 0x80000UL
673 #define BLE_RCB_INTR_MASKED_RX_FIFO_UNDERFLOW_Pos 20UL
674 #define BLE_RCB_INTR_MASKED_RX_FIFO_UNDERFLOW_Msk 0x100000UL
675 
676 
677 /* BLE_BLELL.COMMAND_REGISTER */
678 #define BLE_BLELL_COMMAND_REGISTER_COMMAND_Pos  0UL
679 #define BLE_BLELL_COMMAND_REGISTER_COMMAND_Msk  0xFFUL
680 /* BLE_BLELL.EVENT_INTR */
681 #define BLE_BLELL_EVENT_INTR_ADV_INTR_Pos       0UL
682 #define BLE_BLELL_EVENT_INTR_ADV_INTR_Msk       0x1UL
683 #define BLE_BLELL_EVENT_INTR_SCAN_INTR_Pos      1UL
684 #define BLE_BLELL_EVENT_INTR_SCAN_INTR_Msk      0x2UL
685 #define BLE_BLELL_EVENT_INTR_INIT_INTR_Pos      2UL
686 #define BLE_BLELL_EVENT_INTR_INIT_INTR_Msk      0x4UL
687 #define BLE_BLELL_EVENT_INTR_CONN_INTR_Pos      3UL
688 #define BLE_BLELL_EVENT_INTR_CONN_INTR_Msk      0x8UL
689 #define BLE_BLELL_EVENT_INTR_SM_INTR_Pos        4UL
690 #define BLE_BLELL_EVENT_INTR_SM_INTR_Msk        0x10UL
691 #define BLE_BLELL_EVENT_INTR_DSM_INTR_Pos       5UL
692 #define BLE_BLELL_EVENT_INTR_DSM_INTR_Msk       0x20UL
693 #define BLE_BLELL_EVENT_INTR_ENC_INTR_Pos       6UL
694 #define BLE_BLELL_EVENT_INTR_ENC_INTR_Msk       0x40UL
695 #define BLE_BLELL_EVENT_INTR_RSSI_RX_DONE_INTR_Pos 7UL
696 #define BLE_BLELL_EVENT_INTR_RSSI_RX_DONE_INTR_Msk 0x80UL
697 /* BLE_BLELL.EVENT_ENABLE */
698 #define BLE_BLELL_EVENT_ENABLE_ADV_INT_EN_Pos   0UL
699 #define BLE_BLELL_EVENT_ENABLE_ADV_INT_EN_Msk   0x1UL
700 #define BLE_BLELL_EVENT_ENABLE_SCN_INT_EN_Pos   1UL
701 #define BLE_BLELL_EVENT_ENABLE_SCN_INT_EN_Msk   0x2UL
702 #define BLE_BLELL_EVENT_ENABLE_INIT_INT_EN_Pos  2UL
703 #define BLE_BLELL_EVENT_ENABLE_INIT_INT_EN_Msk  0x4UL
704 #define BLE_BLELL_EVENT_ENABLE_CONN_INT_EN_Pos  3UL
705 #define BLE_BLELL_EVENT_ENABLE_CONN_INT_EN_Msk  0x8UL
706 #define BLE_BLELL_EVENT_ENABLE_SM_INT_EN_Pos    4UL
707 #define BLE_BLELL_EVENT_ENABLE_SM_INT_EN_Msk    0x10UL
708 #define BLE_BLELL_EVENT_ENABLE_DSM_INT_EN_Pos   5UL
709 #define BLE_BLELL_EVENT_ENABLE_DSM_INT_EN_Msk   0x20UL
710 #define BLE_BLELL_EVENT_ENABLE_ENC_INT_EN_Pos   6UL
711 #define BLE_BLELL_EVENT_ENABLE_ENC_INT_EN_Msk   0x40UL
712 #define BLE_BLELL_EVENT_ENABLE_RSSI_RX_DONE_INT_EN_Pos 7UL
713 #define BLE_BLELL_EVENT_ENABLE_RSSI_RX_DONE_INT_EN_Msk 0x80UL
714 /* BLE_BLELL.ADV_PARAMS */
715 #define BLE_BLELL_ADV_PARAMS_TX_ADDR_Pos        0UL
716 #define BLE_BLELL_ADV_PARAMS_TX_ADDR_Msk        0x1UL
717 #define BLE_BLELL_ADV_PARAMS_ADV_TYPE_Pos       1UL
718 #define BLE_BLELL_ADV_PARAMS_ADV_TYPE_Msk       0x6UL
719 #define BLE_BLELL_ADV_PARAMS_ADV_FILT_POLICY_Pos 3UL
720 #define BLE_BLELL_ADV_PARAMS_ADV_FILT_POLICY_Msk 0x18UL
721 #define BLE_BLELL_ADV_PARAMS_ADV_CHANNEL_MAP_Pos 5UL
722 #define BLE_BLELL_ADV_PARAMS_ADV_CHANNEL_MAP_Msk 0xE0UL
723 #define BLE_BLELL_ADV_PARAMS_RX_ADDR_Pos        8UL
724 #define BLE_BLELL_ADV_PARAMS_RX_ADDR_Msk        0x100UL
725 #define BLE_BLELL_ADV_PARAMS_RX_SEC_ADDR_Pos    9UL
726 #define BLE_BLELL_ADV_PARAMS_RX_SEC_ADDR_Msk    0x200UL
727 #define BLE_BLELL_ADV_PARAMS_ADV_LOW_DUTY_CYCLE_Pos 10UL
728 #define BLE_BLELL_ADV_PARAMS_ADV_LOW_DUTY_CYCLE_Msk 0x400UL
729 #define BLE_BLELL_ADV_PARAMS_INITA_RPA_CHECK_Pos 11UL
730 #define BLE_BLELL_ADV_PARAMS_INITA_RPA_CHECK_Msk 0x800UL
731 #define BLE_BLELL_ADV_PARAMS_TX_ADDR_PRIV_Pos   12UL
732 #define BLE_BLELL_ADV_PARAMS_TX_ADDR_PRIV_Msk   0x1000UL
733 #define BLE_BLELL_ADV_PARAMS_ADV_RCV_IA_IN_PRIV_Pos 13UL
734 #define BLE_BLELL_ADV_PARAMS_ADV_RCV_IA_IN_PRIV_Msk 0x2000UL
735 #define BLE_BLELL_ADV_PARAMS_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV_Pos 14UL
736 #define BLE_BLELL_ADV_PARAMS_ADV_RPT_PEER_NRPA_ADDR_IN_PRIV_Msk 0x4000UL
737 #define BLE_BLELL_ADV_PARAMS_RCV_TX_ADDR_Pos    15UL
738 #define BLE_BLELL_ADV_PARAMS_RCV_TX_ADDR_Msk    0x8000UL
739 /* BLE_BLELL.ADV_INTERVAL_TIMEOUT */
740 #define BLE_BLELL_ADV_INTERVAL_TIMEOUT_ADV_INTERVAL_Pos 0UL
741 #define BLE_BLELL_ADV_INTERVAL_TIMEOUT_ADV_INTERVAL_Msk 0x7FFFUL
742 /* BLE_BLELL.ADV_INTR */
743 #define BLE_BLELL_ADV_INTR_ADV_STRT_INTR_Pos    0UL
744 #define BLE_BLELL_ADV_INTR_ADV_STRT_INTR_Msk    0x1UL
745 #define BLE_BLELL_ADV_INTR_ADV_CLOSE_INTR_Pos   1UL
746 #define BLE_BLELL_ADV_INTR_ADV_CLOSE_INTR_Msk   0x2UL
747 #define BLE_BLELL_ADV_INTR_ADV_TX_INTR_Pos      2UL
748 #define BLE_BLELL_ADV_INTR_ADV_TX_INTR_Msk      0x4UL
749 #define BLE_BLELL_ADV_INTR_SCAN_RSP_TX_INTR_Pos 3UL
750 #define BLE_BLELL_ADV_INTR_SCAN_RSP_TX_INTR_Msk 0x8UL
751 #define BLE_BLELL_ADV_INTR_SCAN_REQ_RX_INTR_Pos 4UL
752 #define BLE_BLELL_ADV_INTR_SCAN_REQ_RX_INTR_Msk 0x10UL
753 #define BLE_BLELL_ADV_INTR_CONN_REQ_RX_INTR_Pos 5UL
754 #define BLE_BLELL_ADV_INTR_CONN_REQ_RX_INTR_Msk 0x20UL
755 #define BLE_BLELL_ADV_INTR_SLV_CONNECTED_Pos    6UL
756 #define BLE_BLELL_ADV_INTR_SLV_CONNECTED_Msk    0x40UL
757 #define BLE_BLELL_ADV_INTR_ADV_TIMEOUT_Pos      7UL
758 #define BLE_BLELL_ADV_INTR_ADV_TIMEOUT_Msk      0x80UL
759 #define BLE_BLELL_ADV_INTR_ADV_ON_Pos           8UL
760 #define BLE_BLELL_ADV_INTR_ADV_ON_Msk           0x100UL
761 #define BLE_BLELL_ADV_INTR_SLV_CONN_PEER_RPA_UNMCH_INTR_Pos 9UL
762 #define BLE_BLELL_ADV_INTR_SLV_CONN_PEER_RPA_UNMCH_INTR_Msk 0x200UL
763 #define BLE_BLELL_ADV_INTR_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR_Pos 10UL
764 #define BLE_BLELL_ADV_INTR_SCAN_REQ_RX_PEER_RPA_UNMCH_INTR_Msk 0x400UL
765 #define BLE_BLELL_ADV_INTR_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 11UL
766 #define BLE_BLELL_ADV_INTR_INIT_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x800UL
767 #define BLE_BLELL_ADV_INTR_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 12UL
768 #define BLE_BLELL_ADV_INTR_SCAN_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x1000UL
769 /* BLE_BLELL.ADV_NEXT_INSTANT */
770 #define BLE_BLELL_ADV_NEXT_INSTANT_ADV_NEXT_INSTANT_Pos 0UL
771 #define BLE_BLELL_ADV_NEXT_INSTANT_ADV_NEXT_INSTANT_Msk 0xFFFFUL
772 /* BLE_BLELL.SCAN_INTERVAL */
773 #define BLE_BLELL_SCAN_INTERVAL_SCAN_INTERVAL_Pos 0UL
774 #define BLE_BLELL_SCAN_INTERVAL_SCAN_INTERVAL_Msk 0xFFFFUL
775 /* BLE_BLELL.SCAN_WINDOW */
776 #define BLE_BLELL_SCAN_WINDOW_SCAN_WINDOW_Pos   0UL
777 #define BLE_BLELL_SCAN_WINDOW_SCAN_WINDOW_Msk   0xFFFFUL
778 /* BLE_BLELL.SCAN_PARAM */
779 #define BLE_BLELL_SCAN_PARAM_TX_ADDR_Pos        0UL
780 #define BLE_BLELL_SCAN_PARAM_TX_ADDR_Msk        0x1UL
781 #define BLE_BLELL_SCAN_PARAM_SCAN_TYPE_Pos      1UL
782 #define BLE_BLELL_SCAN_PARAM_SCAN_TYPE_Msk      0x6UL
783 #define BLE_BLELL_SCAN_PARAM_SCAN_FILT_POLICY_Pos 3UL
784 #define BLE_BLELL_SCAN_PARAM_SCAN_FILT_POLICY_Msk 0x18UL
785 #define BLE_BLELL_SCAN_PARAM_DUP_FILT_EN_Pos    5UL
786 #define BLE_BLELL_SCAN_PARAM_DUP_FILT_EN_Msk    0x20UL
787 #define BLE_BLELL_SCAN_PARAM_DUP_FILT_CHK_ADV_DIR_Pos 6UL
788 #define BLE_BLELL_SCAN_PARAM_DUP_FILT_CHK_ADV_DIR_Msk 0x40UL
789 #define BLE_BLELL_SCAN_PARAM_SCAN_RSP_ADVA_CHECK_Pos 7UL
790 #define BLE_BLELL_SCAN_PARAM_SCAN_RSP_ADVA_CHECK_Msk 0x80UL
791 #define BLE_BLELL_SCAN_PARAM_SCAN_RCV_IA_IN_PRIV_Pos 8UL
792 #define BLE_BLELL_SCAN_PARAM_SCAN_RCV_IA_IN_PRIV_Msk 0x100UL
793 #define BLE_BLELL_SCAN_PARAM_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV_Pos 9UL
794 #define BLE_BLELL_SCAN_PARAM_SCAN_RPT_PEER_NRPA_ADDR_IN_PRIV_Msk 0x200UL
795 /* BLE_BLELL.SCAN_INTR */
796 #define BLE_BLELL_SCAN_INTR_SCAN_STRT_INTR_Pos  0UL
797 #define BLE_BLELL_SCAN_INTR_SCAN_STRT_INTR_Msk  0x1UL
798 #define BLE_BLELL_SCAN_INTR_SCAN_CLOSE_INTR_Pos 1UL
799 #define BLE_BLELL_SCAN_INTR_SCAN_CLOSE_INTR_Msk 0x2UL
800 #define BLE_BLELL_SCAN_INTR_SCAN_TX_INTR_Pos    2UL
801 #define BLE_BLELL_SCAN_INTR_SCAN_TX_INTR_Msk    0x4UL
802 #define BLE_BLELL_SCAN_INTR_ADV_RX_INTR_Pos     3UL
803 #define BLE_BLELL_SCAN_INTR_ADV_RX_INTR_Msk     0x8UL
804 #define BLE_BLELL_SCAN_INTR_SCAN_RSP_RX_INTR_Pos 4UL
805 #define BLE_BLELL_SCAN_INTR_SCAN_RSP_RX_INTR_Msk 0x10UL
806 #define BLE_BLELL_SCAN_INTR_ADV_RX_PEER_RPA_UNMCH_INTR_Pos 5UL
807 #define BLE_BLELL_SCAN_INTR_ADV_RX_PEER_RPA_UNMCH_INTR_Msk 0x20UL
808 #define BLE_BLELL_SCAN_INTR_ADV_RX_SELF_RPA_UNMCH_INTR_Pos 6UL
809 #define BLE_BLELL_SCAN_INTR_ADV_RX_SELF_RPA_UNMCH_INTR_Msk 0x40UL
810 #define BLE_BLELL_SCAN_INTR_SCANA_TX_ADDR_NOT_SET_INTR_Pos 7UL
811 #define BLE_BLELL_SCAN_INTR_SCANA_TX_ADDR_NOT_SET_INTR_Msk 0x80UL
812 #define BLE_BLELL_SCAN_INTR_SCAN_ON_Pos         8UL
813 #define BLE_BLELL_SCAN_INTR_SCAN_ON_Msk         0x100UL
814 #define BLE_BLELL_SCAN_INTR_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 9UL
815 #define BLE_BLELL_SCAN_INTR_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x200UL
816 #define BLE_BLELL_SCAN_INTR_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 10UL
817 #define BLE_BLELL_SCAN_INTR_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x400UL
818 /* BLE_BLELL.SCAN_NEXT_INSTANT */
819 #define BLE_BLELL_SCAN_NEXT_INSTANT_NEXT_SCAN_INSTANT_Pos 0UL
820 #define BLE_BLELL_SCAN_NEXT_INSTANT_NEXT_SCAN_INSTANT_Msk 0xFFFFUL
821 /* BLE_BLELL.INIT_INTERVAL */
822 #define BLE_BLELL_INIT_INTERVAL_INIT_SCAN_INTERVAL_Pos 0UL
823 #define BLE_BLELL_INIT_INTERVAL_INIT_SCAN_INTERVAL_Msk 0xFFFFUL
824 /* BLE_BLELL.INIT_WINDOW */
825 #define BLE_BLELL_INIT_WINDOW_INIT_SCAN_WINDOW_Pos 0UL
826 #define BLE_BLELL_INIT_WINDOW_INIT_SCAN_WINDOW_Msk 0xFFFFUL
827 /* BLE_BLELL.INIT_PARAM */
828 #define BLE_BLELL_INIT_PARAM_TX_ADDR_Pos        0UL
829 #define BLE_BLELL_INIT_PARAM_TX_ADDR_Msk        0x1UL
830 #define BLE_BLELL_INIT_PARAM_RX_ADDR__RX_TX_ADDR_Pos 1UL
831 #define BLE_BLELL_INIT_PARAM_RX_ADDR__RX_TX_ADDR_Msk 0x2UL
832 #define BLE_BLELL_INIT_PARAM_INIT_FILT_POLICY_Pos 3UL
833 #define BLE_BLELL_INIT_PARAM_INIT_FILT_POLICY_Msk 0x8UL
834 #define BLE_BLELL_INIT_PARAM_INIT_RCV_IA_IN_PRIV_Pos 4UL
835 #define BLE_BLELL_INIT_PARAM_INIT_RCV_IA_IN_PRIV_Msk 0x10UL
836 /* BLE_BLELL.INIT_INTR */
837 #define BLE_BLELL_INIT_INTR_INIT_INTERVAL_EXPIRE_INTR_Pos 0UL
838 #define BLE_BLELL_INIT_INTR_INIT_INTERVAL_EXPIRE_INTR_Msk 0x1UL
839 #define BLE_BLELL_INIT_INTR_INIT_CLOSE_WINDOW_INR_Pos 1UL
840 #define BLE_BLELL_INIT_INTR_INIT_CLOSE_WINDOW_INR_Msk 0x2UL
841 #define BLE_BLELL_INIT_INTR_INIT_TX_START_INTR_Pos 2UL
842 #define BLE_BLELL_INIT_INTR_INIT_TX_START_INTR_Msk 0x4UL
843 #define BLE_BLELL_INIT_INTR_MASTER_CONN_CREATED_Pos 4UL
844 #define BLE_BLELL_INIT_INTR_MASTER_CONN_CREATED_Msk 0x10UL
845 #define BLE_BLELL_INIT_INTR_ADV_RX_SELF_ADDR_UNMCH_INTR_Pos 5UL
846 #define BLE_BLELL_INIT_INTR_ADV_RX_SELF_ADDR_UNMCH_INTR_Msk 0x20UL
847 #define BLE_BLELL_INIT_INTR_ADV_RX_PEER_ADDR_UNMCH_INTR_Pos 6UL
848 #define BLE_BLELL_INIT_INTR_ADV_RX_PEER_ADDR_UNMCH_INTR_Msk 0x40UL
849 #define BLE_BLELL_INIT_INTR_INITA_TX_ADDR_NOT_SET_INTR_Pos 7UL
850 #define BLE_BLELL_INIT_INTR_INITA_TX_ADDR_NOT_SET_INTR_Msk 0x80UL
851 #define BLE_BLELL_INIT_INTR_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 8UL
852 #define BLE_BLELL_INIT_INTR_INI_PEER_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x100UL
853 #define BLE_BLELL_INIT_INTR_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR_Pos 9UL
854 #define BLE_BLELL_INIT_INTR_INI_SELF_ADDR_MATCH_PRIV_MISMATCH_INTR_Msk 0x200UL
855 /* BLE_BLELL.INIT_NEXT_INSTANT */
856 #define BLE_BLELL_INIT_NEXT_INSTANT_INIT_NEXT_INSTANT_Pos 0UL
857 #define BLE_BLELL_INIT_NEXT_INSTANT_INIT_NEXT_INSTANT_Msk 0xFFFFUL
858 /* BLE_BLELL.DEVICE_RAND_ADDR_L */
859 #define BLE_BLELL_DEVICE_RAND_ADDR_L_DEVICE_RAND_ADDR_L_Pos 0UL
860 #define BLE_BLELL_DEVICE_RAND_ADDR_L_DEVICE_RAND_ADDR_L_Msk 0xFFFFUL
861 /* BLE_BLELL.DEVICE_RAND_ADDR_M */
862 #define BLE_BLELL_DEVICE_RAND_ADDR_M_DEVICE_RAND_ADDR_M_Pos 0UL
863 #define BLE_BLELL_DEVICE_RAND_ADDR_M_DEVICE_RAND_ADDR_M_Msk 0xFFFFUL
864 /* BLE_BLELL.DEVICE_RAND_ADDR_H */
865 #define BLE_BLELL_DEVICE_RAND_ADDR_H_DEVICE_RAND_ADDR_H_Pos 0UL
866 #define BLE_BLELL_DEVICE_RAND_ADDR_H_DEVICE_RAND_ADDR_H_Msk 0xFFFFUL
867 /* BLE_BLELL.PEER_ADDR_L */
868 #define BLE_BLELL_PEER_ADDR_L_PEER_ADDR_L_Pos   0UL
869 #define BLE_BLELL_PEER_ADDR_L_PEER_ADDR_L_Msk   0xFFFFUL
870 /* BLE_BLELL.PEER_ADDR_M */
871 #define BLE_BLELL_PEER_ADDR_M_PEER_ADDR_M_Pos   0UL
872 #define BLE_BLELL_PEER_ADDR_M_PEER_ADDR_M_Msk   0xFFFFUL
873 /* BLE_BLELL.PEER_ADDR_H */
874 #define BLE_BLELL_PEER_ADDR_H_PEER_ADDR_H_Pos   0UL
875 #define BLE_BLELL_PEER_ADDR_H_PEER_ADDR_H_Msk   0xFFFFUL
876 /* BLE_BLELL.WL_ADDR_TYPE */
877 #define BLE_BLELL_WL_ADDR_TYPE_WL_ADDR_TYPE_Pos 0UL
878 #define BLE_BLELL_WL_ADDR_TYPE_WL_ADDR_TYPE_Msk 0xFFFFUL
879 /* BLE_BLELL.WL_ENABLE */
880 #define BLE_BLELL_WL_ENABLE_WL_ENABLE_Pos       0UL
881 #define BLE_BLELL_WL_ENABLE_WL_ENABLE_Msk       0xFFFFUL
882 /* BLE_BLELL.TRANSMIT_WINDOW_OFFSET */
883 #define BLE_BLELL_TRANSMIT_WINDOW_OFFSET_TX_WINDOW_OFFSET_Pos 0UL
884 #define BLE_BLELL_TRANSMIT_WINDOW_OFFSET_TX_WINDOW_OFFSET_Msk 0xFFFFUL
885 /* BLE_BLELL.TRANSMIT_WINDOW_SIZE */
886 #define BLE_BLELL_TRANSMIT_WINDOW_SIZE_TX_WINDOW_SIZE_Pos 0UL
887 #define BLE_BLELL_TRANSMIT_WINDOW_SIZE_TX_WINDOW_SIZE_Msk 0xFFUL
888 /* BLE_BLELL.DATA_CHANNELS_L0 */
889 #define BLE_BLELL_DATA_CHANNELS_L0_DATA_CHANNELS_L0_Pos 0UL
890 #define BLE_BLELL_DATA_CHANNELS_L0_DATA_CHANNELS_L0_Msk 0xFFFFUL
891 /* BLE_BLELL.DATA_CHANNELS_M0 */
892 #define BLE_BLELL_DATA_CHANNELS_M0_DATA_CHANNELS_M0_Pos 0UL
893 #define BLE_BLELL_DATA_CHANNELS_M0_DATA_CHANNELS_M0_Msk 0xFFFFUL
894 /* BLE_BLELL.DATA_CHANNELS_H0 */
895 #define BLE_BLELL_DATA_CHANNELS_H0_DATA_CHANNELS_H0_Pos 0UL
896 #define BLE_BLELL_DATA_CHANNELS_H0_DATA_CHANNELS_H0_Msk 0x1FUL
897 /* BLE_BLELL.DATA_CHANNELS_L1 */
898 #define BLE_BLELL_DATA_CHANNELS_L1_DATA_CHANNELS_L1_Pos 0UL
899 #define BLE_BLELL_DATA_CHANNELS_L1_DATA_CHANNELS_L1_Msk 0xFFFFUL
900 /* BLE_BLELL.DATA_CHANNELS_M1 */
901 #define BLE_BLELL_DATA_CHANNELS_M1_DATA_CHANNELS_M1_Pos 0UL
902 #define BLE_BLELL_DATA_CHANNELS_M1_DATA_CHANNELS_M1_Msk 0xFFFFUL
903 /* BLE_BLELL.DATA_CHANNELS_H1 */
904 #define BLE_BLELL_DATA_CHANNELS_H1_DATA_CHANNELS_H1_Pos 0UL
905 #define BLE_BLELL_DATA_CHANNELS_H1_DATA_CHANNELS_H1_Msk 0x1FUL
906 /* BLE_BLELL.CONN_INTR */
907 #define BLE_BLELL_CONN_INTR_CONN_CLOSED_Pos     0UL
908 #define BLE_BLELL_CONN_INTR_CONN_CLOSED_Msk     0x1UL
909 #define BLE_BLELL_CONN_INTR_CONN_ESTB_Pos       1UL
910 #define BLE_BLELL_CONN_INTR_CONN_ESTB_Msk       0x2UL
911 #define BLE_BLELL_CONN_INTR_MAP_UPDT_DONE_Pos   2UL
912 #define BLE_BLELL_CONN_INTR_MAP_UPDT_DONE_Msk   0x4UL
913 #define BLE_BLELL_CONN_INTR_START_CE_Pos        3UL
914 #define BLE_BLELL_CONN_INTR_START_CE_Msk        0x8UL
915 #define BLE_BLELL_CONN_INTR_CLOSE_CE_Pos        4UL
916 #define BLE_BLELL_CONN_INTR_CLOSE_CE_Msk        0x10UL
917 #define BLE_BLELL_CONN_INTR_CE_TX_ACK_Pos       5UL
918 #define BLE_BLELL_CONN_INTR_CE_TX_ACK_Msk       0x20UL
919 #define BLE_BLELL_CONN_INTR_CE_RX_Pos           6UL
920 #define BLE_BLELL_CONN_INTR_CE_RX_Msk           0x40UL
921 #define BLE_BLELL_CONN_INTR_CON_UPDT_DONE_Pos   7UL
922 #define BLE_BLELL_CONN_INTR_CON_UPDT_DONE_Msk   0x80UL
923 #define BLE_BLELL_CONN_INTR_DISCON_STATUS_Pos   8UL
924 #define BLE_BLELL_CONN_INTR_DISCON_STATUS_Msk   0x700UL
925 #define BLE_BLELL_CONN_INTR_RX_PDU_STATUS_Pos   11UL
926 #define BLE_BLELL_CONN_INTR_RX_PDU_STATUS_Msk   0x3800UL
927 #define BLE_BLELL_CONN_INTR_PING_TIMER_EXPIRD_INTR_Pos 14UL
928 #define BLE_BLELL_CONN_INTR_PING_TIMER_EXPIRD_INTR_Msk 0x4000UL
929 #define BLE_BLELL_CONN_INTR_PING_NEARLY_EXPIRD_INTR_Pos 15UL
930 #define BLE_BLELL_CONN_INTR_PING_NEARLY_EXPIRD_INTR_Msk 0x8000UL
931 /* BLE_BLELL.CONN_STATUS */
932 #define BLE_BLELL_CONN_STATUS_RECEIVE_PACKET_COUNT_Pos 12UL
933 #define BLE_BLELL_CONN_STATUS_RECEIVE_PACKET_COUNT_Msk 0xF000UL
934 /* BLE_BLELL.CONN_INDEX */
935 #define BLE_BLELL_CONN_INDEX_CONN_INDEX_Pos     0UL
936 #define BLE_BLELL_CONN_INDEX_CONN_INDEX_Msk     0xFFFFUL
937 /* BLE_BLELL.WAKEUP_CONFIG */
938 #define BLE_BLELL_WAKEUP_CONFIG_OSC_STARTUP_DELAY_Pos 0UL
939 #define BLE_BLELL_WAKEUP_CONFIG_OSC_STARTUP_DELAY_Msk 0xFFUL
940 #define BLE_BLELL_WAKEUP_CONFIG_DSM_OFFSET_TO_WAKEUP_INSTANT_Pos 10UL
941 #define BLE_BLELL_WAKEUP_CONFIG_DSM_OFFSET_TO_WAKEUP_INSTANT_Msk 0xFC00UL
942 /* BLE_BLELL.WAKEUP_CONTROL */
943 #define BLE_BLELL_WAKEUP_CONTROL_WAKEUP_INSTANT_Pos 0UL
944 #define BLE_BLELL_WAKEUP_CONTROL_WAKEUP_INSTANT_Msk 0xFFFFUL
945 /* BLE_BLELL.CLOCK_CONFIG */
946 #define BLE_BLELL_CLOCK_CONFIG_ADV_CLK_GATE_EN_Pos 0UL
947 #define BLE_BLELL_CLOCK_CONFIG_ADV_CLK_GATE_EN_Msk 0x1UL
948 #define BLE_BLELL_CLOCK_CONFIG_SCAN_CLK_GATE_EN_Pos 1UL
949 #define BLE_BLELL_CLOCK_CONFIG_SCAN_CLK_GATE_EN_Msk 0x2UL
950 #define BLE_BLELL_CLOCK_CONFIG_INIT_CLK_GATE_EN_Pos 2UL
951 #define BLE_BLELL_CLOCK_CONFIG_INIT_CLK_GATE_EN_Msk 0x4UL
952 #define BLE_BLELL_CLOCK_CONFIG_CONN_CLK_GATE_EN_Pos 3UL
953 #define BLE_BLELL_CLOCK_CONFIG_CONN_CLK_GATE_EN_Msk 0x8UL
954 #define BLE_BLELL_CLOCK_CONFIG_CORECLK_GATE_EN_Pos 4UL
955 #define BLE_BLELL_CLOCK_CONFIG_CORECLK_GATE_EN_Msk 0x10UL
956 #define BLE_BLELL_CLOCK_CONFIG_SYSCLK_GATE_EN_Pos 5UL
957 #define BLE_BLELL_CLOCK_CONFIG_SYSCLK_GATE_EN_Msk 0x20UL
958 #define BLE_BLELL_CLOCK_CONFIG_PHY_CLK_GATE_EN_Pos 6UL
959 #define BLE_BLELL_CLOCK_CONFIG_PHY_CLK_GATE_EN_Msk 0x40UL
960 #define BLE_BLELL_CLOCK_CONFIG_LLH_IDLE_Pos     7UL
961 #define BLE_BLELL_CLOCK_CONFIG_LLH_IDLE_Msk     0x80UL
962 #define BLE_BLELL_CLOCK_CONFIG_LPO_CLK_FREQ_SEL_Pos 8UL
963 #define BLE_BLELL_CLOCK_CONFIG_LPO_CLK_FREQ_SEL_Msk 0x100UL
964 #define BLE_BLELL_CLOCK_CONFIG_LPO_SEL_EXTERNAL_Pos 9UL
965 #define BLE_BLELL_CLOCK_CONFIG_LPO_SEL_EXTERNAL_Msk 0x200UL
966 #define BLE_BLELL_CLOCK_CONFIG_SM_AUTO_WKUP_EN_Pos 10UL
967 #define BLE_BLELL_CLOCK_CONFIG_SM_AUTO_WKUP_EN_Msk 0x400UL
968 #define BLE_BLELL_CLOCK_CONFIG_SM_INTR_EN_Pos   12UL
969 #define BLE_BLELL_CLOCK_CONFIG_SM_INTR_EN_Msk   0x1000UL
970 #define BLE_BLELL_CLOCK_CONFIG_DEEP_SLEEP_AUTO_WKUP_DISABLE_Pos 13UL
971 #define BLE_BLELL_CLOCK_CONFIG_DEEP_SLEEP_AUTO_WKUP_DISABLE_Msk 0x2000UL
972 #define BLE_BLELL_CLOCK_CONFIG_SLEEP_MODE_EN_Pos 14UL
973 #define BLE_BLELL_CLOCK_CONFIG_SLEEP_MODE_EN_Msk 0x4000UL
974 #define BLE_BLELL_CLOCK_CONFIG_DEEP_SLEEP_MODE_EN_Pos 15UL
975 #define BLE_BLELL_CLOCK_CONFIG_DEEP_SLEEP_MODE_EN_Msk 0x8000UL
976 /* BLE_BLELL.TIM_COUNTER_L */
977 #define BLE_BLELL_TIM_COUNTER_L_TIM_REF_CLOCK_Pos 0UL
978 #define BLE_BLELL_TIM_COUNTER_L_TIM_REF_CLOCK_Msk 0xFFFFUL
979 /* BLE_BLELL.WAKEUP_CONFIG_EXTD */
980 #define BLE_BLELL_WAKEUP_CONFIG_EXTD_DSM_LF_OFFSET_Pos 0UL
981 #define BLE_BLELL_WAKEUP_CONFIG_EXTD_DSM_LF_OFFSET_Msk 0x1FUL
982 /* BLE_BLELL.POC_REG__TIM_CONTROL */
983 #define BLE_BLELL_POC_REG__TIM_CONTROL_BB_CLK_FREQ_MINUS_1_Pos 3UL
984 #define BLE_BLELL_POC_REG__TIM_CONTROL_BB_CLK_FREQ_MINUS_1_Msk 0xF8UL
985 #define BLE_BLELL_POC_REG__TIM_CONTROL_START_SLOT_OFFSET_Pos 8UL
986 #define BLE_BLELL_POC_REG__TIM_CONTROL_START_SLOT_OFFSET_Msk 0xF00UL
987 /* BLE_BLELL.ADV_TX_DATA_FIFO */
988 #define BLE_BLELL_ADV_TX_DATA_FIFO_ADV_TX_DATA_Pos 0UL
989 #define BLE_BLELL_ADV_TX_DATA_FIFO_ADV_TX_DATA_Msk 0xFFFFUL
990 /* BLE_BLELL.ADV_SCN_RSP_TX_FIFO */
991 #define BLE_BLELL_ADV_SCN_RSP_TX_FIFO_SCAN_RSP_DATA_Pos 0UL
992 #define BLE_BLELL_ADV_SCN_RSP_TX_FIFO_SCAN_RSP_DATA_Msk 0xFFFFUL
993 /* BLE_BLELL.INIT_SCN_ADV_RX_FIFO */
994 #define BLE_BLELL_INIT_SCN_ADV_RX_FIFO_ADV_SCAN_RSP_RX_DATA_Pos 0UL
995 #define BLE_BLELL_INIT_SCN_ADV_RX_FIFO_ADV_SCAN_RSP_RX_DATA_Msk 0xFFFFUL
996 /* BLE_BLELL.CONN_INTERVAL */
997 #define BLE_BLELL_CONN_INTERVAL_CONNECTION_INTERVAL_Pos 0UL
998 #define BLE_BLELL_CONN_INTERVAL_CONNECTION_INTERVAL_Msk 0xFFFFUL
999 /* BLE_BLELL.SUP_TIMEOUT */
1000 #define BLE_BLELL_SUP_TIMEOUT_SUPERVISION_TIMEOUT_Pos 0UL
1001 #define BLE_BLELL_SUP_TIMEOUT_SUPERVISION_TIMEOUT_Msk 0xFFFFUL
1002 /* BLE_BLELL.SLAVE_LATENCY */
1003 #define BLE_BLELL_SLAVE_LATENCY_SLAVE_LATENCY_Pos 0UL
1004 #define BLE_BLELL_SLAVE_LATENCY_SLAVE_LATENCY_Msk 0xFFFFUL
1005 /* BLE_BLELL.CE_LENGTH */
1006 #define BLE_BLELL_CE_LENGTH_CONNECTION_EVENT_LENGTH_Pos 0UL
1007 #define BLE_BLELL_CE_LENGTH_CONNECTION_EVENT_LENGTH_Msk 0xFFFFUL
1008 /* BLE_BLELL.PDU_ACCESS_ADDR_L_REGISTER */
1009 #define BLE_BLELL_PDU_ACCESS_ADDR_L_REGISTER_PDU_ACCESS_ADDRESS_LOWER_BITS_Pos 0UL
1010 #define BLE_BLELL_PDU_ACCESS_ADDR_L_REGISTER_PDU_ACCESS_ADDRESS_LOWER_BITS_Msk 0xFFFFUL
1011 /* BLE_BLELL.PDU_ACCESS_ADDR_H_REGISTER */
1012 #define BLE_BLELL_PDU_ACCESS_ADDR_H_REGISTER_PDU_ACCESS_ADDRESS_HIGHER_BITS_Pos 0UL
1013 #define BLE_BLELL_PDU_ACCESS_ADDR_H_REGISTER_PDU_ACCESS_ADDRESS_HIGHER_BITS_Msk 0xFFFFUL
1014 /* BLE_BLELL.CONN_CE_INSTANT */
1015 #define BLE_BLELL_CONN_CE_INSTANT_CE_INSTANT_Pos 0UL
1016 #define BLE_BLELL_CONN_CE_INSTANT_CE_INSTANT_Msk 0xFFFFUL
1017 /* BLE_BLELL.CE_CNFG_STS_REGISTER */
1018 #define BLE_BLELL_CE_CNFG_STS_REGISTER_DATA_LIST_INDEX_LAST_ACK_INDEX_Pos 0UL
1019 #define BLE_BLELL_CE_CNFG_STS_REGISTER_DATA_LIST_INDEX_LAST_ACK_INDEX_Msk 0xFUL
1020 #define BLE_BLELL_CE_CNFG_STS_REGISTER_DATA_LIST_HEAD_UP_Pos 4UL
1021 #define BLE_BLELL_CE_CNFG_STS_REGISTER_DATA_LIST_HEAD_UP_Msk 0x10UL
1022 #define BLE_BLELL_CE_CNFG_STS_REGISTER_SPARE_Pos 5UL
1023 #define BLE_BLELL_CE_CNFG_STS_REGISTER_SPARE_Msk 0x20UL
1024 #define BLE_BLELL_CE_CNFG_STS_REGISTER_MD_Pos   6UL
1025 #define BLE_BLELL_CE_CNFG_STS_REGISTER_MD_Msk   0x40UL
1026 #define BLE_BLELL_CE_CNFG_STS_REGISTER_MAP_INDEX__CURR_INDEX_Pos 7UL
1027 #define BLE_BLELL_CE_CNFG_STS_REGISTER_MAP_INDEX__CURR_INDEX_Msk 0x80UL
1028 #define BLE_BLELL_CE_CNFG_STS_REGISTER_PAUSE_DATA_Pos 8UL
1029 #define BLE_BLELL_CE_CNFG_STS_REGISTER_PAUSE_DATA_Msk 0x100UL
1030 #define BLE_BLELL_CE_CNFG_STS_REGISTER_CONN_ACTIVE_Pos 10UL
1031 #define BLE_BLELL_CE_CNFG_STS_REGISTER_CONN_ACTIVE_Msk 0x400UL
1032 #define BLE_BLELL_CE_CNFG_STS_REGISTER_CURRENT_PDU_INDEX_Pos 12UL
1033 #define BLE_BLELL_CE_CNFG_STS_REGISTER_CURRENT_PDU_INDEX_Msk 0xF000UL
1034 /* BLE_BLELL.NEXT_CE_INSTANT */
1035 #define BLE_BLELL_NEXT_CE_INSTANT_NEXT_CE_INSTANT_Pos 0UL
1036 #define BLE_BLELL_NEXT_CE_INSTANT_NEXT_CE_INSTANT_Msk 0xFFFFUL
1037 /* BLE_BLELL.CONN_CE_COUNTER */
1038 #define BLE_BLELL_CONN_CE_COUNTER_CONNECTION_EVENT_COUNTER_Pos 0UL
1039 #define BLE_BLELL_CONN_CE_COUNTER_CONNECTION_EVENT_COUNTER_Msk 0xFFFFUL
1040 /* BLE_BLELL.DATA_LIST_SENT_UPDATE__STATUS */
1041 #define BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS_LIST_INDEX__TX_SENT_3_0_Pos 0UL
1042 #define BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS_LIST_INDEX__TX_SENT_3_0_Msk 0xFUL
1043 #define BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS_SET_CLEAR_Pos 7UL
1044 #define BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS_SET_CLEAR_Msk 0x80UL
1045 /* BLE_BLELL.DATA_LIST_ACK_UPDATE__STATUS */
1046 #define BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS_LIST_INDEX__TX_ACK_3_0_Pos 0UL
1047 #define BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS_LIST_INDEX__TX_ACK_3_0_Msk 0xFUL
1048 #define BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS_SET_CLEAR_Pos 7UL
1049 #define BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS_SET_CLEAR_Msk 0x80UL
1050 /* BLE_BLELL.CE_CNFG_STS_REGISTER_EXT */
1051 #define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_TX_2M_Pos 0UL
1052 #define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_TX_2M_Msk 0x1UL
1053 #define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_RX_2M_Pos 1UL
1054 #define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_RX_2M_Msk 0x2UL
1055 #define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_SN_Pos 2UL
1056 #define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_SN_Msk 0x4UL
1057 #define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_NESN_Pos 3UL
1058 #define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_NESN_Msk 0x8UL
1059 #define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_LAST_UNMAPPED_CHANNEL_Pos 8UL
1060 #define BLE_BLELL_CE_CNFG_STS_REGISTER_EXT_LAST_UNMAPPED_CHANNEL_Msk 0x3F00UL
1061 /* BLE_BLELL.CONN_EXT_INTR */
1062 #define BLE_BLELL_CONN_EXT_INTR_DATARATE_UPDATE_Pos 0UL
1063 #define BLE_BLELL_CONN_EXT_INTR_DATARATE_UPDATE_Msk 0x1UL
1064 #define BLE_BLELL_CONN_EXT_INTR_EARLY_INTR_Pos  1UL
1065 #define BLE_BLELL_CONN_EXT_INTR_EARLY_INTR_Msk  0x2UL
1066 #define BLE_BLELL_CONN_EXT_INTR_GEN_TIMER_INTR_Pos 2UL
1067 #define BLE_BLELL_CONN_EXT_INTR_GEN_TIMER_INTR_Msk 0x4UL
1068 /* BLE_BLELL.CONN_EXT_INTR_MASK */
1069 #define BLE_BLELL_CONN_EXT_INTR_MASK_DATARATE_UPDATE_Pos 0UL
1070 #define BLE_BLELL_CONN_EXT_INTR_MASK_DATARATE_UPDATE_Msk 0x1UL
1071 #define BLE_BLELL_CONN_EXT_INTR_MASK_EARLY_INTR_Pos 1UL
1072 #define BLE_BLELL_CONN_EXT_INTR_MASK_EARLY_INTR_Msk 0x2UL
1073 #define BLE_BLELL_CONN_EXT_INTR_MASK_GEN_TIMER_INTR_Pos 2UL
1074 #define BLE_BLELL_CONN_EXT_INTR_MASK_GEN_TIMER_INTR_Msk 0x4UL
1075 /* BLE_BLELL.DATA_MEM_DESCRIPTOR */
1076 #define BLE_BLELL_DATA_MEM_DESCRIPTOR_LLID_Pos  0UL
1077 #define BLE_BLELL_DATA_MEM_DESCRIPTOR_LLID_Msk  0x3UL
1078 #define BLE_BLELL_DATA_MEM_DESCRIPTOR_DATA_LENGTH_Pos 2UL
1079 #define BLE_BLELL_DATA_MEM_DESCRIPTOR_DATA_LENGTH_Msk 0x3FCUL
1080 /* BLE_BLELL.WINDOW_WIDEN_INTVL */
1081 #define BLE_BLELL_WINDOW_WIDEN_INTVL_WINDOW_WIDEN_INTVL_Pos 0UL
1082 #define BLE_BLELL_WINDOW_WIDEN_INTVL_WINDOW_WIDEN_INTVL_Msk 0xFFFUL
1083 /* BLE_BLELL.WINDOW_WIDEN_WINOFF */
1084 #define BLE_BLELL_WINDOW_WIDEN_WINOFF_WINDOW_WIDEN_WINOFF_Pos 0UL
1085 #define BLE_BLELL_WINDOW_WIDEN_WINOFF_WINDOW_WIDEN_WINOFF_Msk 0xFFFUL
1086 /* BLE_BLELL.LE_RF_TEST_MODE */
1087 #define BLE_BLELL_LE_RF_TEST_MODE_TEST_FREQUENCY_Pos 0UL
1088 #define BLE_BLELL_LE_RF_TEST_MODE_TEST_FREQUENCY_Msk 0x3FUL
1089 #define BLE_BLELL_LE_RF_TEST_MODE_DTM_STATUS__DTM_CONT_RXEN_Pos 6UL
1090 #define BLE_BLELL_LE_RF_TEST_MODE_DTM_STATUS__DTM_CONT_RXEN_Msk 0x40UL
1091 #define BLE_BLELL_LE_RF_TEST_MODE_PKT_PAYLOAD_Pos 7UL
1092 #define BLE_BLELL_LE_RF_TEST_MODE_PKT_PAYLOAD_Msk 0x380UL
1093 #define BLE_BLELL_LE_RF_TEST_MODE_DTM_CONT_TXEN_Pos 13UL
1094 #define BLE_BLELL_LE_RF_TEST_MODE_DTM_CONT_TXEN_Msk 0x2000UL
1095 #define BLE_BLELL_LE_RF_TEST_MODE_DTM_DATA_2MBPS_Pos 15UL
1096 #define BLE_BLELL_LE_RF_TEST_MODE_DTM_DATA_2MBPS_Msk 0x8000UL
1097 /* BLE_BLELL.DTM_RX_PKT_COUNT */
1098 #define BLE_BLELL_DTM_RX_PKT_COUNT_RX_PACKET_COUNT_Pos 0UL
1099 #define BLE_BLELL_DTM_RX_PKT_COUNT_RX_PACKET_COUNT_Msk 0xFFFFUL
1100 /* BLE_BLELL.LE_RF_TEST_MODE_EXT */
1101 #define BLE_BLELL_LE_RF_TEST_MODE_EXT_DTM_PACKET_LENGTH_Pos 0UL
1102 #define BLE_BLELL_LE_RF_TEST_MODE_EXT_DTM_PACKET_LENGTH_Msk 0xFFUL
1103 /* BLE_BLELL.TXRX_HOP */
1104 #define BLE_BLELL_TXRX_HOP_HOP_CH_TX_Pos        0UL
1105 #define BLE_BLELL_TXRX_HOP_HOP_CH_TX_Msk        0x7FUL
1106 #define BLE_BLELL_TXRX_HOP_HOP_CH_RX_Pos        8UL
1107 #define BLE_BLELL_TXRX_HOP_HOP_CH_RX_Msk        0x7F00UL
1108 /* BLE_BLELL.TX_RX_ON_DELAY */
1109 #define BLE_BLELL_TX_RX_ON_DELAY_RXON_DELAY_Pos 0UL
1110 #define BLE_BLELL_TX_RX_ON_DELAY_RXON_DELAY_Msk 0xFFUL
1111 #define BLE_BLELL_TX_RX_ON_DELAY_TXON_DELAY_Pos 8UL
1112 #define BLE_BLELL_TX_RX_ON_DELAY_TXON_DELAY_Msk 0xFF00UL
1113 /* BLE_BLELL.ADV_ACCADDR_L */
1114 #define BLE_BLELL_ADV_ACCADDR_L_ADV_ACCADDR_L_Pos 0UL
1115 #define BLE_BLELL_ADV_ACCADDR_L_ADV_ACCADDR_L_Msk 0xFFFFUL
1116 /* BLE_BLELL.ADV_ACCADDR_H */
1117 #define BLE_BLELL_ADV_ACCADDR_H_ADV_ACCADDR_H_Pos 0UL
1118 #define BLE_BLELL_ADV_ACCADDR_H_ADV_ACCADDR_H_Msk 0xFFFFUL
1119 /* BLE_BLELL.ADV_CH_TX_POWER_LVL_LS */
1120 #define BLE_BLELL_ADV_CH_TX_POWER_LVL_LS_ADV_TRANSMIT_POWER_LVL_LS_Pos 0UL
1121 #define BLE_BLELL_ADV_CH_TX_POWER_LVL_LS_ADV_TRANSMIT_POWER_LVL_LS_Msk 0xFFFFUL
1122 /* BLE_BLELL.ADV_CH_TX_POWER_LVL_MS */
1123 #define BLE_BLELL_ADV_CH_TX_POWER_LVL_MS_ADV_TRANSMIT_POWER_LVL_MS_Pos 0UL
1124 #define BLE_BLELL_ADV_CH_TX_POWER_LVL_MS_ADV_TRANSMIT_POWER_LVL_MS_Msk 0x3UL
1125 /* BLE_BLELL.CONN_CH_TX_POWER_LVL_LS */
1126 #define BLE_BLELL_CONN_CH_TX_POWER_LVL_LS_CONNCH_TRANSMIT_POWER_LVL_LS_Pos 0UL
1127 #define BLE_BLELL_CONN_CH_TX_POWER_LVL_LS_CONNCH_TRANSMIT_POWER_LVL_LS_Msk 0xFFFFUL
1128 /* BLE_BLELL.CONN_CH_TX_POWER_LVL_MS */
1129 #define BLE_BLELL_CONN_CH_TX_POWER_LVL_MS_CONNCH_TRANSMIT_POWER_LVL_MS_Pos 0UL
1130 #define BLE_BLELL_CONN_CH_TX_POWER_LVL_MS_CONNCH_TRANSMIT_POWER_LVL_MS_Msk 0x3UL
1131 /* BLE_BLELL.DEV_PUB_ADDR_L */
1132 #define BLE_BLELL_DEV_PUB_ADDR_L_DEV_PUB_ADDR_L_Pos 0UL
1133 #define BLE_BLELL_DEV_PUB_ADDR_L_DEV_PUB_ADDR_L_Msk 0xFFFFUL
1134 /* BLE_BLELL.DEV_PUB_ADDR_M */
1135 #define BLE_BLELL_DEV_PUB_ADDR_M_DEV_PUB_ADDR_M_Pos 0UL
1136 #define BLE_BLELL_DEV_PUB_ADDR_M_DEV_PUB_ADDR_M_Msk 0xFFFFUL
1137 /* BLE_BLELL.DEV_PUB_ADDR_H */
1138 #define BLE_BLELL_DEV_PUB_ADDR_H_DEV_PUB_ADDR_H_Pos 0UL
1139 #define BLE_BLELL_DEV_PUB_ADDR_H_DEV_PUB_ADDR_H_Msk 0xFFFFUL
1140 /* BLE_BLELL.OFFSET_TO_FIRST_INSTANT */
1141 #define BLE_BLELL_OFFSET_TO_FIRST_INSTANT_OFFSET_TO_FIRST_EVENT_Pos 0UL
1142 #define BLE_BLELL_OFFSET_TO_FIRST_INSTANT_OFFSET_TO_FIRST_EVENT_Msk 0xFFFFUL
1143 /* BLE_BLELL.ADV_CONFIG */
1144 #define BLE_BLELL_ADV_CONFIG_ADV_STRT_EN_Pos    0UL
1145 #define BLE_BLELL_ADV_CONFIG_ADV_STRT_EN_Msk    0x1UL
1146 #define BLE_BLELL_ADV_CONFIG_ADV_CLS_EN_Pos     1UL
1147 #define BLE_BLELL_ADV_CONFIG_ADV_CLS_EN_Msk     0x2UL
1148 #define BLE_BLELL_ADV_CONFIG_ADV_TX_EN_Pos      2UL
1149 #define BLE_BLELL_ADV_CONFIG_ADV_TX_EN_Msk      0x4UL
1150 #define BLE_BLELL_ADV_CONFIG_SCN_RSP_TX_EN_Pos  3UL
1151 #define BLE_BLELL_ADV_CONFIG_SCN_RSP_TX_EN_Msk  0x8UL
1152 #define BLE_BLELL_ADV_CONFIG_ADV_SCN_REQ_RX_EN_Pos 4UL
1153 #define BLE_BLELL_ADV_CONFIG_ADV_SCN_REQ_RX_EN_Msk 0x10UL
1154 #define BLE_BLELL_ADV_CONFIG_ADV_CONN_REQ_RX_EN_Pos 5UL
1155 #define BLE_BLELL_ADV_CONFIG_ADV_CONN_REQ_RX_EN_Msk 0x20UL
1156 #define BLE_BLELL_ADV_CONFIG_SLV_CONNECTED_EN_Pos 6UL
1157 #define BLE_BLELL_ADV_CONFIG_SLV_CONNECTED_EN_Msk 0x40UL
1158 #define BLE_BLELL_ADV_CONFIG_ADV_TIMEOUT_EN_Pos 7UL
1159 #define BLE_BLELL_ADV_CONFIG_ADV_TIMEOUT_EN_Msk 0x80UL
1160 #define BLE_BLELL_ADV_CONFIG_ADV_RAND_DISABLE_Pos 8UL
1161 #define BLE_BLELL_ADV_CONFIG_ADV_RAND_DISABLE_Msk 0x100UL
1162 #define BLE_BLELL_ADV_CONFIG_ADV_SCN_PEER_RPA_UNMCH_EN_Pos 9UL
1163 #define BLE_BLELL_ADV_CONFIG_ADV_SCN_PEER_RPA_UNMCH_EN_Msk 0x200UL
1164 #define BLE_BLELL_ADV_CONFIG_ADV_CONN_PEER_RPA_UNMCH_EN_Pos 10UL
1165 #define BLE_BLELL_ADV_CONFIG_ADV_CONN_PEER_RPA_UNMCH_EN_Msk 0x400UL
1166 #define BLE_BLELL_ADV_CONFIG_ADV_PKT_INTERVAL_Pos 11UL
1167 #define BLE_BLELL_ADV_CONFIG_ADV_PKT_INTERVAL_Msk 0xF800UL
1168 /* BLE_BLELL.SCAN_CONFIG */
1169 #define BLE_BLELL_SCAN_CONFIG_SCN_STRT_EN_Pos   0UL
1170 #define BLE_BLELL_SCAN_CONFIG_SCN_STRT_EN_Msk   0x1UL
1171 #define BLE_BLELL_SCAN_CONFIG_SCN_CLOSE_EN_Pos  1UL
1172 #define BLE_BLELL_SCAN_CONFIG_SCN_CLOSE_EN_Msk  0x2UL
1173 #define BLE_BLELL_SCAN_CONFIG_SCN_TX_EN_Pos     2UL
1174 #define BLE_BLELL_SCAN_CONFIG_SCN_TX_EN_Msk     0x4UL
1175 #define BLE_BLELL_SCAN_CONFIG_ADV_RX_EN_Pos     3UL
1176 #define BLE_BLELL_SCAN_CONFIG_ADV_RX_EN_Msk     0x8UL
1177 #define BLE_BLELL_SCAN_CONFIG_SCN_RSP_RX_EN_Pos 4UL
1178 #define BLE_BLELL_SCAN_CONFIG_SCN_RSP_RX_EN_Msk 0x10UL
1179 #define BLE_BLELL_SCAN_CONFIG_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN_Pos 5UL
1180 #define BLE_BLELL_SCAN_CONFIG_SCN_ADV_RX_INTR_PEER_RPA_UNMCH_EN_Msk 0x20UL
1181 #define BLE_BLELL_SCAN_CONFIG_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN_Pos 6UL
1182 #define BLE_BLELL_SCAN_CONFIG_SCN_ADV_RX_INTR_SELF_RPA_UNMCH_EN_Msk 0x40UL
1183 #define BLE_BLELL_SCAN_CONFIG_SCANA_TX_ADDR_NOT_SET_INTR_EN_Pos 7UL
1184 #define BLE_BLELL_SCAN_CONFIG_SCANA_TX_ADDR_NOT_SET_INTR_EN_Msk 0x80UL
1185 #define BLE_BLELL_SCAN_CONFIG_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN_Pos 8UL
1186 #define BLE_BLELL_SCAN_CONFIG_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_SCN_Msk 0x100UL
1187 #define BLE_BLELL_SCAN_CONFIG_BACKOFF_ENABLE_Pos 11UL
1188 #define BLE_BLELL_SCAN_CONFIG_BACKOFF_ENABLE_Msk 0x800UL
1189 #define BLE_BLELL_SCAN_CONFIG_SCAN_CHANNEL_MAP_Pos 13UL
1190 #define BLE_BLELL_SCAN_CONFIG_SCAN_CHANNEL_MAP_Msk 0xE000UL
1191 /* BLE_BLELL.INIT_CONFIG */
1192 #define BLE_BLELL_INIT_CONFIG_INIT_STRT_EN_Pos  0UL
1193 #define BLE_BLELL_INIT_CONFIG_INIT_STRT_EN_Msk  0x1UL
1194 #define BLE_BLELL_INIT_CONFIG_INIT_CLOSE_EN_Pos 1UL
1195 #define BLE_BLELL_INIT_CONFIG_INIT_CLOSE_EN_Msk 0x2UL
1196 #define BLE_BLELL_INIT_CONFIG_CONN_REQ_TX_EN_Pos 2UL
1197 #define BLE_BLELL_INIT_CONFIG_CONN_REQ_TX_EN_Msk 0x4UL
1198 #define BLE_BLELL_INIT_CONFIG_CONN_CREATED_Pos  4UL
1199 #define BLE_BLELL_INIT_CONFIG_CONN_CREATED_Msk  0x10UL
1200 #define BLE_BLELL_INIT_CONFIG_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN_Pos 5UL
1201 #define BLE_BLELL_INIT_CONFIG_INIT_ADV_RX_INTR_SELF_RPA_UNRES_EN_Msk 0x20UL
1202 #define BLE_BLELL_INIT_CONFIG_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN_Pos 6UL
1203 #define BLE_BLELL_INIT_CONFIG_INIT_ADV_RX_INTR_PEER_RPA_UNRES_EN_Msk 0x40UL
1204 #define BLE_BLELL_INIT_CONFIG_INITA_TX_ADDR_NOT_SET_INTR_EN_Pos 7UL
1205 #define BLE_BLELL_INIT_CONFIG_INITA_TX_ADDR_NOT_SET_INTR_EN_Msk 0x80UL
1206 #define BLE_BLELL_INIT_CONFIG_INIT_CHANNEL_MAP_Pos 13UL
1207 #define BLE_BLELL_INIT_CONFIG_INIT_CHANNEL_MAP_Msk 0xE000UL
1208 /* BLE_BLELL.CONN_CONFIG */
1209 #define BLE_BLELL_CONN_CONFIG_RX_PKT_LIMIT_Pos  0UL
1210 #define BLE_BLELL_CONN_CONFIG_RX_PKT_LIMIT_Msk  0xFUL
1211 #define BLE_BLELL_CONN_CONFIG_RX_INTR_THRESHOLD_Pos 4UL
1212 #define BLE_BLELL_CONN_CONFIG_RX_INTR_THRESHOLD_Msk 0xF0UL
1213 #define BLE_BLELL_CONN_CONFIG_MD_BIT_CLEAR_Pos  8UL
1214 #define BLE_BLELL_CONN_CONFIG_MD_BIT_CLEAR_Msk  0x100UL
1215 #define BLE_BLELL_CONN_CONFIG_DSM_SLOT_VARIANCE_Pos 11UL
1216 #define BLE_BLELL_CONN_CONFIG_DSM_SLOT_VARIANCE_Msk 0x800UL
1217 #define BLE_BLELL_CONN_CONFIG_SLV_MD_CONFIG_Pos 12UL
1218 #define BLE_BLELL_CONN_CONFIG_SLV_MD_CONFIG_Msk 0x1000UL
1219 #define BLE_BLELL_CONN_CONFIG_EXTEND_CU_TX_WIN_Pos 13UL
1220 #define BLE_BLELL_CONN_CONFIG_EXTEND_CU_TX_WIN_Msk 0x2000UL
1221 #define BLE_BLELL_CONN_CONFIG_MASK_SUTO_AT_UPDT_Pos 14UL
1222 #define BLE_BLELL_CONN_CONFIG_MASK_SUTO_AT_UPDT_Msk 0x4000UL
1223 #define BLE_BLELL_CONN_CONFIG_CONN_REQ_1SLOT_EARLY_Pos 15UL
1224 #define BLE_BLELL_CONN_CONFIG_CONN_REQ_1SLOT_EARLY_Msk 0x8000UL
1225 /* BLE_BLELL.CONN_PARAM1 */
1226 #define BLE_BLELL_CONN_PARAM1_SCA_PARAM_Pos     0UL
1227 #define BLE_BLELL_CONN_PARAM1_SCA_PARAM_Msk     0x7UL
1228 #define BLE_BLELL_CONN_PARAM1_HOP_INCREMENT_PARAM_Pos 3UL
1229 #define BLE_BLELL_CONN_PARAM1_HOP_INCREMENT_PARAM_Msk 0xF8UL
1230 #define BLE_BLELL_CONN_PARAM1_CRC_INIT_L_Pos    8UL
1231 #define BLE_BLELL_CONN_PARAM1_CRC_INIT_L_Msk    0xFF00UL
1232 /* BLE_BLELL.CONN_PARAM2 */
1233 #define BLE_BLELL_CONN_PARAM2_CRC_INIT_H_Pos    0UL
1234 #define BLE_BLELL_CONN_PARAM2_CRC_INIT_H_Msk    0xFFFFUL
1235 /* BLE_BLELL.CONN_INTR_MASK */
1236 #define BLE_BLELL_CONN_INTR_MASK_CONN_CL_INT_EN_Pos 0UL
1237 #define BLE_BLELL_CONN_INTR_MASK_CONN_CL_INT_EN_Msk 0x1UL
1238 #define BLE_BLELL_CONN_INTR_MASK_CONN_ESTB_INT_EN_Pos 1UL
1239 #define BLE_BLELL_CONN_INTR_MASK_CONN_ESTB_INT_EN_Msk 0x2UL
1240 #define BLE_BLELL_CONN_INTR_MASK_MAP_UPDT_INT_EN_Pos 2UL
1241 #define BLE_BLELL_CONN_INTR_MASK_MAP_UPDT_INT_EN_Msk 0x4UL
1242 #define BLE_BLELL_CONN_INTR_MASK_START_CE_INT_EN_Pos 3UL
1243 #define BLE_BLELL_CONN_INTR_MASK_START_CE_INT_EN_Msk 0x8UL
1244 #define BLE_BLELL_CONN_INTR_MASK_CLOSE_CE_INT_EN_Pos 4UL
1245 #define BLE_BLELL_CONN_INTR_MASK_CLOSE_CE_INT_EN_Msk 0x10UL
1246 #define BLE_BLELL_CONN_INTR_MASK_CE_TX_ACK_INT_EN_Pos 5UL
1247 #define BLE_BLELL_CONN_INTR_MASK_CE_TX_ACK_INT_EN_Msk 0x20UL
1248 #define BLE_BLELL_CONN_INTR_MASK_CE_RX_INT_EN_Pos 6UL
1249 #define BLE_BLELL_CONN_INTR_MASK_CE_RX_INT_EN_Msk 0x40UL
1250 #define BLE_BLELL_CONN_INTR_MASK_CONN_UPDATE_INTR_EN_Pos 7UL
1251 #define BLE_BLELL_CONN_INTR_MASK_CONN_UPDATE_INTR_EN_Msk 0x80UL
1252 #define BLE_BLELL_CONN_INTR_MASK_RX_GOOD_PDU_INT_EN_Pos 8UL
1253 #define BLE_BLELL_CONN_INTR_MASK_RX_GOOD_PDU_INT_EN_Msk 0x100UL
1254 #define BLE_BLELL_CONN_INTR_MASK_RX_BAD_PDU_INT_EN_Pos 9UL
1255 #define BLE_BLELL_CONN_INTR_MASK_RX_BAD_PDU_INT_EN_Msk 0x200UL
1256 #define BLE_BLELL_CONN_INTR_MASK_CE_CLOSE_NULL_RX_INT_EN_Pos 13UL
1257 #define BLE_BLELL_CONN_INTR_MASK_CE_CLOSE_NULL_RX_INT_EN_Msk 0x2000UL
1258 #define BLE_BLELL_CONN_INTR_MASK_PING_TIMER_EXPIRD_INTR_Pos 14UL
1259 #define BLE_BLELL_CONN_INTR_MASK_PING_TIMER_EXPIRD_INTR_Msk 0x4000UL
1260 #define BLE_BLELL_CONN_INTR_MASK_PING_NEARLY_EXPIRD_INTR_Pos 15UL
1261 #define BLE_BLELL_CONN_INTR_MASK_PING_NEARLY_EXPIRD_INTR_Msk 0x8000UL
1262 /* BLE_BLELL.SLAVE_TIMING_CONTROL */
1263 #define BLE_BLELL_SLAVE_TIMING_CONTROL_SLAVE_TIME_SET_VAL_Pos 0UL
1264 #define BLE_BLELL_SLAVE_TIMING_CONTROL_SLAVE_TIME_SET_VAL_Msk 0xFFUL
1265 #define BLE_BLELL_SLAVE_TIMING_CONTROL_SLAVE_TIME_ADJ_VAL_Pos 8UL
1266 #define BLE_BLELL_SLAVE_TIMING_CONTROL_SLAVE_TIME_ADJ_VAL_Msk 0xFF00UL
1267 /* BLE_BLELL.RECEIVE_TRIG_CTRL */
1268 #define BLE_BLELL_RECEIVE_TRIG_CTRL_ACC_TRIGGER_THRESHOLD_Pos 0UL
1269 #define BLE_BLELL_RECEIVE_TRIG_CTRL_ACC_TRIGGER_THRESHOLD_Msk 0x3FUL
1270 #define BLE_BLELL_RECEIVE_TRIG_CTRL_ACC_TRIGGER_TIMEOUT_Pos 8UL
1271 #define BLE_BLELL_RECEIVE_TRIG_CTRL_ACC_TRIGGER_TIMEOUT_Msk 0xFF00UL
1272 /* BLE_BLELL.LL_DBG_1 */
1273 #define BLE_BLELL_LL_DBG_1_CONN_RX_WR_PTR_Pos   0UL
1274 #define BLE_BLELL_LL_DBG_1_CONN_RX_WR_PTR_Msk   0x3FFUL
1275 /* BLE_BLELL.LL_DBG_2 */
1276 #define BLE_BLELL_LL_DBG_2_CONN_RX_RD_PTR_Pos   0UL
1277 #define BLE_BLELL_LL_DBG_2_CONN_RX_RD_PTR_Msk   0x3FFUL
1278 /* BLE_BLELL.LL_DBG_3 */
1279 #define BLE_BLELL_LL_DBG_3_CONN_RX_WR_PTR_STORE_Pos 0UL
1280 #define BLE_BLELL_LL_DBG_3_CONN_RX_WR_PTR_STORE_Msk 0x3FFUL
1281 /* BLE_BLELL.LL_DBG_4 */
1282 #define BLE_BLELL_LL_DBG_4_CONNECTION_FSM_STATE_Pos 0UL
1283 #define BLE_BLELL_LL_DBG_4_CONNECTION_FSM_STATE_Msk 0xFUL
1284 #define BLE_BLELL_LL_DBG_4_SLAVE_LATENCY_FSM_STATE_Pos 4UL
1285 #define BLE_BLELL_LL_DBG_4_SLAVE_LATENCY_FSM_STATE_Msk 0x30UL
1286 #define BLE_BLELL_LL_DBG_4_ADVERTISER_FSM_STATE_Pos 6UL
1287 #define BLE_BLELL_LL_DBG_4_ADVERTISER_FSM_STATE_Msk 0x7C0UL
1288 /* BLE_BLELL.LL_DBG_5 */
1289 #define BLE_BLELL_LL_DBG_5_INIT_FSM_STATE_Pos   0UL
1290 #define BLE_BLELL_LL_DBG_5_INIT_FSM_STATE_Msk   0x1FUL
1291 #define BLE_BLELL_LL_DBG_5_SCAN_FSM_STATE_Pos   5UL
1292 #define BLE_BLELL_LL_DBG_5_SCAN_FSM_STATE_Msk   0x3E0UL
1293 /* BLE_BLELL.LL_DBG_6 */
1294 #define BLE_BLELL_LL_DBG_6_ADV_TX_WR_PTR_Pos    0UL
1295 #define BLE_BLELL_LL_DBG_6_ADV_TX_WR_PTR_Msk    0xFUL
1296 #define BLE_BLELL_LL_DBG_6_SCAN_RSP_TX_WR_PTR_Pos 4UL
1297 #define BLE_BLELL_LL_DBG_6_SCAN_RSP_TX_WR_PTR_Msk 0xF0UL
1298 #define BLE_BLELL_LL_DBG_6_ADV_TX_RD_PTR_Pos    8UL
1299 #define BLE_BLELL_LL_DBG_6_ADV_TX_RD_PTR_Msk    0x3F00UL
1300 /* BLE_BLELL.LL_DBG_7 */
1301 #define BLE_BLELL_LL_DBG_7_ADV_RX_WR_PTR_Pos    0UL
1302 #define BLE_BLELL_LL_DBG_7_ADV_RX_WR_PTR_Msk    0x7FUL
1303 #define BLE_BLELL_LL_DBG_7_ADV_RX_RD_PTR_Pos    7UL
1304 #define BLE_BLELL_LL_DBG_7_ADV_RX_RD_PTR_Msk    0x3F80UL
1305 /* BLE_BLELL.LL_DBG_8 */
1306 #define BLE_BLELL_LL_DBG_8_ADV_RX_WR_PTR_STORE_Pos 0UL
1307 #define BLE_BLELL_LL_DBG_8_ADV_RX_WR_PTR_STORE_Msk 0x7FUL
1308 #define BLE_BLELL_LL_DBG_8_WLF_PTR_Pos          7UL
1309 #define BLE_BLELL_LL_DBG_8_WLF_PTR_Msk          0x3F80UL
1310 /* BLE_BLELL.LL_DBG_9 */
1311 #define BLE_BLELL_LL_DBG_9_WINDOW_WIDEN_Pos     0UL
1312 #define BLE_BLELL_LL_DBG_9_WINDOW_WIDEN_Msk     0xFFFFUL
1313 /* BLE_BLELL.LL_DBG_10 */
1314 #define BLE_BLELL_LL_DBG_10_RF_CHANNEL_NUM_Pos  0UL
1315 #define BLE_BLELL_LL_DBG_10_RF_CHANNEL_NUM_Msk  0x3FUL
1316 /* BLE_BLELL.PEER_ADDR_INIT_L */
1317 #define BLE_BLELL_PEER_ADDR_INIT_L_PEER_ADDR_L_Pos 0UL
1318 #define BLE_BLELL_PEER_ADDR_INIT_L_PEER_ADDR_L_Msk 0xFFFFUL
1319 /* BLE_BLELL.PEER_ADDR_INIT_M */
1320 #define BLE_BLELL_PEER_ADDR_INIT_M_PEER_ADDR_M_Pos 0UL
1321 #define BLE_BLELL_PEER_ADDR_INIT_M_PEER_ADDR_M_Msk 0xFFFFUL
1322 /* BLE_BLELL.PEER_ADDR_INIT_H */
1323 #define BLE_BLELL_PEER_ADDR_INIT_H_PEER_ADDR_H_Pos 0UL
1324 #define BLE_BLELL_PEER_ADDR_INIT_H_PEER_ADDR_H_Msk 0xFFFFUL
1325 /* BLE_BLELL.PEER_SEC_ADDR_ADV_L */
1326 #define BLE_BLELL_PEER_SEC_ADDR_ADV_L_PEER_SEC_ADDR_L_Pos 0UL
1327 #define BLE_BLELL_PEER_SEC_ADDR_ADV_L_PEER_SEC_ADDR_L_Msk 0xFFFFUL
1328 /* BLE_BLELL.PEER_SEC_ADDR_ADV_M */
1329 #define BLE_BLELL_PEER_SEC_ADDR_ADV_M_PEER_SEC_ADDR_M_Pos 0UL
1330 #define BLE_BLELL_PEER_SEC_ADDR_ADV_M_PEER_SEC_ADDR_M_Msk 0xFFFFUL
1331 /* BLE_BLELL.PEER_SEC_ADDR_ADV_H */
1332 #define BLE_BLELL_PEER_SEC_ADDR_ADV_H_PEER_SEC_ADDR_H_Pos 0UL
1333 #define BLE_BLELL_PEER_SEC_ADDR_ADV_H_PEER_SEC_ADDR_H_Msk 0xFFFFUL
1334 /* BLE_BLELL.INIT_WINDOW_TIMER_CTRL */
1335 #define BLE_BLELL_INIT_WINDOW_TIMER_CTRL_INIT_WINDOW_OFFSET_SEL_Pos 0UL
1336 #define BLE_BLELL_INIT_WINDOW_TIMER_CTRL_INIT_WINDOW_OFFSET_SEL_Msk 0x1UL
1337 /* BLE_BLELL.CONN_CONFIG_EXT */
1338 #define BLE_BLELL_CONN_CONFIG_EXT_CONN_REQ_2SLOT_EARLY_Pos 0UL
1339 #define BLE_BLELL_CONN_CONFIG_EXT_CONN_REQ_2SLOT_EARLY_Msk 0x1UL
1340 #define BLE_BLELL_CONN_CONFIG_EXT_CONN_REQ_3SLOT_EARLY_Pos 1UL
1341 #define BLE_BLELL_CONN_CONFIG_EXT_CONN_REQ_3SLOT_EARLY_Msk 0x2UL
1342 #define BLE_BLELL_CONN_CONFIG_EXT_FW_PKT_RCV_CONN_INDEX_Pos 2UL
1343 #define BLE_BLELL_CONN_CONFIG_EXT_FW_PKT_RCV_CONN_INDEX_Msk 0x7CUL
1344 #define BLE_BLELL_CONN_CONFIG_EXT_MMMS_RX_PKT_LIMIT_Pos 8UL
1345 #define BLE_BLELL_CONN_CONFIG_EXT_MMMS_RX_PKT_LIMIT_Msk 0x3F00UL
1346 #define BLE_BLELL_CONN_CONFIG_EXT_DEBUG_CE_EXPIRE_Pos 14UL
1347 #define BLE_BLELL_CONN_CONFIG_EXT_DEBUG_CE_EXPIRE_Msk 0x4000UL
1348 #define BLE_BLELL_CONN_CONFIG_EXT_MT_PDU_CE_EXPIRE_Pos 15UL
1349 #define BLE_BLELL_CONN_CONFIG_EXT_MT_PDU_CE_EXPIRE_Msk 0x8000UL
1350 /* BLE_BLELL.DPLL_CONFIG */
1351 #define BLE_BLELL_DPLL_CONFIG_DPLL_CORREL_CONFIG_Pos 0UL
1352 #define BLE_BLELL_DPLL_CONFIG_DPLL_CORREL_CONFIG_Msk 0xFFFFUL
1353 /* BLE_BLELL.INIT_NI_VAL */
1354 #define BLE_BLELL_INIT_NI_VAL_INIT_NI_VAL_Pos   0UL
1355 #define BLE_BLELL_INIT_NI_VAL_INIT_NI_VAL_Msk   0xFFFFUL
1356 /* BLE_BLELL.INIT_WINDOW_OFFSET */
1357 #define BLE_BLELL_INIT_WINDOW_OFFSET_INIT_WINDOW_NI_Pos 0UL
1358 #define BLE_BLELL_INIT_WINDOW_OFFSET_INIT_WINDOW_NI_Msk 0xFFFFUL
1359 /* BLE_BLELL.INIT_WINDOW_NI_ANCHOR_PT */
1360 #define BLE_BLELL_INIT_WINDOW_NI_ANCHOR_PT_INIT_INT_OFF_CAPT_Pos 0UL
1361 #define BLE_BLELL_INIT_WINDOW_NI_ANCHOR_PT_INIT_INT_OFF_CAPT_Msk 0xFFFFUL
1362 /* BLE_BLELL.CONN_UPDATE_NEW_INTERVAL */
1363 #define BLE_BLELL_CONN_UPDATE_NEW_INTERVAL_CONN_UPDT_INTERVAL_Pos 0UL
1364 #define BLE_BLELL_CONN_UPDATE_NEW_INTERVAL_CONN_UPDT_INTERVAL_Msk 0xFFFFUL
1365 /* BLE_BLELL.CONN_UPDATE_NEW_LATENCY */
1366 #define BLE_BLELL_CONN_UPDATE_NEW_LATENCY_CONN_UPDT_SLV_LATENCY_Pos 0UL
1367 #define BLE_BLELL_CONN_UPDATE_NEW_LATENCY_CONN_UPDT_SLV_LATENCY_Msk 0xFFFFUL
1368 /* BLE_BLELL.CONN_UPDATE_NEW_SUP_TO */
1369 #define BLE_BLELL_CONN_UPDATE_NEW_SUP_TO_CONN_UPDT_SUP_TO_Pos 0UL
1370 #define BLE_BLELL_CONN_UPDATE_NEW_SUP_TO_CONN_UPDT_SUP_TO_Msk 0xFFFFUL
1371 /* BLE_BLELL.CONN_UPDATE_NEW_SL_INTERVAL */
1372 #define BLE_BLELL_CONN_UPDATE_NEW_SL_INTERVAL_SL_CONN_INTERVAL_VAL_Pos 0UL
1373 #define BLE_BLELL_CONN_UPDATE_NEW_SL_INTERVAL_SL_CONN_INTERVAL_VAL_Msk 0xFFFFUL
1374 /* BLE_BLELL.CONN_REQ_WORD0 */
1375 #define BLE_BLELL_CONN_REQ_WORD0_ACCESS_ADDR_LOWER_Pos 0UL
1376 #define BLE_BLELL_CONN_REQ_WORD0_ACCESS_ADDR_LOWER_Msk 0xFFFFUL
1377 /* BLE_BLELL.CONN_REQ_WORD1 */
1378 #define BLE_BLELL_CONN_REQ_WORD1_ACCESS_ADDR_UPPER_Pos 0UL
1379 #define BLE_BLELL_CONN_REQ_WORD1_ACCESS_ADDR_UPPER_Msk 0xFFFFUL
1380 /* BLE_BLELL.CONN_REQ_WORD2 */
1381 #define BLE_BLELL_CONN_REQ_WORD2_TX_WINDOW_SIZE_VAL_Pos 0UL
1382 #define BLE_BLELL_CONN_REQ_WORD2_TX_WINDOW_SIZE_VAL_Msk 0xFFUL
1383 #define BLE_BLELL_CONN_REQ_WORD2_CRC_INIT_LOWER_Pos 8UL
1384 #define BLE_BLELL_CONN_REQ_WORD2_CRC_INIT_LOWER_Msk 0xFF00UL
1385 /* BLE_BLELL.CONN_REQ_WORD3 */
1386 #define BLE_BLELL_CONN_REQ_WORD3_CRC_INIT_UPPER_Pos 0UL
1387 #define BLE_BLELL_CONN_REQ_WORD3_CRC_INIT_UPPER_Msk 0xFFFFUL
1388 /* BLE_BLELL.CONN_REQ_WORD4 */
1389 #define BLE_BLELL_CONN_REQ_WORD4_TX_WINDOW_OFFSET_Pos 0UL
1390 #define BLE_BLELL_CONN_REQ_WORD4_TX_WINDOW_OFFSET_Msk 0xFFFFUL
1391 /* BLE_BLELL.CONN_REQ_WORD5 */
1392 #define BLE_BLELL_CONN_REQ_WORD5_CONNECTION_INTERVAL_VAL_Pos 0UL
1393 #define BLE_BLELL_CONN_REQ_WORD5_CONNECTION_INTERVAL_VAL_Msk 0xFFFFUL
1394 /* BLE_BLELL.CONN_REQ_WORD6 */
1395 #define BLE_BLELL_CONN_REQ_WORD6_SLAVE_LATENCY_VAL_Pos 0UL
1396 #define BLE_BLELL_CONN_REQ_WORD6_SLAVE_LATENCY_VAL_Msk 0xFFFFUL
1397 /* BLE_BLELL.CONN_REQ_WORD7 */
1398 #define BLE_BLELL_CONN_REQ_WORD7_SUPERVISION_TIMEOUT_VAL_Pos 0UL
1399 #define BLE_BLELL_CONN_REQ_WORD7_SUPERVISION_TIMEOUT_VAL_Msk 0xFFFFUL
1400 /* BLE_BLELL.CONN_REQ_WORD8 */
1401 #define BLE_BLELL_CONN_REQ_WORD8_DATA_CHANNELS_LOWER_Pos 0UL
1402 #define BLE_BLELL_CONN_REQ_WORD8_DATA_CHANNELS_LOWER_Msk 0xFFFFUL
1403 /* BLE_BLELL.CONN_REQ_WORD9 */
1404 #define BLE_BLELL_CONN_REQ_WORD9_DATA_CHANNELS_MID_Pos 0UL
1405 #define BLE_BLELL_CONN_REQ_WORD9_DATA_CHANNELS_MID_Msk 0xFFFFUL
1406 /* BLE_BLELL.CONN_REQ_WORD10 */
1407 #define BLE_BLELL_CONN_REQ_WORD10_DATA_CHANNELS_UPPER_Pos 0UL
1408 #define BLE_BLELL_CONN_REQ_WORD10_DATA_CHANNELS_UPPER_Msk 0x1FUL
1409 /* BLE_BLELL.CONN_REQ_WORD11 */
1410 #define BLE_BLELL_CONN_REQ_WORD11_HOP_INCREMENT_2_Pos 0UL
1411 #define BLE_BLELL_CONN_REQ_WORD11_HOP_INCREMENT_2_Msk 0x1FUL
1412 #define BLE_BLELL_CONN_REQ_WORD11_SCA_2_Pos     5UL
1413 #define BLE_BLELL_CONN_REQ_WORD11_SCA_2_Msk     0xE0UL
1414 /* BLE_BLELL.PDU_RESP_TIMER */
1415 #define BLE_BLELL_PDU_RESP_TIMER_PDU_RESP_TIME_VAL_Pos 0UL
1416 #define BLE_BLELL_PDU_RESP_TIMER_PDU_RESP_TIME_VAL_Msk 0xFFFFUL
1417 /* BLE_BLELL.NEXT_RESP_TIMER_EXP */
1418 #define BLE_BLELL_NEXT_RESP_TIMER_EXP_NEXT_RESPONSE_INSTANT_Pos 0UL
1419 #define BLE_BLELL_NEXT_RESP_TIMER_EXP_NEXT_RESPONSE_INSTANT_Msk 0xFFFFUL
1420 /* BLE_BLELL.NEXT_SUP_TO */
1421 #define BLE_BLELL_NEXT_SUP_TO_NEXT_TIMEOUT_INSTANT_Pos 0UL
1422 #define BLE_BLELL_NEXT_SUP_TO_NEXT_TIMEOUT_INSTANT_Msk 0xFFFFUL
1423 /* BLE_BLELL.LLH_FEATURE_CONFIG */
1424 #define BLE_BLELL_LLH_FEATURE_CONFIG_QUICK_TRANSMIT_Pos 0UL
1425 #define BLE_BLELL_LLH_FEATURE_CONFIG_QUICK_TRANSMIT_Msk 0x1UL
1426 #define BLE_BLELL_LLH_FEATURE_CONFIG_SL_DSM_EN_Pos 1UL
1427 #define BLE_BLELL_LLH_FEATURE_CONFIG_SL_DSM_EN_Msk 0x2UL
1428 #define BLE_BLELL_LLH_FEATURE_CONFIG_US_COUNTER_OFFSET_ADJ_Pos 2UL
1429 #define BLE_BLELL_LLH_FEATURE_CONFIG_US_COUNTER_OFFSET_ADJ_Msk 0x4UL
1430 /* BLE_BLELL.WIN_MIN_STEP_SIZE */
1431 #define BLE_BLELL_WIN_MIN_STEP_SIZE_STEPDN_Pos  0UL
1432 #define BLE_BLELL_WIN_MIN_STEP_SIZE_STEPDN_Msk  0xFUL
1433 #define BLE_BLELL_WIN_MIN_STEP_SIZE_STEPUP_Pos  4UL
1434 #define BLE_BLELL_WIN_MIN_STEP_SIZE_STEPUP_Msk  0xF0UL
1435 #define BLE_BLELL_WIN_MIN_STEP_SIZE_WINDOW_MIN_FW_Pos 8UL
1436 #define BLE_BLELL_WIN_MIN_STEP_SIZE_WINDOW_MIN_FW_Msk 0xFF00UL
1437 /* BLE_BLELL.SLV_WIN_ADJ */
1438 #define BLE_BLELL_SLV_WIN_ADJ_SLV_WIN_ADJ_Pos   0UL
1439 #define BLE_BLELL_SLV_WIN_ADJ_SLV_WIN_ADJ_Msk   0x7FFUL
1440 /* BLE_BLELL.SL_CONN_INTERVAL */
1441 #define BLE_BLELL_SL_CONN_INTERVAL_SL_CONN_INTERVAL_VAL_Pos 0UL
1442 #define BLE_BLELL_SL_CONN_INTERVAL_SL_CONN_INTERVAL_VAL_Msk 0xFFFFUL
1443 /* BLE_BLELL.LE_PING_TIMER_ADDR */
1444 #define BLE_BLELL_LE_PING_TIMER_ADDR_CONN_PING_TIMER_ADDR_Pos 0UL
1445 #define BLE_BLELL_LE_PING_TIMER_ADDR_CONN_PING_TIMER_ADDR_Msk 0xFFFFUL
1446 /* BLE_BLELL.LE_PING_TIMER_OFFSET */
1447 #define BLE_BLELL_LE_PING_TIMER_OFFSET_CONN_PING_TIMER_OFFSET_Pos 0UL
1448 #define BLE_BLELL_LE_PING_TIMER_OFFSET_CONN_PING_TIMER_OFFSET_Msk 0xFFFFUL
1449 /* BLE_BLELL.LE_PING_TIMER_NEXT_EXP */
1450 #define BLE_BLELL_LE_PING_TIMER_NEXT_EXP_CONN_PING_TIMER_NEXT_EXP_Pos 0UL
1451 #define BLE_BLELL_LE_PING_TIMER_NEXT_EXP_CONN_PING_TIMER_NEXT_EXP_Msk 0xFFFFUL
1452 /* BLE_BLELL.LE_PING_TIMER_WRAP_COUNT */
1453 #define BLE_BLELL_LE_PING_TIMER_WRAP_COUNT_CONN_SEC_CURRENT_WRAP_Pos 0UL
1454 #define BLE_BLELL_LE_PING_TIMER_WRAP_COUNT_CONN_SEC_CURRENT_WRAP_Msk 0xFFFFUL
1455 /* BLE_BLELL.TX_EN_EXT_DELAY */
1456 #define BLE_BLELL_TX_EN_EXT_DELAY_TXEN_EXT_DELAY_Pos 0UL
1457 #define BLE_BLELL_TX_EN_EXT_DELAY_TXEN_EXT_DELAY_Msk 0xFUL
1458 #define BLE_BLELL_TX_EN_EXT_DELAY_RXEN_EXT_DELAY_Pos 4UL
1459 #define BLE_BLELL_TX_EN_EXT_DELAY_RXEN_EXT_DELAY_Msk 0xF0UL
1460 #define BLE_BLELL_TX_EN_EXT_DELAY_DEMOD_2M_COMP_DLY_Pos 8UL
1461 #define BLE_BLELL_TX_EN_EXT_DELAY_DEMOD_2M_COMP_DLY_Msk 0xF00UL
1462 #define BLE_BLELL_TX_EN_EXT_DELAY_MOD_2M_COMP_DLY_Pos 12UL
1463 #define BLE_BLELL_TX_EN_EXT_DELAY_MOD_2M_COMP_DLY_Msk 0xF000UL
1464 /* BLE_BLELL.TX_RX_SYNTH_DELAY */
1465 #define BLE_BLELL_TX_RX_SYNTH_DELAY_RX_EN_DELAY_Pos 0UL
1466 #define BLE_BLELL_TX_RX_SYNTH_DELAY_RX_EN_DELAY_Msk 0xFFUL
1467 #define BLE_BLELL_TX_RX_SYNTH_DELAY_TX_EN_DELAY_Pos 8UL
1468 #define BLE_BLELL_TX_RX_SYNTH_DELAY_TX_EN_DELAY_Msk 0xFF00UL
1469 /* BLE_BLELL.EXT_PA_LNA_DLY_CNFG */
1470 #define BLE_BLELL_EXT_PA_LNA_DLY_CNFG_LNA_CTL_DELAY_Pos 0UL
1471 #define BLE_BLELL_EXT_PA_LNA_DLY_CNFG_LNA_CTL_DELAY_Msk 0xFFUL
1472 #define BLE_BLELL_EXT_PA_LNA_DLY_CNFG_PA_CTL_DELAY_Pos 8UL
1473 #define BLE_BLELL_EXT_PA_LNA_DLY_CNFG_PA_CTL_DELAY_Msk 0xFF00UL
1474 /* BLE_BLELL.LL_CONFIG */
1475 #define BLE_BLELL_LL_CONFIG_RSSI_SEL_Pos        0UL
1476 #define BLE_BLELL_LL_CONFIG_RSSI_SEL_Msk        0x1UL
1477 #define BLE_BLELL_LL_CONFIG_TX_RX_CTRL_SEL_Pos  1UL
1478 #define BLE_BLELL_LL_CONFIG_TX_RX_CTRL_SEL_Msk  0x2UL
1479 #define BLE_BLELL_LL_CONFIG_TIFS_ENABLE_Pos     2UL
1480 #define BLE_BLELL_LL_CONFIG_TIFS_ENABLE_Msk     0x4UL
1481 #define BLE_BLELL_LL_CONFIG_TIMER_LF_SLOT_ENABLE_Pos 3UL
1482 #define BLE_BLELL_LL_CONFIG_TIMER_LF_SLOT_ENABLE_Msk 0x8UL
1483 #define BLE_BLELL_LL_CONFIG_RSSI_INTR_SEL_Pos   5UL
1484 #define BLE_BLELL_LL_CONFIG_RSSI_INTR_SEL_Msk   0x20UL
1485 #define BLE_BLELL_LL_CONFIG_RSSI_EARLY_CNFG_Pos 6UL
1486 #define BLE_BLELL_LL_CONFIG_RSSI_EARLY_CNFG_Msk 0x40UL
1487 #define BLE_BLELL_LL_CONFIG_TX_RX_PIN_DLY_Pos   7UL
1488 #define BLE_BLELL_LL_CONFIG_TX_RX_PIN_DLY_Msk   0x80UL
1489 #define BLE_BLELL_LL_CONFIG_TX_PA_PWR_LVL_TYPE_Pos 8UL
1490 #define BLE_BLELL_LL_CONFIG_TX_PA_PWR_LVL_TYPE_Msk 0x100UL
1491 #define BLE_BLELL_LL_CONFIG_RSSI_ENERGY_RD_Pos  9UL
1492 #define BLE_BLELL_LL_CONFIG_RSSI_ENERGY_RD_Msk  0x200UL
1493 #define BLE_BLELL_LL_CONFIG_RSSI_EACH_PKT_Pos   10UL
1494 #define BLE_BLELL_LL_CONFIG_RSSI_EACH_PKT_Msk   0x400UL
1495 #define BLE_BLELL_LL_CONFIG_FORCE_TRIG_RCB_UPDATE_Pos 11UL
1496 #define BLE_BLELL_LL_CONFIG_FORCE_TRIG_RCB_UPDATE_Msk 0x800UL
1497 #define BLE_BLELL_LL_CONFIG_CHECK_DUP_CONN_Pos  12UL
1498 #define BLE_BLELL_LL_CONFIG_CHECK_DUP_CONN_Msk  0x1000UL
1499 #define BLE_BLELL_LL_CONFIG_MULTI_ENGINE_LPM_Pos 13UL
1500 #define BLE_BLELL_LL_CONFIG_MULTI_ENGINE_LPM_Msk 0x2000UL
1501 #define BLE_BLELL_LL_CONFIG_ADV_DIR_DEVICE_PRIV_EN_Pos 14UL
1502 #define BLE_BLELL_LL_CONFIG_ADV_DIR_DEVICE_PRIV_EN_Msk 0x4000UL
1503 /* BLE_BLELL.LL_CONTROL */
1504 #define BLE_BLELL_LL_CONTROL_PRIV_1_2_Pos       0UL
1505 #define BLE_BLELL_LL_CONTROL_PRIV_1_2_Msk       0x1UL
1506 #define BLE_BLELL_LL_CONTROL_DLE_Pos            1UL
1507 #define BLE_BLELL_LL_CONTROL_DLE_Msk            0x2UL
1508 #define BLE_BLELL_LL_CONTROL_WL_READ_AS_MEM_Pos 2UL
1509 #define BLE_BLELL_LL_CONTROL_WL_READ_AS_MEM_Msk 0x4UL
1510 #define BLE_BLELL_LL_CONTROL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL_Pos 3UL
1511 #define BLE_BLELL_LL_CONTROL_ADVCH_FIFO_PRIV_1_2_FLUSH_CTRL_Msk 0x8UL
1512 #define BLE_BLELL_LL_CONTROL_HW_RSLV_LIST_FULL_Pos 4UL
1513 #define BLE_BLELL_LL_CONTROL_HW_RSLV_LIST_FULL_Msk 0x10UL
1514 #define BLE_BLELL_LL_CONTROL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV_Pos 5UL
1515 #define BLE_BLELL_LL_CONTROL_RPT_INIT_ADDR_MATCH_PRIV_MISMATCH_ADV_Msk 0x20UL
1516 #define BLE_BLELL_LL_CONTROL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV_Pos 6UL
1517 #define BLE_BLELL_LL_CONTROL_RPT_SCAN_ADDR_MATCH_PRIV_MISMATCH_ADV_Msk 0x40UL
1518 #define BLE_BLELL_LL_CONTROL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN_Pos 7UL
1519 #define BLE_BLELL_LL_CONTROL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_SCN_Msk 0x80UL
1520 #define BLE_BLELL_LL_CONTROL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI_Pos 8UL
1521 #define BLE_BLELL_LL_CONTROL_RPT_PEER_ADDR_MATCH_PRIV_MISMATCH_INI_Msk 0x100UL
1522 #define BLE_BLELL_LL_CONTROL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI_Pos 9UL
1523 #define BLE_BLELL_LL_CONTROL_RPT_SELF_ADDR_MATCH_PRIV_MISMATCH_INI_Msk 0x200UL
1524 #define BLE_BLELL_LL_CONTROL_PRIV_1_2_ADV_Pos   10UL
1525 #define BLE_BLELL_LL_CONTROL_PRIV_1_2_ADV_Msk   0x400UL
1526 #define BLE_BLELL_LL_CONTROL_PRIV_1_2_SCAN_Pos  11UL
1527 #define BLE_BLELL_LL_CONTROL_PRIV_1_2_SCAN_Msk  0x800UL
1528 #define BLE_BLELL_LL_CONTROL_PRIV_1_2_INIT_Pos  12UL
1529 #define BLE_BLELL_LL_CONTROL_PRIV_1_2_INIT_Msk  0x1000UL
1530 #define BLE_BLELL_LL_CONTROL_EN_CONN_RX_EN_MOD_Pos 13UL
1531 #define BLE_BLELL_LL_CONTROL_EN_CONN_RX_EN_MOD_Msk 0x2000UL
1532 #define BLE_BLELL_LL_CONTROL_SLV_CONN_PEER_RPA_NOT_RSLVD_Pos 14UL
1533 #define BLE_BLELL_LL_CONTROL_SLV_CONN_PEER_RPA_NOT_RSLVD_Msk 0x4000UL
1534 #define BLE_BLELL_LL_CONTROL_ADVCH_FIFO_FLUSH_Pos 15UL
1535 #define BLE_BLELL_LL_CONTROL_ADVCH_FIFO_FLUSH_Msk 0x8000UL
1536 /* BLE_BLELL.DEV_PA_ADDR_L */
1537 #define BLE_BLELL_DEV_PA_ADDR_L_DEV_PA_ADDR_L_Pos 0UL
1538 #define BLE_BLELL_DEV_PA_ADDR_L_DEV_PA_ADDR_L_Msk 0xFFFFUL
1539 /* BLE_BLELL.DEV_PA_ADDR_M */
1540 #define BLE_BLELL_DEV_PA_ADDR_M_DEV_PA_ADDR_M_Pos 0UL
1541 #define BLE_BLELL_DEV_PA_ADDR_M_DEV_PA_ADDR_M_Msk 0xFFFFUL
1542 /* BLE_BLELL.DEV_PA_ADDR_H */
1543 #define BLE_BLELL_DEV_PA_ADDR_H_DEV_PA_ADDR_H_Pos 0UL
1544 #define BLE_BLELL_DEV_PA_ADDR_H_DEV_PA_ADDR_H_Msk 0xFFFFUL
1545 /* BLE_BLELL.RSLV_LIST_ENABLE */
1546 #define BLE_BLELL_RSLV_LIST_ENABLE_VALID_ENTRY_Pos 0UL
1547 #define BLE_BLELL_RSLV_LIST_ENABLE_VALID_ENTRY_Msk 0x1UL
1548 #define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_IRK_SET_Pos 1UL
1549 #define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_IRK_SET_Msk 0x2UL
1550 #define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_IRK_SET_RX_Pos 2UL
1551 #define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_IRK_SET_RX_Msk 0x4UL
1552 #define BLE_BLELL_RSLV_LIST_ENABLE_WHITELISTED_PEER_Pos 3UL
1553 #define BLE_BLELL_RSLV_LIST_ENABLE_WHITELISTED_PEER_Msk 0x8UL
1554 #define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_TYPE_Pos 4UL
1555 #define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_TYPE_Msk 0x10UL
1556 #define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_RPA_VAL_Pos 5UL
1557 #define BLE_BLELL_RSLV_LIST_ENABLE_PEER_ADDR_RPA_VAL_Msk 0x20UL
1558 #define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_RXD_RPA_VAL_Pos 6UL
1559 #define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_RXD_RPA_VAL_Msk 0x40UL
1560 #define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_TX_RPA_VAL_Pos 7UL
1561 #define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_TX_RPA_VAL_Msk 0x80UL
1562 #define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_INIT_RPA_SEL_Pos 8UL
1563 #define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_INIT_RPA_SEL_Msk 0x100UL
1564 #define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_TYPE_TX_Pos 9UL
1565 #define BLE_BLELL_RSLV_LIST_ENABLE_SELF_ADDR_TYPE_TX_Msk 0x200UL
1566 #define BLE_BLELL_RSLV_LIST_ENABLE_ENTRY_CONNECTED_Pos 10UL
1567 #define BLE_BLELL_RSLV_LIST_ENABLE_ENTRY_CONNECTED_Msk 0x400UL
1568 /* BLE_BLELL.WL_CONNECTION_STATUS */
1569 #define BLE_BLELL_WL_CONNECTION_STATUS_WL_ENTRY_CONNECTED_Pos 0UL
1570 #define BLE_BLELL_WL_CONNECTION_STATUS_WL_ENTRY_CONNECTED_Msk 0xFFFFUL
1571 /* BLE_BLELL.CONN_RXMEM_BASE_ADDR_DLE */
1572 #define BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE_CONN_RX_MEM_BASE_ADDR_DLE_Pos 0UL
1573 #define BLE_BLELL_CONN_RXMEM_BASE_ADDR_DLE_CONN_RX_MEM_BASE_ADDR_DLE_Msk 0xFFFFFFFFUL
1574 /* BLE_BLELL.CONN_TXMEM_BASE_ADDR_DLE */
1575 #define BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE_CONN_TX_MEM_BASE_ADDR_DLE_Pos 0UL
1576 #define BLE_BLELL_CONN_TXMEM_BASE_ADDR_DLE_CONN_TX_MEM_BASE_ADDR_DLE_Msk 0xFFFFFFFFUL
1577 /* BLE_BLELL.CONN_1_PARAM_MEM_BASE_ADDR */
1578 #define BLE_BLELL_CONN_1_PARAM_MEM_BASE_ADDR_CONN_1_PARAM_Pos 0UL
1579 #define BLE_BLELL_CONN_1_PARAM_MEM_BASE_ADDR_CONN_1_PARAM_Msk 0xFFFFUL
1580 /* BLE_BLELL.CONN_2_PARAM_MEM_BASE_ADDR */
1581 #define BLE_BLELL_CONN_2_PARAM_MEM_BASE_ADDR_CONN_2_PARAM_Pos 0UL
1582 #define BLE_BLELL_CONN_2_PARAM_MEM_BASE_ADDR_CONN_2_PARAM_Msk 0xFFFFUL
1583 /* BLE_BLELL.CONN_3_PARAM_MEM_BASE_ADDR */
1584 #define BLE_BLELL_CONN_3_PARAM_MEM_BASE_ADDR_CONN_3_PARAM_Pos 0UL
1585 #define BLE_BLELL_CONN_3_PARAM_MEM_BASE_ADDR_CONN_3_PARAM_Msk 0xFFFFUL
1586 /* BLE_BLELL.CONN_4_PARAM_MEM_BASE_ADDR */
1587 #define BLE_BLELL_CONN_4_PARAM_MEM_BASE_ADDR_CONN_4_PARAM_Pos 0UL
1588 #define BLE_BLELL_CONN_4_PARAM_MEM_BASE_ADDR_CONN_4_PARAM_Msk 0xFFFFUL
1589 /* BLE_BLELL.NI_TIMER */
1590 #define BLE_BLELL_NI_TIMER_NI_TIMER_Pos         0UL
1591 #define BLE_BLELL_NI_TIMER_NI_TIMER_Msk         0xFFFFUL
1592 /* BLE_BLELL.US_OFFSET */
1593 #define BLE_BLELL_US_OFFSET_US_OFFSET_SLOT_BOUNDARY_Pos 0UL
1594 #define BLE_BLELL_US_OFFSET_US_OFFSET_SLOT_BOUNDARY_Msk 0x3FFUL
1595 /* BLE_BLELL.NEXT_CONN */
1596 #define BLE_BLELL_NEXT_CONN_NEXT_CONN_INDEX_Pos 0UL
1597 #define BLE_BLELL_NEXT_CONN_NEXT_CONN_INDEX_Msk 0x1FUL
1598 #define BLE_BLELL_NEXT_CONN_NEXT_CONN_TYPE_Pos  5UL
1599 #define BLE_BLELL_NEXT_CONN_NEXT_CONN_TYPE_Msk  0x20UL
1600 #define BLE_BLELL_NEXT_CONN_NI_VALID_Pos        6UL
1601 #define BLE_BLELL_NEXT_CONN_NI_VALID_Msk        0x40UL
1602 /* BLE_BLELL.NI_ABORT */
1603 #define BLE_BLELL_NI_ABORT_NI_ABORT_Pos         0UL
1604 #define BLE_BLELL_NI_ABORT_NI_ABORT_Msk         0x1UL
1605 #define BLE_BLELL_NI_ABORT_ABORT_ACK_Pos        1UL
1606 #define BLE_BLELL_NI_ABORT_ABORT_ACK_Msk        0x2UL
1607 /* BLE_BLELL.CONN_NI_STATUS */
1608 #define BLE_BLELL_CONN_NI_STATUS_CONN_NI_Pos    0UL
1609 #define BLE_BLELL_CONN_NI_STATUS_CONN_NI_Msk    0xFFFFUL
1610 /* BLE_BLELL.NEXT_SUP_TO_STATUS */
1611 #define BLE_BLELL_NEXT_SUP_TO_STATUS_NEXT_SUP_TO_Pos 0UL
1612 #define BLE_BLELL_NEXT_SUP_TO_STATUS_NEXT_SUP_TO_Msk 0xFFFFUL
1613 /* BLE_BLELL.MMMS_CONN_STATUS */
1614 #define BLE_BLELL_MMMS_CONN_STATUS_CURR_CONN_INDEX_Pos 0UL
1615 #define BLE_BLELL_MMMS_CONN_STATUS_CURR_CONN_INDEX_Msk 0x1FUL
1616 #define BLE_BLELL_MMMS_CONN_STATUS_CURR_CONN_TYPE_Pos 5UL
1617 #define BLE_BLELL_MMMS_CONN_STATUS_CURR_CONN_TYPE_Msk 0x20UL
1618 #define BLE_BLELL_MMMS_CONN_STATUS_SN_CURR_Pos  6UL
1619 #define BLE_BLELL_MMMS_CONN_STATUS_SN_CURR_Msk  0x40UL
1620 #define BLE_BLELL_MMMS_CONN_STATUS_NESN_CURR_Pos 7UL
1621 #define BLE_BLELL_MMMS_CONN_STATUS_NESN_CURR_Msk 0x80UL
1622 #define BLE_BLELL_MMMS_CONN_STATUS_LAST_UNMAPPED_CHANNEL_Pos 8UL
1623 #define BLE_BLELL_MMMS_CONN_STATUS_LAST_UNMAPPED_CHANNEL_Msk 0x3F00UL
1624 #define BLE_BLELL_MMMS_CONN_STATUS_PKT_MISS_Pos 14UL
1625 #define BLE_BLELL_MMMS_CONN_STATUS_PKT_MISS_Msk 0x4000UL
1626 #define BLE_BLELL_MMMS_CONN_STATUS_ANCHOR_PT_STATE_Pos 15UL
1627 #define BLE_BLELL_MMMS_CONN_STATUS_ANCHOR_PT_STATE_Msk 0x8000UL
1628 /* BLE_BLELL.BT_SLOT_CAPT_STATUS */
1629 #define BLE_BLELL_BT_SLOT_CAPT_STATUS_BT_SLOT_Pos 0UL
1630 #define BLE_BLELL_BT_SLOT_CAPT_STATUS_BT_SLOT_Msk 0xFFFFUL
1631 /* BLE_BLELL.US_CAPT_STATUS */
1632 #define BLE_BLELL_US_CAPT_STATUS_US_CAPT_Pos    0UL
1633 #define BLE_BLELL_US_CAPT_STATUS_US_CAPT_Msk    0x3FFUL
1634 /* BLE_BLELL.US_OFFSET_STATUS */
1635 #define BLE_BLELL_US_OFFSET_STATUS_US_OFFSET_Pos 0UL
1636 #define BLE_BLELL_US_OFFSET_STATUS_US_OFFSET_Msk 0xFFFFUL
1637 /* BLE_BLELL.ACCU_WINDOW_WIDEN_STATUS */
1638 #define BLE_BLELL_ACCU_WINDOW_WIDEN_STATUS_ACCU_WINDOW_WIDEN_Pos 0UL
1639 #define BLE_BLELL_ACCU_WINDOW_WIDEN_STATUS_ACCU_WINDOW_WIDEN_Msk 0xFFFFUL
1640 /* BLE_BLELL.EARLY_INTR_STATUS */
1641 #define BLE_BLELL_EARLY_INTR_STATUS_CONN_INDEX_FOR_EARLY_INTR_Pos 0UL
1642 #define BLE_BLELL_EARLY_INTR_STATUS_CONN_INDEX_FOR_EARLY_INTR_Msk 0x1FUL
1643 #define BLE_BLELL_EARLY_INTR_STATUS_CONN_TYPE_FOR_EARLY_INTR_Pos 5UL
1644 #define BLE_BLELL_EARLY_INTR_STATUS_CONN_TYPE_FOR_EARLY_INTR_Msk 0x20UL
1645 #define BLE_BLELL_EARLY_INTR_STATUS_US_FOR_EARLY_INTR_Pos 6UL
1646 #define BLE_BLELL_EARLY_INTR_STATUS_US_FOR_EARLY_INTR_Msk 0xFFC0UL
1647 /* BLE_BLELL.MMMS_CONFIG */
1648 #define BLE_BLELL_MMMS_CONFIG_MMMS_ENABLE_Pos   0UL
1649 #define BLE_BLELL_MMMS_CONFIG_MMMS_ENABLE_Msk   0x1UL
1650 #define BLE_BLELL_MMMS_CONFIG_DISABLE_CONN_REQ_PARAM_IN_MEM_Pos 1UL
1651 #define BLE_BLELL_MMMS_CONFIG_DISABLE_CONN_REQ_PARAM_IN_MEM_Msk 0x2UL
1652 #define BLE_BLELL_MMMS_CONFIG_DISABLE_CONN_PARAM_MEM_WR_Pos 2UL
1653 #define BLE_BLELL_MMMS_CONFIG_DISABLE_CONN_PARAM_MEM_WR_Msk 0x4UL
1654 #define BLE_BLELL_MMMS_CONFIG_CONN_PARAM_FROM_REG_Pos 3UL
1655 #define BLE_BLELL_MMMS_CONFIG_CONN_PARAM_FROM_REG_Msk 0x8UL
1656 #define BLE_BLELL_MMMS_CONFIG_ADV_CONN_INDEX_Pos 4UL
1657 #define BLE_BLELL_MMMS_CONFIG_ADV_CONN_INDEX_Msk 0x1F0UL
1658 #define BLE_BLELL_MMMS_CONFIG_CE_LEN_IMMEDIATE_EXPIRE_Pos 9UL
1659 #define BLE_BLELL_MMMS_CONFIG_CE_LEN_IMMEDIATE_EXPIRE_Msk 0x200UL
1660 #define BLE_BLELL_MMMS_CONFIG_RESET_RX_FIFO_PTR_Pos 10UL
1661 #define BLE_BLELL_MMMS_CONFIG_RESET_RX_FIFO_PTR_Msk 0x400UL
1662 /* BLE_BLELL.US_COUNTER */
1663 #define BLE_BLELL_US_COUNTER_US_COUNTER_Pos     0UL
1664 #define BLE_BLELL_US_COUNTER_US_COUNTER_Msk     0x3FFUL
1665 /* BLE_BLELL.US_CAPT_PREV */
1666 #define BLE_BLELL_US_CAPT_PREV_US_CAPT_LOAD_Pos 0UL
1667 #define BLE_BLELL_US_CAPT_PREV_US_CAPT_LOAD_Msk 0x3FFUL
1668 /* BLE_BLELL.EARLY_INTR_NI */
1669 #define BLE_BLELL_EARLY_INTR_NI_EARLY_INTR_NI_Pos 0UL
1670 #define BLE_BLELL_EARLY_INTR_NI_EARLY_INTR_NI_Msk 0xFFFFUL
1671 /* BLE_BLELL.MMMS_MASTER_CREATE_BT_CAPT */
1672 #define BLE_BLELL_MMMS_MASTER_CREATE_BT_CAPT_BT_SLOT_Pos 0UL
1673 #define BLE_BLELL_MMMS_MASTER_CREATE_BT_CAPT_BT_SLOT_Msk 0xFFFFUL
1674 /* BLE_BLELL.MMMS_SLAVE_CREATE_BT_CAPT */
1675 #define BLE_BLELL_MMMS_SLAVE_CREATE_BT_CAPT_US_CAPT_Pos 0UL
1676 #define BLE_BLELL_MMMS_SLAVE_CREATE_BT_CAPT_US_CAPT_Msk 0x3FFUL
1677 /* BLE_BLELL.MMMS_SLAVE_CREATE_US_CAPT */
1678 #define BLE_BLELL_MMMS_SLAVE_CREATE_US_CAPT_US_OFFSET_SLAVE_CREATED_Pos 0UL
1679 #define BLE_BLELL_MMMS_SLAVE_CREATE_US_CAPT_US_OFFSET_SLAVE_CREATED_Msk 0xFFFFUL
1680 /* BLE_BLELL.MMMS_DATA_MEM_DESCRIPTOR */
1681 #define BLE_BLELL_MMMS_DATA_MEM_DESCRIPTOR_LLID_C1_Pos 0UL
1682 #define BLE_BLELL_MMMS_DATA_MEM_DESCRIPTOR_LLID_C1_Msk 0x3UL
1683 #define BLE_BLELL_MMMS_DATA_MEM_DESCRIPTOR_DATA_LENGTH_C1_Pos 2UL
1684 #define BLE_BLELL_MMMS_DATA_MEM_DESCRIPTOR_DATA_LENGTH_C1_Msk 0x3FCUL
1685 /* BLE_BLELL.CONN_1_DATA_LIST_SENT */
1686 #define BLE_BLELL_CONN_1_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Pos 0UL
1687 #define BLE_BLELL_CONN_1_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Msk 0xFUL
1688 #define BLE_BLELL_CONN_1_DATA_LIST_SENT_SET_CLEAR_C1_Pos 7UL
1689 #define BLE_BLELL_CONN_1_DATA_LIST_SENT_SET_CLEAR_C1_Msk 0x80UL
1690 #define BLE_BLELL_CONN_1_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Pos 8UL
1691 #define BLE_BLELL_CONN_1_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Msk 0xF00UL
1692 /* BLE_BLELL.CONN_1_DATA_LIST_ACK */
1693 #define BLE_BLELL_CONN_1_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Pos 0UL
1694 #define BLE_BLELL_CONN_1_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Msk 0xFUL
1695 #define BLE_BLELL_CONN_1_DATA_LIST_ACK_SET_CLEAR_C1_Pos 7UL
1696 #define BLE_BLELL_CONN_1_DATA_LIST_ACK_SET_CLEAR_C1_Msk 0x80UL
1697 /* BLE_BLELL.CONN_1_CE_DATA_LIST_CFG */
1698 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Pos 0UL
1699 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Msk 0xFUL
1700 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Pos 4UL
1701 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Msk 0x10UL
1702 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Pos 5UL
1703 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Msk 0x20UL
1704 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_MD_C1_Pos 6UL
1705 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_MD_C1_Msk 0x40UL
1706 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Pos 7UL
1707 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Msk 0x80UL
1708 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Pos 8UL
1709 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Msk 0x100UL
1710 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_KILL_CONN_Pos 9UL
1711 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_KILL_CONN_Msk 0x200UL
1712 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Pos 10UL
1713 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Msk 0x400UL
1714 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Pos 11UL
1715 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Msk 0x800UL
1716 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Pos 12UL
1717 #define BLE_BLELL_CONN_1_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Msk 0xF000UL
1718 /* BLE_BLELL.CONN_2_DATA_LIST_SENT */
1719 #define BLE_BLELL_CONN_2_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Pos 0UL
1720 #define BLE_BLELL_CONN_2_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Msk 0xFUL
1721 #define BLE_BLELL_CONN_2_DATA_LIST_SENT_SET_CLEAR_C1_Pos 7UL
1722 #define BLE_BLELL_CONN_2_DATA_LIST_SENT_SET_CLEAR_C1_Msk 0x80UL
1723 #define BLE_BLELL_CONN_2_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Pos 8UL
1724 #define BLE_BLELL_CONN_2_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Msk 0xF00UL
1725 /* BLE_BLELL.CONN_2_DATA_LIST_ACK */
1726 #define BLE_BLELL_CONN_2_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Pos 0UL
1727 #define BLE_BLELL_CONN_2_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Msk 0xFUL
1728 #define BLE_BLELL_CONN_2_DATA_LIST_ACK_SET_CLEAR_C1_Pos 7UL
1729 #define BLE_BLELL_CONN_2_DATA_LIST_ACK_SET_CLEAR_C1_Msk 0x80UL
1730 /* BLE_BLELL.CONN_2_CE_DATA_LIST_CFG */
1731 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Pos 0UL
1732 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Msk 0xFUL
1733 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Pos 4UL
1734 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Msk 0x10UL
1735 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Pos 5UL
1736 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Msk 0x20UL
1737 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_MD_C1_Pos 6UL
1738 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_MD_C1_Msk 0x40UL
1739 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Pos 7UL
1740 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Msk 0x80UL
1741 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Pos 8UL
1742 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Msk 0x100UL
1743 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_KILL_CONN_Pos 9UL
1744 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_KILL_CONN_Msk 0x200UL
1745 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Pos 10UL
1746 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Msk 0x400UL
1747 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Pos 11UL
1748 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Msk 0x800UL
1749 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Pos 12UL
1750 #define BLE_BLELL_CONN_2_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Msk 0xF000UL
1751 /* BLE_BLELL.CONN_3_DATA_LIST_SENT */
1752 #define BLE_BLELL_CONN_3_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Pos 0UL
1753 #define BLE_BLELL_CONN_3_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Msk 0xFUL
1754 #define BLE_BLELL_CONN_3_DATA_LIST_SENT_SET_CLEAR_C1_Pos 7UL
1755 #define BLE_BLELL_CONN_3_DATA_LIST_SENT_SET_CLEAR_C1_Msk 0x80UL
1756 #define BLE_BLELL_CONN_3_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Pos 8UL
1757 #define BLE_BLELL_CONN_3_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Msk 0xF00UL
1758 /* BLE_BLELL.CONN_3_DATA_LIST_ACK */
1759 #define BLE_BLELL_CONN_3_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Pos 0UL
1760 #define BLE_BLELL_CONN_3_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Msk 0xFUL
1761 #define BLE_BLELL_CONN_3_DATA_LIST_ACK_SET_CLEAR_C1_Pos 7UL
1762 #define BLE_BLELL_CONN_3_DATA_LIST_ACK_SET_CLEAR_C1_Msk 0x80UL
1763 /* BLE_BLELL.CONN_3_CE_DATA_LIST_CFG */
1764 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Pos 0UL
1765 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Msk 0xFUL
1766 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Pos 4UL
1767 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Msk 0x10UL
1768 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Pos 5UL
1769 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Msk 0x20UL
1770 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_MD_C1_Pos 6UL
1771 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_MD_C1_Msk 0x40UL
1772 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Pos 7UL
1773 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Msk 0x80UL
1774 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Pos 8UL
1775 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Msk 0x100UL
1776 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_KILL_CONN_Pos 9UL
1777 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_KILL_CONN_Msk 0x200UL
1778 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Pos 10UL
1779 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Msk 0x400UL
1780 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Pos 11UL
1781 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Msk 0x800UL
1782 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Pos 12UL
1783 #define BLE_BLELL_CONN_3_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Msk 0xF000UL
1784 /* BLE_BLELL.CONN_4_DATA_LIST_SENT */
1785 #define BLE_BLELL_CONN_4_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Pos 0UL
1786 #define BLE_BLELL_CONN_4_DATA_LIST_SENT_LIST_INDEX__TX_SENT_3_0_C1_Msk 0xFUL
1787 #define BLE_BLELL_CONN_4_DATA_LIST_SENT_SET_CLEAR_C1_Pos 7UL
1788 #define BLE_BLELL_CONN_4_DATA_LIST_SENT_SET_CLEAR_C1_Msk 0x80UL
1789 #define BLE_BLELL_CONN_4_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Pos 8UL
1790 #define BLE_BLELL_CONN_4_DATA_LIST_SENT_BUFFER_NUM_TX_SENT_3_0_C1_Msk 0xF00UL
1791 /* BLE_BLELL.CONN_4_DATA_LIST_ACK */
1792 #define BLE_BLELL_CONN_4_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Pos 0UL
1793 #define BLE_BLELL_CONN_4_DATA_LIST_ACK_LIST_INDEX__TX_ACK_3_0_C1_Msk 0xFUL
1794 #define BLE_BLELL_CONN_4_DATA_LIST_ACK_SET_CLEAR_C1_Pos 7UL
1795 #define BLE_BLELL_CONN_4_DATA_LIST_ACK_SET_CLEAR_C1_Msk 0x80UL
1796 /* BLE_BLELL.CONN_4_CE_DATA_LIST_CFG */
1797 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Pos 0UL
1798 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_DATA_LIST_INDEX_LAST_ACK_INDEX_C1_Msk 0xFUL
1799 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Pos 4UL
1800 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_DATA_LIST_HEAD_UP_C1_Msk 0x10UL
1801 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Pos 5UL
1802 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_SLV_MD_CONFIG_C1_Msk 0x20UL
1803 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_MD_C1_Pos 6UL
1804 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_MD_C1_Msk 0x40UL
1805 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Pos 7UL
1806 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_MD_BIT_CLEAR_C1_Msk 0x80UL
1807 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Pos 8UL
1808 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_PAUSE_DATA_C1_Msk 0x100UL
1809 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_KILL_CONN_Pos 9UL
1810 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_KILL_CONN_Msk 0x200UL
1811 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Pos 10UL
1812 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_KILL_CONN_AFTER_TX_Msk 0x400UL
1813 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Pos 11UL
1814 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_EMPTYPDU_SENT_Msk 0x800UL
1815 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Pos 12UL
1816 #define BLE_BLELL_CONN_4_CE_DATA_LIST_CFG_CURRENT_PDU_INDEX_C1_Msk 0xF000UL
1817 /* BLE_BLELL.MMMS_ADVCH_NI_ENABLE */
1818 #define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_ADV_NI_ENABLE_Pos 0UL
1819 #define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_ADV_NI_ENABLE_Msk 0x1UL
1820 #define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_SCAN_NI_ENABLE_Pos 1UL
1821 #define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_SCAN_NI_ENABLE_Msk 0x2UL
1822 #define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_INIT_NI_ENABLE_Pos 2UL
1823 #define BLE_BLELL_MMMS_ADVCH_NI_ENABLE_INIT_NI_ENABLE_Msk 0x4UL
1824 /* BLE_BLELL.MMMS_ADVCH_NI_VALID */
1825 #define BLE_BLELL_MMMS_ADVCH_NI_VALID_ADV_NI_VALID_Pos 0UL
1826 #define BLE_BLELL_MMMS_ADVCH_NI_VALID_ADV_NI_VALID_Msk 0x1UL
1827 #define BLE_BLELL_MMMS_ADVCH_NI_VALID_SCAN_NI_VALID_Pos 1UL
1828 #define BLE_BLELL_MMMS_ADVCH_NI_VALID_SCAN_NI_VALID_Msk 0x2UL
1829 #define BLE_BLELL_MMMS_ADVCH_NI_VALID_INIT_NI_VALID_Pos 2UL
1830 #define BLE_BLELL_MMMS_ADVCH_NI_VALID_INIT_NI_VALID_Msk 0x4UL
1831 /* BLE_BLELL.MMMS_ADVCH_NI_ABORT */
1832 #define BLE_BLELL_MMMS_ADVCH_NI_ABORT_ADVCH_NI_ABORT_Pos 0UL
1833 #define BLE_BLELL_MMMS_ADVCH_NI_ABORT_ADVCH_NI_ABORT_Msk 0x1UL
1834 #define BLE_BLELL_MMMS_ADVCH_NI_ABORT_ADVCH_ABORT_STATUS_Pos 1UL
1835 #define BLE_BLELL_MMMS_ADVCH_NI_ABORT_ADVCH_ABORT_STATUS_Msk 0x2UL
1836 /* BLE_BLELL.CONN_PARAM_NEXT_SUP_TO */
1837 #define BLE_BLELL_CONN_PARAM_NEXT_SUP_TO_NEXT_SUP_TO_LOAD_Pos 0UL
1838 #define BLE_BLELL_CONN_PARAM_NEXT_SUP_TO_NEXT_SUP_TO_LOAD_Msk 0xFFFFUL
1839 /* BLE_BLELL.CONN_PARAM_ACC_WIN_WIDEN */
1840 #define BLE_BLELL_CONN_PARAM_ACC_WIN_WIDEN_ACC_WINDOW_WIDEN_Pos 0UL
1841 #define BLE_BLELL_CONN_PARAM_ACC_WIN_WIDEN_ACC_WINDOW_WIDEN_Msk 0x3FFUL
1842 /* BLE_BLELL.HW_LOAD_OFFSET */
1843 #define BLE_BLELL_HW_LOAD_OFFSET_LOAD_OFFSET_Pos 0UL
1844 #define BLE_BLELL_HW_LOAD_OFFSET_LOAD_OFFSET_Msk 0x1FUL
1845 /* BLE_BLELL.ADV_RAND */
1846 #define BLE_BLELL_ADV_RAND_ADV_RAND_Pos         0UL
1847 #define BLE_BLELL_ADV_RAND_ADV_RAND_Msk         0xFUL
1848 /* BLE_BLELL.MMMS_RX_PKT_CNTR */
1849 #define BLE_BLELL_MMMS_RX_PKT_CNTR_MMMS_RX_PKT_CNT_Pos 0UL
1850 #define BLE_BLELL_MMMS_RX_PKT_CNTR_MMMS_RX_PKT_CNT_Msk 0x3FUL
1851 /* BLE_BLELL.CONN_RX_PKT_CNTR */
1852 #define BLE_BLELL_CONN_RX_PKT_CNTR_RX_PKT_CNT_Pos 0UL
1853 #define BLE_BLELL_CONN_RX_PKT_CNTR_RX_PKT_CNT_Msk 0x3FUL
1854 /* BLE_BLELL.WHITELIST_BASE_ADDR */
1855 #define BLE_BLELL_WHITELIST_BASE_ADDR_WL_BASE_ADDR_Pos 0UL
1856 #define BLE_BLELL_WHITELIST_BASE_ADDR_WL_BASE_ADDR_Msk 0xFFFFUL
1857 /* BLE_BLELL.RSLV_LIST_PEER_IDNTT_BASE_ADDR */
1858 #define BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR_RSLV_LIST_PEER_IDNTT_BASE_ADDR_Pos 0UL
1859 #define BLE_BLELL_RSLV_LIST_PEER_IDNTT_BASE_ADDR_RSLV_LIST_PEER_IDNTT_BASE_ADDR_Msk 0xFFFFUL
1860 /* BLE_BLELL.RSLV_LIST_PEER_RPA_BASE_ADDR */
1861 #define BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR_RSLV_LIST_PEER_RPA_BASE_ADDR_Pos 0UL
1862 #define BLE_BLELL_RSLV_LIST_PEER_RPA_BASE_ADDR_RSLV_LIST_PEER_RPA_BASE_ADDR_Msk 0xFFFFUL
1863 /* BLE_BLELL.RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR */
1864 #define BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR_Pos 0UL
1865 #define BLE_BLELL_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR_RSLV_LIST_RCVD_INIT_RPA_BASE_ADDR_Msk 0xFFFFUL
1866 /* BLE_BLELL.RSLV_LIST_TX_INIT_RPA_BASE_ADDR */
1867 #define BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR_RSLV_LIST_TX_INIT_RPA_BASE_ADDR_Pos 0UL
1868 #define BLE_BLELL_RSLV_LIST_TX_INIT_RPA_BASE_ADDR_RSLV_LIST_TX_INIT_RPA_BASE_ADDR_Msk 0xFFFFUL
1869 
1870 
1871 /* BLE_BLESS.DDFT_CONFIG */
1872 #define BLE_BLESS_DDFT_CONFIG_DDFT_ENABLE_Pos   0UL
1873 #define BLE_BLESS_DDFT_CONFIG_DDFT_ENABLE_Msk   0x1UL
1874 #define BLE_BLESS_DDFT_CONFIG_BLERD_DDFT_EN_Pos 1UL
1875 #define BLE_BLESS_DDFT_CONFIG_BLERD_DDFT_EN_Msk 0x2UL
1876 #define BLE_BLESS_DDFT_CONFIG_DDFT_MUX_CFG1_Pos 8UL
1877 #define BLE_BLESS_DDFT_CONFIG_DDFT_MUX_CFG1_Msk 0x1F00UL
1878 #define BLE_BLESS_DDFT_CONFIG_DDFT_MUX_CFG2_Pos 16UL
1879 #define BLE_BLESS_DDFT_CONFIG_DDFT_MUX_CFG2_Msk 0x1F0000UL
1880 /* BLE_BLESS.XTAL_CLK_DIV_CONFIG */
1881 #define BLE_BLESS_XTAL_CLK_DIV_CONFIG_SYSCLK_DIV_Pos 0UL
1882 #define BLE_BLESS_XTAL_CLK_DIV_CONFIG_SYSCLK_DIV_Msk 0x3UL
1883 #define BLE_BLESS_XTAL_CLK_DIV_CONFIG_LLCLK_DIV_Pos 2UL
1884 #define BLE_BLESS_XTAL_CLK_DIV_CONFIG_LLCLK_DIV_Msk 0xCUL
1885 /* BLE_BLESS.INTR_STAT */
1886 #define BLE_BLESS_INTR_STAT_DSM_ENTERED_INTR_Pos 0UL
1887 #define BLE_BLESS_INTR_STAT_DSM_ENTERED_INTR_Msk 0x1UL
1888 #define BLE_BLESS_INTR_STAT_DSM_EXITED_INTR_Pos 1UL
1889 #define BLE_BLESS_INTR_STAT_DSM_EXITED_INTR_Msk 0x2UL
1890 #define BLE_BLESS_INTR_STAT_RCBLL_DONE_INTR_Pos 2UL
1891 #define BLE_BLESS_INTR_STAT_RCBLL_DONE_INTR_Msk 0x4UL
1892 #define BLE_BLESS_INTR_STAT_BLERD_ACTIVE_INTR_Pos 3UL
1893 #define BLE_BLESS_INTR_STAT_BLERD_ACTIVE_INTR_Msk 0x8UL
1894 #define BLE_BLESS_INTR_STAT_RCB_INTR_Pos        4UL
1895 #define BLE_BLESS_INTR_STAT_RCB_INTR_Msk        0x10UL
1896 #define BLE_BLESS_INTR_STAT_LL_INTR_Pos         5UL
1897 #define BLE_BLESS_INTR_STAT_LL_INTR_Msk         0x20UL
1898 #define BLE_BLESS_INTR_STAT_GPIO_INTR_Pos       6UL
1899 #define BLE_BLESS_INTR_STAT_GPIO_INTR_Msk       0x40UL
1900 #define BLE_BLESS_INTR_STAT_EFUSE_INTR_Pos      7UL
1901 #define BLE_BLESS_INTR_STAT_EFUSE_INTR_Msk      0x80UL
1902 #define BLE_BLESS_INTR_STAT_XTAL_ON_INTR_Pos    8UL
1903 #define BLE_BLESS_INTR_STAT_XTAL_ON_INTR_Msk    0x100UL
1904 #define BLE_BLESS_INTR_STAT_ENC_INTR_Pos        9UL
1905 #define BLE_BLESS_INTR_STAT_ENC_INTR_Msk        0x200UL
1906 #define BLE_BLESS_INTR_STAT_HVLDO_LV_DETECT_POS_Pos 10UL
1907 #define BLE_BLESS_INTR_STAT_HVLDO_LV_DETECT_POS_Msk 0x400UL
1908 #define BLE_BLESS_INTR_STAT_HVLDO_LV_DETECT_NEG_Pos 11UL
1909 #define BLE_BLESS_INTR_STAT_HVLDO_LV_DETECT_NEG_Msk 0x800UL
1910 /* BLE_BLESS.INTR_MASK */
1911 #define BLE_BLESS_INTR_MASK_DSM_EXIT_Pos        0UL
1912 #define BLE_BLESS_INTR_MASK_DSM_EXIT_Msk        0x1UL
1913 #define BLE_BLESS_INTR_MASK_DSM_ENTERED_INTR_MASK_Pos 1UL
1914 #define BLE_BLESS_INTR_MASK_DSM_ENTERED_INTR_MASK_Msk 0x2UL
1915 #define BLE_BLESS_INTR_MASK_DSM_EXITED_INTR_MASK_Pos 2UL
1916 #define BLE_BLESS_INTR_MASK_DSM_EXITED_INTR_MASK_Msk 0x4UL
1917 #define BLE_BLESS_INTR_MASK_XTAL_ON_INTR_MASK_Pos 3UL
1918 #define BLE_BLESS_INTR_MASK_XTAL_ON_INTR_MASK_Msk 0x8UL
1919 #define BLE_BLESS_INTR_MASK_RCBLL_INTR_MASK_Pos 4UL
1920 #define BLE_BLESS_INTR_MASK_RCBLL_INTR_MASK_Msk 0x10UL
1921 #define BLE_BLESS_INTR_MASK_BLERD_ACTIVE_INTR_MASK_Pos 5UL
1922 #define BLE_BLESS_INTR_MASK_BLERD_ACTIVE_INTR_MASK_Msk 0x20UL
1923 #define BLE_BLESS_INTR_MASK_RCB_INTR_MASK_Pos   6UL
1924 #define BLE_BLESS_INTR_MASK_RCB_INTR_MASK_Msk   0x40UL
1925 #define BLE_BLESS_INTR_MASK_LL_INTR_MASK_Pos    7UL
1926 #define BLE_BLESS_INTR_MASK_LL_INTR_MASK_Msk    0x80UL
1927 #define BLE_BLESS_INTR_MASK_GPIO_INTR_MASK_Pos  8UL
1928 #define BLE_BLESS_INTR_MASK_GPIO_INTR_MASK_Msk  0x100UL
1929 #define BLE_BLESS_INTR_MASK_EFUSE_INTR_MASK_Pos 9UL
1930 #define BLE_BLESS_INTR_MASK_EFUSE_INTR_MASK_Msk 0x200UL
1931 #define BLE_BLESS_INTR_MASK_ENC_INTR_MASK_Pos   10UL
1932 #define BLE_BLESS_INTR_MASK_ENC_INTR_MASK_Msk   0x400UL
1933 #define BLE_BLESS_INTR_MASK_HVLDO_LV_DETECT_POS_MASK_Pos 11UL
1934 #define BLE_BLESS_INTR_MASK_HVLDO_LV_DETECT_POS_MASK_Msk 0x800UL
1935 #define BLE_BLESS_INTR_MASK_HVLDO_LV_DETECT_NEG_MASK_Pos 12UL
1936 #define BLE_BLESS_INTR_MASK_HVLDO_LV_DETECT_NEG_MASK_Msk 0x1000UL
1937 /* BLE_BLESS.LL_CLK_EN */
1938 #define BLE_BLESS_LL_CLK_EN_CLK_EN_Pos          0UL
1939 #define BLE_BLESS_LL_CLK_EN_CLK_EN_Msk          0x1UL
1940 #define BLE_BLESS_LL_CLK_EN_CY_CORREL_EN_Pos    1UL
1941 #define BLE_BLESS_LL_CLK_EN_CY_CORREL_EN_Msk    0x2UL
1942 #define BLE_BLESS_LL_CLK_EN_MXD_IF_OPTION_Pos   2UL
1943 #define BLE_BLESS_LL_CLK_EN_MXD_IF_OPTION_Msk   0x4UL
1944 #define BLE_BLESS_LL_CLK_EN_SEL_RCB_CLK_Pos     3UL
1945 #define BLE_BLESS_LL_CLK_EN_SEL_RCB_CLK_Msk     0x8UL
1946 #define BLE_BLESS_LL_CLK_EN_BLESS_RESET_Pos     4UL
1947 #define BLE_BLESS_LL_CLK_EN_BLESS_RESET_Msk     0x10UL
1948 #define BLE_BLESS_LL_CLK_EN_DPSLP_HWRCB_EN_Pos  5UL
1949 #define BLE_BLESS_LL_CLK_EN_DPSLP_HWRCB_EN_Msk  0x20UL
1950 /* BLE_BLESS.LF_CLK_CTRL */
1951 #define BLE_BLESS_LF_CLK_CTRL_DISABLE_LF_CLK_Pos 0UL
1952 #define BLE_BLESS_LF_CLK_CTRL_DISABLE_LF_CLK_Msk 0x1UL
1953 #define BLE_BLESS_LF_CLK_CTRL_ENABLE_ENC_CLK_Pos 1UL
1954 #define BLE_BLESS_LF_CLK_CTRL_ENABLE_ENC_CLK_Msk 0x2UL
1955 #define BLE_BLESS_LF_CLK_CTRL_M0S8BLESS_REV_ID_Pos 29UL
1956 #define BLE_BLESS_LF_CLK_CTRL_M0S8BLESS_REV_ID_Msk 0xE0000000UL
1957 /* BLE_BLESS.EXT_PA_LNA_CTRL */
1958 #define BLE_BLESS_EXT_PA_LNA_CTRL_ENABLE_EXT_PA_LNA_Pos 1UL
1959 #define BLE_BLESS_EXT_PA_LNA_CTRL_ENABLE_EXT_PA_LNA_Msk 0x2UL
1960 #define BLE_BLESS_EXT_PA_LNA_CTRL_CHIP_EN_POL_Pos 2UL
1961 #define BLE_BLESS_EXT_PA_LNA_CTRL_CHIP_EN_POL_Msk 0x4UL
1962 #define BLE_BLESS_EXT_PA_LNA_CTRL_PA_CTRL_POL_Pos 3UL
1963 #define BLE_BLESS_EXT_PA_LNA_CTRL_PA_CTRL_POL_Msk 0x8UL
1964 #define BLE_BLESS_EXT_PA_LNA_CTRL_LNA_CTRL_POL_Pos 4UL
1965 #define BLE_BLESS_EXT_PA_LNA_CTRL_LNA_CTRL_POL_Msk 0x10UL
1966 #define BLE_BLESS_EXT_PA_LNA_CTRL_OUT_EN_DRIVE_VAL_Pos 5UL
1967 #define BLE_BLESS_EXT_PA_LNA_CTRL_OUT_EN_DRIVE_VAL_Msk 0x20UL
1968 /* BLE_BLESS.LL_PKT_RSSI_CH_ENERGY */
1969 #define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_RSSI_Pos 0UL
1970 #define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_RSSI_Msk 0xFFFFUL
1971 #define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_RX_CHANNEL_Pos 16UL
1972 #define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_RX_CHANNEL_Msk 0x3F0000UL
1973 #define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_PKT_RSSI_OR_CH_ENERGY_Pos 22UL
1974 #define BLE_BLESS_LL_PKT_RSSI_CH_ENERGY_PKT_RSSI_OR_CH_ENERGY_Msk 0x400000UL
1975 /* BLE_BLESS.BT_CLOCK_CAPT */
1976 #define BLE_BLESS_BT_CLOCK_CAPT_BT_CLOCK_Pos    0UL
1977 #define BLE_BLESS_BT_CLOCK_CAPT_BT_CLOCK_Msk    0xFFFFUL
1978 /* BLE_BLESS.MT_CFG */
1979 #define BLE_BLESS_MT_CFG_ENABLE_BLERD_Pos       0UL
1980 #define BLE_BLESS_MT_CFG_ENABLE_BLERD_Msk       0x1UL
1981 #define BLE_BLESS_MT_CFG_DEEPSLEEP_EXIT_CFG_Pos 1UL
1982 #define BLE_BLESS_MT_CFG_DEEPSLEEP_EXIT_CFG_Msk 0x2UL
1983 #define BLE_BLESS_MT_CFG_DEEPSLEEP_EXITED_Pos   2UL
1984 #define BLE_BLESS_MT_CFG_DEEPSLEEP_EXITED_Msk   0x4UL
1985 #define BLE_BLESS_MT_CFG_ACT_LDO_NOT_BUCK_Pos   3UL
1986 #define BLE_BLESS_MT_CFG_ACT_LDO_NOT_BUCK_Msk   0x8UL
1987 #define BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_BYPASS_Pos 4UL
1988 #define BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_BYPASS_Msk 0x10UL
1989 #define BLE_BLESS_MT_CFG_HVLDO_BYPASS_Pos       5UL
1990 #define BLE_BLESS_MT_CFG_HVLDO_BYPASS_Msk       0x20UL
1991 #define BLE_BLESS_MT_CFG_OVERRIDE_ACT_REGULATOR_Pos 6UL
1992 #define BLE_BLESS_MT_CFG_OVERRIDE_ACT_REGULATOR_Msk 0x40UL
1993 #define BLE_BLESS_MT_CFG_ACT_REGULATOR_EN_Pos   7UL
1994 #define BLE_BLESS_MT_CFG_ACT_REGULATOR_EN_Msk   0x80UL
1995 #define BLE_BLESS_MT_CFG_OVERRIDE_DIG_REGULATOR_Pos 8UL
1996 #define BLE_BLESS_MT_CFG_OVERRIDE_DIG_REGULATOR_Msk 0x100UL
1997 #define BLE_BLESS_MT_CFG_DIG_REGULATOR_EN_Pos   9UL
1998 #define BLE_BLESS_MT_CFG_DIG_REGULATOR_EN_Msk   0x200UL
1999 #define BLE_BLESS_MT_CFG_OVERRIDE_RET_SWITCH_Pos 10UL
2000 #define BLE_BLESS_MT_CFG_OVERRIDE_RET_SWITCH_Msk 0x400UL
2001 #define BLE_BLESS_MT_CFG_RET_SWITCH_Pos         11UL
2002 #define BLE_BLESS_MT_CFG_RET_SWITCH_Msk         0x800UL
2003 #define BLE_BLESS_MT_CFG_OVERRIDE_ISOLATE_Pos   12UL
2004 #define BLE_BLESS_MT_CFG_OVERRIDE_ISOLATE_Msk   0x1000UL
2005 #define BLE_BLESS_MT_CFG_ISOLATE_N_Pos          13UL
2006 #define BLE_BLESS_MT_CFG_ISOLATE_N_Msk          0x2000UL
2007 #define BLE_BLESS_MT_CFG_OVERRIDE_LL_CLK_EN_Pos 14UL
2008 #define BLE_BLESS_MT_CFG_OVERRIDE_LL_CLK_EN_Msk 0x4000UL
2009 #define BLE_BLESS_MT_CFG_LL_CLK_EN_Pos          15UL
2010 #define BLE_BLESS_MT_CFG_LL_CLK_EN_Msk          0x8000UL
2011 #define BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_EN_Pos  16UL
2012 #define BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_EN_Msk  0x10000UL
2013 #define BLE_BLESS_MT_CFG_HVLDO_EN_Pos           17UL
2014 #define BLE_BLESS_MT_CFG_HVLDO_EN_Msk           0x20000UL
2015 #define BLE_BLESS_MT_CFG_DPSLP_ECO_ON_Pos       18UL
2016 #define BLE_BLESS_MT_CFG_DPSLP_ECO_ON_Msk       0x40000UL
2017 #define BLE_BLESS_MT_CFG_OVERRIDE_RESET_N_Pos   19UL
2018 #define BLE_BLESS_MT_CFG_OVERRIDE_RESET_N_Msk   0x80000UL
2019 #define BLE_BLESS_MT_CFG_RESET_N_Pos            20UL
2020 #define BLE_BLESS_MT_CFG_RESET_N_Msk            0x100000UL
2021 #define BLE_BLESS_MT_CFG_OVERRIDE_XTAL_EN_Pos   21UL
2022 #define BLE_BLESS_MT_CFG_OVERRIDE_XTAL_EN_Msk   0x200000UL
2023 #define BLE_BLESS_MT_CFG_XTAL_EN_Pos            22UL
2024 #define BLE_BLESS_MT_CFG_XTAL_EN_Msk            0x400000UL
2025 #define BLE_BLESS_MT_CFG_OVERRIDE_CLK_EN_Pos    23UL
2026 #define BLE_BLESS_MT_CFG_OVERRIDE_CLK_EN_Msk    0x800000UL
2027 #define BLE_BLESS_MT_CFG_BLERD_CLK_EN_Pos       24UL
2028 #define BLE_BLESS_MT_CFG_BLERD_CLK_EN_Msk       0x1000000UL
2029 #define BLE_BLESS_MT_CFG_OVERRIDE_RET_LDO_OL_Pos 25UL
2030 #define BLE_BLESS_MT_CFG_OVERRIDE_RET_LDO_OL_Msk 0x2000000UL
2031 #define BLE_BLESS_MT_CFG_RET_LDO_OL_Pos         26UL
2032 #define BLE_BLESS_MT_CFG_RET_LDO_OL_Msk         0x4000000UL
2033 #define BLE_BLESS_MT_CFG_HVLDO_POR_HV_Pos       27UL
2034 #define BLE_BLESS_MT_CFG_HVLDO_POR_HV_Msk       0x8000000UL
2035 /* BLE_BLESS.MT_DELAY_CFG */
2036 #define BLE_BLESS_MT_DELAY_CFG_HVLDO_STARTUP_DELAY_Pos 0UL
2037 #define BLE_BLESS_MT_DELAY_CFG_HVLDO_STARTUP_DELAY_Msk 0xFFUL
2038 #define BLE_BLESS_MT_DELAY_CFG_ISOLATE_DEASSERT_DELAY_Pos 8UL
2039 #define BLE_BLESS_MT_DELAY_CFG_ISOLATE_DEASSERT_DELAY_Msk 0xFF00UL
2040 #define BLE_BLESS_MT_DELAY_CFG_ACT_TO_SWITCH_DELAY_Pos 16UL
2041 #define BLE_BLESS_MT_DELAY_CFG_ACT_TO_SWITCH_DELAY_Msk 0xFF0000UL
2042 #define BLE_BLESS_MT_DELAY_CFG_HVLDO_DISABLE_DELAY_Pos 24UL
2043 #define BLE_BLESS_MT_DELAY_CFG_HVLDO_DISABLE_DELAY_Msk 0xFF000000UL
2044 /* BLE_BLESS.MT_DELAY_CFG2 */
2045 #define BLE_BLESS_MT_DELAY_CFG2_OSC_STARTUP_DELAY_LF_Pos 0UL
2046 #define BLE_BLESS_MT_DELAY_CFG2_OSC_STARTUP_DELAY_LF_Msk 0xFFUL
2047 #define BLE_BLESS_MT_DELAY_CFG2_DSM_OFFSET_TO_WAKEUP_INSTANT_LF_Pos 8UL
2048 #define BLE_BLESS_MT_DELAY_CFG2_DSM_OFFSET_TO_WAKEUP_INSTANT_LF_Msk 0xFF00UL
2049 #define BLE_BLESS_MT_DELAY_CFG2_ACT_STARTUP_DELAY_Pos 16UL
2050 #define BLE_BLESS_MT_DELAY_CFG2_ACT_STARTUP_DELAY_Msk 0xFF0000UL
2051 #define BLE_BLESS_MT_DELAY_CFG2_DIG_LDO_STARTUP_DELAY_Pos 24UL
2052 #define BLE_BLESS_MT_DELAY_CFG2_DIG_LDO_STARTUP_DELAY_Msk 0xFF000000UL
2053 /* BLE_BLESS.MT_DELAY_CFG3 */
2054 #define BLE_BLESS_MT_DELAY_CFG3_XTAL_DISABLE_DELAY_Pos 0UL
2055 #define BLE_BLESS_MT_DELAY_CFG3_XTAL_DISABLE_DELAY_Msk 0xFFUL
2056 #define BLE_BLESS_MT_DELAY_CFG3_DIG_LDO_DISABLE_DELAY_Pos 8UL
2057 #define BLE_BLESS_MT_DELAY_CFG3_DIG_LDO_DISABLE_DELAY_Msk 0xFF00UL
2058 #define BLE_BLESS_MT_DELAY_CFG3_VDDR_STABLE_DELAY_Pos 16UL
2059 #define BLE_BLESS_MT_DELAY_CFG3_VDDR_STABLE_DELAY_Msk 0xFF0000UL
2060 /* BLE_BLESS.MT_VIO_CTRL */
2061 #define BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Pos 0UL
2062 #define BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Msk 0x1UL
2063 #define BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_DLY_Pos 1UL
2064 #define BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_DLY_Msk 0x2UL
2065 /* BLE_BLESS.MT_STATUS */
2066 #define BLE_BLESS_MT_STATUS_BLESS_STATE_Pos     0UL
2067 #define BLE_BLESS_MT_STATUS_BLESS_STATE_Msk     0x1UL
2068 #define BLE_BLESS_MT_STATUS_MT_CURR_STATE_Pos   1UL
2069 #define BLE_BLESS_MT_STATUS_MT_CURR_STATE_Msk   0x1EUL
2070 #define BLE_BLESS_MT_STATUS_HVLDO_STARTUP_CURR_STATE_Pos 5UL
2071 #define BLE_BLESS_MT_STATUS_HVLDO_STARTUP_CURR_STATE_Msk 0xE0UL
2072 #define BLE_BLESS_MT_STATUS_LL_CLK_STATE_Pos    8UL
2073 #define BLE_BLESS_MT_STATUS_LL_CLK_STATE_Msk    0x100UL
2074 /* BLE_BLESS.PWR_CTRL_SM_ST */
2075 #define BLE_BLESS_PWR_CTRL_SM_ST_PWR_CTRL_SM_CURR_STATE_Pos 0UL
2076 #define BLE_BLESS_PWR_CTRL_SM_ST_PWR_CTRL_SM_CURR_STATE_Msk 0xFUL
2077 /* BLE_BLESS.HVLDO_CTRL */
2078 #define BLE_BLESS_HVLDO_CTRL_ADFT_EN_Pos        0UL
2079 #define BLE_BLESS_HVLDO_CTRL_ADFT_EN_Msk        0x1UL
2080 #define BLE_BLESS_HVLDO_CTRL_ADFT_CTRL_Pos      1UL
2081 #define BLE_BLESS_HVLDO_CTRL_ADFT_CTRL_Msk      0x1EUL
2082 #define BLE_BLESS_HVLDO_CTRL_VREF_EXT_EN_Pos    6UL
2083 #define BLE_BLESS_HVLDO_CTRL_VREF_EXT_EN_Msk    0x40UL
2084 #define BLE_BLESS_HVLDO_CTRL_STATUS_Pos         31UL
2085 #define BLE_BLESS_HVLDO_CTRL_STATUS_Msk         0x80000000UL
2086 /* BLE_BLESS.MISC_EN_CTRL */
2087 #define BLE_BLESS_MISC_EN_CTRL_BUCK_EN_CTRL_Pos 0UL
2088 #define BLE_BLESS_MISC_EN_CTRL_BUCK_EN_CTRL_Msk 0x1UL
2089 #define BLE_BLESS_MISC_EN_CTRL_ACT_REG_EN_CTRL_Pos 1UL
2090 #define BLE_BLESS_MISC_EN_CTRL_ACT_REG_EN_CTRL_Msk 0x2UL
2091 #define BLE_BLESS_MISC_EN_CTRL_LPM_DRIFT_EN_Pos 2UL
2092 #define BLE_BLESS_MISC_EN_CTRL_LPM_DRIFT_EN_Msk 0x4UL
2093 #define BLE_BLESS_MISC_EN_CTRL_LPM_DRIFT_MULTI_Pos 3UL
2094 #define BLE_BLESS_MISC_EN_CTRL_LPM_DRIFT_MULTI_Msk 0x8UL
2095 #define BLE_BLESS_MISC_EN_CTRL_LPM_ENTRY_CTRL_MODE_Pos 4UL
2096 #define BLE_BLESS_MISC_EN_CTRL_LPM_ENTRY_CTRL_MODE_Msk 0x10UL
2097 /* BLE_BLESS.EFUSE_CONFIG */
2098 #define BLE_BLESS_EFUSE_CONFIG_EFUSE_MODE_Pos   0UL
2099 #define BLE_BLESS_EFUSE_CONFIG_EFUSE_MODE_Msk   0x1UL
2100 #define BLE_BLESS_EFUSE_CONFIG_EFUSE_READ_Pos   1UL
2101 #define BLE_BLESS_EFUSE_CONFIG_EFUSE_READ_Msk   0x2UL
2102 #define BLE_BLESS_EFUSE_CONFIG_EFUSE_WRITE_Pos  2UL
2103 #define BLE_BLESS_EFUSE_CONFIG_EFUSE_WRITE_Msk  0x4UL
2104 /* BLE_BLESS.EFUSE_TIM_CTRL1 */
2105 #define BLE_BLESS_EFUSE_TIM_CTRL1_SCLK_HIGH_Pos 0UL
2106 #define BLE_BLESS_EFUSE_TIM_CTRL1_SCLK_HIGH_Msk 0xFFUL
2107 #define BLE_BLESS_EFUSE_TIM_CTRL1_SCLK_LOW_Pos  8UL
2108 #define BLE_BLESS_EFUSE_TIM_CTRL1_SCLK_LOW_Msk  0xFF00UL
2109 #define BLE_BLESS_EFUSE_TIM_CTRL1_CS_SCLK_SETUP_TIME_Pos 16UL
2110 #define BLE_BLESS_EFUSE_TIM_CTRL1_CS_SCLK_SETUP_TIME_Msk 0xF0000UL
2111 #define BLE_BLESS_EFUSE_TIM_CTRL1_CS_SCLK_HOLD_TIME_Pos 20UL
2112 #define BLE_BLESS_EFUSE_TIM_CTRL1_CS_SCLK_HOLD_TIME_Msk 0xF00000UL
2113 #define BLE_BLESS_EFUSE_TIM_CTRL1_RW_CS_SETUP_TIME_Pos 24UL
2114 #define BLE_BLESS_EFUSE_TIM_CTRL1_RW_CS_SETUP_TIME_Msk 0xF000000UL
2115 #define BLE_BLESS_EFUSE_TIM_CTRL1_RW_CS_HOLD_TIME_Pos 28UL
2116 #define BLE_BLESS_EFUSE_TIM_CTRL1_RW_CS_HOLD_TIME_Msk 0xF0000000UL
2117 /* BLE_BLESS.EFUSE_TIM_CTRL2 */
2118 #define BLE_BLESS_EFUSE_TIM_CTRL2_DATA_SAMPLE_TIME_Pos 0UL
2119 #define BLE_BLESS_EFUSE_TIM_CTRL2_DATA_SAMPLE_TIME_Msk 0xFFUL
2120 #define BLE_BLESS_EFUSE_TIM_CTRL2_DOUT_CS_HOLD_TIME_Pos 8UL
2121 #define BLE_BLESS_EFUSE_TIM_CTRL2_DOUT_CS_HOLD_TIME_Msk 0xF00UL
2122 /* BLE_BLESS.EFUSE_TIM_CTRL3 */
2123 #define BLE_BLESS_EFUSE_TIM_CTRL3_PGM_SCLK_SETUP_TIME_Pos 0UL
2124 #define BLE_BLESS_EFUSE_TIM_CTRL3_PGM_SCLK_SETUP_TIME_Msk 0xFUL
2125 #define BLE_BLESS_EFUSE_TIM_CTRL3_PGM_SCLK_HOLD_TIME_Pos 4UL
2126 #define BLE_BLESS_EFUSE_TIM_CTRL3_PGM_SCLK_HOLD_TIME_Msk 0xF0UL
2127 #define BLE_BLESS_EFUSE_TIM_CTRL3_AVDD_CS_SETUP_TIME_Pos 8UL
2128 #define BLE_BLESS_EFUSE_TIM_CTRL3_AVDD_CS_SETUP_TIME_Msk 0xFF00UL
2129 #define BLE_BLESS_EFUSE_TIM_CTRL3_AVDD_CS_HOLD_TIME_Pos 16UL
2130 #define BLE_BLESS_EFUSE_TIM_CTRL3_AVDD_CS_HOLD_TIME_Msk 0xFF0000UL
2131 /* BLE_BLESS.EFUSE_RDATA_L */
2132 #define BLE_BLESS_EFUSE_RDATA_L_DATA_Pos        0UL
2133 #define BLE_BLESS_EFUSE_RDATA_L_DATA_Msk        0xFFFFFFFFUL
2134 /* BLE_BLESS.EFUSE_RDATA_H */
2135 #define BLE_BLESS_EFUSE_RDATA_H_DATA_Pos        0UL
2136 #define BLE_BLESS_EFUSE_RDATA_H_DATA_Msk        0xFFFFFFFFUL
2137 /* BLE_BLESS.EFUSE_WDATA_L */
2138 #define BLE_BLESS_EFUSE_WDATA_L_DATA_Pos        0UL
2139 #define BLE_BLESS_EFUSE_WDATA_L_DATA_Msk        0xFFFFFFFFUL
2140 /* BLE_BLESS.EFUSE_WDATA_H */
2141 #define BLE_BLESS_EFUSE_WDATA_H_DATA_Pos        0UL
2142 #define BLE_BLESS_EFUSE_WDATA_H_DATA_Msk        0xFFFFFFFFUL
2143 /* BLE_BLESS.DIV_BY_625_CFG */
2144 #define BLE_BLESS_DIV_BY_625_CFG_ENABLE_Pos     1UL
2145 #define BLE_BLESS_DIV_BY_625_CFG_ENABLE_Msk     0x2UL
2146 #define BLE_BLESS_DIV_BY_625_CFG_DIVIDEND_Pos   8UL
2147 #define BLE_BLESS_DIV_BY_625_CFG_DIVIDEND_Msk   0xFFFF00UL
2148 /* BLE_BLESS.DIV_BY_625_STS */
2149 #define BLE_BLESS_DIV_BY_625_STS_QUOTIENT_Pos   0UL
2150 #define BLE_BLESS_DIV_BY_625_STS_QUOTIENT_Msk   0x3FUL
2151 #define BLE_BLESS_DIV_BY_625_STS_REMAINDER_Pos  8UL
2152 #define BLE_BLESS_DIV_BY_625_STS_REMAINDER_Msk  0x3FF00UL
2153 /* BLE_BLESS.PACKET_COUNTER0 */
2154 #define BLE_BLESS_PACKET_COUNTER0_PACKET_COUNTER_LOWER_Pos 0UL
2155 #define BLE_BLESS_PACKET_COUNTER0_PACKET_COUNTER_LOWER_Msk 0xFFFFFFFFUL
2156 /* BLE_BLESS.PACKET_COUNTER2 */
2157 #define BLE_BLESS_PACKET_COUNTER2_PACKET_COUNTER_UPPER_Pos 0UL
2158 #define BLE_BLESS_PACKET_COUNTER2_PACKET_COUNTER_UPPER_Msk 0xFFUL
2159 /* BLE_BLESS.IV_MASTER0 */
2160 #define BLE_BLESS_IV_MASTER0_IV_MASTER_Pos      0UL
2161 #define BLE_BLESS_IV_MASTER0_IV_MASTER_Msk      0xFFFFFFFFUL
2162 /* BLE_BLESS.IV_SLAVE0 */
2163 #define BLE_BLESS_IV_SLAVE0_IV_SLAVE_Pos        0UL
2164 #define BLE_BLESS_IV_SLAVE0_IV_SLAVE_Msk        0xFFFFFFFFUL
2165 /* BLE_BLESS.ENC_KEY */
2166 #define BLE_BLESS_ENC_KEY_ENC_KEY_Pos           0UL
2167 #define BLE_BLESS_ENC_KEY_ENC_KEY_Msk           0xFFFFFFFFUL
2168 /* BLE_BLESS.MIC_IN0 */
2169 #define BLE_BLESS_MIC_IN0_MIC_IN_Pos            0UL
2170 #define BLE_BLESS_MIC_IN0_MIC_IN_Msk            0xFFFFFFFFUL
2171 /* BLE_BLESS.MIC_OUT0 */
2172 #define BLE_BLESS_MIC_OUT0_MIC_OUT_Pos          0UL
2173 #define BLE_BLESS_MIC_OUT0_MIC_OUT_Msk          0xFFFFFFFFUL
2174 /* BLE_BLESS.ENC_PARAMS */
2175 #define BLE_BLESS_ENC_PARAMS_DATA_PDU_HEADER_Pos 0UL
2176 #define BLE_BLESS_ENC_PARAMS_DATA_PDU_HEADER_Msk 0x3UL
2177 #define BLE_BLESS_ENC_PARAMS_PAYLOAD_LENGTH_LSB_Pos 2UL
2178 #define BLE_BLESS_ENC_PARAMS_PAYLOAD_LENGTH_LSB_Msk 0x7CUL
2179 #define BLE_BLESS_ENC_PARAMS_DIRECTION_Pos      7UL
2180 #define BLE_BLESS_ENC_PARAMS_DIRECTION_Msk      0x80UL
2181 #define BLE_BLESS_ENC_PARAMS_PAYLOAD_LENGTH_LSB_EXT_Pos 8UL
2182 #define BLE_BLESS_ENC_PARAMS_PAYLOAD_LENGTH_LSB_EXT_Msk 0x700UL
2183 #define BLE_BLESS_ENC_PARAMS_MEM_LATENCY_HIDE_Pos 11UL
2184 #define BLE_BLESS_ENC_PARAMS_MEM_LATENCY_HIDE_Msk 0x800UL
2185 /* BLE_BLESS.ENC_CONFIG */
2186 #define BLE_BLESS_ENC_CONFIG_START_PROC_Pos     0UL
2187 #define BLE_BLESS_ENC_CONFIG_START_PROC_Msk     0x1UL
2188 #define BLE_BLESS_ENC_CONFIG_ECB_CCM_Pos        1UL
2189 #define BLE_BLESS_ENC_CONFIG_ECB_CCM_Msk        0x2UL
2190 #define BLE_BLESS_ENC_CONFIG_DEC_ENC_Pos        2UL
2191 #define BLE_BLESS_ENC_CONFIG_DEC_ENC_Msk        0x4UL
2192 #define BLE_BLESS_ENC_CONFIG_PAYLOAD_LENGTH_MSB_Pos 8UL
2193 #define BLE_BLESS_ENC_CONFIG_PAYLOAD_LENGTH_MSB_Msk 0xFF00UL
2194 #define BLE_BLESS_ENC_CONFIG_B0_FLAGS_Pos       16UL
2195 #define BLE_BLESS_ENC_CONFIG_B0_FLAGS_Msk       0xFF0000UL
2196 #define BLE_BLESS_ENC_CONFIG_AES_B0_DATA_OVERRIDE_Pos 24UL
2197 #define BLE_BLESS_ENC_CONFIG_AES_B0_DATA_OVERRIDE_Msk 0x1000000UL
2198 /* BLE_BLESS.ENC_INTR_EN */
2199 #define BLE_BLESS_ENC_INTR_EN_AUTH_PASS_INTR_EN_Pos 0UL
2200 #define BLE_BLESS_ENC_INTR_EN_AUTH_PASS_INTR_EN_Msk 0x1UL
2201 #define BLE_BLESS_ENC_INTR_EN_ECB_PROC_INTR_EN_Pos 1UL
2202 #define BLE_BLESS_ENC_INTR_EN_ECB_PROC_INTR_EN_Msk 0x2UL
2203 #define BLE_BLESS_ENC_INTR_EN_CCM_PROC_INTR_EN_Pos 2UL
2204 #define BLE_BLESS_ENC_INTR_EN_CCM_PROC_INTR_EN_Msk 0x4UL
2205 /* BLE_BLESS.ENC_INTR */
2206 #define BLE_BLESS_ENC_INTR_AUTH_PASS_INTR_Pos   0UL
2207 #define BLE_BLESS_ENC_INTR_AUTH_PASS_INTR_Msk   0x1UL
2208 #define BLE_BLESS_ENC_INTR_ECB_PROC_INTR_Pos    1UL
2209 #define BLE_BLESS_ENC_INTR_ECB_PROC_INTR_Msk    0x2UL
2210 #define BLE_BLESS_ENC_INTR_CCM_PROC_INTR_Pos    2UL
2211 #define BLE_BLESS_ENC_INTR_CCM_PROC_INTR_Msk    0x4UL
2212 #define BLE_BLESS_ENC_INTR_IN_DATA_CLEAR_Pos    3UL
2213 #define BLE_BLESS_ENC_INTR_IN_DATA_CLEAR_Msk    0x8UL
2214 /* BLE_BLESS.B1_DATA_REG */
2215 #define BLE_BLESS_B1_DATA_REG_B1_DATA_Pos       0UL
2216 #define BLE_BLESS_B1_DATA_REG_B1_DATA_Msk       0xFFFFFFFFUL
2217 /* BLE_BLESS.ENC_MEM_BASE_ADDR */
2218 #define BLE_BLESS_ENC_MEM_BASE_ADDR_ENC_MEM_Pos 0UL
2219 #define BLE_BLESS_ENC_MEM_BASE_ADDR_ENC_MEM_Msk 0xFFFFFFFFUL
2220 /* BLE_BLESS.TRIM_LDO_0 */
2221 #define BLE_BLESS_TRIM_LDO_0_ACT_LDO_VREG_Pos   0UL
2222 #define BLE_BLESS_TRIM_LDO_0_ACT_LDO_VREG_Msk   0xFUL
2223 #define BLE_BLESS_TRIM_LDO_0_ACT_LDO_ITAIL_Pos  4UL
2224 #define BLE_BLESS_TRIM_LDO_0_ACT_LDO_ITAIL_Msk  0xF0UL
2225 /* BLE_BLESS.TRIM_LDO_1 */
2226 #define BLE_BLESS_TRIM_LDO_1_ACT_REF_BGR_Pos    0UL
2227 #define BLE_BLESS_TRIM_LDO_1_ACT_REF_BGR_Msk    0xFUL
2228 #define BLE_BLESS_TRIM_LDO_1_SB_BGRES_Pos       4UL
2229 #define BLE_BLESS_TRIM_LDO_1_SB_BGRES_Msk       0xF0UL
2230 /* BLE_BLESS.TRIM_LDO_2 */
2231 #define BLE_BLESS_TRIM_LDO_2_SB_BMULT_RES_Pos   0UL
2232 #define BLE_BLESS_TRIM_LDO_2_SB_BMULT_RES_Msk   0x1FUL
2233 #define BLE_BLESS_TRIM_LDO_2_SB_BMULT_NBIAS_Pos 5UL
2234 #define BLE_BLESS_TRIM_LDO_2_SB_BMULT_NBIAS_Msk 0x60UL
2235 /* BLE_BLESS.TRIM_LDO_3 */
2236 #define BLE_BLESS_TRIM_LDO_3_LVDET_Pos          0UL
2237 #define BLE_BLESS_TRIM_LDO_3_LVDET_Msk          0x1FUL
2238 #define BLE_BLESS_TRIM_LDO_3_SLOPE_SB_BMULT_Pos 5UL
2239 #define BLE_BLESS_TRIM_LDO_3_SLOPE_SB_BMULT_Msk 0x60UL
2240 /* BLE_BLESS.TRIM_MXD */
2241 #define BLE_BLESS_TRIM_MXD_MXD_TRIM_BITS_Pos    0UL
2242 #define BLE_BLESS_TRIM_MXD_MXD_TRIM_BITS_Msk    0xFFUL
2243 /* BLE_BLESS.TRIM_LDO_4 */
2244 #define BLE_BLESS_TRIM_LDO_4_T_LDO_Pos          0UL
2245 #define BLE_BLESS_TRIM_LDO_4_T_LDO_Msk          0xFFUL
2246 /* BLE_BLESS.TRIM_LDO_5 */
2247 #define BLE_BLESS_TRIM_LDO_5_RESERVED_Pos       0UL
2248 #define BLE_BLESS_TRIM_LDO_5_RESERVED_Msk       0xFFUL
2249 
2250 
2251 #endif /* _CYIP_BLE_H_ */
2252 
2253 
2254 /* [] END OF FILE */
2255