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Searched refs:stsRegQuadEnableMask (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/include/
Dcy_smif_memslot.h794 … uint32_t stsRegQuadEnableMask; /**< The QE mask for the status registers */ member
1270 device->stsRegQuadEnableMask = CY_SMIF_NO_COMMAND_OR_MODE; in SfdpGetQuadEnableParameters()
1281 device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_1_OF_SR_2; in SfdpGetQuadEnableParameters()
1293 device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_6_OF_SR_1; in SfdpGetQuadEnableParameters()
1305 device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_7_OF_SR_2; in SfdpGetQuadEnableParameters()
1317 device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_1_OF_SR_2; in SfdpGetQuadEnableParameters()
/hal_infineon-3.6.0/mtb-template-cat1/files/cat1b/
Dcybsp_smif_init.c224 uint8_t maskQE = (uint8_t)memConfig->deviceCfg->stsRegQuadEnableMask; in cybsp_is_quad_enabled()
/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/
Dcy_smif_memslot.c549 uint32_t qeMask = device->stsRegQuadEnableMask; in Cy_SMIF_MemQuadEnable()
897 uint32_t qeMask = memDevice->deviceCfg->stsRegQuadEnableMask; in Cy_SMIF_MemCmdWriteStatus()
1535 uint8_t maskQE = (uint8_t) memConfig->deviceCfg->stsRegQuadEnableMask; in Cy_SMIF_MemIsQuadEnabled()