Searched refs:kDiv (Results 1 – 3 of 3) sorted by relevance
4409 uint32_t pDiv, kDiv, nDiv; in Cy_SysClk_DpllHpConfigure() local4419 … for (kDiv = CY_SYSCLK_DPLL_HP_MIN_KDIV; kDiv <= CY_SYSCLK_DPLL_HP_MAX_KDIV; kDiv++) in Cy_SysClk_DpllHpConfigure()4421 uint64_t tempDcro = ((uint64_t)config->outputFreq) * ((uint64_t)kDiv); in Cy_SysClk_DpllHpConfigure()4427 …t64_t)config->inputFreq * ((uint64_t)nDiv + 1U)) / (((uint64_t)pDiv + 1U) * ((uint64_t)kDiv + 1U)); in Cy_SysClk_DpllHpConfigure()4440 manualConfig.hpPllCfg->kDiv = (uint8_t)kDiv; in Cy_SysClk_DpllHpConfigure()4488 …(config->hpPllCfg->kDiv < CY_SYSCLK_DPLL_HP_MIN_KDIV) || (CY_SYSCLK_DPLL_HP_MAX_KDIV < co… in Cy_SysClk_DpllHpManualConfigure()4501 _VAL2FLD(CLK_DPLL_HP_CONFIG_PLL_FREQ_KDIV_SEL, config->hpPllCfg->kDiv) | in Cy_SysClk_DpllHpManualConfigure()4578 …config->hpPllCfg->kDiv = (uint8_t)_FLD2VAL(CLK_DPLL_HP_CONFIG_PLL_FREQ_KDIV_SEL, tempReg); in Cy_SysClk_DpllHpGetConfiguration()4694 uint32_t kDiv; in Cy_SysClk_DpllHpGetFrequency() local4708 kDiv = pllcfg.hpPllCfg->kDiv; in Cy_SysClk_DpllHpGetFrequency()[all …]
2139 uint8_t kDiv; /**< CONFIG register, KDIV bits, Post-Divider */ member
1609 *outputDiv = cfg->hpPllCfg->kDiv + 1; in _cyhal_clock_extract_pll_params()
