1 /***************************************************************************//**
2 * \file cy_ctb.h
3 * \version 2.20
4 *
5 * Header file for the CTB driver
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2017-2020 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24
25 /**
26 * \addtogroup group_ctb
27 * \{
28 * This driver provides API functions to configure and use the analog CTB.
29 *
30 * The functions and other declarations used in this driver are in cy_ctb.h.
31 * You can include cy_pdl.h to get access to all functions
32 * and declarations in the PDL.
33 *
34 * The CTB comprises two identical opamps, a switch routing matrix,
35 * and a sample and hold (SH) circuit. The high level features are:
36 *
37 * - Two highly configurable opamps
38 * - Each opamp has programmable power and output drive strength
39 * - Each opamp can be configured as a voltage follower using internal routing
40 * - Each opamp can be configured as a comparator with optional 10 mV hysteresis
41 * - Flexible input and output routing
42 * - Works as a buffer or amplifier for SAR ADC inputs
43 * - Works as a buffer, amplifier, or sample and hold (SH) for the CTDAC output
44 * - Can operate in Deep Sleep power mode
45 *
46 * Each opamp, marked OA0 and OA1, has one input and three output stages,
47 * all of which share the common input stage.
48 * Note that only one output stage can be selected at a time.
49 * The output stage can operate as a low-drive strength opamp for internal connections (1X), a high-drive strength
50 * opamp for driving a device pin (10X), or a comparator.
51 *
52 * Using the switching matrix, the opamp inputs and outputs
53 * can be connected to dedicated general-purpose I/Os or other internal analog
54 * blocks. See the device datasheet for the dedicated CTB port.
55 *
56 * \image html ctb_block_diagram.png "CTB Switch Diagram" width=1000px
57 * \image latex ctb_block_diagram.png
58 *
59 * \section group_ctb_init Initialization and Enable
60 *
61 * Before enabling the CTB, set up any external components (such as resistors)
62 * that are needed for the design and initialize \ref group_sysanalog by calling
63 * \ref Cy_SysAnalog_Init and \ref Cy_SysAnalog_Enable functions.
64 * To configure the entire hardware CTB block, call \ref Cy_CTB_Init.
65 * The base address of the CTB hardware can be found in the device specific header file.
66 * Alternatively, to configure only one opamp without any routing, call \ref Cy_CTB_OpampInit.
67 * The driver also provides a \ref Cy_CTB_FastInit function for fast and easy initialization of the CTB
68 * based on commonly used configurations. They are pre-defined in the driver as:
69 *
70 * <b> Opamp0 </b>
71 * - \ref Cy_CTB_Fast_Opamp0_Unused
72 * - \ref Cy_CTB_Fast_Opamp0_Comp
73 * - \ref Cy_CTB_Fast_Opamp0_Opamp1x
74 * - \ref Cy_CTB_Fast_Opamp0_Opamp10x
75 * - \ref Cy_CTB_Fast_Opamp0_Diffamp
76 * - \ref Cy_CTB_Fast_Opamp0_Vdac_Out
77 * - \ref Cy_CTB_Fast_Opamp0_Vdac_Out_SH
78 *
79 * <b> Opamp1 </b>
80 * - \ref Cy_CTB_Fast_Opamp1_Unused
81 * - \ref Cy_CTB_Fast_Opamp1_Comp
82 * - \ref Cy_CTB_Fast_Opamp1_Opamp1x
83 * - \ref Cy_CTB_Fast_Opamp1_Opamp10x
84 * - \ref Cy_CTB_Fast_Opamp1_Diffamp
85 * - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref
86 * - \ref Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5
87 *
88 * After initialization, call \ref Cy_CTB_Enable to enable the hardware.
89 *
90 * \section group_ctb_io_connections Input/Output Connections
91 *
92 * The CTB has internal switches to support flexible input and output routing. If these switches
93 * have not been configured during initialization, call \ref Cy_CTB_SetAnalogSwitch to
94 * make the input and output connections.
95 *
96 * \snippet ctb/snippet/main.c CTB_SNIPPET_SET_ANALOG_SWITCH
97 *
98 * As shown in the CTB switch diagram, the 10x output of OA0 and OA1 have dedicated
99 * connections to Pin 2 and Pin 3, respectively, of the CTB port. If different output
100 * connections are required, the other CTB switches and/or AMUXBUX A/B switches can be used.
101 *
102 * \section group_ctb_comparator Comparator Mode
103 *
104 * Each opamp can be configured as a comparator. Note that when used as a
105 * comparator, the hardware shuts down the 1X and 10X output drivers.
106 * Specific to the comparator mode, there is an optional 10 mV input hysteresis
107 * and configurable edge detection interrupt handling.
108 *
109 * - Negative input terminal: This input is usually connected to the reference voltage.
110 * - Positive input terminal: This input is usually connected to the voltage that is being compared.
111 * - Comparator digital output: This output goes high when the positive input voltage
112 * is greater than the negative input voltage.
113 *
114 * The comparator output can be routed to a pin or other components using HSIOM or trigger muxes.
115 *
116 * \snippet ctb/snippet/main.c SNIPPET_COMP_OUT_ROUTING
117 *
118 * \subsection group_ctb_comparator_handling_interrupts Handling interrupts
119 *
120 * The comparator output is connected to an edge detector
121 * block, which is used to detect the edge (rising, falling, both, or disabled)
122 * for interrupt generation.
123 *
124 * The following code snippet demonstrates how to implement a routine to handle the interrupt.
125 * The routine gets called when any comparator on the device generates an interrupt.
126 *
127 * \snippet ctb/snippet/main.c SNIPPET_COMP_ISR
128 *
129 * The following code snippet demonstrates how to configure and enable the interrupt.
130 *
131 * \snippet ctb/snippet/main.c SNIPPET_COMP_INTR_SETUP
132 *
133 * \section group_ctb_opamp_range Opamp Input and Output Range
134 *
135 * The input range of the opamp can be rail-to-rail if the charge pump is enabled.
136 * Without the charge pump, the input range is 0 V to VDDA - 1.5 V. The output range
137 * of the opamp is typically 0.2 V to VDDA - 0.2 V and will depend on the load. See the
138 * device datasheet for more detail.
139 *
140 * <table class="doxtable">
141 * <tr>
142 * <th>Charge Pump</th>
143 * <th>Input Range</th></tr>
144 * <th>Output Range</th></tr>
145 * <tr>
146 * <td>Enabled</td>
147 * <td>0 V to VDDA</td>
148 * <td>0.2 V to VDDA - 0.2 V</td>
149 * </tr>
150 * <tr>
151 * <td>Disabled</td>
152 * <td>0 V to VDDA - 1.5 V</td>
153 * <td>0.2 V to VDDA - 0.2 V</td>
154 * </tr>
155 * </table>
156 *
157 * \section group_ctb_sample_hold Sample and Hold Mode
158 *
159 * The CTB has a sample and hold (SH) circuit at the non-inverting input of Opamp0.
160 * The circuit includes a hold capacitor, Chold, with a firmware controlled switch, CHD.
161 * Sampling and holding the source voltage is performed
162 * by closing and opening appropriate switches in the CTB using firmware.
163 * If the SH circuit is used for the CTDAC, the \ref Cy_CTB_DACSampleAndHold function
164 * should be called.
165 *
166 * \image html ctb_fast_config_vdac_sh.png
167 * \image latex ctb_fast_config_vdac_sh.png
168 *
169 * \section group_ctb_dependencies Configuration Dependencies
170 *
171 * The CTB relies on other blocks to function properly. The dependencies
172 * are documented here.
173 *
174 * \subsection group_ctb_dependencies_charge_pump Charge Pump Configuration
175 *
176 * Each opamp of the CTB has a charge pump that when enabled increases the
177 * input range to the supply rails. When disabled, the opamp input range is 0 - VDDA - 1.5 V.
178 * When enabled, the pump requires a clock.
179 * Call the \ref Cy_CTB_SetPumpClkSource function in the \ref group_sysanalog driver to
180 * set the clock source for all CTBs. This clock can come from one of two sources:
181 *
182 * -# A dedicated clock divider from one of the CLK_PATH in the SRSS
183 *
184 * Call the following functions to configure the pump clock from the SRSS:
185 * - \ref Cy_SysClk_ClkPumpSetSource
186 * - \ref Cy_SysClk_ClkPumpSetDivider
187 * - \ref Cy_SysClk_ClkPumpEnable
188 *
189 * \snippet ctb/snippet/main.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_SRSS
190 *
191 * -# One of the Peri Clock dividers
192 *
193 * Call the following functions to configure a Peri Clock divider as the
194 * pump clock:
195 * - \ref Cy_SysClk_PeriphAssignDivider with the IP block set to PCLK_PASS_CLOCK_PUMP_PERI
196 * - \ref Cy_SysClk_PeriphSetDivider
197 * - \ref Cy_SysClk_PeriphEnableDivider
198 *
199 * \snippet ctb/snippet/main.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_PERI
200 *
201 * When the charge pump is enabled, the clock frequency should be set as follows:
202 *
203 * <table class="doxtable">
204 * <tr><th>Opamp Power Level</th><th>Pump Clock Freq</th></tr>
205 * <tr>
206 * <td>Low or Medium</td>
207 * <td>8 - 24 MHz</td>
208 * </tr>
209 * <tr>
210 * <td>High</td>
211 * <td>24 MHz</td>
212 * </tr>
213 * </table>
214 *
215 * The High power level of the opamp requires a 24 MHz pump clock.
216 * In Deep Sleep mode, all high frequency clocks are
217 * disabled and the charge pump will be disabled.
218 *
219 * \note
220 * The same pump clock is used by all opamps on the device. Be aware of this
221 * when configuring different opamps to different power levels.
222 *
223 * \subsection group_ctb_dependencies_reference_current Reference Current Configurations
224 *
225 * The CTB uses two reference current generators, IPTAT and IZTAT, from
226 * the AREF block (see \ref group_sysanalog driver). The IPTAT current is
227 * used to trim the slope of the opamp offset across temperature.
228 * The AREF must be initialized and enabled for the CTB to function properly.
229 *
230 * If the CTB is configured to operate in Deep Sleep mode,
231 * the appropriate reference current generators from the AREF block must be enabled in Deep Sleep.
232 * When waking up from Deep Sleep,
233 * the AREF block has a wakeup time that must be
234 * considered. Note that configurations in the AREF block
235 * are chip wide and affect all CTBs on the device.
236 *
237 * The following reference current configurations are supported:
238 *
239 * <table class="doxtable">
240 * <tr><th>Reference Current Level</th><th>Supported Mode</th><th>Input Range</th></tr>
241 * <tr>
242 * <td>1 uA</td>
243 * <td>Active/Low Power</td>
244 * <td>Rail-to-Rail (charge pump enabled)</td>
245 * </tr>
246 * <tr>
247 * <td>1 uA</td>
248 * <td>Active/Low Power/Deep Sleep</td>
249 * <td>0 - VDDA-1.5 V (charge pump disabled)</td>
250 * </tr>
251 * <tr>
252 * <td>100 nA</td>
253 * <td>Active/Low Power/Deep Sleep</td>
254 * <td>0 - VDDA-1.5 V (charge pump disabled)</td>
255 * </tr>
256 * </table>
257 *
258 * The first configuration provides low offset and drift with maximum input range
259 * while consuming the most current.
260 * For Deep Sleep operation, use the other two configurations with the charge pump disabled.
261 * For ultra low power, use the 100 nA current level.
262 * To configure the opamps to operate in one of these options, call \ref Cy_CTB_SetCurrentMode.
263 *
264 * \subsection group_ctb_dependencies_sample_hold Sample and Hold Switch Control
265 *
266 * If you are using rev-08 of the CY8CKIT-062, the following eight switches
267 * in the CTB are enabled by the CTDAC IP block:
268 *
269 * - COS, CA0, CHD, CH6, COB, COR, CRS, and CRD
270 *
271 * On the rev-08 board, if any of the above switches are used, you must call \ref Cy_CTDAC_Enable
272 * to enable these switches.
273 *
274 * Additionally, on the rev-08 board, if any of the switches are used in Deep Sleep mode,
275 * the CTDAC must also be configured to operate in Deep Sleep (see \ref Cy_CTDAC_SetDeepSleepMode).
276 *
277 * In later revisions of the board, the switches are enabled by the CTB block so
278 * calls to the CTDAC IP block are not necessary.
279 *
280 * \section group_ctb_more_information More Information
281 *
282 * Refer to technical reference manual (TRM) and the device datasheet.
283 *
284 * \section group_ctb_changelog Changelog
285 * <table class="doxtable">
286 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
287 * <tr>
288 * <td rowspan="2">2.20</td>
289 * <td>The \ref Cy_CTB_SetPumpClkSource implementation is changed to support the IP header update.</td>
290 * <td>API workaround.</td>
291 * </tr>
292 * <tr>
293 * <td>Fixed power level validation in debug mode.</td>
294 * <td>Bug Fixing.</td>
295 * </tr>
296 * <tr>
297 * <td>2.10</td>
298 * <td>Added new power saver modes: \ref CY_CTB_POWER_PS_LOW, \ref CY_CTB_POWER_PS_MEDIUM and \ref CY_CTB_POWER_PS_HIGH.</td>
299 * <td>API enhancement.</td>
300 * </tr>
301 * <tr>
302 * <td rowspan="2">2.0</td>
303 * <td>Added new function \ref Cy_CTB_SetPumpClkSource with new pump clock source \ref CY_CTB_CLK_PUMP_DEEPSLEEP for PASS_v2.</td>
304 * <td>New silicon family support.</td>
305 * </tr>
306 * <tr>
307 * <td>The analog routing switches are opening on power down.</td>
308 * <td>A FW workaround for possible side-effects of the weak pull-ups at OpAmps terminals in PASS_v2.</td>
309 * </tr>
310 * <tr>
311 * <td>1.20</td>
312 * <td>Fixed the \ref Cy_CTB_OpampInit function to do not affect another OpAmp instance.</td>
313 * <td>Bug fixing.</td>
314 * </tr>
315 * <tr>
316 * <td>1.10.3</td>
317 * <td>Minor documentation updates.</td>
318 * <td>Documentation enhancement.</td>
319 * </tr>
320 * <tr>
321 * <td>1.10.2</td>
322 * <td>The \ref Cy_CTB_Init function description is expanded with a
323 * clarification note.</td>
324 * <td>Documentation enhancement based on a usability feedback.</td>
325 * </tr>
326 * <tr>
327 * <td>1.10.1</td>
328 * <td>Added header guard CY_IP_MXS40PASS to the source file.</td>
329 * <td>To enable the PDL compilation with wounded out IP blocks.</td>
330 * </tr>
331 * <tr>
332 * <td rowspan="2">1.10</td>
333 * <td>Flattened the organization of the driver source code into the single
334 * source directory and the single include directory.
335 * </td>
336 * <td>Driver library directory-structure simplification.</td>
337 * </td>
338 * </tr>
339 * <tr>
340 * <td>Added register access layer. Use register access macros instead
341 * of direct register access using dereferenced pointers.</td>
342 * <td>Makes register access device-independent, so that the PDL does
343 * not need to be recompiled for each supported part number.</td>
344 * </tr>
345 * <tr>
346 * <td>1.0</td>
347 * <td>Initial version</td>
348 * <td></td>
349 * </tr>
350 * </table>
351 *
352 * \defgroup group_ctb_macros Macros
353 * \defgroup group_ctb_functions Functions
354 * \{
355 * \defgroup group_ctb_functions_init Initialization Functions
356 * \defgroup group_ctb_functions_basic Basic Configuration Functions
357 * \defgroup group_ctb_functions_comparator Comparator Functions
358 * \defgroup group_ctb_functions_sample_hold Sample and Hold Functions
359 * \defgroup group_ctb_functions_interrupts Interrupt Functions
360 * \defgroup group_ctb_functions_switches Switch Control Functions
361 * \defgroup group_ctb_functions_trim Offset and Slope Trim Functions
362 * \defgroup group_ctb_functions_aref Reference Current Mode Functions
363 * \}
364 * \defgroup group_ctb_globals Global Variables
365 * \defgroup group_ctb_data_structures Data Structures
366 * \defgroup group_ctb_enums Enumerated Types
367 */
368
369 #if !defined(CY_CTB_H)
370 #define CY_CTB_H
371
372 #include "cy_device.h"
373
374 #ifdef CY_IP_MXS40PASS_CTB
375
376 #include <stdint.h>
377 #include <stdbool.h>
378 #include <stddef.h>
379 #include "cy_syslib.h"
380 #include "cy_sysanalog.h"
381
382 #if defined(__cplusplus)
383 extern "C" {
384 #endif
385 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 11.3', 24, \
386 'CTBM_Type will typecast to either CTBM_V1_Type or CTBM_V2_Type but not both on PDL initialization based on the target device at compile time.')
387
388 /** \addtogroup group_ctb_macros
389 * \{
390 */
391
392 /** Driver major version */
393 #define CY_CTB_DRV_VERSION_MAJOR 2
394
395 /** Driver minor version */
396 #define CY_CTB_DRV_VERSION_MINOR 20
397
398 /** CTB driver identifier*/
399 #define CY_CTB_ID CY_PDL_DRV_ID(0x0Bu)
400
401 /** \cond INTERNAL */
402
403 /**< De-init value for most CTB registers */
404 #define CY_CTB_DEINIT (0UL)
405
406 /**< De-init value for the opamp0 switch control register */
407 #define CY_CTB_DEINIT_OA0_SW (CTBM_OA0_SW_CLEAR_OA0P_A00_Msk \
408 | CTBM_OA0_SW_CLEAR_OA0P_A20_Msk \
409 | CTBM_OA0_SW_CLEAR_OA0P_A30_Msk \
410 | CTBM_OA0_SW_CLEAR_OA0M_A11_Msk \
411 | CTBM_OA0_SW_CLEAR_OA0M_A81_Msk \
412 | CTBM_OA0_SW_CLEAR_OA0O_D51_Msk \
413 | CTBM_OA0_SW_CLEAR_OA0O_D81_Msk)
414
415 /**< De-init value for the opamp1 switch control register */
416 #define CY_CTB_DEINIT_OA1_SW (CTBM_OA1_SW_CLEAR_OA1P_A03_Msk \
417 | CTBM_OA1_SW_CLEAR_OA1P_A13_Msk \
418 | CTBM_OA1_SW_CLEAR_OA1P_A43_Msk \
419 | CTBM_OA1_SW_CLEAR_OA1P_A73_Msk \
420 | CTBM_OA1_SW_CLEAR_OA1M_A22_Msk \
421 | CTBM_OA1_SW_CLEAR_OA1M_A82_Msk \
422 | CTBM_OA1_SW_CLEAR_OA1O_D52_Msk \
423 | CTBM_OA1_SW_CLEAR_OA1O_D62_Msk \
424 | CTBM_OA1_SW_CLEAR_OA1O_D82_Msk)
425
426 /**< De-init value for the CTDAC switch control register */
427 #define CY_CTB_DEINIT_CTD_SW (CTBM_CTD_SW_CLEAR_CTDD_CRD_Msk \
428 | CTBM_CTD_SW_CLEAR_CTDS_CRS_Msk \
429 | CTBM_CTD_SW_CLEAR_CTDS_COR_Msk \
430 | CTBM_CTD_SW_CLEAR_CTDO_C6H_Msk \
431 | CTBM_CTD_SW_CLEAR_CTDO_COS_Msk \
432 | CTBM_CTD_SW_CLEAR_CTDH_COB_Msk \
433 | CTBM_CTD_SW_CLEAR_CTDH_CHD_Msk \
434 | CTBM_CTD_SW_CLEAR_CTDH_CA0_Msk \
435 | CTBM_CTD_SW_CLEAR_CTDH_CIS_Msk \
436 | CTBM_CTD_SW_CLEAR_CTDH_ILR_Msk)
437
438 #define CY_CTB_TRIM_VALUE_MAX (63UL)
439
440 /**< Macros for conditions used by CY_ASSERT calls */
441
442 #define CY_CTB_OPAMPNUM(num) (((num) == CY_CTB_OPAMP_0) || ((num) == CY_CTB_OPAMP_1) || ((num) == CY_CTB_OPAMP_BOTH))
443 #define CY_CTB_OPAMPNUM_0_1(num) (((num) == CY_CTB_OPAMP_0) || ((num) == CY_CTB_OPAMP_1))
444 #define CY_CTB_OPAMPNUM_ALL(num) (((num) == CY_CTB_OPAMP_NONE) \
445 || ((num) == CY_CTB_OPAMP_0) \
446 || ((num) == CY_CTB_OPAMP_1) \
447 || ((num) == CY_CTB_OPAMP_BOTH))
448 #define CY_CTB_IPTAT(iptat) (((iptat) == CY_CTB_IPTAT_NORMAL) || ((iptat) == CY_CTB_IPTAT_LOW))
449 #define CY_CTB_CLKPUMP(clkPump) (((clkPump) == CY_CTB_CLK_PUMP_SRSS) || \
450 ((clkPump) == CY_CTB_CLK_PUMP_PERI) || \
451 ((clkPump) == CY_CTB_CLK_PUMP_DEEPSLEEP))
452 #define CY_CTB_DEEPSLEEP(deepSleep) (((deepSleep) == CY_CTB_DEEPSLEEP_DISABLE) || ((deepSleep) == CY_CTB_DEEPSLEEP_ENABLE))
453 #define CY_CTB_OAPOWER(power) (((power) == CY_CTB_POWER_OFF) || \
454 ((power) == CY_CTB_POWER_LOW) || \
455 ((power) == CY_CTB_POWER_MEDIUM) || \
456 ((power) == CY_CTB_POWER_HIGH) || \
457 ((power) == CY_CTB_POWER_PS_LOW) || \
458 ((power) == CY_CTB_POWER_PS_MEDIUM) || \
459 ((power) == CY_CTB_POWER_PS_HIGH))
460 #define CY_CTB_OAMODE(mode) (((mode) == CY_CTB_MODE_OPAMP1X) \
461 || ((mode) == CY_CTB_MODE_OPAMP10X) \
462 || ((mode) == CY_CTB_MODE_COMP))
463 #define CY_CTB_OAPUMP(pump) (((pump) == CY_CTB_PUMP_DISABLE) || ((pump) == CY_CTB_PUMP_ENABLE))
464 #define CY_CTB_COMPEDGE(edge) (((edge) == CY_CTB_COMP_EDGE_DISABLE) \
465 || ((edge) == CY_CTB_COMP_EDGE_RISING) \
466 || ((edge) == CY_CTB_COMP_EDGE_FALLING) \
467 || ((edge) == CY_CTB_COMP_EDGE_BOTH))
468 #define CY_CTB_COMPLEVEL(level) (((level) == CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE) || ((level) == CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL))
469 #define CY_CTB_COMPBYPASS(bypass) (((bypass) == CY_CTB_COMP_BYPASS_SYNC) || ((bypass) == CY_CTB_COMP_BYPASS_NO_SYNC))
470 #define CY_CTB_COMPHYST(hyst) (((hyst) == CY_CTB_COMP_HYST_DISABLE) || ((hyst) == CY_CTB_COMP_HYST_10MV))
471 #define CY_CTB_CURRENTMODE(mode) (((mode) == CY_CTB_CURRENT_HIGH_ACTIVE) \
472 || ((mode) == CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP) \
473 || ((mode) == CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP))
474 #define CY_CTB_SAMPLEHOLD(mode) ((mode) <= CY_CTB_SH_HOLD)
475 #define CY_CTB_TRIM(trim) ((trim) <= CY_CTB_TRIM_VALUE_MAX)
476 #define CY_CTB_SWITCHSELECT(select) (((select) == CY_CTB_SWITCH_OA0_SW) \
477 || ((select) == CY_CTB_SWITCH_OA1_SW) \
478 || ((select) == CY_CTB_SWITCH_CTD_SW))
479 #define CY_CTB_SWITCHSTATE(state) (((state) == CY_CTB_SWITCH_OPEN) || ((state) == CY_CTB_SWITCH_CLOSE))
480 #define CY_CTB_OA0SWITCH(mask) (((mask) & (~CY_CTB_DEINIT_OA0_SW)) == 0UL)
481 #define CY_CTB_OA1SWITCH(mask) (((mask) & (~CY_CTB_DEINIT_OA1_SW)) == 0UL)
482 #define CY_CTB_CTDSWITCH(mask) (((mask) & (~CY_CTB_DEINIT_CTD_SW)) == 0UL)
483 #define CY_CTB_SWITCHMASK(select,mask) (((select) == CY_CTB_SWITCH_OA0_SW) ? (((mask) & (~CY_CTB_DEINIT_OA0_SW)) == 0UL) : \
484 (((select) == CY_CTB_SWITCH_OA1_SW) ? (((mask) & (~CY_CTB_DEINIT_OA1_SW)) == 0UL) : \
485 (((mask) & (~CY_CTB_DEINIT_CTD_SW)) == 0UL)))
486 #define CY_CTB_SARSEQCTRL(mask) (((mask) == CY_CTB_SW_SEQ_CTRL_D51_MASK) \
487 || ((mask) == CY_CTB_SW_SEQ_CTRL_D52_D62_MASK) \
488 || ((mask) == CY_CTB_SW_SEQ_CTRL_D51_D52_D62_MASK))
489
490 /** \endcond */
491
492 /** \} group_ctb_macros */
493
494 /***************************************
495 * Enumerated Types
496 ***************************************/
497
498 /**
499 * \addtogroup group_ctb_enums
500 * \{
501 */
502
503 /**
504 * Most functions allow you to configure a single opamp or both opamps at once.
505 * The \ref Cy_CTB_SetInterruptMask function can be called with \ref CY_CTB_OPAMP_NONE
506 * and interrupts will be disabled.
507 */
508 typedef enum{
509 CY_CTB_OPAMP_NONE = 0UL, /**< For disabling interrupts for both opamps. Used with \ref Cy_CTB_SetInterruptMask */
510 CY_CTB_OPAMP_0 = CTBM_INTR_COMP0_Msk, /**< For configuring Opamp0 */
511 CY_CTB_OPAMP_1 = CTBM_INTR_COMP1_Msk, /**< For configuring Opamp1 */
512 CY_CTB_OPAMP_BOTH = CTBM_INTR_COMP0_Msk | CTBM_INTR_COMP1_Msk, /**< For configuring both Opamp0 and Opamp1 */
513 }cy_en_ctb_opamp_sel_t;
514
515 /** Enable or disable CTB while in Deep Sleep mode.
516 */
517 typedef enum {
518 CY_CTB_DEEPSLEEP_DISABLE = 0UL, /**< CTB is disabled during Deep Sleep power mode */
519 CY_CTB_DEEPSLEEP_ENABLE = CTBM_CTB_CTRL_DEEPSLEEP_ON_Msk, /**< CTB remains enabled during Deep Sleep power mode */
520 }cy_en_ctb_deep_sleep_t;
521
522 /**
523 * Configure the power mode of each opamp. Each power setting
524 * consumes different levels of current and supports a different
525 * input range and gain bandwidth.
526 *
527 * <table class="doxtable">
528 * <tr><th>Opamp Power</th><th>IDD</th><th>Gain bandwidth</th></tr>
529 * <tr>
530 * <td>OFF</td>
531 * <td>0</td>
532 * <td>NA</td>
533 * </tr>
534 * <tr>
535 * <td>LOW</td>
536 * <td>350 uA</td>
537 * <td>1 MHz</td>
538 * </tr>
539 * <tr>
540 * <td>MEDIUM</td>
541 * <td>600 uA</td>
542 * <td>3 MHz for 1X, 2.5 MHz for 10x</td>
543 * </tr>
544 * <tr>
545 * <td>HIGH</td>
546 * <td>1.5 mA</td>
547 * <td>8 MHz for 1X, 6 MHz for 10x</td>
548 * </tr>
549 * </table>
550 *
551 */
552 typedef enum {
553 CY_CTB_POWER_OFF = 0UL, /**< Opamp is off */
554 CY_CTB_POWER_LOW = 1UL, /**< Low power: IDD = 350 uA, GBW = 1 MHz for both 1x and 10x */
555 CY_CTB_POWER_MEDIUM = 2UL, /**< Medium power: IDD = 600 uA, GBW = 3 MHz for 1x and 2.5 MHz for 10x */
556 CY_CTB_POWER_HIGH = 3UL, /**< High power: IDD = 1500 uA, GBW = 8 MHz for 1x and 6 MHz for 10x */
557 CY_CTB_POWER_PS_LOW = 5UL, /**< Power Saver Low power mode: IDD = ~20uA with 1uA bias from AREF, GBW = ~100kHz for 1x/10x, offset correcting IDAC is disabled */
558 CY_CTB_POWER_PS_MEDIUM = 6UL, /**< Power Saver Medium power mode: IDD = ~40uA with 1uA bias from AREF, GBW = ~100kHz for 1x/10x, offset correcting IDAC is enabled */
559 CY_CTB_POWER_PS_HIGH = 7UL, /**< Power Saver High power mode: IDD = ~60uA with 1uA bias from AREF, GBW = ~200kHz for 1x/10x, offset correcting IDAC is enabled */
560 }cy_en_ctb_power_t;
561
562 /**
563 * The output stage of each opamp can be configured for low-drive strength (1X) to drive internal circuits,
564 * for high-drive strength (10X) to drive external circuits, or as a comparator.
565 */
566 typedef enum {
567 CY_CTB_MODE_OPAMP1X = 0UL, /**< Configure opamp for low drive strength for internal connections (1x) */
568 CY_CTB_MODE_OPAMP10X = 1UL << CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Pos, /**< Configure opamp high drive strength for driving a device pin (10x) */
569 CY_CTB_MODE_COMP = 1UL << CTBM_OA_RES0_CTRL_OA0_COMP_EN_Pos, /**< Configure opamp as a comparator */
570 }cy_en_ctb_mode_t;
571
572 /**
573 * Each opamp has a charge pump to increase the input range to the rails.
574 * When the charge pump is enabled, the input range is 0 to VDDA.
575 * When disabled, the input range is 0 to VDDA - 1.5 V.
576 *
577 ** <table class="doxtable">
578 * <tr><th>Charge Pump</th><th>Input Range (V)</th></tr>
579 * <tr>
580 * <td>OFF</td>
581 * <td>0 to VDDA-1.5</td>
582 * </tr>
583 * <tr>
584 * <td>ON</td>
585 * <td>0 to VDDA</td>
586 * </tr>
587 * </table>
588 *
589 * Note that in Deep Sleep mode, the charge pump is disabled so the input
590 * range is reduced.
591 */
592 typedef enum{
593 CY_CTB_PUMP_DISABLE = 0UL, /**< Charge pump is disabled for an input range of 0 to VDDA - 1.5 V */
594 CY_CTB_PUMP_ENABLE = CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk, /**< Charge pump is enabled for an input range of 0 to VDDA */
595 }cy_en_ctb_pump_t;
596
597 /**
598 * Configure the type of edge that will trigger a comparator interrupt or
599 * disable the interrupt entirely.
600 */
601 typedef enum
602 {
603 CY_CTB_COMP_EDGE_DISABLE = 0UL, /**< Disabled, no interrupts generated */
604 CY_CTB_COMP_EDGE_RISING = 1UL << CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos, /**< Rising edge generates an interrupt */
605 CY_CTB_COMP_EDGE_FALLING = 2UL << CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos, /**< Falling edge generates an interrupt */
606 CY_CTB_COMP_EDGE_BOTH = 3UL << CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos, /**< Both edges generate an interrupt */
607 }cy_en_ctb_comp_edge_t;
608
609 /** Configure the comparator DSI trigger output level when output is synchronized. */
610 typedef enum
611 {
612 CY_CTB_COMP_DSI_TRIGGER_OUT_PULSE = 0UL, /**< Send pulse on DSI for each edge of comparator output */
613 CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL = CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk, /**< DSI output is synchronized version of comparator output */
614 }cy_en_ctb_comp_level_t;
615
616 /** Bypass the comparator output synchronization for DSI trigger. */
617 typedef enum
618 {
619 CY_CTB_COMP_BYPASS_SYNC = 0UL, /**< Comparator output is synchronized for DSI trigger */
620 CY_CTB_COMP_BYPASS_NO_SYNC = CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk, /**< Comparator output is not synchronized for DSI trigger */
621 }cy_en_ctb_comp_bypass_t;
622
623 /** Disable or enable the 10 mV hysteresis for the comparator. */
624 typedef enum
625 {
626 CY_CTB_COMP_HYST_DISABLE = 0UL, /**< Disable hysteresis */
627 CY_CTB_COMP_HYST_10MV = CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk, /**< Enable the 10 mV hysteresis */
628 }cy_en_ctb_comp_hyst_t;
629
630 /** Switch state, either open or closed, to be used in \ref Cy_CTB_SetAnalogSwitch. */
631 typedef enum
632 {
633 CY_CTB_SWITCH_OPEN = 0UL, /**< Open the switch */
634 CY_CTB_SWITCH_CLOSE = 1UL /**< Close the switch */
635 }cy_en_ctb_switch_state_t;
636
637 /**
638 * The switch register to be used in \ref Cy_CTB_SetAnalogSwitch.
639 * The CTB has three registers for configuring the switch routing matrix.
640 * */
641 typedef enum
642 {
643 CY_CTB_SWITCH_OA0_SW = 0UL, /**< Switch register for Opamp0 */
644 CY_CTB_SWITCH_OA1_SW = 1UL, /**< Switch register for Opamp1 */
645 CY_CTB_SWITCH_CTD_SW = 2UL, /**< Switch register for CTDAC routing */
646 }cy_en_ctb_switch_register_sel_t;
647
648 /**
649 * Switch masks for Opamp0 to be used in \ref Cy_CTB_SetAnalogSwitch.
650 */
651 typedef enum
652 {
653 CY_CTB_SW_OA0_POS_AMUXBUSA_MASK = CTBM_OA0_SW_OA0P_A00_Msk, /**< Switch A00: Opamp0 non-inverting input to AMUXBUS A */
654 CY_CTB_SW_OA0_POS_PIN0_MASK = CTBM_OA0_SW_OA0P_A20_Msk, /**< Switch A20: Opamp0 non-inverting input to Pin 0 of CTB device port */
655 CY_CTB_SW_OA0_POS_PIN6_MASK = CTBM_OA0_SW_OA0P_A30_Msk, /**< Switch A30: Opamp0 non-inverting input to Pin 6 of CTB device port */
656 CY_CTB_SW_OA0_NEG_PIN1_MASK = CTBM_OA0_SW_OA0M_A11_Msk, /**< Switch A11: Opamp0 inverting input to Pin 1 of CTB device port */
657 CY_CTB_SW_OA0_NEG_OUT_MASK = CTBM_OA0_SW_OA0M_A81_Msk, /**< Switch A81: Opamp0 inverting input to Opamp0 output */
658 CY_CTB_SW_OA0_OUT_SARBUS0_MASK = CTBM_OA0_SW_OA0O_D51_Msk, /**< Switch D51: Opamp0 output to sarbus0 */
659 CY_CTB_SW_OA0_OUT_SHORT_1X_10X_MASK = CTBM_OA0_SW_OA0O_D81_Msk, /**< Switch D81: Short Opamp0 1x with 10x outputs */
660 }cy_en_ctb_oa0_switches_t;
661
662 /**
663 * Switch masks for Opamp1 to be used in \ref Cy_CTB_SetAnalogSwitch.
664 */
665 typedef enum
666 {
667 CY_CTB_SW_OA1_POS_AMUXBUSB_MASK = CTBM_OA1_SW_OA1P_A03_Msk, /**< Switch A03: Opamp1 non-inverting input to AMUXBUS B */
668 CY_CTB_SW_OA1_POS_PIN5_MASK = CTBM_OA1_SW_OA1P_A13_Msk, /**< Switch A13: Opamp1 non-inverting input to Pin 5 of CTB device port */
669 CY_CTB_SW_OA1_POS_PIN7_MASK = CTBM_OA1_SW_OA1P_A43_Msk, /**< Switch A43: Opamp1 non-inverting input to Pin 7 of CTB device port */
670 CY_CTB_SW_OA1_POS_AREF_MASK = CTBM_OA1_SW_OA1P_A73_Msk, /**< Switch A73: Opamp1 non-inverting input to device Analog Reference (AREF) */
671 CY_CTB_SW_OA1_NEG_PIN4_MASK = CTBM_OA1_SW_OA1M_A22_Msk, /**< Switch A22: Opamp1 inverting input to Pin 4 of CTB device port */
672 CY_CTB_SW_OA1_NEG_OUT_MASK = CTBM_OA1_SW_OA1M_A82_Msk, /**< switch A82: Opamp1 inverting input to Opamp1 output */
673 CY_CTB_SW_OA1_OUT_SARBUS0_MASK = CTBM_OA1_SW_OA1O_D52_Msk, /**< Switch D52: Opamp1 output to sarbus0 */
674 CY_CTB_SW_OA1_OUT_SARBUS1_MASK = CTBM_OA1_SW_OA1O_D62_Msk, /**< Switch D62: Opamp1 output to sarbus1 */
675 CY_CTB_SW_OA1_OUT_SHORT_1X_10X_MASK = CTBM_OA1_SW_OA1O_D82_Msk, /**< Switch D82: Short Opamp1 1x with 10x outputs */
676 }cy_en_ctb_oa1_switches_t;
677
678 /**
679 * Switch masks for CTDAC to CTB routing to be used in \ref Cy_CTB_SetAnalogSwitch.
680 */
681 typedef enum
682 {
683 CY_CTB_SW_CTD_REF_OA1_OUT_MASK = CTBM_CTD_SW_CTDD_CRD_Msk, /**< Switch CRD: Opamp1 output to CTDAC reference. */
684 CY_CTB_SW_CTD_REFSENSE_OA1_NEG_MASK = CTBM_CTD_SW_CTDS_CRS_Msk, /**< Switch CRS: CTDAC reference sense to Opamp1 inverting input. */
685 CY_CTB_SW_CTD_OUT_OA1_NEG_MASK = CTBM_CTD_SW_CTDS_COR_Msk, /**< Switch COR: CTDAC output to Opamp1 inverting input. */
686 CY_CTB_SW_CTD_OUT_PIN6_MASK = CTBM_CTD_SW_CTDO_C6H_Msk, /**< Switch C6H: CTDAC output to P6 of CTB device port. */
687 CY_CTB_SW_CTD_OUT_CHOLD_MASK = CTBM_CTD_SW_CTDO_COS_Msk, /**< Switch COS: CTDAC output to hold cap (deglitch capable). */
688 CY_CTB_SW_CTD_OUT_OA0_1X_OUT_MASK = CTBM_CTD_SW_CTDH_COB_Msk, /**< Switch COB: Drive CTDAC output with opamp0 1x output during hold mode. */
689 CY_CTB_SW_CTD_CHOLD_CONNECT_MASK = CTBM_CTD_SW_CTDH_CHD_Msk, /**< Switch CHD: Hold cap connection. */
690 CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK = CTBM_CTD_SW_CTDH_CA0_Msk, /**< Switch CA0: Hold cap to Opamp0 non-inverting input. */
691 CY_CTB_SW_CTD_CHOLD_OA0_POS_ISOLATE_MASK = CTBM_CTD_SW_CTDH_CIS_Msk, /**< Switch CIS: Opamp0 non-inverting input isolation (for hold cap) */
692 CY_CTB_SW_CTD_CHOLD_LEAKAGE_REDUCTION_MASK = CTBM_CTD_SW_CTDH_ILR_Msk, /**< Switch ILR: Hold cap leakage reduction (drives far side of isolation switch CIS) */
693 }cy_en_ctb_ctd_switches_t;
694
695
696 /**
697 * Masks for CTB switches that can be controlled by the SAR sequencer.
698 * These masks are used in \ref Cy_CTB_EnableSarSeqCtrl and \ref Cy_CTB_DisableSarSeqCtrl.
699 *
700 * The SAR ADC subsystem supports analog routes through three CTB switches on SARBUS0 and SARBUS1.
701 * This control allows for pins on the CTB dedicated port to route to the SAR ADC input channels:
702 *
703 * - D51: Connects the inverting terminal of OA0 to SARBUS0
704 * - D52: Connects the inverting terminal of OA1 to SARBUS0
705 * - D62: Connects the inverting terminal of OA1 to SARBUS1
706 */
707 typedef enum
708 {
709 CY_CTB_SW_SEQ_CTRL_D51_MASK = CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk, /**< Enable SAR sequencer control of the D51 switch */
710 CY_CTB_SW_SEQ_CTRL_D52_D62_MASK = CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk, /**< Enable SAR sequencer control of the D52 and D62 switches */
711 CY_CTB_SW_SEQ_CTRL_D51_D52_D62_MASK = CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk | CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk, /**< Enable SAR sequencer control of all three switches */
712 }cy_en_ctb_switch_sar_seq_t;
713
714 /**
715 * Each opamp also has a programmable compensation capacitor block,
716 * that optimizes the stability of the opamp performance based on output load.
717 * The compensation cap will be set by the driver based on the opamp drive strength (1x or 10x) selection.
718 */
719 typedef enum
720 {
721 CY_CTB_OPAMP_COMPENSATION_CAP_OFF = 0UL, /**< No compensation */
722 CY_CTB_OPAMP_COMPENSATION_CAP_MIN = 1UL, /**< Minimum compensation - for 1x drive*/
723 CY_CTB_OPAMP_COMPENSATION_CAP_MED = 2UL, /**< Medium compensation */
724 CY_CTB_OPAMP_COMPENSATION_CAP_MAX = 3UL, /**< Maximum compensation - for 10x drive */
725 }cy_en_ctb_compensation_cap_t;
726
727 /** Enable or disable the gain booster.
728 * The gain booster will be set by the driver based on the opamp drive strength (1x or 10x) selection.
729 */
730 typedef enum
731 {
732 CY_CTB_OPAMP_BOOST_DISABLE = 0UL, /**< Disable gain booster - for 10x drive */
733 CY_CTB_OPAMP_BOOST_ENABLE = CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Msk, /**< Enable gain booster - for 1x drive */
734 }cy_en_ctb_boost_en_t;
735
736 /** Sample and hold modes for firmware sampling of the CTDAC output.
737 *
738 * To perform a sample or a hold, a preparation step must first be executed to
739 * open the required switches.
740 *
741 * -# Call \ref Cy_CTB_DACSampleAndHold with \ref CY_CTB_SH_PREPARE_SAMPLE or \ref CY_CTB_SH_PREPARE_HOLD
742 * -# Enable or disable CTDAC output
743 * -# Call \ref Cy_CTB_DACSampleAndHold with \ref CY_CTB_SH_SAMPLE or \ref CY_CTB_SH_HOLD
744 */
745 typedef enum
746 {
747 CY_CTB_SH_DISABLE = 0UL, /**< The hold capacitor is not connected - this disables sample and hold */
748 CY_CTB_SH_PREPARE_SAMPLE = 1UL, /**< Prepares the required switches for a following sample */
749 CY_CTB_SH_SAMPLE = 2UL, /**< Performs a sample of the voltage */
750 CY_CTB_SH_PREPARE_HOLD = 3UL, /**< Prepares the required switches for a following hold */
751 CY_CTB_SH_HOLD = 4UL, /**< Performs a hold of the previously sampled voltage */
752 }cy_en_ctb_sample_hold_mode_t;
753
754 /** AREF IPTAT bias current output for the CTB
755 *
756 * The CTB bias current can be 1 uA (normal) or 100 nA (low current).
757 */
758 typedef enum
759 {
760 CY_CTB_IPTAT_NORMAL = 0UL, /**< 1 uA bias current to the CTB */
761 CY_CTB_IPTAT_LOW = 1UL << PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Pos, /**< 100 nA bias current to the CTB */
762 }cy_en_ctb_iptat_t;
763
764 /** CTB charge pump clock sources
765 *
766 * The CTB pump clock can come from:
767 * - a dedicated divider clock in the SRSS
768 * - one of the CLK_PERI dividers
769 */
770 typedef enum
771 {
772 CY_CTB_CLK_PUMP_SRSS = 0UL, /**< Use the dedicated pump clock from SRSSp */
773 CY_CTB_CLK_PUMP_PERI = 1UL << PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Pos, /**< Use one of the CLK_PERI dividers */
774 CY_CTB_CLK_PUMP_DEEPSLEEP = 1UL /**< Use the Deep Sleep Clock (\ref group_sysanalog_dpslp) - applicable for PASS_v2 only */
775 }cy_en_ctb_clk_pump_source_t;
776
777 /** High level opamp current modes */
778 typedef enum
779 {
780 CY_CTB_CURRENT_HIGH_ACTIVE = 0UL, /**< Uses 1 uA reference current with charge pump enabled. Available in Active and Low Power */
781 CY_CTB_CURRENT_HIGH_ACTIVE_DEEPSLEEP = 1UL, /**< Uses 1 uA reference current with charge pump disabled. Available in all power modes */
782 CY_CTB_CURRENT_LOW_ACTIVE_DEEPSLEEP = 2UL, /**< Uses 100 nA reference current with charge pump disabled. Available in all power modes */
783 }cy_en_ctb_current_mode_t;
784
785 /** Return states for \ref Cy_CTB_Init, \ref Cy_CTB_OpampInit, \ref Cy_CTB_DeInit, and \ref Cy_CTB_FastInit */
786 typedef enum {
787 CY_CTB_SUCCESS = 0x00UL, /**< Initialization completed successfully */
788 CY_CTB_BAD_PARAM = CY_CTB_ID | CY_PDL_STATUS_ERROR | 0x01UL, /**< Input pointers were NULL and initialization could not be completed */
789 }cy_en_ctb_status_t;
790
791 /** \} group_ctb_enums */
792
793 /***************************************
794 * Configuration Structures
795 ***************************************/
796
797 /**
798 * \addtogroup group_ctb_data_structures
799 * \{
800 */
801
802 /**
803 * Configuration structure to set up the entire CTB to be used with \ref Cy_CTB_Init.
804 */
805 typedef struct {
806 cy_en_ctb_deep_sleep_t deepSleep; /**< Enable or disable the CTB during Deep Sleep */
807
808 /* Opamp0 configuration */
809 cy_en_ctb_power_t oa0Power; /**< Opamp0 power mode: off, low, medium, or high */
810 cy_en_ctb_mode_t oa0Mode; /**< Opamp0 usage mode: 1x drive, 10x drive, or as a comparator */
811 cy_en_ctb_pump_t oa0Pump; /**< Opamp0 charge pump: enable to increase input range for rail-to-rail operation */
812 cy_en_ctb_comp_edge_t oa0CompEdge; /**< Opamp0 comparator edge detection: disable, rising, falling, or both */
813 cy_en_ctb_comp_level_t oa0CompLevel; /**< Opamp0 comparator DSI (trigger) output: pulse or level */
814 cy_en_ctb_comp_bypass_t oa0CompBypass; /**< Opamp0 comparator DSI (trigger) output synchronization */
815 cy_en_ctb_comp_hyst_t oa0CompHyst; /**< Opamp0 comparator hysteresis: enable for 10 mV hysteresis */
816 bool oa0CompIntrEn; /**< Opamp0 comparator interrupt enable */
817
818 /* Opamp1 configuration */
819 cy_en_ctb_power_t oa1Power; /**< Opamp1 power mode: off, low, medium, or high */
820 cy_en_ctb_mode_t oa1Mode; /**< Opamp1 usage mode: 1x drive, 10x drive, or as a comparator */
821 cy_en_ctb_pump_t oa1Pump; /**< Opamp1 charge pump: enable to increase input range for rail-to-rail operation */
822 cy_en_ctb_comp_edge_t oa1CompEdge; /**< Opamp1 comparator edge detection: disable, rising, falling, or both */
823 cy_en_ctb_comp_level_t oa1CompLevel; /**< Opamp1 comparator DSI (trigger) output: pulse or level */
824 cy_en_ctb_comp_bypass_t oa1CompBypass; /**< Opamp1 comparator DSI (trigger) output synchronization */
825 cy_en_ctb_comp_hyst_t oa1CompHyst; /**< Opamp1 comparator hysteresis: enable for 10 mV hysteresis */
826 bool oa1CompIntrEn; /**< Opamp1 comparator interrupt enable */
827
828 /* Switch analog routing configuration */
829 bool configRouting; /**< Configure or ignore routing related registers */
830 uint32_t oa0SwitchCtrl; /**< Opamp0 routing control */
831 uint32_t oa1SwitchCtrl; /**< Opamp1 routing control */
832 uint32_t ctdSwitchCtrl; /**< Routing control between the CTDAC and CTB blocks */
833 }cy_stc_ctb_config_t;
834
835 /**
836 * This configuration structure is used to initialize only one opamp of the CTB
837 * without impacting analog routing. This structure is used with \ref Cy_CTB_OpampInit.
838 */
839 typedef struct {
840 cy_en_ctb_deep_sleep_t deepSleep; /**< Enable or disable the CTB during Deep Sleep */
841
842 /* Opamp configuration */
843 cy_en_ctb_power_t oaPower; /**< Opamp power mode: off, low, medium, or high */
844 cy_en_ctb_mode_t oaMode; /**< Opamp usage mode: 1x drive, 10x drive, or as a comparator */
845 cy_en_ctb_pump_t oaPump; /**< Opamp charge pump: enable to increase input range for rail-to-rail operation */
846 cy_en_ctb_comp_edge_t oaCompEdge; /**< Opamp comparator edge detection: disable, rising, falling, or both */
847 cy_en_ctb_comp_level_t oaCompLevel; /**< Opamp comparator DSI (trigger) output: pulse or level */
848 cy_en_ctb_comp_bypass_t oaCompBypass; /**< Opamp comparator DSI (trigger) output synchronization */
849 cy_en_ctb_comp_hyst_t oaCompHyst; /**< Opamp comparator hysteresis: enable for 10 mV hysteresis */
850 bool oaCompIntrEn; /**< Opamp comparator interrupt enable */
851 }cy_stc_ctb_opamp_config_t;
852
853 /** This configuration structure is used to quickly initialize Opamp0 for the most commonly used configurations.
854 *
855 * Other configuration options are set to:
856 * - .oa0Pump = \ref CY_CTB_PUMP_ENABLE
857 * - .oa0CompEdge = \ref CY_CTB_COMP_EDGE_BOTH
858 * - .oa0CompLevel = \ref CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL
859 * - .oa0CompBypass = \ref CY_CTB_COMP_BYPASS_SYNC
860 * - .oa0CompHyst = \ref CY_CTB_COMP_HYST_10MV
861 * - .oa0CompIntrEn = true
862 */
863 typedef struct
864 {
865 cy_en_ctb_power_t oa0Power; /**< Opamp0 power mode: off, low, medium, or high */
866 cy_en_ctb_mode_t oa0Mode; /**< Opamp0 usage mode: 1x drive, 10x drive, or as a comparator */
867 uint32_t oa0SwitchCtrl; /**< Opamp0 routing control */
868 uint32_t ctdSwitchCtrl; /**< Routing control between the CTDAC and CTB blocks */
869 }cy_stc_ctb_fast_config_oa0_t;
870
871 /** This configuration structure is used to quickly initialize Opamp1 for the most commonly used configurations.
872 *
873 * Other configuration options are set to:
874 * - .oa1Pump = \ref CY_CTB_PUMP_ENABLE
875 * - .oa1CompEdge = \ref CY_CTB_COMP_EDGE_BOTH
876 * - .oa1CompLevel = \ref CY_CTB_COMP_DSI_TRIGGER_OUT_LEVEL
877 * - .oa1CompBypass = \ref CY_CTB_COMP_BYPASS_SYNC
878 * - .oa1CompHyst = \ref CY_CTB_COMP_HYST_10MV
879 * - .oa1CompIntrEn = true
880 */
881 typedef struct
882 {
883 cy_en_ctb_power_t oa1Power; /**< Opamp1 power mode: off, low, medium, or high */
884 cy_en_ctb_mode_t oa1Mode; /**< Opamp1 usage mode: 1x drive, 10x drive, or as a comparator */
885 uint32_t oa1SwitchCtrl; /**< Opamp1 routing control */
886 uint32_t ctdSwitchCtrl; /**< Routing control between the CTDAC and CTB blocks */
887 }cy_stc_ctb_fast_config_oa1_t;
888
889 /** \} group_ctb_data_structures */
890
891
892 /** \addtogroup group_ctb_globals
893 * \{
894 */
895 /***************************************
896 * Predefined Configurations
897 ***************************************/
898
899 /** Configure Opamp0 as unused - powered down. See \ref Cy_CTB_FastInit. */
900 extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Unused;
901
902 /** Configure Opamp0 as a comparator. No routing is configured.
903 *
904 * \image html ctb_fast_config_comp.png
905 * \image latex ctb_fast_config_comp.png width=100px
906 *
907 * See \ref Cy_CTB_FastInit.
908 */
909 extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Comp;
910
911 /** Configure Opamp0 as an opamp with 1x drive. No routing is configured.
912 *
913 * \image html ctb_fast_config_opamp1x.png
914 * \image latex ctb_fast_config_opamp1x.png width=100px
915 *
916 * See \ref Cy_CTB_FastInit.
917 */
918 extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp1x;
919
920 /** Configure Opamp0 as an opamp with 10x drive. No routing is configured.
921 *
922 * \image html ctb_fast_config_opamp10x.png
923 * \image latex ctb_fast_config_opamp10x.png width=100px
924 *
925 * See \ref Cy_CTB_FastInit.
926 */
927 extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Opamp10x;
928
929 /** Configure Opamp0 as one stage of a differential amplifier.
930 * The opamp is in 10x drive and the switches shown are closed.
931 *
932 * \image html ctb_fast_config_oa0_diffamp.png
933 * \image latex ctb_fast_config_oa0_diffamp.png width=100px
934 *
935 * See the device datasheet for the dedicated CTB port.
936 *
937 * To be used with \ref Cy_CTB_FastInit and \ref Cy_CTB_Fast_Opamp1_Diffamp.
938 */
939 extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Diffamp;
940
941 /** Configure Opamp0 as a buffer for the CTDAC output.
942 * The buffer is in 10x drive and the switches shown are closed.
943 * Configure the CTDAC for output buffer mode by calling \ref Cy_CTDAC_FastInit
944 * with \ref Cy_CTDAC_Fast_VddaRef_BufferedOut or \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut.
945 *
946 * \image html ctb_fast_config_vdac_output.png
947 * \image latex ctb_fast_config_vdac_output.png
948 *
949 * See the device datasheet for the dedicated CTB port.
950 *
951 * See \ref Cy_CTB_FastInit.
952 */
953 extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Vdac_Out;
954
955 /** Configure Opamp0 as a buffer for the CTDAC output with the sample and hold capacitor connected.
956 * The buffer is in 10x drive and the switches shown are closed.
957 * Configure the CTDAC for output buffer mode by calling \ref Cy_CTDAC_FastInit
958 * with \ref Cy_CTDAC_Fast_VddaRef_BufferedOut or \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut.
959
960 * \image html ctb_fast_config_vdac_sh.png
961 * \image latex ctb_fast_config_vdac_sh.png
962 *
963 * See the device datasheet for the dedicated CTB port.
964 *
965 * See \ref Cy_CTB_FastInit.
966 */
967 extern const cy_stc_ctb_fast_config_oa0_t Cy_CTB_Fast_Opamp0_Vdac_Out_SH;
968
969 /** Configure Opamp1 as unused - powered down. See \ref Cy_CTB_FastInit.*/
970 extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Unused;
971
972 /** Configure Opamp1 as a comparator. No routing is configured.
973 *
974 * \image html ctb_fast_config_comp.png
975 * \image latex ctb_fast_config_comp.png width=100px
976 *
977 * See \ref Cy_CTB_FastInit.
978 */
979 extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Comp;
980
981 /** Configure Opamp1 as an opamp with 1x drive. No routing is configured.
982 *
983 * \image html ctb_fast_config_opamp1x.png
984 * \image latex ctb_fast_config_opamp1x.png width=100px
985 *
986 * See \ref Cy_CTB_FastInit.
987 */
988 extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp1x;
989
990 /** Configure Opamp1 as an opamp with 10x drive. No routing is configured.
991 *
992 * \image html ctb_fast_config_opamp10x.png
993 * \image latex ctb_fast_config_opamp10x.png width=100px
994 *
995 * See \ref Cy_CTB_FastInit.
996 */
997 extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Opamp10x;
998
999 /** Configure Opamp1 as one stage of a differential amplifier.
1000 * The opamp is in 10x drive and the switches shown are closed.
1001 *
1002 * \image html ctb_fast_config_oa1_diffamp.png
1003 * \image latex ctb_fast_config_oa1_diffamp.png width=100px
1004 *
1005 * See the device datasheet for the dedicated CTB port.
1006 *
1007 * To be used with \ref Cy_CTB_FastInit and \ref Cy_CTB_Fast_Opamp0_Diffamp.
1008 *
1009 */
1010 extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Diffamp;
1011
1012 /** Configure Opamp1 as a buffer for the CTDAC reference. The reference comes from the
1013 * internal analog reference block (AREF).
1014 * The buffer is in 1x drive and the switches shown are closed.
1015 * Configure the CTDAC to use the buffered reference by calling \ref Cy_CTDAC_FastInit
1016 * with \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut or \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut.
1017 *
1018 * \image html ctb_fast_config_vdac_aref.png
1019 * \image latex ctb_fast_config_vdac_aref.png
1020 *
1021 * See \ref Cy_CTB_FastInit.
1022 *
1023 * Note the AREF block needs to be configured using a separate driver.
1024 */
1025 extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Aref;
1026
1027 /** Configure Opamp1 as a buffer for the CTDAC reference. The reference comes from Pin 5.
1028 * The buffer is in 1x drive and the switches shown are closed.
1029 * Configure the CTDAC to use the buffered reference by calling \ref Cy_CTDAC_FastInit
1030 * with \ref Cy_CTDAC_Fast_OA1Ref_UnbufferedOut or \ref Cy_CTDAC_Fast_OA1Ref_BufferedOut.
1031 *
1032 * \image html ctb_fast_config_vdac_pin5.png
1033 * \image latex ctb_fast_config_vdac_pin5.png
1034 *
1035 * See the device datasheet for the dedicated CTB port.
1036 *
1037 * See \ref Cy_CTB_FastInit.
1038 */
1039 extern const cy_stc_ctb_fast_config_oa1_t Cy_CTB_Fast_Opamp1_Vdac_Ref_Pin5;
1040
1041 /** \} group_ctb_globals */
1042
1043 /***************************************
1044 * Function Prototypes
1045 ***************************************/
1046
1047 /**
1048 * \addtogroup group_ctb_functions
1049 * \{
1050 */
1051
1052 /**
1053 * \addtogroup group_ctb_functions_init
1054 * This set of functions are for initializing, enabling, and disabling the CTB.
1055 * \{
1056 */
1057 cy_en_ctb_status_t Cy_CTB_Init(CTBM_Type *base, const cy_stc_ctb_config_t *config);
1058 cy_en_ctb_status_t Cy_CTB_OpampInit(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, const cy_stc_ctb_opamp_config_t *config);
1059 cy_en_ctb_status_t Cy_CTB_DeInit(CTBM_Type *base, bool deInitRouting);
1060 cy_en_ctb_status_t Cy_CTB_FastInit(CTBM_Type *base, const cy_stc_ctb_fast_config_oa0_t *config0, const cy_stc_ctb_fast_config_oa1_t *config1);
1061 void Cy_CTB_Enable(CTBM_Type *base);
1062 void Cy_CTB_Disable(CTBM_Type *base);
1063 /** \} */
1064
1065 /**
1066 * \addtogroup group_ctb_functions_basic
1067 * This set of functions are for configuring basic usage of the CTB.
1068 * \{
1069 */
1070 void Cy_CTB_SetDeepSleepMode(CTBM_Type *base, cy_en_ctb_deep_sleep_t deepSleep);
1071 void Cy_CTB_SetOutputMode(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_mode_t mode);
1072 void Cy_CTB_SetPower(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, cy_en_ctb_power_t power, cy_en_ctb_pump_t pump);
1073 /** \} */
1074
1075 /**
1076 * \addtogroup group_ctb_functions_sample_hold
1077 * This function enables sample and hold of the CTDAC output.
1078 * \{
1079 */
1080 void Cy_CTB_DACSampleAndHold(CTBM_Type *base, cy_en_ctb_sample_hold_mode_t mode);
1081 /** \} */
1082
1083 /**
1084 * \addtogroup group_ctb_functions_comparator
1085 * This set of functions are specific to the comparator mode
1086 * \{
1087 */
1088 void Cy_CTB_CompSetConfig(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_level_t level, cy_en_ctb_comp_bypass_t bypass, cy_en_ctb_comp_hyst_t hyst);
1089 uint32_t Cy_CTB_CompGetConfig(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
1090 void Cy_CTB_CompSetInterruptEdgeType(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum, cy_en_ctb_comp_edge_t edge);
1091 uint32_t Cy_CTB_CompGetStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
1092 /** \} */
1093
1094 /**
1095 * \addtogroup group_ctb_functions_trim
1096 * These are advanced functions for trimming the offset and slope of the opamps.
1097 * Most users do not need to call these functions and can use the factory trimmed values.
1098 * \{
1099 */
1100 void Cy_CTB_OpampSetOffset(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim);
1101 uint32_t Cy_CTB_OpampGetOffset(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum);
1102 void Cy_CTB_OpampSetSlope(CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum, uint32_t trim);
1103 uint32_t Cy_CTB_OpampGetSlope(const CTBM_Type *base, cy_en_ctb_opamp_sel_t opampNum);
1104 /** \} */
1105
1106 /**
1107 * \addtogroup group_ctb_functions_switches
1108 * This set of functions is for controlling routing switches.
1109 * \{
1110 */
1111 void Cy_CTB_SetAnalogSwitch(CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_ctb_switch_state_t state);
1112 uint32_t Cy_CTB_GetAnalogSwitch(const CTBM_Type *base, cy_en_ctb_switch_register_sel_t switchSelect);
1113 __STATIC_INLINE void Cy_CTB_OpenAllSwitches(CTBM_Type *base);
1114 __STATIC_INLINE void Cy_CTB_EnableSarSeqCtrl(CTBM_Type *base, cy_en_ctb_switch_sar_seq_t switchMask);
1115 __STATIC_INLINE void Cy_CTB_DisableSarSeqCtrl(CTBM_Type *base, cy_en_ctb_switch_sar_seq_t switchMask);
1116 /** \} */
1117
1118 /**
1119 * \addtogroup group_ctb_functions_interrupts
1120 * This set of functions is related to the comparator interrupts.
1121 * \{
1122 */
1123 __STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
1124 __STATIC_INLINE void Cy_CTB_ClearInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
1125 __STATIC_INLINE void Cy_CTB_SetInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
1126 __STATIC_INLINE void Cy_CTB_SetInterruptMask(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
1127 __STATIC_INLINE uint32_t Cy_CTB_GetInterruptMask(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
1128 __STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatusMasked(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum);
1129 /** \} */
1130
1131 /**
1132 * \addtogroup group_ctb_functions_aref
1133 * This set of functions impacts all opamps on the chip.
1134 * Notice how some of these functions do not take a base address input.
1135 * When calling \ref Cy_CTB_SetCurrentMode for a CTB instance on the device,
1136 * it should be called for all other CTB instances as well. This is because
1137 * there is only one IPTAT level (1 uA or 100 nA) chip wide.
1138 * \{
1139 */
1140 void Cy_CTB_SetCurrentMode(CTBM_Type *base, cy_en_ctb_current_mode_t currentMode);
1141 __STATIC_INLINE void Cy_CTB_SetIptatLevel(cy_en_ctb_iptat_t iptat);
1142 __STATIC_INLINE void Cy_CTB_SetPumpClkSource(PASS_Type * base, cy_en_ctb_clk_pump_source_t pumpClk);
1143 __STATIC_INLINE void Cy_CTB_EnableRedirect(void);
1144 __STATIC_INLINE void Cy_CTB_DisableRedirect(void);
1145 /** \} */
1146
1147 /**
1148 * \addtogroup group_ctb_functions_switches
1149 * \{
1150 */
1151
1152 /*******************************************************************************
1153 * Function Name: Cy_CTB_OpenAllSwitches
1154 ****************************************************************************//**
1155 *
1156 * Open all the switches and disable all hardware (SAR Sequencer and DSI) control of the switches.
1157 * Primarily used as a quick method of re-configuring all analog connections
1158 * that are sparsely closed.
1159 *
1160 * \param base
1161 * Pointer to structure describing registers
1162 *
1163 * \return None
1164 *
1165 * \funcusage
1166 *
1167 * \snippet ctb/snippet/main.c CTB_SNIPPET_OPEN_ALL_SWITCHES
1168 *
1169 *******************************************************************************/
Cy_CTB_OpenAllSwitches(CTBM_Type * base)1170 __STATIC_INLINE void Cy_CTB_OpenAllSwitches(CTBM_Type *base)
1171 {
1172 CTBM_OA0_SW_CLEAR(base) = CY_CTB_DEINIT_OA0_SW;
1173 CTBM_OA1_SW_CLEAR(base) = CY_CTB_DEINIT_OA1_SW;
1174 CTBM_CTD_SW_CLEAR(base) = CY_CTB_DEINIT_CTD_SW;
1175 CTBM_CTB_SW_DS_CTRL(base) = CY_CTB_DEINIT;
1176 CTBM_CTB_SW_SQ_CTRL(base) = CY_CTB_DEINIT;
1177 }
1178
1179 /*******************************************************************************
1180 * Function Name: Cy_CTB_EnableSarSeqCtrl
1181 ****************************************************************************//**
1182 *
1183 * Enable SAR sequencer control of specified switch(es).
1184 *
1185 * This allows the SAR ADC to use routes through the CTB when configuring its channels.
1186 *
1187 * There are three switches in the CTB that can be enabled by the SAR sequencer.
1188 * - D51: This switch connects the negative input of Opamp0 to the SARBUS0
1189 * - D52: This switch connects the positive input of Opamp1 to the SARBUS0
1190 * - D62: This switch connects the positive input of Opamp1 to the SARBUS1
1191 *
1192 * \param base
1193 * Pointer to structure describing registers
1194 *
1195 * \param switchMask
1196 * The switch or switches in which to enable SAR sequencer control.
1197 * Use an enumerated value from \ref cy_en_ctb_switch_sar_seq_t.
1198 *
1199 * \return None
1200 *
1201 * \funcusage
1202 *
1203 * \snippet ctb/snippet/main.c CTB_SNIPPET_ENABLE_SAR_SEQ_CTRL
1204 *
1205 *******************************************************************************/
Cy_CTB_EnableSarSeqCtrl(CTBM_Type * base,cy_en_ctb_switch_sar_seq_t switchMask)1206 __STATIC_INLINE void Cy_CTB_EnableSarSeqCtrl(CTBM_Type *base, cy_en_ctb_switch_sar_seq_t switchMask)
1207 {
1208 CY_ASSERT_L3(CY_CTB_SARSEQCTRL(switchMask));
1209
1210 CTBM_CTB_SW_SQ_CTRL(base) |= (uint32_t) switchMask;
1211 }
1212
1213 /*******************************************************************************
1214 * Function Name: Cy_CTB_DisableSarSeqCtrl
1215 ****************************************************************************//**
1216 *
1217 * Disable SAR sequencer control of specified switch(es).
1218 *
1219 * \param base
1220 * Pointer to structure describing registers
1221 *
1222 * \param switchMask
1223 * The switch or switches in which to disable SAR sequencer control.
1224 * Use an enumerated value from \ref cy_en_ctb_switch_sar_seq_t.
1225 *
1226 * \return None
1227 *
1228 * \funcusage
1229 *
1230 * \snippet ctb/snippet/main.c CTB_SNIPPET_DISABLE_SAR_SEQ_CTRL
1231 *
1232 *******************************************************************************/
Cy_CTB_DisableSarSeqCtrl(CTBM_Type * base,cy_en_ctb_switch_sar_seq_t switchMask)1233 __STATIC_INLINE void Cy_CTB_DisableSarSeqCtrl(CTBM_Type *base, cy_en_ctb_switch_sar_seq_t switchMask)
1234 {
1235 CY_ASSERT_L3(CY_CTB_SARSEQCTRL(switchMask));
1236
1237 CTBM_CTB_SW_SQ_CTRL(base) &= ~((uint32_t) switchMask);
1238 }
1239 /** \} */
1240
1241 /**
1242 * \addtogroup group_ctb_functions_interrupts
1243 * \{
1244 */
1245
1246 /*******************************************************************************
1247 * Function Name: Cy_CTB_GetInterruptStatus
1248 ****************************************************************************//**
1249 *
1250 * Return the status of the interrupt when the configured comparator
1251 * edge is detected.
1252 *
1253 * \param base
1254 * Pointer to structure describing registers
1255 *
1256 * \param compNum
1257 * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
1258 *
1259 * \return
1260 * The interrupt status.
1261 * If compNum is \ref CY_CTB_OPAMP_BOTH, cast the returned status
1262 * to \ref cy_en_ctb_opamp_sel_t to determine which comparator edge (or both)
1263 * was detected.
1264 * - 0: Edge was not detected
1265 * - Non-zero: Configured edge type was detected
1266 *
1267 * \funcusage
1268 *
1269 * \snippet ctb/snippet/main.c SNIPPET_COMP_GETINTERRUPTSTATUS
1270 *
1271 *******************************************************************************/
Cy_CTB_GetInterruptStatus(const CTBM_Type * base,cy_en_ctb_opamp_sel_t compNum)1272 __STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatus(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
1273 {
1274 CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum));
1275
1276 return CTBM_INTR(base) & (uint32_t) compNum;
1277 }
1278
1279 /*******************************************************************************
1280 * Function Name: Cy_CTB_ClearInterrupt
1281 ****************************************************************************//**
1282 *
1283 * Clear the CTB comparator triggered interrupt.
1284 * The interrupt must be cleared with this function so that the hardware
1285 * can set subsequent interrupts and those interrupts can be forwarded
1286 * to the interrupt controller, if enabled.
1287 *
1288 * \param base
1289 * Pointer to structure describing registers
1290 *
1291 * \param compNum
1292 * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
1293 *
1294 * \return None
1295 *
1296 *******************************************************************************/
Cy_CTB_ClearInterrupt(CTBM_Type * base,cy_en_ctb_opamp_sel_t compNum)1297 __STATIC_INLINE void Cy_CTB_ClearInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
1298 {
1299 CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum));
1300
1301 CTBM_INTR(base) = (uint32_t) compNum;
1302
1303 /* This dummy reading is necessary here. It provides a guarantee that interrupt is cleared at returning from this function. */
1304 (void) CTBM_INTR(base);
1305 }
1306
1307 /*******************************************************************************
1308 * Function Name: Cy_CTB_SetInterrupt
1309 ****************************************************************************//**
1310 *
1311 * Force the CTB interrupt to trigger using software.
1312 *
1313 * \param base
1314 * Pointer to structure describing registers
1315 *
1316 * \param compNum
1317 * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
1318 *
1319 * \return None
1320 *
1321 *******************************************************************************/
Cy_CTB_SetInterrupt(CTBM_Type * base,cy_en_ctb_opamp_sel_t compNum)1322 __STATIC_INLINE void Cy_CTB_SetInterrupt(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
1323 {
1324 CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum));
1325
1326 CTBM_INTR_SET(base) = (uint32_t) compNum;
1327 }
1328
1329 /*******************************************************************************
1330 * Function Name: Cy_CTB_SetInterruptMask
1331 ****************************************************************************//**
1332 *
1333 * Configure the CTB comparator edge interrupt to be forwarded to the
1334 * CPU interrupt controller.
1335 *
1336 * \param base
1337 * Pointer to structure describing registers
1338 *
1339 * \param compNum
1340 * \ref CY_CTB_OPAMP_NONE, \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH.
1341 * Calling this function with CY_CTB_OPAMP_NONE will disable all interrupt requests.
1342 *
1343 * \return None
1344 *
1345 * \funcusage
1346 *
1347 * \snippet ctb/snippet/main.c CTB_SNIPPET_SET_INTERRUPT_MASK
1348 *
1349 *******************************************************************************/
Cy_CTB_SetInterruptMask(CTBM_Type * base,cy_en_ctb_opamp_sel_t compNum)1350 __STATIC_INLINE void Cy_CTB_SetInterruptMask(CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
1351 {
1352 CY_ASSERT_L3(CY_CTB_OPAMPNUM_ALL(compNum));
1353
1354 CTBM_INTR_MASK(base) = (uint32_t) compNum;
1355 }
1356
1357 /*******************************************************************************
1358 * Function Name: Cy_CTB_GetInterruptMask
1359 ****************************************************************************//**
1360 *
1361 * Return whether the CTB comparator edge interrupt output is
1362 * forwarded to the CPU interrupt controller as configured by
1363 * \ref Cy_CTB_SetInterruptMask.
1364 *
1365 * \param base
1366 * Pointer to structure describing registers
1367 *
1368 * \param compNum
1369 * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
1370 *
1371 * \return
1372 * The interrupt mask.
1373 * If compNum is \ref CY_CTB_OPAMP_BOTH, cast the returned mask
1374 * to \ref cy_en_ctb_opamp_sel_t to determine which comparator interrupt
1375 * output (or both) is forwarded.
1376 * - 0: Interrupt output not forwarded to interrupt controller
1377 * - Non-zero: Interrupt output forwarded to interrupt controller
1378 *
1379 * \funcusage
1380 *
1381 * \snippet ctb/snippet/main.c CTB_SNIPPET_GET_INTERRUPT_MASK
1382 *
1383 *******************************************************************************/
Cy_CTB_GetInterruptMask(const CTBM_Type * base,cy_en_ctb_opamp_sel_t compNum)1384 __STATIC_INLINE uint32_t Cy_CTB_GetInterruptMask(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
1385 {
1386 CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum));
1387
1388 return CTBM_INTR_MASK(base) & (uint32_t) compNum;
1389 }
1390
1391 /*******************************************************************************
1392 * Function Name: Cy_CTB_GetInterruptStatusMasked
1393 ****************************************************************************//**
1394 *
1395 * Return the CTB comparator edge output interrupt state after being masked.
1396 * This is the bitwise AND of \ref Cy_CTB_GetInterruptStatus and \ref Cy_CTB_GetInterruptMask.
1397 *
1398 * \param base
1399 * Pointer to structure describing registers
1400 *
1401 * \param compNum
1402 * \ref CY_CTB_OPAMP_0, \ref CY_CTB_OPAMP_1, or \ref CY_CTB_OPAMP_BOTH
1403 *
1404 * \return
1405 * If compNum is \ref CY_CTB_OPAMP_BOTH, cast the returned value
1406 * to \ref cy_en_ctb_opamp_sel_t to determine which comparator interrupt
1407 * output (or both) is detected and masked.
1408 * - 0: Configured edge not detected or not masked
1409 * - Non-zero: Configured edge type detected and masked
1410 *
1411 *******************************************************************************/
Cy_CTB_GetInterruptStatusMasked(const CTBM_Type * base,cy_en_ctb_opamp_sel_t compNum)1412 __STATIC_INLINE uint32_t Cy_CTB_GetInterruptStatusMasked(const CTBM_Type *base, cy_en_ctb_opamp_sel_t compNum)
1413 {
1414 CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum));
1415
1416 return CTBM_INTR_MASKED(base) & (uint32_t) compNum;
1417 }
1418 /** \} */
1419
1420 /**
1421 * \addtogroup group_ctb_functions_aref
1422 * \{
1423 */
1424
1425 /*******************************************************************************
1426 * Function Name: Cy_CTB_SetIptatLevel
1427 ****************************************************************************//**
1428 *
1429 * Set the IPTAT reference level to 1 uA or 100 nA. The IPTAT generator is used by the CTB
1430 * for slope offset drift.
1431 *
1432 * \param iptat
1433 * Value from enum \ref cy_en_ctb_iptat_t
1434 *
1435 * \return None
1436 *
1437 * \funcusage
1438 *
1439 * \snippet ctb/snippet/main.c CTB_SNIPPET_SET_IPTAT_LEVEL
1440 *
1441 *******************************************************************************/
Cy_CTB_SetIptatLevel(cy_en_ctb_iptat_t iptat)1442 __STATIC_INLINE void Cy_CTB_SetIptatLevel(cy_en_ctb_iptat_t iptat)
1443 {
1444 CY_ASSERT_L3(CY_CTB_IPTAT(iptat));
1445
1446 PASS_AREF_AREF_CTRL = (PASS_AREF_AREF_CTRL & ~PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Msk) | (uint32_t) iptat;
1447 }
1448
1449 /*******************************************************************************
1450 * Function Name: Cy_CTB_SetPumpClkSource
1451 ****************************************************************************//**
1452 *
1453 * Set the clock source for both charge pumps in the CTB. Recall that each opamp
1454 * has its own charge pump. The clock can come from:
1455 *
1456 * - \ref CY_CTB_CLK_PUMP_SRSS - a dedicated clock pump divider \ref group_sysclk_clk_pump.
1457 * Call the following functions to configure the pump clock from the SRSS:
1458 * - \ref Cy_SysClk_ClkPumpSetSource
1459 * - \ref Cy_SysClk_ClkPumpDisable
1460 * - \ref Cy_SysClk_ClkPumpSetDivider
1461 * - \ref Cy_SysClk_ClkPumpEnable
1462 * - \ref CY_CTB_CLK_PUMP_PERI - one of the peripheral clock dividers \ref group_sysclk_clk_peripheral.
1463 * Call the following functions to configure a Peri Clock divider as the
1464 * pump clock:
1465 * - \ref Cy_SysClk_PeriphDisableDivider
1466 * - \ref Cy_SysClk_PeriphAssignDivider with the IP block set to PCLK_PASS_CLOCK_PUMP_PERI
1467 * - \ref Cy_SysClk_PeriphSetDivider
1468 * - \ref Cy_SysClk_PeriphEnableDivider
1469 * - \ref CY_CTB_CLK_PUMP_DEEPSLEEP - a PASS_v2 deep sleep clock source \ref group_sysanalog_dpslp.
1470 * Call the following functions to configure the Deep Sleep Clock Source:
1471 * - \ref Cy_SysAnalog_Init with proper Deep Sleep Clock source and divider settings
1472 * and either:
1473 * - \ref Cy_SysAnalog_LpOscEnable
1474 * or:
1475 * - \ref Cy_SysClk_MfoEnable
1476 * - \ref Cy_SysClk_ClkMfSetDivider (if needed)
1477 * - \ref Cy_SysClk_ClkMfEnable
1478 *
1479 * \param base Pointer to the PASS register structure.
1480 *
1481 * \param pumpClk
1482 * Clock source selection (PumpClk, PeriClk or Deep Sleep Clock) for the pump.
1483 * Select a value from \ref cy_en_ctb_clk_pump_source_t
1484 *
1485 * \return None
1486 *
1487 * \funcusage
1488 * \snippet ctb/snippet/main.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_SRSS
1489 * \snippet ctb/snippet/main.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_PERI
1490 * \snippet ctb/snippet/main.c CTB_SNIPPET_SET_CLK_PUMP_SOURCE_DSCLK
1491 *
1492 *******************************************************************************/
Cy_CTB_SetPumpClkSource(PASS_Type * base,cy_en_ctb_clk_pump_source_t pumpClk)1493 __STATIC_INLINE void Cy_CTB_SetPumpClkSource(PASS_Type * base, cy_en_ctb_clk_pump_source_t pumpClk)
1494 {
1495 CY_ASSERT_L3(CY_CTB_CLKPUMP(pumpClk));
1496 CY_UNUSED_PARAMETER(base);
1497
1498 if (CY_CTB_CLK_PUMP_DEEPSLEEP == pumpClk)
1499 {
1500 if (!CY_PASS_V1)
1501 {
1502 /* CTBM0 is a temporary workaround for the DRIVERS-8283 */
1503 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 14.3','CTBM0 is a temporary workaround for the DRIVERS-8283');
1504 CY_REG32_CLR_SET(PASS_CTBM_CLOCK_SEL(CTBM0), PASS_V2_CTBM_CLOCK_SEL_PUMP_CLOCK_SEL, pumpClk);
1505 }
1506 else
1507 {
1508 CY_ASSERT_L1(false); /* The CY_CTB_CLK_PUMP_DEEPSLEEP value is not applicable for PASS6Av1 */
1509 }
1510 }
1511 else
1512 {
1513 CY_REG32_CLR_SET(PASS_AREF_AREF_CTRL, PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL, (CY_CTB_CLK_PUMP_PERI == pumpClk) ? 1UL : 0UL);
1514 }
1515 }
1516
1517 /** \cond **********************************************************************
1518 * Deprecated legacy function - strongly not recommended for new designs.
1519 * Use Cy_CTB_SetPumpClkSource instead.
1520 *******************************************************************************/
Cy_CTB_SetClkPumpSource(cy_en_ctb_clk_pump_source_t clkPump)1521 __STATIC_INLINE void Cy_CTB_SetClkPumpSource(cy_en_ctb_clk_pump_source_t clkPump)
1522 {
1523 if (CY_PASS_V1)
1524 {
1525 CY_ASSERT_L1(CY_CTB_CLK_PUMP_DEEPSLEEP != clkPump);
1526 CY_REG32_CLR_SET(PASS_AREF_AREF_CTRL, PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL, (CY_CTB_CLK_PUMP_PERI == clkPump) ? 1UL : 0UL);
1527 }
1528 } /** \endcond */
1529
1530 /*******************************************************************************
1531 * Function Name: Cy_CTB_EnableRedirect
1532 ****************************************************************************//**
1533 *
1534 * Normally, the AREF IZTAT is routed to the CTB IZTAT and the AREF IPTAT
1535 * is routed to the CTB IPTAT:
1536 *
1537 * - CTB.IZTAT = AREF.IZTAT
1538 * - CTB.IPTAT = AREF.IPTAT
1539 *
1540 * However, the AREF IPTAT can be redirected to the CTB IZTAT and the CTB IPTAT
1541 * is off.
1542 *
1543 * - CTB.IZTAT = AREF.IPTAT
1544 * - CTB.IPTAT = HiZ
1545 *
1546 * The redirection applies to all opamps on the device and
1547 * should be used when the IPTAT bias level is set to 100 nA
1548 * (see \ref Cy_CTB_SetIptatLevel).
1549 *
1550 * When the CTB.IPTAT is HiZ, the CTB cannot compensate for the slope of
1551 * the offset across temperature.
1552 *
1553 * \return None
1554 *
1555 * \funcusage
1556 *
1557 * \snippet ctb/snippet/main.c CTB_SNIPPET_ENABLE_REDIRECT
1558 *
1559 *******************************************************************************/
Cy_CTB_EnableRedirect(void)1560 __STATIC_INLINE void Cy_CTB_EnableRedirect(void)
1561 {
1562 PASS_AREF_AREF_CTRL |= PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk;
1563 }
1564
1565 /*******************************************************************************
1566 * Function Name: Cy_CTB_DisableRedirect
1567 ****************************************************************************//**
1568 *
1569 * Disable the redirection of the AREF IPTAT to the CTB IZTAT for all opamps
1570 * on the device as enabled by \ref Cy_CTB_EnableRedirect.
1571 *
1572 * \return None
1573 *
1574 *******************************************************************************/
Cy_CTB_DisableRedirect(void)1575 __STATIC_INLINE void Cy_CTB_DisableRedirect(void)
1576 {
1577 PASS_AREF_AREF_CTRL &= ~(PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk);
1578 }
1579
1580 /** \} */
1581
1582 /** \} group_ctb_functions */
1583 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 11.3')
1584
1585 #if defined(__cplusplus)
1586 }
1587 #endif
1588
1589 #endif /* CY_IP_MXS40PASS_CTB */
1590
1591 #endif /** !defined(CY_CTB_H) */
1592
1593 /** \} group_ctb */
1594
1595 /* [] END OF FILE */
1596
