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Searched refs:clkSel (Results 1 – 6 of 6) sorted by relevance

/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/include/
Dcy_rtc.h612 void Cy_RTC_SelectFrequencyPrescaler(cy_en_rtc_clock_freq_t clkSel);
614 void Cy_RTC_SelectClockSource(cy_en_rtc_clk_select_sources_t clkSel);
874 #define CY_RTC_IS_CLK_VALID(clkSel) (((clkSel) == CY_RTC_FREQ_WCO_32768_HZ) || \ argument
875 ((clkSel) == CY_RTC_FREQ_60_HZ) || \
876 ((clkSel) == CY_RTC_FREQ_50_HZ))
881 #define CY_RTC_IS_SRC_CLK_SELECT_VALID(clkSel) (((clkSel) == CY_RTC_CLK_SELECT_WCO) |… argument
882 ((clkSel) == CY_RTC_CLK_SELECT_ALTBAK) || \
883 ((clkSel) == CY_RTC_CLK_SELECT_ILO) || \
884 … ((clkSel) == CY_RTC_CLK_SELECT_LPECO_PRESCALER) || \
885 ((clkSel) == CY_RTC_CLK_SELECT_PILO))
[all …]
Dcy_smif.h705 #define CY_SMIF_CLOCK_SEL_VALID(clkSel) ((CY_SMIF_SEL_OUTPUT_CLK == (cy_en_smif_clk_select_t)(c… argument
706 … (CY_SMIF_SEL_INVERTED_OUTPUT_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
707 … (CY_SMIF_SEL_INTERNAL_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
708 … (CY_SMIF_SEL_INVERTED_INTERNAL_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
709 … (CY_SMIF_SEL_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
710 … (CY_SMIF_SEL_INVERTED_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)) ||\
711 … (CY_SMIF_SEL_INVERTED_SPHB_RWDS_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
712 … (CY_SMIF_SEL_SPHB_RWDS_CLK == (cy_en_smif_clk_select_t)(clkSel)))
714 #define CY_SMIF_CLOCK_SEL_VALID(clkSel) ((CY_SMIF_SEL_INTERNAL_CLK == (cy_en_smif_clk_select_t)…
715 … (CY_SMIF_SEL_INVERTED_INTERNAL_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
[all …]
Dcy_tdm.h326 …cy_en_tdm_clock_sel_t clkSel; /**< Interface clock "clk_if" selection, \ref c… member
351 …cy_en_tdm_clock_sel_t clkSel; /**< Interface clock "clk_if" selection, \ref c… member
/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/
Dcy_rtc.c853 void Cy_RTC_SelectFrequencyPrescaler(cy_en_rtc_clock_freq_t clkSel) in Cy_RTC_SelectFrequencyPrescaler() argument
855 CY_ASSERT_L3(CY_RTC_IS_CLK_VALID(clkSel)); in Cy_RTC_SelectFrequencyPrescaler()
858 BACKUP_CTL = (_CLR_SET_FLD32U(BACKUP_CTL, SRSS_CLK_WCO_CONFIG_PRESCALER, (uint32_t) clkSel)); in Cy_RTC_SelectFrequencyPrescaler()
860 BACKUP_CTL = (_CLR_SET_FLD32U(BACKUP_CTL, BACKUP_CTL_PRESCALER, (uint32_t) clkSel)); in Cy_RTC_SelectFrequencyPrescaler()
874 void Cy_RTC_SelectClockSource(cy_en_rtc_clk_select_sources_t clkSel) in Cy_RTC_SelectClockSource() argument
876 CY_ASSERT_L3(CY_RTC_IS_SRC_CLK_SELECT_VALID(clkSel)); in Cy_RTC_SelectClockSource()
879 BACKUP_CTL = (_CLR_SET_FLD32U(BACKUP_CTL, SRSS_CLK_WCO_CONFIG_CLK_RTC_SEL, (uint32_t) clkSel)); in Cy_RTC_SelectClockSource()
881 BACKUP_CTL = (_CLR_SET_FLD32U(BACKUP_CTL, BACKUP_CTL_CLK_SEL, (uint32_t) clkSel)); in Cy_RTC_SelectClockSource()
Dcy_tdm.c124 _VAL2FLD(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CLOCK_SEL, config->clkSel) | in Cy_AudioTDM_TX_Init()
169 _VAL2FLD(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CLOCK_SEL, config->clkSel) | in Cy_AudioTDM_RX_Init()
/hal_infineon-3.6.0/mtb-hal-cat1/source/
Dcyhal_audio_common.c984 …false == cfg->config->rx_config->enable) || (CY_TDM_SEL_MCLK_IN == cfg->config->rx_config->clkSel)) in _cyhal_audioss_init_cfg()
985 …alse == cfg->config->tx_config->enable) || (CY_TDM_SEL_MCLK_IN == cfg->config->tx_config->clkSel)); in _cyhal_audioss_init_cfg()
1648 …pdl_config->tx_config->clkSel = (cy_en_tdm_clock_sel_t)_FLD2VAL(TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF… in _cyhal_audioss_reconstruct_pdl_config()
1669 …pdl_config->rx_config->clkSel = (cy_en_tdm_clock_sel_t)_FLD2VAL(TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF… in _cyhal_audioss_reconstruct_pdl_config()
1790 pdl_config->tx_config->clkSel = mclk_tx ? CY_TDM_SEL_MCLK_IN : CY_TDM_SEL_SRSS_CLK0; in _cyhal_audioss_populate_pdl_config()
1809 pdl_config->rx_config->clkSel = mclk_rx ? CY_TDM_SEL_MCLK_IN : CY_TDM_SEL_SRSS_CLK0; in _cyhal_audioss_populate_pdl_config()