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Searched refs:base (Results 1 – 25 of 219) sorted by relevance

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/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h317 #define CANFD_CTL(base) (((CANFD_V1_Type *)(base))->CTL) argument
318 #define CANFD_STATUS(base) (((CANFD_V1_Type *)(base))->STATUS) argument
319 #define CANFD_NBTP(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.NBTP) argument
320 #define CANFD_IR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.IR) argument
321 #define CANFD_IE(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.IE) argument
322 #define CANFD_ILS(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.ILS) argument
323 #define CANFD_ILE(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.ILE) argument
324 #define CANFD_CCCR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.CCCR) argument
325 #define CANFD_SIDFC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.SIDF… argument
326 #define CANFD_XIDFC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.XIDF… argument
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/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h92 #define SDHC_WRAP_CTL(base) (((SDHC_Type *)(base))->WRAP.CTL) argument
93 #define SDHC_CORE_SDMASA_R(base) (((SDHC_Type *)(base))->CORE.SDMASA_R) argument
94 #define SDHC_CORE_BLOCKSIZE_R(base) (((SDHC_Type *)(base))->CORE.BLOCKSIZE_R) argument
95 #define SDHC_CORE_BLOCKCOUNT_R(base) (((SDHC_Type *)(base))->CORE.BLOCKCOUNT_R) argument
96 #define SDHC_CORE_ARGUMENT_R(base) (((SDHC_Type *)(base))->CORE.ARGUMENT_R) argument
97 #define SDHC_CORE_XFER_MODE_R(base) (((SDHC_Type *)(base))->CORE.XFER_MODE_R) argument
98 #define SDHC_CORE_CMD_R(base) (((SDHC_Type *)(base))->CORE.CMD_R) argument
99 #define SDHC_CORE_RESP01_R(base) (((SDHC_Type *)(base))->CORE.RESP01_R) argument
100 #define SDHC_CORE_RESP23_R(base) (((SDHC_Type *)(base))->CORE.RESP23_R) argument
101 #define SDHC_CORE_RESP45_R(base) (((SDHC_Type *)(base))->CORE.RESP45_R) argument
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/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h311 #define CANFD_CTL(base) (((CANFD_Type *)(base))->CTL) argument
312 #define CANFD_STATUS(base) (((CANFD_Type *)(base))->STATUS) argument
313 #define CANFD_NBTP(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.NBTP) argument
314 #define CANFD_IR(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.IR) argument
315 #define CANFD_IE(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.IE) argument
316 #define CANFD_ILS(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.ILS) argument
317 #define CANFD_ILE(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.ILE) argument
318 #define CANFD_CCCR(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.CCCR) argument
319 #define CANFD_SIDFC(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.SIDFC) argument
320 #define CANFD_XIDFC(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.XIDFC) argument
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/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/include/
Dcy_crypto_core_hw.h479 #define REG_CRYPTO_CTL(base) (((CRYPTO_Type*)(base))->CTL) argument
480 #define REG_CRYPTO_ERROR_STATUS0(base) (((CRYPTO_Type*)(base))->ERROR_STATUS0) argument
481 #define REG_CRYPTO_ERROR_STATUS1(base) (((CRYPTO_Type*)(base))->ERROR_STATUS1) argument
482 #define REG_CRYPTO_PR_LFSR_CTL0(base) (((CRYPTO_Type*)(base))->PR_LFSR_CTL0) argument
483 #define REG_CRYPTO_PR_LFSR_CTL1(base) (((CRYPTO_Type*)(base))->PR_LFSR_CTL1) argument
484 #define REG_CRYPTO_PR_LFSR_CTL2(base) (((CRYPTO_Type*)(base))->PR_LFSR_CTL2) argument
485 #define REG_CRYPTO_TR_CTL0(base) (((CRYPTO_Type*)(base))->TR_CTL0) argument
486 #define REG_CRYPTO_TR_CTL1(base) (((CRYPTO_Type*)(base))->TR_CTL1) argument
487 #define REG_CRYPTO_TR_GARO_CTL(base) (((CRYPTO_Type*)(base))->TR_GARO_CTL) argument
488 #define REG_CRYPTO_TR_FIRO_CTL(base) (((CRYPTO_Type*)(base))->TR_FIRO_CTL) argument
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Dcy_scb_common.h358 __STATIC_FORCEINLINE uint32_t Cy_SCB_ReadRxFifo (CySCB_Type const *base);
359 __STATIC_INLINE void Cy_SCB_SetRxFifoLevel(CySCB_Type *base, uint32_t level);
360 __STATIC_INLINE uint32_t Cy_SCB_GetNumInRxFifo(CySCB_Type const *base);
361 __STATIC_INLINE uint32_t Cy_SCB_GetRxSrValid (CySCB_Type const *base);
362 __STATIC_INLINE void Cy_SCB_ClearRxFifo (CySCB_Type *base);
364 __STATIC_FORCEINLINE void Cy_SCB_WriteTxFifo (CySCB_Type *base, uint32_t data);
365 __STATIC_INLINE void Cy_SCB_SetTxFifoLevel(CySCB_Type *base, uint32_t level);
366 __STATIC_INLINE uint32_t Cy_SCB_GetNumInTxFifo(CySCB_Type const *base);
367 __STATIC_INLINE uint32_t Cy_SCB_GetTxSrValid (CySCB_Type const *base);
368 __STATIC_INLINE bool Cy_SCB_IsTxComplete (CySCB_Type const *base);
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Dcy_usbfs_dev_drv_reg.h105 __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieInterruptStatus(USBFS_Type const *base);
106 __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieInterruptMask (USBFS_Type *base, uint32_t mask);
107 __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieInterruptMask (USBFS_Type const *base);
108 __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetSieInterruptStatusMasked(USBFS_Type const *base);
109 __STATIC_INLINE void Cy_USBFS_Dev_Drv_ClearSieInterrupt (USBFS_Type *base, uint32_t mask);
110 __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetSieInterrupt (USBFS_Type *base, uint32_t mask);
119 __STATIC_INLINE void Cy_USBFS_Dev_Drv_WriteEp0Mode(USBFS_Type *base, uint32_t mode);
120 __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_ReadEp0Mode(USBFS_Type const *base);
122 __STATIC_INLINE void Cy_USBFS_Dev_Drv_SetEp0Count(USBFS_Type *base, uint32_t count, uint32_t to…
123 __STATIC_INLINE uint32_t Cy_USBFS_Dev_Drv_GetEp0Count(USBFS_Type const *base);
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Dcy_cryptolite_hw.h40 #define REG_CRYPTOLITE_CTL(base) (((CRYPTOLITE_Type*)(base))->CTL) argument
41 #define REG_CRYPTOLITE_STATUS(base) (((CRYPTOLITE_Type*)(base))->STATUS) argument
42 #define REG_CRYPTOLITE_AES_DESCR(base) (((CRYPTOLITE_Type*)(base))->AES_DESCR) argument
43 #define REG_CRYPTOLITE_SHA_DESCR(base) (((CRYPTOLITE_Type*)(base))->SHA_DESCR) argument
44 #define REG_CRYPTOLITE_VU_DESCR(base) (((CRYPTOLITE_Type*)(base))->VU_DESCR) argument
45 #define REG_CRYPTOLITE_SHA_INTR_ERROR(base) (((CRYPTOLITE_Type*)(base))->INTR_ERROR) argument
46 #define REG_CRYPTOLITE_SHA_INTR_ERROR_SET(base) (((CRYPTOLITE_Type*)(base))->INTR_ERROR_SE… argument
47 #define REG_CRYPTOLITE_SHA_INTR_ERROR_MASK(base) (((CRYPTOLITE_Type*)(base))->INTR_ERROR_MA… argument
48 #define REG_CRYPTOLITE_SHA_INTR_ERROR_MASKED(base) (((CRYPTOLITE_Type*)(base))->INTR_ERROR_MA… argument
50 #define REG_CRYPTOLITE_TRNG_CTL0(base) (((CRYPTOLITE_Type*)(base))->TRNG_CTL0) argument
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Dcy_cryptolite_trng.h219 cy_en_cryptolite_status_t Cy_Cryptolite_Trng(CRYPTOLITE_Type *base, uint32_t *randomNum);
291 __STATIC_INLINE bool Cy_Cryptolite_Trng_IsInitialized(CRYPTOLITE_Type *base);
292 __STATIC_INLINE uint8_t Cy_Cryptolite_Trng_GetRoStatus(CRYPTOLITE_Type *base, cy_en_cryptolite_trng…
293 __STATIC_INLINE void Cy_Cryptolite_Trng_SetRoStatus(CRYPTOLITE_Type *base,
295 __STATIC_INLINE uint32_t Cy_Cryptolite_Trng_GetData(CRYPTOLITE_Type *base);
296 __STATIC_INLINE void Cy_Cryptolite_Trng_SetGaroPoly(CRYPTOLITE_Type *base, uint32_t poly);
297 __STATIC_INLINE void Cy_Cryptolite_Trng_SetFiroPoly(CRYPTOLITE_Type *base, uint32_t poly);
298 __STATIC_INLINE uint32_t Cy_Cryptolite_Trng_GetGaroPoly(CRYPTOLITE_Type *base);
299 __STATIC_INLINE uint32_t Cy_Cryptolite_Trng_GetFiroPoly(CRYPTOLITE_Type *base);
301 __STATIC_INLINE uint8_t Cy_Cryptolite_Trng_MonGetHealthStatus(CRYPTOLITE_Type *base);
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Dcy_tdm.h458 cy_en_tdm_status_t Cy_AudioTDM_Init( TDM_STRUCT_Type * base, cy_stc_tdm_config_t const * config);
459 void Cy_AudioTDM_DeInit( TDM_STRUCT_Type * base);
466 __STATIC_INLINE void Cy_AudioTDM_EnableTx( TDM_TX_STRUCT_Type * base);
467 __STATIC_INLINE void Cy_AudioTDM_DisableTx( TDM_TX_STRUCT_Type * base);
468 __STATIC_INLINE void Cy_AudioTDM_EnableRx( TDM_RX_STRUCT_Type * base);
469 __STATIC_INLINE void Cy_AudioTDM_DisableRx( TDM_RX_STRUCT_Type * base);
471 __STATIC_INLINE void Cy_AudioTDM_WriteTxData( TDM_TX_STRUCT_Type * base, uint32_t data);
472 __STATIC_INLINE void Cy_AudioTDM_FreezeTxFifo( TDM_TX_STRUCT_Type * base);
473 __STATIC_INLINE void Cy_AudioTDM_UnfreezeTxFifo( TDM_TX_STRUCT_Type * base);
474 __STATIC_INLINE void Cy_AudioTDM_MuteTxFifo( TDM_TX_STRUCT_Type * base);
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Dcy_tcpwm.h546 __STATIC_INLINE void Cy_TCPWM_Enable_Multiple(TCPWM_Type *base, uint32_t counters);
547 __STATIC_INLINE void Cy_TCPWM_Disable_Multiple(TCPWM_Type *base, uint32_t counters);
548 __STATIC_INLINE void Cy_TCPWM_TriggerStart(TCPWM_Type *base, uint32_t counters);
549 __STATIC_INLINE void Cy_TCPWM_TriggerReloadOrIndex(TCPWM_Type *base, uint32_t counters);
550 __STATIC_INLINE void Cy_TCPWM_TriggerStopOrKill(TCPWM_Type *base, uint32_t counters);
551 __STATIC_INLINE void Cy_TCPWM_TriggerCaptureOrSwap(TCPWM_Type *base, uint32_t counters);
553 __STATIC_INLINE void Cy_TCPWM_Enable_Single(TCPWM_Type *base, uint32_t cntNum);
554 __STATIC_INLINE void Cy_TCPWM_Disable_Single(TCPWM_Type *base, uint32_t cntNum);
555 __STATIC_INLINE uint32_t Cy_TCPWM_GetInterruptStatus(TCPWM_Type const *base, uint32_t cntNum);
556 __STATIC_INLINE void Cy_TCPWM_ClearInterrupt(TCPWM_Type *base, uint32_t cntNum, uint32_t source);
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Dcy_crypto_core_trng.h49 typedef cy_en_crypto_status_t (*cy_crypto_trng_func_t)(CRYPTO_Type *base,
76 void Cy_Crypto_Core_Trng_Init(CRYPTO_Type *base, cy_stc_crypto_trng_config_t *config);
90 void Cy_Crypto_Core_Trng_DeInit(CRYPTO_Type *base);
110 cy_en_crypto_status_t Cy_Crypto_Core_Trng_Start(CRYPTO_Type *base, uint32_t dataSize);
132 cy_en_crypto_status_t Cy_Crypto_Core_Trng_ReadData(CRYPTO_Type *base, uint32_t *randomData);
160 cy_en_crypto_status_t Cy_Crypto_Core_Trng(CRYPTO_Type *base,
213 __STATIC_INLINE bool Cy_Crypto_Core_Trng_IsInitialized(CRYPTO_Type *base);
215 __STATIC_INLINE uint8_t Cy_Crypto_Core_Trng_GetRoStatus(CRYPTO_Type *base, cy_en_crypto_trng_ro_sel…
216 __STATIC_INLINE void Cy_Crypto_Core_Trng_SetRoStatus(CRYPTO_Type *base,
218 __STATIC_INLINE bool Cy_Crypto_Core_Trng_IsRoEnabled(CRYPTO_Type *base, cy_en_crypto_trng_ro_sel_t …
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Dcy_mcwdt.h606 cy_en_mcwdt_status_t Cy_MCWDT_Init(MCWDT_STRUCT_Type *base, cy_stc_mcwdt_config_t const *config…
607 void Cy_MCWDT_DeInit(MCWDT_STRUCT_Type *base);
608 __STATIC_INLINE void Cy_MCWDT_Enable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitU…
609 __STATIC_INLINE void Cy_MCWDT_Disable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t wait…
610 __STATIC_INLINE uint32_t Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t …
611 __STATIC_INLINE void Cy_MCWDT_Lock(MCWDT_STRUCT_Type *base);
612 __STATIC_INLINE void Cy_MCWDT_Unlock(MCWDT_STRUCT_Type *base);
613 __STATIC_INLINE uint32_t Cy_MCWDT_GetLockedStatus(MCWDT_STRUCT_Type const *base);
615 __STATIC_INLINE void Cy_MCWDT_SetMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, cy_en_…
616 __STATIC_INLINE cy_en_mcwdtmode_t Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t …
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Dcy_sar2.h291 #define CY_SAR2_CHAN_NUM(base) ((PASS0_SAR0 == (base)) ? PASS_SAR_SLICE_NR0_SAR_SAR_M… argument
292 … (PASS0_SAR1 == (base)) ? PASS_SAR_SLICE_NR1_SAR_SAR_MUX_IN :\
295 #define CY_SAR2_CHAN_NUM_VALID(base, channel) (CY_SAR2_CHAN_NUM(base) > (channel)) argument
643 cy_en_sar2_status_t Cy_SAR2_Init(PASS_SAR_Type * base, const cy_stc_sar2_config_t * config);
644 __STATIC_INLINE void Cy_SAR2_DeInit(PASS_SAR_Type * base);
645 __STATIC_INLINE void Cy_SAR2_Enable(PASS_SAR_Type * base);
646 __STATIC_INLINE void Cy_SAR2_Disable(PASS_SAR_Type * base);
647 __STATIC_INLINE uint32_t Cy_SAR2_GetPendingStatus(const PASS_SAR_Type * base);
648 __STATIC_INLINE uint32_t Cy_SAR2_GetWorkValidStatus(const PASS_SAR_Type * base);
649 __STATIC_INLINE uint32_t Cy_SAR2_GetWorkRangeStatus(const PASS_SAR_Type * base);
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Dcy_scb_uart.h591 cy_en_scb_uart_status_t Cy_SCB_UART_Init(CySCB_Type *base, cy_stc_scb_uart_config_t const *config,
593 void Cy_SCB_UART_DeInit (CySCB_Type *base);
594 __STATIC_INLINE void Cy_SCB_UART_Enable(CySCB_Type *base);
595 void Cy_SCB_UART_Disable(CySCB_Type *base, cy_stc_scb_uart_context_t *context);
597 __STATIC_INLINE void Cy_SCB_UART_EnableCts (CySCB_Type *base);
598 __STATIC_INLINE void Cy_SCB_UART_DisableCts (CySCB_Type *base);
599 __STATIC_INLINE void Cy_SCB_UART_SetRtsFifoLevel(CySCB_Type *base, uint32_t level);
600 __STATIC_INLINE uint32_t Cy_SCB_UART_GetRtsFifoLevel(CySCB_Type const *base);
602 __STATIC_INLINE void Cy_SCB_UART_EnableSkipStart (CySCB_Type *base);
603 __STATIC_INLINE void Cy_SCB_UART_DisableSkipStart(CySCB_Type *base);
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Dcy_sd_host.h1515 cy_en_sd_host_status_t Cy_SD_Host_InitCard(SDHC_Type *base,
1518 cy_en_sd_host_status_t Cy_SD_Host_Read(SDHC_Type *base,
1521 cy_en_sd_host_status_t Cy_SD_Host_Write(SDHC_Type *base,
1524 cy_en_sd_host_status_t Cy_SD_Host_Erase(SDHC_Type *base,
1537 cy_en_sd_host_status_t Cy_SD_Host_Init(SDHC_Type *base,
1540 void Cy_SD_Host_DeInit(SDHC_Type *base);
1541 void Cy_SD_Host_Enable(SDHC_Type *base);
1542 void Cy_SD_Host_Disable(SDHC_Type *base);
1543 __STATIC_INLINE void Cy_SD_Host_EnableSdClk(SDHC_Type *base);
1544 __STATIC_INLINE void Cy_SD_Host_DisableSdClk(SDHC_Type *base);
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Dcy_i2s.h515 cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config);
516 void Cy_I2S_DeInit(I2S_Type * base);
525 __STATIC_INLINE void Cy_I2S_EnableTx(I2S_Type * base);
526 __STATIC_INLINE void Cy_I2S_PauseTx(I2S_Type * base);
527 __STATIC_INLINE void Cy_I2S_ResumeTx(I2S_Type * base);
528 __STATIC_INLINE void Cy_I2S_DisableTx(I2S_Type * base);
529 __STATIC_INLINE void Cy_I2S_EnableRx(I2S_Type * base);
530 __STATIC_INLINE void Cy_I2S_DisableRx(I2S_Type * base);
531 __STATIC_INLINE uint32_t Cy_I2S_GetCurrentState(I2S_Type const * base);
533 __STATIC_INLINE void Cy_I2S_ClearTxFifo(I2S_Type * base);
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Dcy_crypto_core_hw_vu.h203 …e CY_CRYPTO_VU1_WAIT_FOR_COMPLETE(base) do { ; } while (0uL != _FLD2VAL(CRYPTO_STATUS_VU_BUSY, RE… argument
204 #define CY_CRYPTO_VU_READ_SP_REG(base) CY_CRYPTO_VU_GET_REG_DATA(REG_CRYPTO_VU_RF_DATA(base… argument
206 __STATIC_INLINE void CY_CRYPTO_VU_SAVE_REG (CRYPTO_Type *base, uint32_t rsrc, uint32_t *data);
207 __STATIC_INLINE void CY_CRYPTO_VU_RESTORE_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t data);
208 __STATIC_INLINE void CY_CRYPTO_VU_SET_REG (CRYPTO_Type *base, uint32_t rdst, uint32_t data, uint32_…
211 __STATIC_INLINE void CY_CRYPTO_VU_COND_MOV_REG_TO_STATUS (CRYPTO_Type *base, uint32_t cc, uint32_t … in CY_CRYPTO_VU_COND_MOV_REG_TO_STATUS() argument
213 Cy_Crypto_Core_Vu_RunInstr(base, CY_CRYPTO_SYNC_NON_BLOCKING, in CY_CRYPTO_VU_COND_MOV_REG_TO_STATUS()
219 __STATIC_INLINE void CY_CRYPTO_VU_MOV_REG_TO_STATUS (CRYPTO_Type *base, uint32_t rsrc) in CY_CRYPTO_VU_MOV_REG_TO_STATUS() argument
221 CY_CRYPTO_VU_COND_MOV_REG_TO_STATUS (base, CY_CRYPTO_VU_COND_ALWAYS, rsrc); in CY_CRYPTO_VU_MOV_REG_TO_STATUS()
224 __STATIC_INLINE void CY_CRYPTO_VU_COND_MOV_STATUS_TO_REG (CRYPTO_Type *base, uint32_t cc, uint32_t … in CY_CRYPTO_VU_COND_MOV_STATUS_TO_REG() argument
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/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/
Dcy_crypto_core_ecc_nist_p.c79 static void Cy_Crypto_Core_EC_CS_MUL_Red_P192(CRYPTO_Type *base, uint32_t z, uint32_t x);
80 static void Cy_Crypto_Core_EC_SM_MUL_Red_P192(CRYPTO_Type *base, uint32_t z, uint32_t x);
84 static void Cy_Crypto_Core_EC_CS_MUL_Red_P224(CRYPTO_Type *base, uint32_t z, uint32_t x);
85 static void Cy_Crypto_Core_EC_SM_MUL_Red_P224(CRYPTO_Type *base, uint32_t z, uint32_t x);
89 static void Cy_Crypto_Core_EC_CS_MUL_Red_P256(CRYPTO_Type *base, uint32_t z, uint32_t x);
90 static void Cy_Crypto_Core_EC_SM_MUL_Red_P256(CRYPTO_Type *base, uint32_t z, uint32_t x);
94 static void Cy_Crypto_Core_EC_CS_MUL_Red_P384(CRYPTO_Type *base, uint32_t z, uint32_t x);
95 static void Cy_Crypto_Core_EC_SM_MUL_Red_P384(CRYPTO_Type *base, uint32_t z, uint32_t x);
99 static void Cy_Crypto_Core_EC_CS_MUL_Red_P521(CRYPTO_Type *base, uint32_t z, uint32_t x);
100 static void Cy_Crypto_Core_EC_SM_MUL_Red_P521(CRYPTO_Type *base, uint32_t z, uint32_t x);
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Dcy_usbfs_dev_drv.c53 static void LpmIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context);
54 static void SofIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context);
55 static void Ep0IntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context);
56 static void BusResetIntrHandler(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context);
57 static void ArbiterIntrHandler (USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context);
58 static void SieEnpointIntrHandler(USBFS_Type *base, uint32_t endpoint, cy_stc_usbfs_dev_drv_context…
60 static uint32_t WriteEp0Buffer(USBFS_Type *base, uint8_t const *buffer, uint32_t size);
61 static uint32_t ReadEp0Buffer (USBFS_Type const *base, uint8_t *buffer, uint32_t size);
63 static void RestoreDeviceConfiguration(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context);
65 static void EndpointTransferComplete(USBFS_Type *base, uint32_t endpoint,
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Dcy_sar.c36 #define IS_RIGHT_ALIGN (!_FLD2BOOL(SAR_SAMPLE_CTRL_LEFT_ALIGN, SAR_SAMPLE_CTRL(base)))
105 cy_en_sar_status_t Cy_SAR_CommonInit(PASS_Type * base, const cy_stc_sar_common_config_t * trigConf… in Cy_SAR_CommonInit() argument
109 if((!CY_PASS_V1) && (NULL != base) && (NULL != trigConfig)) in Cy_SAR_CommonInit()
149 …PASS_SAR_SIMULT_CTRL(base) = _VAL2FLD(PASS_V2_SAR_SIMULT_CTRL_SIMULT_HW_TR_EN, trigConfig->simultC… in Cy_SAR_CommonInit()
156 …PASS_SAR_TR_SCAN_CNT(base) = _VAL2FLD(PASS_V2_SAR_TR_SCAN_CNT_SCAN_CNT, trigConfig->scanCount - 1U… in Cy_SAR_CommonInit()
159 …CY_REG32_CLR_SET(PASS_ANA_PWR_CFG(base), PASS_V2_ANA_PWR_CFG_PWR_UP_DELAY, trigConfig->pwrUpDelay); in Cy_SAR_CommonInit()
198 cy_en_sar_status_t Cy_SAR_Init(SAR_Type * base, const cy_stc_sar_config_t * config) in Cy_SAR_Init() argument
202 CY_ASSERT_L1(NULL != base); in Cy_SAR_Init()
205 if ((NULL != base) && (NULL != config)) in Cy_SAR_Init()
234 SAR_CTRL(base) = (config->ctrl | SAR_CTRL_REFBUF_EN_Msk) & ~SAR_CTRL_ENABLED_Msk; in Cy_SAR_Init()
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Dcy_crypto_core_rsa.c46 static void Cy_Crypto_Core_Rsa_MontCoeff(CRYPTO_Type *base, uint32_t modDerReg, uint32_t modReg, ui…
47 static void Cy_Crypto_Core_Rsa_BarrettGetU(CRYPTO_Type *base, uint32_t barrettUReg, uint32_t modReg…
48 static void Cy_Crypto_Core_Rsa_MontTransform(CRYPTO_Type *base, uint32_t z, uint32_t a, uint32_t ba…
49 static void Cy_Crypto_Core_Rsa_MontMul(CRYPTO_Type *base, uint32_t z, uint32_t a, uint32_t b, uint3…
51 static void Cy_Crypto_Core_Rsa_expModByMont(CRYPTO_Type *base,
109 cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Verify(CRYPTO_Type *base, in Cy_Crypto_Core_Rsa_Verify() argument
121 return Cy_Crypto_Core_Rsa_Verify_Ext(base, in Cy_Crypto_Core_Rsa_Verify()
172 cy_en_crypto_status_t Cy_Crypto_Core_Rsa_Verify_Ext(CRYPTO_Type *base, in Cy_Crypto_Core_Rsa_Verify_Ext() argument
358 cmpRes = Cy_Crypto_Core_MemCmp(base, (void const *)encodingArr, in Cy_Crypto_Core_Rsa_Verify_Ext()
367 cmpRes = Cy_Crypto_Core_MemCmp(base, (void const *)digest, in Cy_Crypto_Core_Rsa_Verify_Ext()
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Dcy_gpio.c80 cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const cy_stc_gpio_pin_co… in Cy_GPIO_Pin_Init() argument
84 if ((NULL != base) && (NULL != config)) in Cy_GPIO_Pin_Init()
118 pinType = CY_PRA_GET_PIN_PROT_TYPE(base, pinNum); in Cy_GPIO_Pin_Init()
131 …tempReg = CY_PRA_REG32_GET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT)) & ~(mas… in Cy_GPIO_Pin_Init()
135 tempReg = GPIO_PRT_CFG_OUT(base) & ~(maskCfgOut); in Cy_GPIO_Pin_Init()
138 tempReg = GPIO_PRT_CFG_OUT(base) & ~(maskCfgOut); in Cy_GPIO_Pin_Init()
147 … CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT), tempReg2); in Cy_GPIO_Pin_Init()
151 GPIO_PRT_CFG_OUT(base) = tempReg2; in Cy_GPIO_Pin_Init()
154 GPIO_PRT_CFG_OUT(base) = tempReg2; in Cy_GPIO_Pin_Init()
161 Cy_GPIO_SetHSIOM_SecPin(base, pinNum, config->nonSec); in Cy_GPIO_Pin_Init()
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Dcy_mcwdt_b.c55 cy_en_mcwdt_status_t Cy_MCWDT_Init(MCWDT_Type *base, cy_stc_mcwdt_config_t const *config) in Cy_MCWDT_Init() argument
58 if ((base != NULL) && (config != NULL)) in Cy_MCWDT_Init()
60 Cy_MCWDT_Unlock(base); in Cy_MCWDT_Init()
62 Cy_MCWDT_CpuSelectForDpSlpPauseAction(base, config->coreSelect); in Cy_MCWDT_Init()
64 Cy_MCWDT_SetLowerLimit(base, CY_MCWDT_COUNTER0, config->c0LowerLimit, 0); in Cy_MCWDT_Init()
65 Cy_MCWDT_SetUpperLimit(base, CY_MCWDT_COUNTER0, config->c0UpperLimit, 0); in Cy_MCWDT_Init()
66 Cy_MCWDT_SetWarnLimit(base, CY_MCWDT_COUNTER0, config->c0WarnLimit, 0); in Cy_MCWDT_Init()
68 …MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0) = _VAL2FLD(MCWDT_CTR_CONFIG_LOWER_ACTION, config->c0Lowe… in Cy_MCWDT_Init()
76 Cy_MCWDT_SetLowerLimit(base, CY_MCWDT_COUNTER1, config->c1LowerLimit, 0); in Cy_MCWDT_Init()
77 Cy_MCWDT_SetUpperLimit(base, CY_MCWDT_COUNTER1, config->c1UpperLimit, 0); in Cy_MCWDT_Init()
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Dcy_scb_i2c.c39 static void SlaveHandleAddress (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
40 static void SlaveHandleDataReceive (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
41 static void SlaveHandleDataTransmit(CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
42 static void SlaveHandleStop (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
44 static void MasterHandleEvents (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
45 static void MasterHandleDataTransmit(CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
46 static void MasterHandleDataReceive (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
47 static void MasterHandleStop (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
48 static void MasterHandleComplete (CySCB_Type *base, cy_stc_scb_i2c_context_t *context);
50 static cy_en_scb_i2c_status_t HandleStatus(CySCB_Type *base, uint32_t status,
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Dcy_scb_uart.c36 static void HandleDataReceive (CySCB_Type *base, cy_stc_scb_uart_context_t *context);
37 static void HandleRingBuffer (CySCB_Type *base, cy_stc_scb_uart_context_t *context);
38 static void HandleDataTransmit(CySCB_Type *base, cy_stc_scb_uart_context_t *context);
39 static uint32_t SelectRxFifoLevel(CySCB_Type const *base);
69 cy_en_scb_uart_status_t Cy_SCB_UART_SetOverSample(CySCB_Type *base, uint32_t overSample, cy_stc_scb… in Cy_SCB_UART_SetOverSample() argument
73 if((NULL == base) || (NULL == context) || in Cy_SCB_UART_SetOverSample()
74 …Sample, ((cy_en_scb_uart_mode_t)_FLD2VAL(SCB_UART_CTRL_MODE,SCB_UART_CTRL(base))), context->irdaEn… in Cy_SCB_UART_SetOverSample()
82 …if (((uint32_t)CY_SCB_UART_IRDA == _FLD2VAL(SCB_UART_CTRL_MODE,SCB_UART_CTRL(base))) && (!context-… in Cy_SCB_UART_SetOverSample()
93 CY_REG32_CLR_SET(SCB_CTRL(base), SCB_CTRL_OVS, ovs); in Cy_SCB_UART_SetOverSample()
116 void Cy_SCB_UART_SetDataWidth(CySCB_Type *base, uint32_t dataWidth) in Cy_SCB_UART_SetDataWidth() argument
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