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Searched refs:_CLR_SET_FLD32U (Results 1 – 25 of 28) sorted by relevance

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/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/
Dcy_mcwdt_b.c202 … MCWDT_CPU_SELECT(base) = _CLR_SET_FLD32U(MCWDT_CPU_SELECT(base), MCWDT_CPU_SELECT_CPU_SEL, core); in Cy_MCWDT_CpuSelectForDpSlpPauseAction()
233 …MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTE… in Cy_MCWDT_SetLowerAction()
236 …MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTE… in Cy_MCWDT_SetLowerAction()
272 …MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTE… in Cy_MCWDT_SetUpperAction()
275 …MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTE… in Cy_MCWDT_SetUpperAction()
311 …MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTE… in Cy_MCWDT_SetWarnAction()
314 …MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTE… in Cy_MCWDT_SetWarnAction()
344 …MCWDT_CTR2_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CTR2_CONFIG(base), MCWDT_CTR2_CONFIG_ACTION, actio… in Cy_MCWDT_SetSubCounter2Action()
529 …MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER0) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTE… in Cy_MCWDT_SetAutoService()
532 …MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTER1) = _CLR_SET_FLD32U(MCWDT_CTR_CONFIG(base, CY_MCWDT_COUNTE… in Cy_MCWDT_SetAutoService()
[all …]
Dcy_lpcomp.c405 …LPCOMP_CMP0_CTRL(base) = _CLR_SET_FLD32U(LPCOMP_CMP0_CTRL(base), LPCOMP_CMP0_CTRL_INTTYPE0, (uint3… in Cy_LPComp_SetInterruptTriggerMode_Ext()
409 …LPCOMP_CMP1_CTRL(base) = _CLR_SET_FLD32U(LPCOMP_CMP1_CTRL(base), LPCOMP_CMP1_CTRL_INTTYPE1, (uint3… in Cy_LPComp_SetInterruptTriggerMode_Ext()
456 …LPCOMP_CMP0_CTRL(base) = _CLR_SET_FLD32U(LPCOMP_CMP0_CTRL(base), LPCOMP_CMP0_CTRL_INTTYPE0, (uint3… in Cy_LPComp_SetInterruptTriggerMode()
460 …LPCOMP_CMP1_CTRL(base) = _CLR_SET_FLD32U(LPCOMP_CMP1_CTRL(base), LPCOMP_CMP1_CTRL_INTTYPE1, (uint3… in Cy_LPComp_SetInterruptTriggerMode()
518 …LPCOMP_CMP0_CTRL(base) = _CLR_SET_FLD32U(LPCOMP_CMP0_CTRL(base), LPCOMP_CMP0_CTRL_MODE0, (uint32_t… in Cy_LPComp_SetPower_Ext()
522 …LPCOMP_CMP1_CTRL(base) = _CLR_SET_FLD32U(LPCOMP_CMP1_CTRL(base), LPCOMP_CMP1_CTRL_MODE1, (uint32_t… in Cy_LPComp_SetPower_Ext()
569 …LPCOMP_CMP0_CTRL(base) = _CLR_SET_FLD32U(LPCOMP_CMP0_CTRL(base), LPCOMP_CMP0_CTRL_MODE0, (uint32_t… in Cy_LPComp_SetPower()
573 …LPCOMP_CMP1_CTRL(base) = _CLR_SET_FLD32U(LPCOMP_CMP1_CTRL(base), LPCOMP_CMP1_CTRL_MODE1, (uint32_t… in Cy_LPComp_SetPower()
606 …LPCOMP_CMP0_CTRL(base) = _CLR_SET_FLD32U(LPCOMP_CMP0_CTRL(base), LPCOMP_CMP0_CTRL_HYST0, (uint32_t… in Cy_LPComp_SetHysteresis()
610 …LPCOMP_CMP1_CTRL(base) = _CLR_SET_FLD32U(LPCOMP_CMP1_CTRL(base) , LPCOMP_CMP1_CTRL_HYST1, (uint32_… in Cy_LPComp_SetHysteresis()
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Dcy_syslib.c445 CPUSS_ROM_CTL = _CLR_SET_FLD32U(CPUSS_ROM_CTL, CPUSS_ROM_CTL_SLOW_WS, waitStates); in Cy_SysLib_SetWaitStates()
446 CPUSS_ROM_CTL = _CLR_SET_FLD32U(CPUSS_ROM_CTL, CPUSS_ROM_CTL_FAST_WS, 0UL); in Cy_SysLib_SetWaitStates()
449 CPUSS_RAM0_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM0_CTL0, CPUSS_RAM0_CTL0_SLOW_WS, waitStates); in Cy_SysLib_SetWaitStates()
450 CPUSS_RAM0_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM0_CTL0, CPUSS_RAM0_CTL0_FAST_WS, 0UL); in Cy_SysLib_SetWaitStates()
452 CPUSS_RAM1_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM1_CTL0, CPUSS_RAM1_CTL0_SLOW_WS, waitStates); in Cy_SysLib_SetWaitStates()
453 CPUSS_RAM1_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM1_CTL0, CPUSS_RAM1_CTL0_FAST_WS, 0UL); in Cy_SysLib_SetWaitStates()
456 CPUSS_RAM2_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM2_CTL0, CPUSS_RAM2_CTL0_SLOW_WS, waitStates); in Cy_SysLib_SetWaitStates()
457 CPUSS_RAM2_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM2_CTL0, CPUSS_RAM2_CTL0_FAST_WS, 0UL); in Cy_SysLib_SetWaitStates()
471 FLASHC_FLASH_CTL = _CLR_SET_FLD32U(FLASHC_FLASH_CTL, FLASHC_FLASH_CTL_WS, waitStates); in Cy_SysLib_SetWaitStates()
488 FLASHC_FLASH_CTL = _CLR_SET_FLD32U(FLASHC_FLASH_CTL, FLASHC_FLASH_CTL_MAIN_WS, waitStates); in Cy_SysLib_SetWaitStates()
Dcy_wdt.c144 SRSS_WDT_MATCH = _CLR_SET_FLD32U((SRSS_WDT_MATCH), SRSS_WDT_MATCH_MATCH, match); in Cy_WDT_SetMatch()
176 …SRSS_WDT_MATCH2 = _CLR_SET_FLD32U((SRSS_WDT_MATCH2), SRSS_WDT_MATCH2_IGNORE_BITS_ABOVE, (WDT_MAX_I… in Cy_WDT_SetIgnoreBits()
178 SRSS_WDT_MATCH = _CLR_SET_FLD32U((SRSS_WDT_MATCH), SRSS_WDT_MATCH_IGNORE_BITS, bitsNum); in Cy_WDT_SetIgnoreBits()
213 … SRSS_WDT_MATCH2 = _CLR_SET_FLD32U((SRSS_WDT_MATCH2), SRSS_WDT_MATCH2_IGNORE_BITS_ABOVE, bitPos); in Cy_WDT_SetMatchBits()
Dcy_syspm.c538 … _CLR_SET_FLD32U(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, SYSPM_CLK_DIVIDER); in Cy_SysPm_CpuEnterDeepSleep()
541 … _CLR_SET_FLD32U(CPUSS_CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, SYSPM_CLK_DIVIDER); in Cy_SysPm_CpuEnterDeepSleep()
548 _CLR_SET_FLD32U(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, 1); in Cy_SysPm_CpuEnterDeepSleep()
551 _CLR_SET_FLD32U(CPUSS_CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, 1); in Cy_SysPm_CpuEnterDeepSleep()
1148 SRSS_PWR_TRIM_PWRSYS_CTL = _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL), in Cy_SysPm_BuckEnable()
1168 SRSS_PWR_TRIM_PWRSYS_CTL = _CLR_SET_FLD32U((SRSS_PWR_TRIM_PWRSYS_CTL), in Cy_SysPm_BuckEnable()
1186 … _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, (uint32_t) voltage); in Cy_SysPm_BuckEnable()
1262 … _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, BUCK_OUT1_VOLTAGE_0_95V); in Cy_SysPm_BuckSetVoltage1()
1282 … _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, (uint32_t) voltage); in Cy_SysPm_BuckSetVoltage1()
1388 … _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL2), SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL, (uint32_t) voltage); in Cy_SysPm_BuckSetVoltage2()
[all …]
Dcy_sar2.c320 …base->DIAG_CTL = _CLR_SET_FLD32U(base->DIAG_CTL, PASS_SAR_DIAG_CTL_DIAG_SEL, diagConfig->reference… in Cy_SAR2_Diag_Init()
640 … base->PASS_CTL = _CLR_SET_FLD32U(base->PASS_CTL, PASS_EPASS_MMIO_PASS_CTL_DBG_FREEZE_EN, temp); in Cy_SAR2_SetDebugFreezeMode()
688 base->SAR_TR_IN_SEL[numOfAdc] = _CLR_SET_FLD32U(base->SAR_TR_IN_SEL[numOfAdc], in Cy_SAR2_SetGenericTriggerInput()
692 base->SAR_TR_IN_SEL[numOfAdc] = _CLR_SET_FLD32U(base->SAR_TR_IN_SEL[numOfAdc], in Cy_SAR2_SetGenericTriggerInput()
696 base->SAR_TR_IN_SEL[numOfAdc] = _CLR_SET_FLD32U(base->SAR_TR_IN_SEL[numOfAdc], in Cy_SAR2_SetGenericTriggerInput()
700 base->SAR_TR_IN_SEL[numOfAdc] = _CLR_SET_FLD32U(base->SAR_TR_IN_SEL[numOfAdc], in Cy_SAR2_SetGenericTriggerInput()
704 base->SAR_TR_IN_SEL[numOfAdc] = _CLR_SET_FLD32U(base->SAR_TR_IN_SEL[numOfAdc], in Cy_SAR2_SetGenericTriggerInput()
754 base->SAR_TR_OUT_SEL[numOfAdc] = _CLR_SET_FLD32U(base->SAR_TR_OUT_SEL[numOfAdc], in Cy_SAR2_SetGenericTriggerOutput()
758 base->SAR_TR_OUT_SEL[numOfAdc] = _CLR_SET_FLD32U(base->SAR_TR_OUT_SEL[numOfAdc], in Cy_SAR2_SetGenericTriggerOutput()
Dcy_syspm_v3.c916 SRSS_PWR_HIBERNATE = _CLR_SET_FLD32U((SRSS_PWR_HIBERNATE), SRSS_PWR_HIBERNATE_UNLOCK, 0u); in Cy_SysPm_IoFreeze()
979 BACKUP_CTL = _CLR_SET_FLD32U((BACKUP_CTL), BACKUP_CTL_VDDBAK_CTL, (uint32_t) vddBackControl); in Cy_SysPm_BackupSetSupply()
1022 …BACKUP_CTL = _CLR_SET_FLD32U((BACKUP_CTL), BACKUP_CTL_EN_CHARGE_KEY, (uint32_t) CY_SYSPM_SC_CHARGE… in Cy_SysPm_BackupSuperCapCharge()
1378 _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_POLARITY, polarity)) & in Cy_SysPm_PmicDisable()
1413 BACKUP_PMIC_CTL = _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_UNLOCK, 0u); in Cy_SysPm_PmicLock()
1419 …BACKUP_PMIC_CTL = _CLR_SET_FLD32U(BACKUP_PMIC_CTL, BACKUP_PMIC_CTL_UNLOCK, CY_SYSPM_PMIC_UNLOCK_KE… in Cy_SysPm_PmicUnlock()
1488 SRSS_PWR_SSV_CTL = _CLR_SET_FLD32U(SRSS_PWR_SSV_CTL, SRSS_PWR_SSV_CTL_OVDVDDD_VSEL, ovdVdddSel); in Cy_SysPm_OvdVdddSelect()
1494 SRSS_PWR_SSV_CTL = _CLR_SET_FLD32U(SRSS_PWR_SSV_CTL, SRSS_PWR_SSV_CTL_OVDVDDA_VSEL, ovdVddaSel); in Cy_SysPm_OvdVddaSelect()
1502 …SRSS_PWR_SSV_CTL = _CLR_SET_FLD32U(SRSS_PWR_SSV_CTL, SRSS_PWR_SSV_CTL_OVDVDDA_ACTION, ovdActionSel… in Cy_SysPm_OvdActionSelect()
1554 SRSS_PWR_SSV_CTL = _CLR_SET_FLD32U(SRSS_PWR_SSV_CTL, SRSS_PWR_SSV_CTL_BODVDDD_VSEL, bodVdddSel); in Cy_SysPm_BodVdddSelect()
[all …]
Dcy_rtc.c732 … curTime = (_CLR_SET_FLD32U(curTime, BACKUP_RTC_TIME_RTC_HOUR, CONVERT_DEC_TO_BCD(hourValue))); in Cy_RTC_SetHoursFormat()
741 (_CLR_SET_FLD32U(curTime, BACKUP_RTC_TIME_RTC_HOUR, in Cy_RTC_SetHoursFormat()
749 … curTime = (_CLR_SET_FLD32U(curTime, BACKUP_RTC_TIME_RTC_HOUR, CONVERT_DEC_TO_BCD(hourValue))); in Cy_RTC_SetHoursFormat()
774 … curTime = (_CLR_SET_FLD32U(curTime, BACKUP_RTC_TIME_RTC_HOUR, CONVERT_DEC_TO_BCD(hourValue))); in Cy_RTC_SetHoursFormat()
858 BACKUP_CTL = (_CLR_SET_FLD32U(BACKUP_CTL, SRSS_CLK_WCO_CONFIG_PRESCALER, (uint32_t) clkSel)); in Cy_RTC_SelectFrequencyPrescaler()
860 BACKUP_CTL = (_CLR_SET_FLD32U(BACKUP_CTL, BACKUP_CTL_PRESCALER, (uint32_t) clkSel)); in Cy_RTC_SelectFrequencyPrescaler()
879 BACKUP_CTL = (_CLR_SET_FLD32U(BACKUP_CTL, SRSS_CLK_WCO_CONFIG_CLK_RTC_SEL, (uint32_t) clkSel)); in Cy_RTC_SelectClockSource()
881 BACKUP_CTL = (_CLR_SET_FLD32U(BACKUP_CTL, BACKUP_CTL_CLK_SEL, (uint32_t) clkSel)); in Cy_RTC_SelectClockSource()
Dcy_canfd.c1316 CANFD_RXF0A(base, chan) = _CLR_SET_FLD32U(CANFD_RXF0A(base, chan), in Cy_CANFD_ExtractMsgFromRXBuffer()
1342 CANFD_RXF1A(base, chan) = _CLR_SET_FLD32U(CANFD_RXF1A(base, chan), in Cy_CANFD_ExtractMsgFromRXBuffer()
1440 CANFD_RXF0A(base, chan) = _CLR_SET_FLD32U(CANFD_RXF0A(base, chan), in Cy_CANFD_AckRxFifo()
1446 CANFD_RXF1A(base, chan) = _CLR_SET_FLD32U(CANFD_RXF1A(base, chan), in Cy_CANFD_AckRxFifo()
1595 CANFD_RXF0A(base, chan) = _CLR_SET_FLD32U(CANFD_RXF0A(base, chan), in Cy_CANFD_IrqHandler()
1642 CANFD_RXF1A(base, chan) = _CLR_SET_FLD32U(CANFD_RXF1A(base, chan), in Cy_CANFD_IrqHandler()
Dcy_prot.c1016 …PERI_MS_PPU_PR_SL_SIZE(base) = _CLR_SET_FLD32U((PERI_MS_PPU_PR_SL_SIZE(base)), PERI_MS_PPU_PR_V2_S… in Cy_Prot_ConfigPpuProgSlaveAddr()
1125 …_CLR_SET_FLD32U((PERI_MS_PPU_PR_SL_SIZE(base)), PERI_MS_PPU_PR_V2_SL_SIZE_VALID, CY_PROT_STRUCT_EN… in Cy_Prot_EnablePpuProgSlaveRegion()
1172 …_CLR_SET_FLD32U((PERI_MS_PPU_PR_SL_SIZE(base)), PERI_MS_PPU_PR_V2_SL_SIZE_VALID, CY_PROT_STRUCT_DI… in Cy_Prot_DisablePpuProgSlaveRegion()
Dcy_syspm_v2.c1734 BACKUP_CTL = _CLR_SET_FLD32U((BACKUP_CTL), BACKUP_CTL_VDDBAK_CTL, (uint32_t) vddBackControl); in Cy_SysPm_BackupSetSupply()
1765 …BACKUP_CTL = _CLR_SET_FLD32U((BACKUP_CTL), BACKUP_CTL_EN_CHARGE_KEY, (uint32_t) CY_SYSPM_SC_CHARGE… in Cy_SysPm_BackupSuperCapCharge()
Dcy_sd_host.c2994 SDHC_WRAP_CTL(base) = _CLR_SET_FLD32U(SDHC_WRAP_CTL(base), in Cy_SD_Host_DeInit()
4222 SDHC_WRAP_CTL(base) = _CLR_SET_FLD32U(SDHC_WRAP_CTL(base), in Cy_SD_Host_Enable()
4267 SDHC_WRAP_CTL(base) = _CLR_SET_FLD32U(SDHC_WRAP_CTL(base), in Cy_SD_Host_Disable()
/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/include/
Dcy_mcwdt.h871 … MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_LOCK_MCWDT_LOCK, CY_MCWDT_LOCK_SET01); in Cy_MCWDT_Lock()
873 …MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t… in Cy_MCWDT_Lock()
896 …MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOC… in Cy_MCWDT_Unlock()
897 …MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOC… in Cy_MCWDT_Unlock()
899 …MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t… in Cy_MCWDT_Unlock()
900 …MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t… in Cy_MCWDT_Unlock()
1037 …MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, ena… in Cy_MCWDT_SetClearOnMatch()
1041 …MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, ena… in Cy_MCWDT_SetClearOnMatch()
1111 … MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1, in Cy_MCWDT_SetCascade()
1113 … MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2, in Cy_MCWDT_SetCascade()
[all …]
Dcy_lvd_ht.h332 …SRSS_PWR_LVD_CTL = _CLR_SET_FLD32U(SRSS_PWR_LVD_CTL, SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT, threshold… in Cy_LVD_HT_SetThreshold()
336 …SRSS_PWR_LVD_CTL2 = _CLR_SET_FLD32U(SRSS_PWR_LVD_CTL2, SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT, thresh… in Cy_LVD_HT_SetThreshold()
583 …SRSS_PWR_LVD_CTL = _CLR_SET_FLD32U(SRSS_PWR_LVD_CTL, SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL, lvdInterrup… in Cy_LVD_HT_SetInterruptConfig()
587 …SRSS_PWR_LVD_CTL2 = _CLR_SET_FLD32U(SRSS_PWR_LVD_CTL2, SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL, lvdInter… in Cy_LVD_HT_SetInterruptConfig()
610 …SRSS_PWR_LVD_CTL = _CLR_SET_FLD32U(SRSS_PWR_LVD_CTL, SRSS_PWR_LVD_CTL_HVLVD1_ACTION, lvdActionConf… in Cy_LVD_HT_SetActionConfig()
614 …SRSS_PWR_LVD_CTL2 = _CLR_SET_FLD32U(SRSS_PWR_LVD_CTL2, SRSS_PWR_LVD_CTL2_HVLVD2_ACTION, lvdActionC… in Cy_LVD_HT_SetActionConfig()
Dcy_lvd.h442 … SRSS_PWR_LVD_CTL = _CLR_SET_FLD32U(SRSS_PWR_LVD_CTL, SRSS_PWR_LVD_CTL_HVLVD_TRIPSEL, threshold); in Cy_LVD_SetThreshold()
444 … SRSS_PWR_LVD_CTL = _CLR_SET_FLD32U(SRSS_PWR_LVD_CTL, SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL, threshold); in Cy_LVD_SetThreshold()
640 …SRSS_SRSS_INTR_CFG = _CLR_SET_FLD32U(SRSS_SRSS_INTR_CFG, SRSS_SRSS_INTR_CFG_HVLVD1_EDGE_SEL, lvdIn… in Cy_LVD_SetInterruptConfig()
642 …SRSS_PWR_LVD_CTL = _CLR_SET_FLD32U(SRSS_PWR_LVD_CTL, SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL, lvdInterrup… in Cy_LVD_SetInterruptConfig()
648 …SRSS_PWR_LVD_CTL = _CLR_SET_FLD32U(SRSS_PWR_LVD_CTL, SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL, lvdInterrup… in Cy_LVD_SetInterruptConfig()
Dcy_canfd.h1188 CANFD_CTL(base) = _CLR_SET_FLD32U(CANFD_CTL(base), in Cy_CANFD_Enable()
1223 CANFD_CTL(base) = _CLR_SET_FLD32U(CANFD_CTL(base), in Cy_CANFD_Disable()
1269 CANFD_CTL(base) = _CLR_SET_FLD32U(CANFD_CTL(base), CANFD_CTL_MRAM_OFF, 0UL); in Cy_CANFD_EnableMRAM()
1302 CANFD_CTL(base) = _CLR_SET_FLD32U(CANFD_CTL(base), in Cy_CANFD_DisableMRAM()
1573 CANFD_DBTP(base, chan) = _CLR_SET_FLD32U(CANFD_DBTP(base, chan), in Cy_CANFD_SetTDC()
Dcy_lpcomp.h826 …LPCOMP_CMP0_SW(base) = _CLR_SET_FLD32U(LPCOMP_CMP0_SW(base), LPCOMP_CMP0_SW_CMP0_VN0, CY_LPCOMP_RE… in Cy_LPComp_ConnectULPReference()
831 …LPCOMP_CMP1_SW(base) = _CLR_SET_FLD32U(LPCOMP_CMP1_SW(base), LPCOMP_CMP1_SW_CMP1_VN1, CY_LPCOMP_RE… in Cy_LPComp_ConnectULPReference()
Dcy_wdt.h660 SRSS_WDT_CTL = _CLR_SET_FLD32U((SRSS_WDT_CTL), SRSS_WDT_CTL_WDT_CLK_SEL, src); in Cy_WDT_SetClkSource()
Dcy_usbfs_dev_drv_reg.h631 USBFS_DEV_SIE_EP_CR0(base, endpoint) = _CLR_SET_FLD32U(USBFS_DEV_SIE_EP_CR0(base, endpoint), in Cy_USBFS_Dev_Drv_SetSieEpMode()
712 uint32_t regVal = _CLR_SET_FLD32U(USBFS_DEV_SIE_EP_CR0(base, endpoint), in Cy_USBFS_Dev_Drv_ClearSieEpStall()
Dcy_usbfs_dev_drv.h1515 base->USBDEV.CR0 = _CLR_SET_FLD32U(base->USBDEV.CR0, USBFS_USBDEV_CR0_DEVICE_ADDRESS, address); in Cy_USBFS_Dev_Drv_SetDeviceAddress()
2013 USBFS_DEV_LPM_LPM_CTL(base) = _CLR_SET_FLD32U(USBFS_DEV_LPM_LPM_CTL(base), in Cy_USBFS_Dev_Drv_Lpm_SetResponse()
Dcy_sar2.h1224 base->PASS_CTL = _CLR_SET_FLD32U(base->PASS_CTL, PASS_EPASS_MMIO_PASS_CTL_REFBUF_MODE, mode); in Cy_SAR2_SetReferenceBufferMode()
Dcy_sar.h1754 …SAR_INJ_CHAN_CONFIG(base) = _CLR_SET_FLD32U(SAR_INJ_CHAN_CONFIG(base), SAR_INJ_CHAN_CONFIG_INJ_TAI… in Cy_SAR_EnableInjection()
/hal_infineon-3.6.0/core-lib/include/
Dcy_utils.h299 #define _CLR_SET_FLD32U(reg, field, value) \ macro
312 #define CY_REG32_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD32U((reg), field, (value)))
/hal_infineon-3.6.0/core-lib/
DREADME.md29 …* `_CLR_SET_FLD32U`: The macro for setting a register with a name field and value for providing g…
30 …* `CY_REG32_CLR_SET`: Uses _CLR_SET_FLD32U macro for providing get-clear-modify-write operations w…
DRELEASE.md25 …* _CLR_SET_FLD32U: The macro for setting a register with a name field and value for providing get…
26 …* CY_REG32_CLR_SET: Uses _CLR_SET_FLD32U macro for providing get-clear-modify-write operations wit…

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