1 /**
2 * @file xmc1_scu.h
3 * @date 2019-03-20
4 *
5 * @cond
6 *********************************************************************************************************************
7 * XMClib v2.1.24 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015-2019, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
22 * products derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
33 * Infineon Technologies AG dave@infineon.com).
34 *********************************************************************************************************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-02-20:
40 * - Initial
41 *
42 * 2015-05-20:
43 * - Description updated <br>
44 *
45 * 2015-06-20:
46 * - XMC_SCU_INTERRUPT_EVENT enum elements are typecasted to int64_t
47 *
48 * 2015-06-20:
49 * - Added support for XMC1400
50 *
51 * 2015-11-30:
52 * - Documentation improved
53 *
54 * 2015-12-09:
55 * - Added XMC_SCU_EnablePrefetchUnit and XMC_SCU_DisablePrefetchUnit
56 *
57 * 2016-03-09:
58 * - Added XMC_SCU_POWER_EnableMonitor/XMC_SCU_POWER_DisableMonitor
59 *
60 * 2017-03-28:
61 * - Fixed prescaler formula comments for XMC_SCU_CLOCK_EnableDCO1ExtRefCalibration()
62 * - Added XMC_SCU_SetBMI()
63 *
64 * 2017-08-03:
65 * - Removed unused XMC_SCU_CLOCK_DEEP_SLEEP_t
66 * - Added XMC_SCU_CLOCK_EnableFlashPowerDown() and XMC_SCU_CLOCK_DisableFlashPowerDown()
67 *
68 * 2017-09-15:
69 * - Added XMC_SCU_GetBMI()
70 * - Make XMC_SCU_CLOCK_EnableFlashPowerDown() and XMC_SCU_CLOCK_DisableFlashPowerDown() available to all XMC1 families
71 * - Added XMC_SCU_BMI_HWCFG_PINDIS for XMC1400
72 *
73 * 2019-03-20:
74 * - Added XMC_SCU_CLOCK_SetHighPerformanceOscillatorMode() and XMC_SCU_CLOCK_SetLowPerformanceOscillatorMode()
75 *
76 * @endcond
77 *
78 */
79
80 #ifndef XMC1_SCU_H
81 #define XMC1_SCU_H
82
83 /*********************************************************************************************************************
84 * HEADER FILES
85 ********************************************************************************************************************/
86 #include "xmc_common.h"
87
88 #if UC_FAMILY == XMC1
89
90 /**
91 * @addtogroup XMClib XMC Peripheral Library
92 * @{
93 */
94
95 /**
96 * @addtogroup SCU
97 * @{
98 */
99
100 /*********************************************************************************************************************
101 * MACROS
102 ********************************************************************************************************************/
103
104 /*
105 * List of events
106 */
107 #define XMC_SCU_INTERRUPT_EVENT_WDT_WARN SCU_INTERRUPT_SRMSK_PRWARN_Msk /**< WDT pre-warning event. */
108 #define XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC SCU_INTERRUPT_SRCLR_PI_Msk /**< RTC periodic event. */
109 #define XMC_SCU_INTERRUPT_EVENT_RTC_ALARM SCU_INTERRUPT_SRCLR_AI_Msk /**< RTC alarm event. */
110 #define XMC_SCU_INTERRUPT_EVENT_VDDPI SCU_INTERRUPT_SRMSK_VDDPI_Msk /**< VDDP pre-warning event. */
111 #if defined(COMPARATOR)
112 #define XMC_SCU_INTERRUPT_EVENT_ACMP0 SCU_INTERRUPT_SRMSK_ACMP0I_Msk /**< Analog comparator-0 output event. */
113 #define XMC_SCU_INTERRUPT_EVENT_ACMP1 SCU_INTERRUPT_SRMSK_ACMP1I_Msk /**< Analog comparator-1 output event. */
114 #define XMC_SCU_INTERRUPT_EVENT_ACMP2 SCU_INTERRUPT_SRMSK_ACMP2I_Msk /**< Analog comparator-2 output event. */
115 #if (UC_SERIES == XMC14) || defined(DOXYGEN)
116 #define XMC_SCU_INTERRUPT_EVENT_ACMP3 (((int64_t)SCU_INTERRUPT_SRMSK1_ACMP3I_Msk) << 32U) /**< Analog comparator-3 output event. @note Only available for XMC1400 series */
117 #endif
118 #endif
119 #define XMC_SCU_INTERRUPT_EVENT_VDROP SCU_INTERRUPT_SRMSK_VDROPI_Msk /**< VDROP event. */
120 #if UC_SERIES != XMC11
121 #define XMC_SCU_INTERRUPT_EVENT_ORC0 SCU_INTERRUPT_SRMSK_ORC0I_Msk /**< Out of range comparator-0 event. */
122 #define XMC_SCU_INTERRUPT_EVENT_ORC1 SCU_INTERRUPT_SRMSK_ORC1I_Msk /**< Out of range comparator-1 event. */
123 #define XMC_SCU_INTERRUPT_EVENT_ORC2 SCU_INTERRUPT_SRMSK_ORC2I_Msk /**< Out of range comparator-2 event. */
124 #define XMC_SCU_INTERRUPT_EVENT_ORC3 SCU_INTERRUPT_SRMSK_ORC3I_Msk /**< Out of range comparator-3 event. */
125 #define XMC_SCU_INTERRUPT_EVENT_ORC4 SCU_INTERRUPT_SRMSK_ORC4I_Msk /**< Out of range comparator-4 event. */
126 #define XMC_SCU_INTERRUPT_EVENT_ORC5 SCU_INTERRUPT_SRMSK_ORC5I_Msk /**< Out of range comparator-5 event. */
127 #define XMC_SCU_INTERRUPT_EVENT_ORC6 SCU_INTERRUPT_SRMSK_ORC6I_Msk /**< Out of range comparator-6 event. */
128 #define XMC_SCU_INTERRUPT_EVENT_ORC7 SCU_INTERRUPT_SRMSK_ORC7I_Msk /**< Out of range comparator-7 event. */
129 #endif
130 #define XMC_SCU_INTERRUPT_EVENT_LOCI SCU_INTERRUPT_SRMSK_LOCI_Msk /**< Loss of clock event. */
131 #define XMC_SCU_INTERRUPT_EVENT_PESRAM SCU_INTERRUPT_SRMSK_PESRAMI_Msk /**< PSRAM Parity error event. */
132 #define XMC_SCU_INTERRUPT_EVENT_PEUSIC0 SCU_INTERRUPT_SRMSK_PEU0I_Msk /**< USIC0 Parity error event. */
133 #if defined(USIC1)
134 #define XMC_SCU_INTERRUPT_EVENT_PEUSIC1 (((int64_t)SCU_INTERRUPT_SRMSK1_PEU1I_Msk) << 32U) /**< USIC1 Parity error event. */
135 #endif
136 #define XMC_SCU_INTERRUPT_EVENT_FLASH_ERROR SCU_INTERRUPT_SRMSK_FLECC2I_Msk /**< Flash ECC double bit error event. */
137 #define XMC_SCU_INTERRUPT_EVENT_FLASH_COMPLETED SCU_INTERRUPT_SRCLR_FLCMPLTI_Msk /**< Flash operation completion event. */
138 #define XMC_SCU_INTERRUPT_EVENT_VCLIP SCU_INTERRUPT_SRMSK_VCLIPI_Msk /**< VCLIP event. */
139 #define XMC_SCU_INTERRUPT_EVENT_STDBYCLKFAIL SCU_INTERRUPT_SRMSK_SBYCLKFI_Msk /**< Standby clock failure event. */
140 #define XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED SCU_INTERRUPT_SRMSK_RTC_CTR_Msk /**< RTCCTR register update event. */
141 #define XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk /**< RTCATIM0 register update event. */
142 #define XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk /**< RTCATIM1 register update event. */
143 #define XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk /**< RTCTIM0 register update event. */
144 #define XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk /**< RTCTIM1 register update event. */
145 #define XMC_SCU_INTERRUPT_EVENT_TSE_DONE SCU_INTERRUPT_SRMSK_TSE_DONE_Msk /**< Temperature measurement Completion event. */
146 #define XMC_SCU_INTERRUPT_EVENT_TSE_HIGH SCU_INTERRUPT_SRMSK_TSE_HIGH_Msk /**< Temperature too high event. */
147 #define XMC_SCU_INTERRUPT_EVENT_TSE_LOW SCU_INTERRUPT_SRMSK_TSE_LOW_Msk /**< Temperature too low event. */
148 #if defined(CAN)
149 #define XMC_SCU_INTERRUPT_EVENT_PEMCAN (((int64_t)SCU_INTERRUPT_SRMSK1_PEMCI_Msk) << 32U) /**< MultiCAN SRAM Parity Error Event. */
150 #endif
151 #if (UC_SERIES == XMC14) || defined(DOXYGEN)
152 #define XMC_SCU_INTERRUPT_EVENT_LOSS_EXT_CLOCK (((int64_t)SCU_INTERRUPT_SRMSK1_LOECI_Msk) << 32U) /**< Loss of external OSC_HP clock event. @note Only available for XMC1400 series */
153 #define XMC_SCU_INTERRUPT_EVENT_DCO1_OUT_SYNC (((int64_t)SCU_INTERRUPT_SRMSK1_DCO1OFSI_Msk) << 32U) /**< DCO1 Out of SYNC Event. @note Only available for XMC1400 series */
154 #endif
155
156 /*
157 * These are the flags which may be passed to XMC_SCU_SetBMI().
158 */
159 #if defined(CAN) || defined(DOXYGEN)
160 #define XMC_SCU_BMI_HWCFG_CAN_BSL (0x0000U) /**< CAN Bootstrap Loader Start-up Mode */
161 #define XMC_SCU_BMI_HWCFG_CAN_BSLTO (0x0010U) /**< CAN Bootstrap Loader Start-up Mode with time-out */
162 #define XMC_SCU_BMI_HWCFG_SBSL_CANOPEN (0x0020U) /**< Secure Bootstrap Loader Start-up Mode over CANopen */
163 #endif
164
165 #define XMC_SCU_BMI_HWCFG_ASC_BSL (0x0040U) /**< ASC Bootstrap Loader Start-up Mode */
166 #define XMC_SCU_BMI_HWCFG_UPM (0x0041U) /**< User productive Start-up Mode */
167 #define XMC_SCU_BMI_HWCFG_UMD (0x0043U) /**< User Start-up Mode with debug enabled */
168 #define XMC_SCU_BMI_HWCFG_UMHAR (0x0047U) /**< User Start-up Mode with debug enabled and halt after reset (HAR) */
169 #define XMC_SCU_BMI_HWCFG_SSC_BSL (0x0048U) /**< SSC Bootstrap Loader Start-up Mode */
170 #define XMC_SCU_BMI_HWCFG_ASC_BSLTO (0x0050U) /**< ASC BSL Start-up Mode with time-out */
171 #define XMC_SCU_BMI_HWCFG_SSC_BSLTO (0x0058U) /**< SSC BSL Start-up Mode with time-out */
172 #define XMC_SCU_BMI_HWCFG_SBSL (0x007AU) /**< Secure Bootstrap Loader Start-up Mode over ASC */
173
174 #if (UC_SERIES == XMC14) || defined(DOXYGEN)
175 #define XMC_SCU_BMI_HWCFG_PINDIS (0x0080U) /**< Boot Configuration Type Selection, Boot from BMI is selected */
176 #endif
177
178 #define XMC_SCU_BMI_DAPTYP_SWD (0U << 8) /**< Serial wire debug (SWD) interface is selected */
179 #define XMC_SCU_BMI_DAPTYP_SPD (1U << 8) /**< Single pin debug (SPD) interface is selected */
180
181 #define XMC_SCU_BMI_DAPDIS_CHANNEL_0 (0U << 9) /**< SWD/SPD_0 pin is selected */
182 #define XMC_SCU_BMI_DAPDIS_CHANNEL_1 (1U << 9) /**< SWD/SPD_1 pin is selected */
183
184 #if defined(CAN) || defined(DOXYGEN)
185 #define XMC_SCU_BMI_CANCLK_DCO1 (0U << 11) /**< Synchronous CAN clock via internal oscillator (DCO1) with enabled trimming via external reference is selected */
186 #define XMC_SCU_BMI_CANCLK_OSCHP (1U << 11) /**< Synchronous CAN clock via external oscillator (OSC_HP) is selected */
187 #endif
188
189 #define XMC_BMI_ADDR (0x10000e00U) /**< Boot Mode Index (BMI) address holding information about start-up mode and debug configuration of the device. */
190
191 /*********************************************************************************************************************
192 * ENUMS
193 ********************************************************************************************************************/
194
195 /**
196 * Defines the cause of last reset. The cause of last reset gets automatically stored in
197 * the \a SCU_RSTSTAT register and can be checked by user software to determine the state of the system and for debug
198 * purpose. All the enum items are tabulated as per bits present in \a SCU_RSTSTAT register.
199 * Use type \a XMC_SCU_RESET_REASON_t for accessing these enum parameters.
200 */
201 typedef enum XMC_SCU_RESET_REASON
202 {
203 XMC_SCU_RESET_REASON_PORST = (1UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Power On reset. */
204 XMC_SCU_RESET_REASON_MASTER = (2UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Master reset. */
205 XMC_SCU_RESET_REASON_SW = (4UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to Software initiated reset. */
206 XMC_SCU_RESET_REASON_LOCKUP = (8UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to CPU lockup. */
207 XMC_SCU_RESET_REASON_FLASH = (16UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to flash error. */
208 XMC_SCU_RESET_REASON_WATCHDOG = (32UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to watchdog. */
209 XMC_SCU_RESET_REASON_CLOCK_LOSS = (64UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos), /**< Reset due to clock loss. */
210 XMC_SCU_RESET_REASON_PARITY_ERROR = (128UL << SCU_RESET_RSTSTAT_RSTSTAT_Pos) /**< Reset due to RAM parity error. */
211 } XMC_SCU_RESET_REASON_t;
212
213 /**
214 * Defines the reset sources that can cause device reset. These enums can be used to configure reset source in reset
215 * control \a RSTCON register which enables different reset sources to identify the reset cause. The \a SCU_RSTSTAT
216 * register can be checked by user software to determine the state of the system and for debug
217 * purpose. Use type \a XMC_SCU_SYSTEM_RESET_REQUEST_t for accessing these enum parameters.
218 */
219 typedef enum XMC_SCU_SYSTEM_RESET_REQUEST
220 {
221 XMC_SCU_RESET_REQUEST_FLASH_ECC_ERROR = SCU_RESET_RSTCON_ECCRSTEN_Msk, /**< Reset when ECC double bit error occurs.*/
222 XMC_SCU_RESET_REQUEST_CLOCK_LOSS = SCU_RESET_RSTCON_LOCRSTEN_Msk, /**< Reset when loss of clock occurs.*/
223 XMC_SCU_RESET_REQUEST_SRAM_PARITY_ERROR = SCU_RESET_RSTCON_SPERSTEN_Msk, /**< Reset when SRAM parity error occurs.*/
224 XMC_SCU_RESET_REQUEST_USIC_SRAM_PARITY_ERROR = SCU_RESET_RSTCON_U0PERSTEN_Msk /**< Reset when USIC0 memory parity error occurs.*/
225 } XMC_SCU_SYSTEM_RESET_REQUEST_t;
226
227 /**
228 * Defines list of events that can generate SCU interrupt. These enums can be used to configure events
229 * in \a SRMSK register for assertion of interrupt. All the enum items are tabulated as per bits present
230 * in \a SRMSK register. Use type \a XMC_SCU_INTERRUPT_EVENT_t for accessing these enum parameters. These
231 * enums can also be used for checking the status of events from the \a SRSTAT register.
232 */
233 #if (UC_SERIES == XMC14)
234 typedef uint64_t XMC_SCU_INTERRUPT_EVENT_t;
235 #else
236 typedef uint32_t XMC_SCU_INTERRUPT_EVENT_t;
237 #endif
238
239 /**
240 * Defines possible sources of RTC clock. These enums can be used to configure \a RTCCLKSEL bits of \a CLKCR Clock Control
241 * Register. Use type \a XMC_SCU_CLOCK_RTCCLKSRC_t for accessing these enum parameters.
242 */
243 typedef enum XMC_SCU_CLOCK_RTCCLKSRC
244 {
245 XMC_SCU_CLOCK_RTCCLKSRC_DCO2 = (0x0UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos), /**< RTC clock source is standby clock. */
246 XMC_SCU_CLOCK_RTCCLKSRC_ERU_IOUT0 = (0x1UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos), /**< RTC clock source is external clock from
247 ERU0.IOUT0. */
248 XMC_SCU_CLOCK_RTCCLKSRC_ACMP0_OUT = (0x2UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos), /**< RTC clock source is external clock from
249 ACMP0.OUT. */
250 XMC_SCU_CLOCK_RTCCLKSRC_ACMP1_OUT = (0x3UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos), /**< RTC clock source is external clock from
251 ACMP1.OUT. */
252 XMC_SCU_CLOCK_RTCCLKSRC_ACMP2_OUT = (0x4UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos), /**< RTC clock source is external clock from
253 ACMP2.OUT. */
254 #if (UC_SERIES == XMC14) || defined(DOXYGEN)
255 XMC_SCU_CLOCK_RTCCLKSRC_OSCLP = (0x5UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos) /**< 32.768kHz XTAL clock via OSC_LP. @note Only available for XMC1400 series */
256 #endif
257 } XMC_SCU_CLOCK_RTCCLKSRC_t;
258
259 /**
260 * Defines possible sources of peripheral clock (PCLK). These enums can be used to configure \a PCLKSEL bits of \a CLKCR
261 * Clock Control Register. Use type \a XMC_SCU_CLOCK_PCLKSRC_t for accessing these enum parameters.
262 */
263 typedef enum XMC_SCU_CLOCK_PCLKSRC
264 {
265 XMC_SCU_CLOCK_PCLKSRC_MCLK = (0UL << SCU_CLK_CLKCR_PCLKSEL_Pos), /**< MCLK as the source for PCLK. */
266 XMC_SCU_CLOCK_PCLKSRC_DOUBLE_MCLK = (1UL << SCU_CLK_CLKCR_PCLKSEL_Pos) /**< Source of PCLK is twice the MCLK. */
267 } XMC_SCU_CLOCK_PCLKSRC_t;
268
269 #if (UC_SERIES == XMC14) || defined(DOXYGEN)
270 /**
271 * DCLK clock source selection
272 * @note Only available in XMC1400 series
273 */
274 typedef enum XMC_SCU_CLOCK_DCLKSRC
275 {
276 XMC_SCU_CLOCK_DCLKSRC_DCO1 = 0UL << SCU_CLK_CLKCR1_DCLKSEL_Pos, /**< Internal oscillator DCO1 (48MHz) */
277 XMC_SCU_CLOCK_DCLKSRC_EXT_XTAL = 1UL << SCU_CLK_CLKCR1_DCLKSEL_Pos, /**< External crystal oscillator */
278 } XMC_SCU_CLOCK_DCLKSRC_t;
279
280 /**
281 * OSCHP mode
282 * @note Only available in XMC1400 series
283 */
284 typedef enum XMC_SCU_CLOCK_OSCHP_MODE
285 {
286 XMC_SCU_CLOCK_OSCHP_MODE_OSC = 0UL << SCU_ANALOG_ANAOSCHPCTRL_MODE_Pos, /**< Oscillator is enabled and in active power mode with shaper enabled */
287 XMC_SCU_CLOCK_OSCHP_MODE_DIRECT = 1UL << SCU_ANALOG_ANAOSCHPCTRL_MODE_Pos, /**< Oscillator in power down mode with shaper enabled */
288 XMC_SCU_CLOCK_OSCHP_MODE_DISABLED = 3UL << SCU_ANALOG_ANAOSCHPCTRL_MODE_Pos, /**< Oscillator in power down mode with shaper enabled */
289 } XMC_SCU_CLOCK_OSCHP_MODE_t;
290
291 /**
292 * OSCLP mode
293 * @note Only available in XMC1400 series
294 */
295 typedef enum XMC_SCU_CLOCK_OSCLP_MODE
296 {
297 XMC_SCU_CLOCK_OSCLP_MODE_OSC = 0UL << SCU_ANALOG_ANAOSCLPCTRL_MODE_Pos, /**< Oscillator is enabled and in active power mode with shaper enabled */
298 XMC_SCU_CLOCK_OSCLP_MODE_DISABLED = 3UL << SCU_ANALOG_ANAOSCLPCTRL_MODE_Pos, /**< Oscillator in power down mode with shaper enabled */
299 } XMC_SCU_CLOCK_OSCLP_MODE_t;
300
301 /**
302 * Clock source for synchronization
303 * @note Only available in XMC1400 series
304 */
305 typedef enum XMC_SCU_CLOCK_SYNC_CLKSRC
306 {
307 XMC_SCU_CLOCK_SYNC_CLKSRC_OSCLP = 0U << SCU_ANALOG_ANASYNC1_XTAL_SEL_Pos,
308 XMC_SCU_CLOCK_SYNC_CLKSRC_OSCHP = 1U << SCU_ANALOG_ANASYNC1_XTAL_SEL_Pos,
309 } XMC_SCU_CLOCK_SYNC_CLKSRC_t;
310
311 #endif /* (UC_SERIES == XMC14) */
312
313 /**
314 * Defines the list of peripherals that support clock gating. After a master reset, only core, memories, SCU
315 * and PORT peripheral are not clock gated. The rest of the peripherals are by default clock gated.
316 * All the enum items are tabulated as per bits present in \a CGATSTAT0 register.
317 * Use type \a XMC_SCU_PERIPHERAL_CLOCK_t for accessing these enum parameters.
318 * @note Peripherals availability depends on device
319 */
320 typedef enum XMC_SCU_PERIPHERAL_CLOCK
321 {
322 #if defined(VADC)
323 XMC_SCU_PERIPHERAL_CLOCK_VADC = SCU_CLK_CGATSTAT0_VADC_Msk, /**< VADC peripheral clock gate. */
324 #endif
325 #if defined(CCU80)
326 XMC_SCU_PERIPHERAL_CLOCK_CCU80 = SCU_CLK_CGATSTAT0_CCU80_Msk, /**< CCU80 peripheral clock gate. */
327 #endif
328 #if defined(CCU40)
329 XMC_SCU_PERIPHERAL_CLOCK_CCU40 = SCU_CLK_CGATSTAT0_CCU40_Msk, /**< CCU40 peripheral clock gate. */
330 #endif
331 #if defined(USIC0)
332 XMC_SCU_PERIPHERAL_CLOCK_USIC0 = SCU_CLK_CGATSTAT0_USIC0_Msk, /**< USIC0 peripheral clock gate. */
333 #endif
334 #if defined(BCCU0)
335 XMC_SCU_PERIPHERAL_CLOCK_BCCU0 = SCU_CLK_CGATSTAT0_BCCU0_Msk, /**< BCCU0 peripheral clock gate. */
336 #endif
337 #if defined(LEDTS0)
338 XMC_SCU_PERIPHERAL_CLOCK_LEDTS0 = SCU_CLK_CGATSTAT0_LEDTS0_Msk, /**< LEDTS0 peripheral clock gate. */
339 #endif
340 #if defined(LEDTS1)
341 XMC_SCU_PERIPHERAL_CLOCK_LEDTS1 = SCU_CLK_CGATSTAT0_LEDTS1_Msk, /**< LEDTS1 peripheral clock gate. */
342 #endif
343 #if defined(POSIF0)
344 XMC_SCU_PERIPHERAL_CLOCK_POSIF0 = SCU_CLK_CGATSTAT0_POSIF0_Msk, /**< POSIF0 peripheral clock gate. */
345 #endif
346 #if defined(MATH)
347 XMC_SCU_PERIPHERAL_CLOCK_MATH = SCU_CLK_CGATSTAT0_MATH_Msk, /**< MATH peripheral clock gate. */
348 #endif
349 XMC_SCU_PERIPHERAL_CLOCK_WDT = SCU_CLK_CGATSTAT0_WDT_Msk, /**< WDT peripheral clock gate. */
350 XMC_SCU_PERIPHERAL_CLOCK_RTC = SCU_CLK_CGATSTAT0_RTC_Msk, /**< RTC peripheral clock gate. */
351 #if defined(CCU81)
352 XMC_SCU_PERIPHERAL_CLOCK_CCU81 = SCU_CLK_CGATSTAT0_CCU81_Msk, /**< CCU80 peripheral clock gate. */
353 #endif
354 #if defined(CCU41)
355 XMC_SCU_PERIPHERAL_CLOCK_CCU41 = SCU_CLK_CGATSTAT0_CCU41_Msk, /**< CCU80 peripheral clock gate. */
356 #endif
357 #if defined(USIC1)
358 XMC_SCU_PERIPHERAL_CLOCK_USIC1 = SCU_CLK_CGATSTAT0_USIC1_Msk, /**< USIC0 peripheral clock gate. */
359 #endif
360 #if defined(LEDTS2)
361 XMC_SCU_PERIPHERAL_CLOCK_LEDTS2 = SCU_CLK_CGATSTAT0_LEDTS2_Msk, /**< LEDTS1 peripheral clock gate. */
362 #endif
363 #if defined(POSIF1)
364 XMC_SCU_PERIPHERAL_CLOCK_POSIF1 = SCU_CLK_CGATSTAT0_POSIF1_Msk, /**< POSIF0 peripheral clock gate. */
365 #endif
366 #if defined(CAN)
367 XMC_SCU_PERIPHERAL_CLOCK_MCAN = SCU_CLK_CGATSTAT0_MCAN0_Msk, /**< POSIF0 peripheral clock gate. */
368 #endif
369 } XMC_SCU_PERIPHERAL_CLOCK_t;
370
371
372 /**
373 * Defines options for Capture/Compare unit timer slice trigger that enables synchronous start function available on the \a SCU,
374 * \a CCUCON register. Use type \a XMC_SCU_CCU_TRIGGER_t for accessing these enum parameters.
375 */
376 typedef enum XMC_SCU_CCU_TRIGGER
377 {
378 XMC_SCU_CCU_TRIGGER_CCU40 = SCU_GENERAL_CCUCON_GSC40_Msk, /**< Trigger CCU40 peripheral. */
379 #if defined(CCU80)
380 XMC_SCU_CCU_TRIGGER_CCU80 = SCU_GENERAL_CCUCON_GSC80_Msk, /**< Trigger CCU80 peripheral. */
381 #endif
382 #if defined(CCU41)
383 XMC_SCU_CCU_TRIGGER_CCU41 = SCU_GENERAL_CCUCON_GSC41_Msk, /**< Trigger CCU40 peripheral. */
384 #endif
385 #if defined(CCU81)
386 XMC_SCU_CCU_TRIGGER_CCU81 = SCU_GENERAL_CCUCON_GSC81_Msk, /**< Trigger CCU80 peripheral. */
387 #endif
388 } XMC_SCU_CCU_TRIGGER_t;
389
390 #if (UC_SERIES == XMC14) || defined(DOXYGEN)
391 /**
392 * Selects the service request connected to the interrupt node.
393 * @image html "xmc1400_irqmux.png"
394 * @note Only available for XMC1400 series
395 */
396 typedef enum XMC_SCU_IRQCTRL
397 {
398 XMC_SCU_IRQCTRL_SCU_SR0_IRQ0 = (0U << 8U) | 0U, /**< SCU_SR0 connected to IRQ0 */
399 #if defined(CAN)
400 XMC_SCU_IRQCTRL_CAN0_SR0_IRQ0 = (0U << 8U) | 1U, /**< CAN0_SR0 connected to IRQ0 */
401 #endif
402 XMC_SCU_IRQCTRL_CCU40_SR0_IRQ0 = (0U << 8U) | 2U, /**< CCU40_SR0 connected to IRQ0 */
403 #if defined(CAN)
404 XMC_SCU_IRQCTRL_SCU_SR0_OR_CAN0_SR0_IRQ0 = (0U << 8U) | 3U, /**< SCU_SR0 and CAN_SR0 are both connected to IRQ0*/
405 #endif
406
407 XMC_SCU_IRQCTRL_SCU_SR1_IRQ1 = (1U << 8U) | 0U, /**< SCU_SR1 connected to IRQ1 */
408 #if defined(CAN)
409 XMC_SCU_IRQCTRL_CAN0_SR1_IRQ1 = (1U << 8U) | 1U, /**< CAN0_SR1 connected to IRQ1 */
410 #endif
411 #if defined(CCU80)
412 XMC_SCU_IRQCTRL_CCU80_SR0_IRQ1 = (1U << 8U) | 2U, /**< CCU80_SR0 connected to IRQ1 */
413 #endif
414 #if defined(CAN)
415 XMC_SCU_IRQCTRL_SCU_SR1_OR_CAN0_SR1_IRQ1 = (1U << 8U) | 3U, /**< SCU_SR1 and CAN0_SR1 connected to IRQ1 */
416 #endif
417
418 XMC_SCU_IRQCTRL_SCU_SR2_IRQ2 = (2U << 8U) | 0U, /**< SCU_SR2 connected to IRQ2 */
419 #if defined(CAN)
420 XMC_SCU_IRQCTRL_CAN0_SR2_IRQ2 = (2U << 8U) | 1U, /**< CAN0_SR2 connected to IRQ2 */
421 #endif
422 #if defined(CCU80)
423 XMC_SCU_IRQCTRL_CCU80_SR1_IRQ2 = (2U << 8U) | 2U, /**< CCU80_SR1 connected to IRQ2 */
424 #endif
425 #if defined(CAN)
426 XMC_SCU_IRQCTRL_SCU_SR2_OR_CAN0_SR2_IRQ2 = (2U << 8U) | 3U, /**< SCU_SR2 and CAN0_SR2 connected to IRQ2 */
427 #endif
428
429 XMC_SCU_IRQCTRL_ERU0_SR0_IRQ3 = (3U << 8U) | 0U, /**< ERU0_SR0 connected to IRQ3 */
430 XMC_SCU_IRQCTRL_ERU1_SR0_IRQ3 = (3U << 8U) | 1U, /**< ERU1_SR0 connected to IRQ3 */
431 #if defined(CAN)
432 XMC_SCU_IRQCTRL_CAN0_SR0_IRQ3 = (3U << 8U) | 2U, /**< CAN0_SR0 connected to IRQ3 */
433 #endif
434 XMC_SCU_IRQCTRL_ERU0_SR0_OR_ERU1_SR0_IRQ3 = (3U << 8U) | 3U, /**< ERU0_SR0 and ERU1_SR0 connected to IRQ3 */
435
436 XMC_SCU_IRQCTRL_ERU0_SR1_IRQ4 = (4U << 8U) | 0U, /**< ERU0_SR1 connected to IRQ4 */
437 XMC_SCU_IRQCTRL_ERU1_SR1_IRQ4 = (4U << 8U) | 1U, /**< ERU1_SR1 connected to IRQ4 */
438 #if defined(CAN)
439 XMC_SCU_IRQCTRL_CAN0_SR1_IRQ4 = (4U << 8U) | 2U, /**< CAN0_SR1 connected to IRQ4 */
440 #endif
441 XMC_SCU_IRQCTRL_ERU0_SR1_OR_ERU1_SR1_IRQ4 = (4U << 8U) | 3U, /**< ERU0_SR1 and ERU1_SR1 connected to IRQ4 */
442
443 XMC_SCU_IRQCTRL_ERU0_SR2_IRQ5 = (5U << 8U) | 0U, /**< ERU0_SR2 connected to IRQ5 */
444 XMC_SCU_IRQCTRL_ERU1_SR2_IRQ5 = (5U << 8U) | 1U, /**< ERU1_SR2 connected to IRQ5 */
445 #if defined(CAN)
446 XMC_SCU_IRQCTRL_CAN0_SR2_IRQ5 = (5U << 8U) | 2U, /**< CAN0_SR2 connected to IRQ5 */
447 #endif
448 XMC_SCU_IRQCTRL_ERU0_SR2_OR_ERU1_SR2_IRQ5 = (5U << 8U) | 3U, /**< ERU0_SR2 and ERU1_SR2 connected to IRQ5 */
449
450 XMC_SCU_IRQCTRL_ERU0_SR3_IRQ6 = (6U << 8U) | 0U, /**< ERU0_SR3 connected to IRQ6 */
451 XMC_SCU_IRQCTRL_ERU1_SR3_IRQ6 = (6U << 8U) | 1U, /**< ERU1_SR3 connected to IRQ6 */
452 #if defined(CAN)
453 XMC_SCU_IRQCTRL_CAN0_SR3_IRQ6 = (6U << 8U) | 2U, /**< CAN0_SR3 connected to IRQ6 */
454 #endif
455 XMC_SCU_IRQCTRL_ERU0_SR3_OR_ERU1_SR3_IRQ6 = (6U << 8U) | 3U, /**< ERU0_SR3 and ERU1_SR3 connected to IRQ6 */
456
457 #if defined(MATH)
458 XMC_SCU_IRQCTRL_MATH_SR0_IRQ7 = (7U << 8U) | 0U, /**< MATH_SR0 connected to IRQ7 */
459 #endif
460 #if defined(CAN)
461 XMC_SCU_IRQCTRL_CAN0_SR3_IRQ7 = (7U << 8U) | 1U, /**< CAN0_SR3 connected to IRQ7 */
462 #endif
463 XMC_SCU_IRQCTRL_CCU40_SR1_IRQ7 = (7U << 8U) | 2U, /**< CCU40_SR1 connected to IRQ7 */
464 #if defined(MATH) && defined(CAN)
465 XMC_SCU_IRQCTRL_MATH_SR0_OR_CAN0_SR3_IRQ7 = (7U << 8U) | 3U, /**< MATH_SR0 and CAN0_SR3 connected to IRQ7 */
466 #endif
467
468 #if defined(LEDTS2)
469 XMC_SCU_IRQCTRL_LEDTS2_SR0_IRQ8 = (8U << 8U) | 0U, /**< LEDTS2_SR0 connected to IRQ8 */
470 #endif
471 XMC_SCU_IRQCTRL_CCU40_SR0_IRQ8 = (8U << 8U) | 1U, /**< CCU40_SR0 connected to IRQ8 */
472 #if defined(CCU80)
473 XMC_SCU_IRQCTRL_CCU80_SR0_IRQ8 = (8U << 8U) | 2U, /**< CCU80_SR0 connected to IRQ8 */
474 #endif
475 #if defined(LEDTS2)
476 XMC_SCU_IRQCTRL_LEDTS2_SR0_OR_CCU40_SR0_IRQ8 = (8U << 8U) | 3U, /**< LEDTS2_SR0 and CCU40_SR0 connected to IRQ8 */
477 #endif
478
479 XMC_SCU_IRQCTRL_USIC0_SR0_IRQ9 = (9U << 8U) | 0U, /**< USIC0_SR0 connected to IRQ9 */
480 #if defined(USIC1)
481 XMC_SCU_IRQCTRL_USIC1_SR0_IRQ9 = (9U << 8U) | 1U, /**< USIC1_SR0 connected to IRQ9 */
482 #endif
483 XMC_SCU_IRQCTRL_ERU0_SR0_IRQ9 = (9U << 8U) | 2U, /**< ERU0_SR0 connected to IRQ9 */
484 #if defined(USIC1)
485 XMC_SCU_IRQCTRL_USIC0_SR0_OR_USIC1_SR0_IRQ9 = (9U << 8U) | 3U, /**< USIC0_SR0 and USIC1_SR0 connected to IRQ9 */
486 #endif
487
488 XMC_SCU_IRQCTRL_USIC0_SR1_IRQ10 = (10U << 8U) | 0U, /**< USIC0_SR1 connected to IRQ10 */
489 #if defined(USIC1)
490 XMC_SCU_IRQCTRL_USIC1_SR1_IRQ10 = (10U << 8U) | 1U, /**< USIC1_SR1 connected to IRQ10 */
491 #endif
492 XMC_SCU_IRQCTRL_ERU0_SR1_IRQ10 = (10U << 8U) | 2U, /**< ERU0_SR1 connected to IRQ10 */
493 #if defined(USIC1)
494 XMC_SCU_IRQCTRL_USIC0_SR1_OR_USIC1_SR1_IRQ10 = (10U << 8U) | 3U, /**< USIC0_SR1 and USIC1_SR1 connected to IRQ10 */
495 #endif
496
497 XMC_SCU_IRQCTRL_USIC0_SR2_IRQ11 = (11U << 8U) | 0U, /**< USIC0_SR2 connected to IRQ11 */
498 #if defined(USIC1)
499 XMC_SCU_IRQCTRL_USIC1_SR2_IRQ11 = (11U << 8U) | 1U, /**< USIC1_SR2 connected to IRQ11 */
500 #endif
501 XMC_SCU_IRQCTRL_ERU0_SR2_IRQ11 = (11U << 8U) | 2U, /**< ERU0_SR2 connected to IRQ11 */
502 #if defined(USIC1)
503 XMC_SCU_IRQCTRL_USIC0_SR2_OR_USIC1_SR2_IRQ11 = (11U << 8U) | 3U, /**< USIC0_SR2 and USIC1_SR2 connected to IRQ11 */
504 #endif
505
506 XMC_SCU_IRQCTRL_USIC0_SR3_IRQ12 = (12U << 8U) | 0U, /**< USIC0_SR3 connected to IRQ12 */
507 #if defined(USIC1)
508 XMC_SCU_IRQCTRL_USIC1_SR3_IRQ12 = (12U << 8U) | 1U, /**< USIC1_SR3 connected to IRQ12 */
509 #endif
510 XMC_SCU_IRQCTRL_ERU0_SR3_IRQ12 = (12U << 8U) | 2U, /**< ERU0_SR3 connected to IRQ12 */
511 #if defined(USIC1)
512 XMC_SCU_IRQCTRL_USIC0_SR3_OR_USIC1_SR3_IRQ12 = (12U << 8U) | 3U, /**< USIC0_SR3 and USIC1_SR3 connected to IRQ12 */
513 #endif
514
515 XMC_SCU_IRQCTRL_USIC0_SR4_IRQ13 = (13U << 8U) | 0U, /**< USIC0_SR4 connected to IRQ13 */
516 #if defined(USIC1)
517 XMC_SCU_IRQCTRL_USIC1_SR4_IRQ13 = (13U << 8U) | 1U, /**< USIC1_SR4 connected to IRQ13 */
518 #endif
519 #if defined(CCU80)
520 XMC_SCU_IRQCTRL_CCU80_SR1_IRQ13 = (13U << 8U) | 2U, /**< CCU80_SR1 connected to IRQ13 */
521 #endif
522 #if defined(USIC1)
523 XMC_SCU_IRQCTRL_USIC0_SR4_OR_USIC1_SR4_IRQ13 = (13U << 8U) | 3U, /**< USIC0_SR4 and USIC1_SR4 connected to IRQ13 */
524 #endif
525
526 XMC_SCU_IRQCTRL_USIC0_SR5_IRQ14 = (14U << 8U) | 0U, /**< USIC0_SR5 connected to IRQ14 */
527 #if defined(USIC1)
528 XMC_SCU_IRQCTRL_USIC1_SR5_IRQ14 = (14U << 8U) | 1U, /**< USIC1_SR5 connected to IRQ14 */
529 #endif
530 #if defined(POSIF0)
531 XMC_SCU_IRQCTRL_POSIF0_SR0_IRQ14 = (14U << 8U) | 2U, /**< POSIF0_SR0 connected to IRQ14 */
532 #endif
533 #if defined(USIC1)
534 XMC_SCU_IRQCTRL_USIC0_SR5_OR_USIC1_SR5_IRQ14 = (14U << 8U) | 3U, /**< USIC0_SR5 and USIC1_SR5 connected to IRQ14 */
535 #endif
536
537 XMC_SCU_IRQCTRL_VADC0_C0SR0_IRQ15 = (15U << 8U) | 0U, /**< VADC0_C0SR0 connected to IRQ15 */
538 XMC_SCU_IRQCTRL_USIC0_SR0_IRQ15 = (15U << 8U) | 1U, /**< USIC0_SR0 connected to IRQ15 */
539 #if defined(POSIF0)
540 XMC_SCU_IRQCTRL_POSIF0_SR1_IRQ15 = (15U << 8U) | 2U, /**< POSIF0_SR1 connected to IRQ15 */
541 #endif
542 XMC_SCU_IRQCTRL_VADC0_C0SR0_OR_USIC0_SR0_IRQ15 = (15U << 8U) | 3U, /**< VADC0_C0SR0 and USIC0_SR0 connected to IRQ15 */
543
544 XMC_SCU_IRQCTRL_VADC0_C0SR1_IRQ16 = (16U << 8U) | 0U, /**< VADC0_C0SR1 connected to IRQ16 */
545 XMC_SCU_IRQCTRL_USIC0_SR1_IRQ16 = (16U << 8U) | 1U, /**< USIC0_SR1 connected to IRQ16 */
546 XMC_SCU_IRQCTRL_CCU40_SR2_IRQ16 = (16U << 8U) | 2U, /**< CCU40_SR2 connected to IRQ16 */
547 XMC_SCU_IRQCTRL_VADC0_C0SR1_OR_USIC0_SR1_IRQ16 = (16U << 8U) | 3U, /**< VADC0_C0SR1 and USIC0_SR1 connected to IRQ16 */
548
549 XMC_SCU_IRQCTRL_VADC0_G0SR0_IRQ17 = (17U << 8U) | 0U, /**< VADC0_G0SR0 connected to IRQ17 */
550 XMC_SCU_IRQCTRL_USIC0_SR2_IRQ17 = (17U << 8U) | 1U, /**< USIC0_SR2 connected to IRQ17 */
551 #if defined(CAN)
552 XMC_SCU_IRQCTRL_CAN0_SR0_IRQ17 = (17U << 8U) | 2U, /**< CAN0_SR0 connected to IRQ17 */
553 #endif
554 XMC_SCU_IRQCTRL_VADC0_G0SR0_OR_USIC0_SR2_IRQ17 = (17U << 8U) | 3U, /**< VADC0_G0SR0 and USIC0_SR2 connected to IRQ17 */
555
556 XMC_SCU_IRQCTRL_VADC0_G0SR1_IRQ18 = (18U << 8U) | 0U, /**< VADC0_G0SR1 connected to IRQ18 */
557 XMC_SCU_IRQCTRL_USIC0_SR3_IRQ18 = (18U << 8U) | 1U, /**< USIC0_SR3 connected to IRQ18 */
558 #if defined(CAN)
559 XMC_SCU_IRQCTRL_CAN0_SR1_IRQ18 = (18U << 8U) | 2U, /**< CAN0_SR1 connected to IRQ18 */
560 #endif
561 XMC_SCU_IRQCTRL_VADC0_G0SR1_OR_USIC0_SR3_IRQ18 = (18U << 8U) | 3U, /**< VADC0_G0SR1 and USIC0_SR3 connected to IRQ18 */
562
563 XMC_SCU_IRQCTRL_VADC0_G1SR0_IRQ19 = (19U << 8U) | 0U, /**< VADC0_G1SR0 connected to IRQ19 */
564 XMC_SCU_IRQCTRL_USIC0_SR4_IRQ19 = (19U << 8U) | 1U, /**< USIC0_SR4 connected to IRQ19 */
565 #if defined(CAN)
566 XMC_SCU_IRQCTRL_CAN0_SR2_IRQ19 = (19U << 8U) | 2U, /**< CAN0_SR2 connected to IRQ19 */
567 #endif
568 XMC_SCU_IRQCTRL_VADC0_G1SR0_OR_USIC0_SR4_IRQ19 = (19U << 8U) | 3U, /**< VADC0_G1SR0 and USIC0_SR4 connected to IRQ19 */
569
570 XMC_SCU_IRQCTRL_VADC0_G1SR1_IRQ20 = (20U << 8U) | 0U, /**< VADC0_G1SR1 connected to IRQ20 */
571 XMC_SCU_IRQCTRL_USIC0_SR5_IRQ20 = (20U << 8U) | 1U, /**< USIC0_SR5 connected to IRQ20 */
572 #if defined(CAN)
573 XMC_SCU_IRQCTRL_CAN0_SR4_IRQ20 = (20U << 8U) | 2U, /**< CAN0_SR4 connected to IRQ20 */
574 #endif
575 XMC_SCU_IRQCTRL_VADC0_G1SR1_OR_USIC0_SR5_IRQ20 = (20U << 8U) | 3U, /**< VADC0_G1SR1 and USIC0_SR5 connected to IRQ20 */
576
577 XMC_SCU_IRQCTRL_CCU40_SR0_IRQ21 = (21U << 8U) | 0U, /**< CCU40_SR0 connected to IRQ21 */
578 #if defined(CCU41)
579 XMC_SCU_IRQCTRL_CCU41_SR0_IRQ21 = (21U << 8U) | 1U, /**< CCU41_SR0 connected to IRQ21 */
580 #endif
581 XMC_SCU_IRQCTRL_USIC0_SR0_IRQ21 = (21U << 8U) | 2U, /**< USIC0_SR0 connected to IRQ21 */
582 #if defined(CCU41)
583 XMC_SCU_IRQCTRL_CCU40_SR0_OR_CCU41_SR0_IRQ21 = (21U << 8U) | 3U, /**< CCU40_SR0 and CCU41_SR0 connected to IRQ21 */
584 #endif
585
586 XMC_SCU_IRQCTRL_CCU40_SR1_IRQ22 = (22U << 8U) | 0U, /**< CCU40_SR1 connected to IRQ22 */
587 #if defined(CCU41)
588 XMC_SCU_IRQCTRL_CCU41_SR1_IRQ22 = (22U << 8U) | 1U, /**< CCU41_SR1 connected to IRQ22 */
589 #endif
590 XMC_SCU_IRQCTRL_USIC0_SR1_IRQ22 = (22U << 8U) | 2U, /**< USIC0_SR1 connected to IRQ22 */
591 #if defined(CCU41)
592 XMC_SCU_IRQCTRL_CCU40_SR0_OR_CCU41_SR0_IRQ22 = (22U << 8U) | 3U, /**< CCU40_SR0 and CCU41_SR0 connected to IRQ22 */
593 #endif
594
595 XMC_SCU_IRQCTRL_CCU40_SR2_IRQ23 = (23U << 8U) | 0U, /**< CCU40_SR2 connected to IRQ23 */
596 #if defined(CCU41)
597 XMC_SCU_IRQCTRL_CCU41_SR2_IRQ23 = (23U << 8U) | 1U, /**< CCU41_SR2 connected to IRQ23 */
598 #endif
599 XMC_SCU_IRQCTRL_USIC0_SR2_IRQ23 = (23U << 8U) | 2U, /**< USIC0_SR2 connected to IRQ23 */
600 #if defined(CCU41)
601 XMC_SCU_IRQCTRL_CCU40_SR2_OR_CCU41_SR2_IRQ23 = (23U << 8U) | 3U, /**< CCU40_SR2 and CCU41_SR2 connected to IRQ23 */
602 #endif
603
604 XMC_SCU_IRQCTRL_CCU40_SR3_IRQ24 = (24U << 8U) | 0U, /**< CCU40_SR3 connected to IRQ24 */
605 #if defined(CCU41)
606 XMC_SCU_IRQCTRL_CCU41_SR3_IRQ24 = (24U << 8U) | 1U, /**< CCU41_SR3 connected to IRQ24 */
607 #endif
608 XMC_SCU_IRQCTRL_USIC0_SR3_IRQ24 = (24U << 8U) | 2U, /**< USIC0_SR3 connected to IRQ24 */
609 #if defined(CCU41)
610 XMC_SCU_IRQCTRL_CCU40_SR3_OR_CCU41_SR3_IRQ24 = (24U << 8U) | 3U, /**< CCU40_SR3 and CCU41_SR3 connected to IRQ24 */
611 #endif
612
613 #if defined(CCU80)
614 XMC_SCU_IRQCTRL_CCU80_SR0_IRQ25 = (25U << 8U) | 0U, /**< CCU80_SR0 connected to IRQ25 */
615 #endif
616 #if defined(CCU81)
617 XMC_SCU_IRQCTRL_CCU81_SR0_IRQ25 = (25U << 8U) | 1U, /**< CCU81_SR0 connected to IRQ25 */
618 #endif
619 XMC_SCU_IRQCTRL_USIC0_SR4_IRQ25 = (25U << 8U) | 2U, /**< USIC0_SR4 connected to IRQ25 */
620 #if defined(CCU80) && defined(CCU81)
621 XMC_SCU_IRQCTRL_CCU80_SR0_OR_CCU81_SR0_IRQ25 = (25U << 8U) | 3U, /**< CCU80_SR0 and CCU81_SR0 connected to IRQ25 */
622 #endif
623
624 #if defined(CCU80)
625 XMC_SCU_IRQCTRL_CCU80_SR1_IRQ26 = (26U << 8U) | 0U, /**< CCU80_SR1 connected to IRQ26 */
626 #endif
627 #if defined(CCU81)
628 XMC_SCU_IRQCTRL_CCU81_SR1_IRQ26 = (26U << 8U) | 1U, /**< CCU81_SR1 connected to IRQ26 */
629 #endif
630 XMC_SCU_IRQCTRL_USIC0_SR5_IRQ26 = (26U << 8U) | 2U, /**< USIC0_SR5 connected to IRQ26 */
631 #if defined(CCU80) && defined(CCU81)
632 XMC_SCU_IRQCTRL_CCU80_SR1_OR_CCU81_SR1_IRQ26 = (26U << 8U) | 3U, /**< CCU80_SR1 and CCU81_SR1 connected to IRQ26 */
633 #endif
634
635 #if defined(POSIF0)
636 XMC_SCU_IRQCTRL_POSIF0_SR0_IRQ27 = (27U << 8U) | 0U, /**< POSIF0_SR0 connected to IRQ27 */
637 #endif
638 #if defined(POSIF1)
639 XMC_SCU_IRQCTRL_POSIF1_SR0_IRQ27 = (27U << 8U) | 1U, /**< POSIF1_SR0 connected to IRQ27 */
640 #endif
641 XMC_SCU_IRQCTRL_CCU40_SR3_IRQ27 = (27U << 8U) | 2U, /**< CCU40_SR3 connected to IRQ27 */
642 #if defined(POSIF0) && defined(POSIF1)
643 XMC_SCU_IRQCTRL_POSIF0_SR0_OR_POSIF1_SR0_IRQ27 = (27U << 8U) | 3U, /**< POSIF0_SR0 and POSIF1_SR0 connected to IRQ27 */
644 #endif
645
646 #if defined(POSIF0)
647 XMC_SCU_IRQCTRL_POSIF0_SR1_IRQ28 = (28U << 8U) | 0U, /**< POSIF0_SR1 connected to IRQ28 */
648 #endif
649 #if defined(POSIF1)
650 XMC_SCU_IRQCTRL_POSIF1_SR1_IRQ28 = (28U << 8U) | 1U, /**< POSIF1_SR1 connected to IRQ28 */
651 #endif
652 XMC_SCU_IRQCTRL_ERU0_SR0_IRQ28 = (28U << 8U) | 2U, /**< ERU0_SR0 connected to IRQ28 */
653 #if defined(POSIF0) && defined(POSIF1)
654 XMC_SCU_IRQCTRL_POSIF0_SR1_OR_POSIF1_SR1_IRQ28 = (28U << 8U) | 3U, /**< POSIF0_SR1 and POSIF1_SR1 connected to IRQ28 */
655 #endif
656
657 #if defined(LEDTS0)
658 XMC_SCU_IRQCTRL_LEDTS0_SR0_IRQ29 = (29U << 8U) | 0U, /**< LEDTS0_SR0 connected to IRQ29 */
659 #endif
660 XMC_SCU_IRQCTRL_CCU40_SR1_IRQ29 = (29U << 8U) | 1U, /**< CCU40_SR1 connected to IRQ29 */
661 XMC_SCU_IRQCTRL_ERU0_SR1_IRQ29 = (29U << 8U) | 2U, /**< ERU0_SR1 connected to IRQ29 */
662 #if defined(LEDTS0)
663 XMC_SCU_IRQCTRL_LEDTS0_SR0_OR_CCU40_SR1_IRQ29 = (29U << 8U) | 3U, /**< LEDTS0_SR0 and CCU40_SR1 connected to IRQ29 */
664 #endif
665
666 #if defined(LEDTS1)
667 XMC_SCU_IRQCTRL_LEDTS1_SR0_IRQ30 = (30U << 8U) | 0U, /**< LEDTS1_SR0 connected to IRQ30 */
668 #endif
669 XMC_SCU_IRQCTRL_CCU40_SR2_IRQ30 = (30U << 8U) | 1U, /**< CCU40_SR2 connected to IRQ30 */
670 XMC_SCU_IRQCTRL_ERU0_SR2_IRQ30 = (30U << 8U) | 2U, /**< ERU0_SR2 connected to IRQ30 */
671 #if defined(LEDTS1)
672 XMC_SCU_IRQCTRL_LEDTS0_SR0_OR_CCU40_SR1_IRQ30 = (30U << 8U) | 3U, /**< LEDTS0_SR0 and CCU40_SR1 connected to IRQ30 */
673 #endif
674
675 #if defined(BCCU0)
676 XMC_SCU_IRQCTRL_BCCU0_SR0_IRQ31 = (31U << 8U) | 0U, /**< BCCU0_SR0 connected to IRQ31 */
677 #endif
678 XMC_SCU_IRQCTRL_CCU40_SR3_IRQ31 = (31U << 8U) | 1U, /**< CCU40_SR3 connected to IRQ31 */
679 XMC_SCU_IRQCTRL_ERU0_SR3_IRQ31 = (31U << 8U) | 2U, /**< ERU0_SR3 connected to IRQ31 */
680 #if defined(BCCU0)
681 XMC_SCU_IRQCTRL_BCCU0_SR0_OR_CCU40_SR3_IRQ31 = (31U << 8U) | 3U, /**< BCCU0_SR0 and CCU40_SR3 connected to IRQ31 */
682 #endif
683 } XMC_SCU_IRQCTRL_t;
684 #endif /* XMC_SERIES = XMC14 */
685
686 /** TODO
687 *
688 */
689 typedef enum XMC_SCU_POWER_MONITOR_RANGE
690 {
691 XMC_SCU_POWER_MONITOR_RANGE_2_25V = 0U << SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos, /**< */
692 XMC_SCU_POWER_MONITOR_RANGE_3_00V = 1U << SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos, /**< */
693 XMC_SCU_POWER_MONITOR_RANGE_4_40V = 2U << SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos /**< */
694 } XMC_SCU_POWER_MONITOR_RANGE_t;
695
696 /** TODO
697 *
698 */
699 typedef enum XMC_SCU_POWER_MONITOR_DELAY
700 {
701 XMC_SCU_POWER_MONITOR_DELAY_1US = 0U << SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos, /**< */
702 XMC_SCU_POWER_MONITOR_DELAY_500NS = 1U << SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos, /**< */
703 XMC_SCU_POWER_MONITOR_DELAY_250NS = 2U << SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos, /**< */
704 XMC_SCU_POWER_MONITOR_DELAY_NONE = 3U << SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos /**< */
705 } XMC_SCU_POWER_MONITOR_DELAY_t;
706
707 /*********************************************************************************************************************
708 * DATA STRUCTURES
709 ********************************************************************************************************************/
710 /**
711 * Defines a data structure for initializing the data of the supply voltage monitoring block.
712 * Supply voltage monitoring block consists of 2 detectors namely External voltage detector (VDEL) and External brownout
713 * detector (BDE) in the EVR that are used to monitor the VDDP. \a VDEL detector compares the supply voltage against a
714 * pre-warning threshold voltage.
715 * Use type \a XMC_SCU_SUPPLYMONITOR_t for accessing these structure parameters.
716 */
717 typedef struct XMC_SCU_SUPPLYMONITOR
718 {
719 uint32_t ext_supply_threshold; /**< External supply range (VDEL Range Select).\n
720 \b Range:
721 <ul>
722 <li>00B sets threshold value to 2.25V
723 <li>01B sets threshold value to 3.0V
724 <li>10B sets threshold value to 4.4V
725 </ul>*/
726 uint32_t ext_supply_monitor_speed; /**< Speed of the voltage monitor(VDEL Timing Setting).\n
727 \b Range:
728 <ul>
729 <li>00B sets monitor speed typ 1us - slowest response time
730 <li>01B sets monitor speed typ 500n
731 <li>10B sets monitor speed typ 250n
732 <li>11B sets monitor speed with no delay - fastest response time.
733 </ul>*/
734 bool enable_prewarning_int; /**< Configure pre-warning interrupt generation.\n
735 \b Range:
736 <ul>
737 <li>\a true to enable the interrupt.
738 <li>\a false to disable the interrupt.
739 </ul>*/
740 bool enable_vdrop_int; /**< Configure VDROP interrupt generation.\n
741 \b Range:
742 <ul>
743 <li>\a true to enable the interrupt.
744 <li>\a false to disable the interrupt.
745 </ul>*/
746 bool enable_vclip_int; /**< Configure VCLIP interrupt.\n
747 \b Range:
748 <ul>
749 <li>\a true to enable the interrupt.
750 <li>\a false to disable the interrupt.
751 </ul>*/
752 bool enable_at_init; /**< Whether the monitor has to be enabled (VDEL unit Enable) after initialization.\n
753 \b Range:
754 <ul>
755 <li>\a true to enable after initialization.
756 <li>\a false to enable after initialization.
757 </ul>*/
758 } XMC_SCU_SUPPLYMONITOR_t;
759
760 /**
761 * Defines a data structure for initializing the data of the clock functional block.
762 * Clock functional block configures clock dividers, peripheral and RTC clock source by configuring corresponding
763 * bits in \a CLKCR clock control register.
764 * Use type \a XMC_SCU_CLOCK_CONFIG_t for accessing these structure parameters.
765 */
766 typedef struct XMC_SCU_CLOCK_CONFIG
767 {
768 #if (UC_SERIES == XMC14)
769 uint16_t fdiv; /**< Fractional clock divider (FDIV). \b Range: 0 to 1023. */
770 #else
771 uint8_t fdiv; /**< Fractional clock divider (FDIV). \b Range: 0 to 255. @note XMC1400 series extends the range to 1023 */
772 #endif
773 uint8_t idiv; /**< Integer clock divider (IDIV). \b Range: 0 to 255. */
774 #if (UC_SERIES == XMC14) || defined(DOXYGEN)
775 XMC_SCU_CLOCK_DCLKSRC_t dclk_src; /**< DCLK clock source selection. @note Only available in XMC1400 series */
776 XMC_SCU_CLOCK_OSCHP_MODE_t oschp_mode; /**< OSCHP mode. @note Only available in XMC1400 series */
777 XMC_SCU_CLOCK_OSCLP_MODE_t osclp_mode; /**< OSCLP mode. @note Only available in XMC1400 series */
778 #endif
779 XMC_SCU_CLOCK_PCLKSRC_t pclk_src; /**< Source of PCLK Clock */
780 XMC_SCU_CLOCK_RTCCLKSRC_t rtc_src; /**< Source of RTC Clock */
781 } XMC_SCU_CLOCK_CONFIG_t;
782
783
784 /*********************************************************************************************************************
785 * API PROTOTYPES
786 ********************************************************************************************************************/
787
788 #ifdef __cplusplus
789 extern "C" {
790 #endif
791
792 /**
793 *
794 * @param freq_khz Required MCLK frequency value in kHz.\n
795 * \b Range: XMC11/XMC12/XMC13 Device: 125 to 32000.
796 * XMC14 Device: 188 to 48000 when DCO1 is clock source for clock control unit.
797 * 79 to 48000 when OSC_HP is clock source for clock control unit.\n
798 *
799 * @return None
800 *
801 * \par<b>Description</b><br>
802 * This API configures main clock (MCLK) frequency to requested frequency value.\n\n
803 * The API configures main clock by setting \a IDIV and \a FDIV bit's of the \a CLKCR register for
804 * XMC11/XMC12/XMC13/XMC14 Device and with additional \a FDIV bit (FDIV[9:8]) of the \a CLKCR1 register settings
805 * for XMC14 device.
806 * \par<b>Related APIs:</b><BR>
807 * XMC_SCU_CLOCK_ScaleMCLKFrequency()\n\n\n
808 */
809 void XMC_SCU_CLOCK_SetMCLKFrequency(uint32_t freq_khz);
810
811 /**
812 *
813 * @param idiv Divider value.\n
814 * \b Range: 0 to 255.\n
815 * @param fdiv Fractional Divider value.\n
816 * \b Range: XMC11/XMC12/XMC13 Device: 0 to 255.
817 * XMC14 Device: 0 to 1023.\n
818 *
819 * @return None
820 *
821 * \par<b>Description</b><br>
822 * This API configures main clock (MCLK) frequency by updating user provided divider values.\n\n
823 * The API configures main clock by setting \a IDIV and \a FDIV bit's of the \a CLKCR register for
824 * XMC11/XMC12/XMC13/XMC14 Device and with additional \a FDIV bit (FDIV[9:8]) of the \a CLKCR1 register settings
825 * for XMC14 device.
826 * \par<b>Related APIs:</b><BR>
827 * XMC_SCU_CLOCK_SetMCLKFrequency()\n\n\n
828 */
829 void XMC_SCU_CLOCK_ScaleMCLKFrequency(uint32_t idiv, uint32_t fdiv);
830
831 /**
832 *
833 * @return None
834 *
835 * \par<b>Description</b><br>
836 * Locks access to protected bit fields of the SCU.\n\n
837 * The bit protection scheme prevents changing selected register bits by unauthorized code.
838 * Bit protection scheme is enabled by writing 000000C3H to \a PASSWD register. By writing
839 * this value, the API is setting the \a MODE bit field to bit protection enabled state.\n
840 * List of Protected Register Bit Fields are mentioned below. \n
841 * <table>
842 * <tr><td> \a Register </td> <td>\a Bit fields </td></tr>
843 * <tr><td> SCU_CLKCR </td> <td> FDIV, IDIV, PCLKSEL, RTCLKSEL </td></tr>
844 * <tr><td> SCU_CGATSET0 </td> <td> All bits </td></tr>
845 * <tr><td> SCU_CGATCLR0 </td> <td> All bits </td></tr>
846 * <tr><td> SCU_ANAOFFSET </td> <td> ADJL_OFFSET </td></tr>
847 * <tr><td> VADC0_ACCPROT0 </td> <td> All bits </td></tr>
848 * <tr><td> VADC0_ACCPROT1 </td> <td> All bits </td></tr>
849 * </table>
850 *
851 * \par<b>Related APIs:</b><BR>
852 * XMC_SCU_UnlockProtectedBits() \n\n\n
853 */
854 void XMC_SCU_LockProtectedBits(void);
855
856 /**
857 *
858 * @return None
859 *
860 * \par<b>Description</b><br>
861 * Unlocks access to protected bit fields of the SCU.\n\n
862 * The bit protection scheme prevents changing selected register bits by unauthorized code.
863 * Bit protection scheme can be temporarily(for 32 MCLK cycles) disabled by writing 000000C0H to \a PASSWD register.
864 * By writing this value, the API is setting the \a MODE bit field to bit protection disabled state. The API
865 * waits for the protection to be disabled after changing the \a MODE.\n
866 * User can change the values of the protected bit fields within 32 MCLK cycles. After 32 MCLK cycles the lock will
867 * be enabled automatically.
868 * List of Protected Register Bit Fields are mentioned below. \n
869 * <table>
870 * <tr><td> \a Register </td> <td>\a Bit fields </td></tr>
871 * <tr><td> SCU_CLKCR </td> <td> FDIV, IDIV, PCLKSEL, RTCLKSEL </td></tr>
872 * <tr><td> SCU_CGATSET0 </td> <td> All bits </td></tr>
873 * <tr><td> SCU_CGATCLR0 </td> <td> All bits </td></tr>
874 * <tr><td> SCU_ANAOFFSET </td> <td> ADJL_OFFSET </td></tr>
875 * <tr><td> VADC0_ACCPROT0 </td> <td> All bits </td></tr>
876 * <tr><td> VADC0_ACCPROT1 </td> <td> All bits </td></tr>
877 * </table>
878 *
879 * \par<b>Related APIs:</b><BR>
880 * XMC_SCU_LockProtectedBits() \n\n\n
881 */
882 void XMC_SCU_UnlockProtectedBits(void);
883
884 /**
885 *
886 * @param obj Pointer to data structure consisting voltage monitoring block configuration.\n
887 * \b Range: Use type @ref XMC_SCU_SUPPLYMONITOR_t for detailed description of structure members.
888 *
889 * @return None
890 *
891 * \par<b>Description</b><br>
892 * Initializes power supply monitoring unit.\n\n
893 * Supply voltage monitoring block consist of 2 detectors namely External voltage detector (VDEL) and External brownout
894 * detector (BDE) in the EVR that are used to monitor the VDDP. \a VDEL detector compares the supply voltage against a
895 * pre-warning threshold voltage \a ext_supply_threshold. The threshold level is programmable via register \a ANAVDEL.VDEL_SELECT. An interrupt
896 * if enabled via \a enable_prewarning_int, will be triggered if a level below this threshold is detected and the flag, VDDPI,
897 * in SRRAW register bit is set. Similarly interrupts can be enabled for the events of VCLIP and prewarning, using the structure members,
898 * \a enable_vclip_int and \a enable_prewarning_int. The handlers for these interrupts have to be explicitly defined using
899 * the API XMC_SCU_INTERRUPT_SetEventHandler().
900 * \par<b>Related APIs:</b><BR>
901 * XMC_SCU_INTERRUPT_SetEventHandler()\n\n\n
902 */
903 void XMC_SCU_SupplyMonitorInit(const XMC_SCU_SUPPLYMONITOR_t *obj);
904
905 /**
906 * @param limit Kelvin degree temperature lower compare limit in range [233,388]
907 * @return XMC_SCU_STATUS_t status of limit installation
908 *
909 * \par<b>Description</b><br>
910 * Set lower temperature compare limit.
911 * A low temperature interrupt (SCU_IRQ1) is triggered if Tchip < limit and the event and interrupt are enabled.
912 * Alternatively XMC_SCU_LowTemperature() can be used to check the status.
913 * \par<b>Related APIs:</b><BR>
914 * XMC_SCU_LowTemperature()\n\n\n
915 *
916 **/
917 XMC_SCU_STATUS_t XMC_SCU_SetTempLowLimit(uint32_t limit);
918
919 /**
920 * @param limit Kelvin degree temperature higher compare limit in range [233,388]
921 * @return XMC_SCU_STATUS_t status of limit installation
922 *
923 * \par<b>Description</b><br>
924 * Set higher temperature compare limit.
925 * A high temperature interrupt (SCU_IRQ1) is triggered if Tchip > limit and the event and interrupt are enabled.
926 * Alternatively XMC_SCU_HighTemperature() can be used to check the status.
927 * \par<b>Related APIs:</b><BR>
928 * XMC_SCU_HighTemperature()\n\n\n
929 *
930 **/
931 XMC_SCU_STATUS_t XMC_SCU_SetTempHighLimit(uint32_t limit);
932
933 /**
934 *
935 * @param lower_temp Lower threshold value for the die temperature.\n
936 * \b Range: 0 to 65535(16 bit unsigned value).
937 * @param upper_temp Upper threshold value for the die temperature.\n
938 * \b Range: 0 to 65535(16 bit unsigned value).
939 *
940 * @return None
941 *
942 * \par<b>Description</b><br>
943 * Configures upper and lower thresholds of die temperature as raw digital values into temperature sensor.\n\n
944 * The API configures \a ANATSEIH and \a ANATSEIL registers for upper and lower die temperature threshold limits
945 * respectively.\n
946 * It is recommended to use following steps:\n
947 * - Call \a XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.\n
948 * - Call \a XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values.\n
949 * - Finally call \a XMC_SCU_StartTempMeasurement to start temperature measurement.\n
950 *
951 * \par<b>Related APIs:</b><BR>
952 * XMC_SCU_StopTempMeasurement(), XMC_SCU_StartTempMeasurement() \n\n\n
953 */
954 void XMC_SCU_SetRawTempLimits(const uint32_t lower_temp, const uint32_t upper_temp);
955
956 // /* API to program temperature limits in centigrade into temperature sensor unit */ // need to implement in future
957 // void XMC_SCU_SetTempLimits(const uint32_t lower_temp, const uint32_t upper_temp);
958 /**
959 *
960 * @return XMC_SCU_STATUS_t Status of starting the temperature measurement.\n
961 * \b Range: Use type @ref XMC_SCU_STATUS_t to identify the result.\n
962 * XMC_SCU_STATUS_OK- Temperature measurement started successfully.\n
963 * Always returns the above status.
964 *
965 * \par<b>Description</b><br>
966 * Starts die temperature measurement using internal temperature sensor.\n\n
967 * The API, enables die temperature measurement and waits for about 10000 cycles until
968 * temperature measurement result is available on \a SCU_ANALOG->ANATSEMON bit fields.\n
969 * It is recommended to use following steps:\n
970 * - Call \a XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.\n
971 * - Call \a XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values if it is needed.\n
972 * - Call \a XMC_SCU_StartTempMeasurement to start temperature measurement.\n
973 * - Read die temperature value using \a XMC_SCU_GetTemperature API.\n
974 * \par<b>Related APIs:</b><BR>
975 * XMC_SCU_StopTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_GetTemperature() \n\n\n
976 */
977 void XMC_SCU_StartTempMeasurement(void);
978
979 /**
980 * @return None
981 *
982 * \par<b>Description</b><br>
983 * Stops the die temperature measurement.\n\n
984 * Die temperature measurement is stopped by disabling the sensor using \a TSE_EN bit of
985 * \a ANATSECTRL register.
986 * \par<b>Related APIs:</b><BR>
987 * XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_GetTemperature() \n\n\n
988 */
989 void XMC_SCU_StopTempMeasurement(void);
990
991 /**
992 *
993 * @return bool Result of checking whether the die temperature is more than the upper threshold.\n
994 * \b Range: \a false if temperature is below the upper threshold. \a true if temperature
995 * has exceeded the upper threshold configured in \a ANATSEIH register.
996 *
997 * \par<b>Description</b><br>
998 * Check if the temperature has exceeded the upper threshold value.\n\n
999 * The API checks for \a TSE_HIGH bit (TSE Compare High Temperature Event Status bit) of \a SRRAW register.
1000 * The bit will be set when the \a TSE_MON value in \a ANATSEMON register exceeds the value of
1001 * \a TSE_IH value in \a ANATSEIH register.
1002 * \par<b>Related APIs:</b><BR>
1003 * XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_GetTemperature(), XMC_SCU_LowTemperature() \n\n\n
1004 */
1005 bool XMC_SCU_HighTemperature(void);
1006
1007 /**
1008 *
1009 * @return bool Result of checking whether the die temperature is less than the lower threshold.\n
1010 * \b Range: \a false if temperature is higher than the lower threshold. \a true if temperature
1011 * has dropped below the lower threshold configured in \a ANATSEIL register.
1012 *
1013 * \par<b>Description</b><br>
1014 * Check if the temperature has dropped below the lower threshold value.\n\n
1015 * The API checks for \a TSE_LOW bit (TSE Compare Low Temperature Event Status bit) of \a SRRAW register.
1016 * The bit will be set when the \a TSE_MON value in \a ANATSEMON register drops below the value of
1017 * \a TSE_IL value in \a ANATSEIL register.
1018 * \par<b>Related APIs:</b><BR>
1019 * XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits(), XMC_SCU_GetTemperature(), XMC_SCU_HighTemperature() \n\n\n
1020 */
1021 bool XMC_SCU_LowTemperature(void);
1022
1023 /**
1024 * @return uint32_t Raw die temperature value. \b Range: 16 bit value.
1025 *
1026 * \par<b>Description</b><br>
1027 * Provides the raw die temperature value.\n\n
1028 * The API reads temperature measurement result from \a SCU_ANALOG->ANATSEMON bit fields.
1029 * \par<b>Related APIs:</b><BR>
1030 * XMC_SCU_StartTempMeasurement() \n\n\n
1031 */
1032 uint32_t XMC_SCU_GetTemperature(void);
1033
1034 /**
1035 * @return uint32_t Calculate die temperature value. \b Range: 16 bit value.
1036 *
1037 * \par<b>Description</b><br>
1038 * Calculates the die temperature value using ROM function.\n\n
1039 * \par<b>Related APIs:</b><BR>
1040 * XMC_SCU_StartTempMeasurement() \n\n\n
1041 */
1042 uint32_t XMC_SCU_CalcTemperature(void);
1043
1044 /**
1045 *
1046 * @return true DTS Measurement Done
1047 * @return false DTS Measurement not Done
1048 *
1049 * \par<b>Description</b><br>
1050 * This functions checks the status of the DTS Measurement completion.\n\n
1051 * \par<b>Related APIs:</b><BR>
1052 * XMC_SCU_StartTempMeasurement() \n\n\n
1053 */
XMC_SCU_IsTempMeasurementDone(void)1054 __STATIC_INLINE bool XMC_SCU_IsTempMeasurementDone(void)
1055 {
1056 return ((SCU_INTERRUPT->SRRAW & SCU_INTERRUPT_SRRAW_TSE_DONE_Msk) != 0U);
1057 }
1058
1059 /**
1060 * @return None
1061 *
1062 * \par<b>Description</b><br>
1063 * Trigger device master reset.\n\n
1064 * The API triggers master reset by setting the \a MRSTEN bit of \a RSTCON register.
1065 * It also internally triggers system reset. Almost all the logics of the device are affected by this reset.
1066 * \par<b>Related APIs:</b><BR>
1067 * XMC_SCU_RESET_EnableResetRequest() \n\n\n
1068 */
XMC_SCU_RESET_AssertMasterReset(void)1069 __STATIC_INLINE void XMC_SCU_RESET_AssertMasterReset(void)
1070 {
1071 SCU_RESET->RSTCON |= SCU_RESET_RSTCON_MRSTEN_Msk;
1072 }
1073 /**
1074 *
1075 * @param request Reset source to trigger the device reset.\n
1076 * \b Range: Use type @ref XMC_SCU_SYSTEM_RESET_REQUEST_t to identify the reset source.\n
1077 * XMC_SCU_RESET_REQUEST_FLASH_ECC_ERROR- Reset when flash memory double bit error is detected.\n
1078 * XMC_SCU_RESET_REQUEST_CLOCK_LOSS- Reset when loss of clock is detected.\n
1079 * XMC_SCU_RESET_REQUEST_SRAM_PARITY_ERROR- Reset when SRAM parity error is detected.\n
1080 * XMC_SCU_RESET_REQUEST_USIC_SRAM_PARITY_ERROR- Reset when USIC0 SRAM parity error is detected.\n
1081 *
1082 * @return None
1083 *
1084 * \par<b>Description</b><br>
1085 * Configures trigger for system reset from the selected source.\n\n
1086 * The API configures the reset source specific bit in the \a RSTCON register.
1087 * Multiple reset sources can be combined using \a OR operation. By enabling
1088 * the reset using this API will not trigger the reset. The reset will happen when
1089 * the configured source event is detected.
1090 * \par<b>Related APIs:</b><BR>
1091 * XMC_SCU_RESET_AssertMasterReset() \n\n\n
1092 */
XMC_SCU_RESET_EnableResetRequest(uint32_t request)1093 __STATIC_INLINE void XMC_SCU_RESET_EnableResetRequest(uint32_t request)
1094 {
1095 SCU_RESET->RSTCON |= request;
1096 }
1097
1098 /**
1099 *
1100 * @return uint32_t Fast peripheral clock frequency in Hertz.
1101 *
1102 * \par<b>Description</b><br>
1103 * Provides the clock frequency of peripherals on the peripheral bus that are using a shared functional clock.\n\n
1104 * The value is derived using the bitfield \a PCLKSEL from \a CLKCR register. Peripheral clock
1105 * can have 2 times the frequency of system clock if the \a PCLKSEL is set.
1106 * \par<b>Related APIs:</b><BR>
1107 * XMC_SCU_CLOCK_SetFastPeripheralClockSource() \n\n\n
1108 */
1109 uint32_t XMC_SCU_CLOCK_GetFastPeripheralClockFrequency(void);
1110
1111 /**
1112 *
1113 * @param source Fast peripheral clock source.\n
1114 * \b Range: Use type @ref XMC_SCU_CLOCK_PCLKSRC_t to identify the clock source.\n
1115 * XMC_SCU_CLOCK_PCLKSRC_MCLK- Use MCLK as the peripheral clock.\n
1116 * XMC_SCU_CLOCK_PCLKSRC_DOUBLE_MCLK- peripheral clock will be 2 times the MCLK frequency.
1117 *
1118 * @return None
1119 *
1120 * \par<b>Description</b><br>
1121 * Configures the source of peripheral clock. \n\n
1122 * The peripheral clock can be either same as MCLK or twice the frequency of MCLK.
1123 * \par<b>Related APIs:</b><BR>
1124 * XMC_SCU_CLOCK_GetFastPeripheralClockFrequency() \n\n\n
1125 */
1126 void XMC_SCU_CLOCK_SetFastPeripheralClockSource(const XMC_SCU_CLOCK_PCLKSRC_t source);
1127
1128 /**
1129 *
1130 * @param temperature measured temperature using the on-chip temperature sensor
1131 *
1132 * @return None
1133 *
1134 * \par<b>Description</b><br>
1135 * DCO1 clock frequency can be calibrated during runtime to achieve a better accuracy.
1136 * This function start the DCO1 calibration based on temperature.
1137 *
1138 */
1139 void XMC_SCU_CLOCK_CalibrateOscillatorOnTemperature(int32_t temperature);
1140
1141 #if (UC_SERIES == XMC14) || defined(DOXYGEN)
1142 /**
1143 *
1144 * @param sync_clk Clock source selected as external reference. @ref XMC_SCU_CLOCK_SYNC_CLKSRC_t
1145 * @param prescaler integer(\f$\frac{syn_preload \times f_{OSC}[MHz]}{48}\f$)
1146 * @param syn_preload max. value 0x1FFF integer(\f$\frac{48 \times prescaler}{f_{OSC}[MHz]}\f$)
1147 *
1148 * @return None
1149 *
1150 * \par<b>Description</b><br>
1151 * DCO1 clock frequency can be calibrated during runtime to achieve a better accuracy.
1152 * This function starts the automatic DCO1 calibration based on the selected clock source.
1153 * @note Only available for XMC1400 series
1154 */
1155 void XMC_SCU_CLOCK_EnableDCO1ExtRefCalibration(XMC_SCU_CLOCK_SYNC_CLKSRC_t sync_clk, uint32_t prescaler, uint32_t syn_preload);
1156
1157 /**
1158 *
1159 * @return None
1160 *
1161 * \par<b>Description</b><br>
1162 * This function stops the automatic DCO1 calibration based on the selected clock source.
1163 * @note Only available for XMC1400 series
1164 */
1165 void XMC_SCU_CLOCK_DisableDCO1ExtRefCalibration(void);
1166
1167 /**
1168 *
1169 * @return true DCO1 is synchronized to the selected XTAL frequency
1170 * @return false Actual DCO1 frequency is out of target
1171 *
1172 * \par<b>Description</b><br>
1173 * This functions checks the status of the synchronisation
1174 * @note Only available for XMC1400 series
1175 */
1176 bool XMC_SCU_CLOCK_IsDCO1ExtRefCalibrationReady(void);
1177
1178 /**
1179 * @param mode Oscillator mode. @ref XMC_SCU_CLOCK_OSCHP_MODE_t
1180 * @return None
1181 *
1182 * \par<b>Description</b><br>
1183 * Configure functional mode of the OSCHP.
1184 */
1185 void XMC_SCU_CLOCK_SetHighPerformanceOscillatorMode(XMC_SCU_CLOCK_OSCHP_MODE_t mode);
1186
1187 /**
1188 * @param mode Oscillator mode. @ref XMC_SCU_CLOCK_OSCLP_MODE_t
1189 * @return None
1190 *
1191 * \par<b>Description</b><br>
1192 * Configure functional mode of the OSCLP.
1193 */
1194 void XMC_SCU_CLOCK_SetLowPerformanceOscillatorMode(XMC_SCU_CLOCK_OSCLP_MODE_t mode);
1195
1196 /**
1197 * This function selects service request source for a NVIC interrupt node.
1198 * The XMC1400 series has up to 54 peripheral service requests.
1199 * The Cortex M0 however has 32 interrupts available for peripherals.
1200 * This function allows you to select which 32 peripheral requests of the 54 the CPU should react on.
1201 *
1202 * @param irq_number Interrupt number, 0 to 31
1203 * @param source Peripheral service request. See @ref XMC_SCU_IRQCTRL_t
1204 *
1205 * @note Only available for XMC1400 series
1206 */
1207 void XMC_SCU_SetInterruptControl(uint8_t irq_number, XMC_SCU_IRQCTRL_t source);
1208
1209 /**
1210 * This function enables the Prefetch Unit (PFU).
1211 * The purpose of the Prefetch unit is to reduce the Flash latency gap at higher system
1212 * frequencies to increase the instruction per cycle performance.
1213 *
1214 * @note Only available for XMC1400 series
1215 */
XMC_SCU_EnablePrefetchUnit(void)1216 __STATIC_INLINE void XMC_SCU_EnablePrefetchUnit(void)
1217 {
1218 SCU_GENERAL->PFUCR &= ~SCU_GENERAL_PFUCR_PFUBYP_Msk;
1219 }
1220
1221 /**
1222 * This function disables the Prefetch Unit (PFU).
1223 * The purpose of the Prefetch unit is to reduce the Flash latency gap at higher system
1224 * frequencies to increase the instruction per cycle performance.
1225 *
1226 * @note Only available for XMC1400 series
1227 */
XMC_SCU_DisablePrefetchUnit(void)1228 __STATIC_INLINE void XMC_SCU_DisablePrefetchUnit(void)
1229 {
1230 SCU_GENERAL->PFUCR |= SCU_GENERAL_PFUCR_PFUBYP_Msk;
1231 }
1232
1233 #endif
1234
1235 /**
1236 *
1237 * @param range VDEL Range Select ::XMC_SCU_POWER_MONITOR_RANGE_t
1238 * @param delay VDEL Timing Setting ::XMC_SCU_POWER_MONITOR_DELAY_t
1239 * @return None
1240 *
1241 * \par<b>Description</b><br>
1242 * Enables VDEL detector. VDEL detector compares the supply voltage against a pre-warning threshold voltage
1243 *
1244 * @note Brown Out Trap need to be enabled previously
1245 */
XMC_SCU_POWER_EnableMonitor(XMC_SCU_POWER_MONITOR_RANGE_t range,XMC_SCU_POWER_MONITOR_DELAY_t delay)1246 __STATIC_INLINE void XMC_SCU_POWER_EnableMonitor(XMC_SCU_POWER_MONITOR_RANGE_t range, XMC_SCU_POWER_MONITOR_DELAY_t delay)
1247 {
1248 SCU_ANALOG->ANAVDEL = SCU_ANALOG_ANAVDEL_VDEL_EN_Msk |
1249 (uint32_t)range |
1250 (uint32_t)delay;
1251 }
1252
1253 /**
1254 *
1255 * @return None
1256 *
1257 * \par<b>Description</b><br>
1258 * Disables VDEL detector
1259 */
XMC_SCU_POWER_DisableMonitor(void)1260 __STATIC_INLINE void XMC_SCU_POWER_DisableMonitor(void)
1261 {
1262 SCU_ANALOG->ANAVDEL &= ~SCU_ANALOG_ANAVDEL_VDEL_EN_Msk;
1263 }
1264
1265 /**
1266 *
1267 * @param flags may be any of: <br>
1268 * \ref XMC_SCU_BMI_HWCFG_CAN_BSL (only available for XMC1400 series with CAN Module)<br>
1269 * \ref XMC_SCU_BMI_HWCFG_CAN_BSLTO (only available for XMC1400 series with CAN Module)<br>
1270 * \ref XMC_SCU_BMI_HWCFG_SBSL_CANOPEN (only available for XMC1400 series with CAN Module)<br>
1271 * \ref XMC_SCU_BMI_HWCFG_ASC_BSL<br>
1272 * \ref XMC_SCU_BMI_HWCFG_UPM<br>
1273 * \ref XMC_SCU_BMI_HWCFG_UMD<br>
1274 * \ref XMC_SCU_BMI_HWCFG_UMHAR<br>
1275 * \ref XMC_SCU_BMI_HWCFG_SSC_BSL<br>
1276 * \ref XMC_SCU_BMI_HWCFG_ASC_BSLTO<br>
1277 * \ref XMC_SCU_BMI_HWCFG_SSC_BSLTO<br>
1278 * \ref XMC_SCU_BMI_HWCFG_SBSL<br><br>
1279 * optionally OR'd together with any of: <br>
1280 * \ref XMC_SCU_BMI_DAPTYP_SWD<br>
1281 * \ref XMC_SCU_BMI_DAPTYP_SPD<br><br>
1282 * optionally OR'd together with any of: <br>
1283 * \ref XMC_SCU_BMI_DAPDIS_CHANNEL_0<br>
1284 * \ref XMC_SCU_BMI_DAPDIS_CHANNEL_1<br><br>
1285 * @image html "xmc1000_debugif.png"
1286 * optionally OR'd together with any of (only available for XMC1400 series with CAN Module): <br>
1287 * \ref XMC_SCU_BMI_CANCLK_DCO1<br>
1288 * \ref XMC_SCU_BMI_CANCLK_OSCHP<br><br>
1289 *
1290 * @param timeout Only relevant if a start up mode is selected that uses timeout. The time-out duration is BSLTO*2664000 MCLK cycles, the supported time-out range is 0.3-5s (333...4995ms)
1291 * @return false only upon error, if OK the procedure triggers a reset and does not return to calling routine
1292 *
1293 * \par<b>Description</b><br>
1294 * This procedure initiates installation of a new BMI value. In particular, it can be used as
1295 * well as to restore the state upon delivery for a device already in User Productive mode.
1296 *
1297 * @code
1298 * // Switch to ASC Bootstrap Loader
1299 * XMC_SCU_SetBMI(XMC_SCU_BMI_HWCFG_ASC_BSL, 0);
1300 *
1301 * // Switch to Debug user mode SWD1 (pins P1.3 and P1.2)
1302 * XMC_SCU_SetBMI(XMC_SCU_BMI_HWCFG_UMD | XMC_SCU_BMI_DAPTYP_SWD | XMC_SCU_BMI_DAPDIS_CHANNEL_1, 0);
1303 * @endcode
1304 */
1305 uint32_t XMC_SCU_SetBMI(uint32_t flags, uint8_t timeout);
1306
1307 /**
1308 *
1309 * @return uint32_t Current BMI value.
1310 *
1311 * \par<b>Description</b><br>
1312 * This procedure initiates installation of a new BMI value. In particular, it can be used as
1313 * well as to restore the state upon delivery for a device already in User Productive mode.
1314 *
1315 * @code
1316 * // Switch to ASC Bootstrap Loader
1317 * bmi_value = XMC_SCU_GetBMI();
1318 *
1319 * if ((bmi_value & 0x000000ffU) != XMC_SCU_BMI_HWCFG_ASC)
1320 * {
1321 * XMC_SCU_SetBMI(XMC_SCU_BMI_HWCFG_ASC, 0);
1322 * }
1323 *
1324 * @endcode
1325 */
XMC_SCU_GetBMI(void)1326 __STATIC_INLINE uint32_t XMC_SCU_GetBMI(void)
1327 {
1328 return *(volatile uint32_t *)XMC_BMI_ADDR;
1329 }
1330
1331 /*
1332 *
1333 * @return None
1334 *
1335 * \par<b>Description</b><br>
1336 * This function enables flash power down when entering power save mode (SLEEP or DEEPSLEEP modes).
1337 * Upon wake-up, CPU is able to fetch code from flash.
1338 *
1339 * @usage
1340 * @code
1341 *
1342 * // The clock of the peripherals that are not needed during sleep state can be gated before entering sleep state
1343 * XMC_SCU_CLOCK_GatePeripheralClock(SCU_CLK_CGATSTAT0_MATH_Msk);
1344 *
1345 * // Enable FLASH power down during SLEEP and DEEPSLEEP mode
1346 * XMC_SCU_CLOCK_EnableFlashPowerDown();
1347 *
1348 * // Make sure that SLEEPDEEP bit is set
1349 * SCB->SCR |= SCB_SCR_DEEPSLEEP_Msk;
1350 *
1351 * // Return to SLEEP mode after handling the wakeup event
1352 * SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
1353 *
1354 * // Put system in DEEPSLEEP state
1355 * __WFI();
1356 *
1357 * @endcode
1358 *
1359 * \par<b>Related APIs:</b><BR>
1360 * XMC_FLASH_EnterSleepMode()
1361 */
XMC_SCU_CLOCK_EnableFlashPowerDown(void)1362 __STATIC_INLINE void XMC_SCU_CLOCK_EnableFlashPowerDown(void)
1363 {
1364 SCU_CLK->PWRSVCR = SCU_CLK_PWRSVCR_FPD_Msk;
1365 }
1366
1367 /*
1368 *
1369 * @return None
1370 *
1371 * \par<b>Description</b><br>
1372 * This function disables flash power down when entering power save mode (SLEEP or DEEPSLEEP modes).
1373 * \par<b>Related APIs:</b><BR>
1374 * XMC_FLASH_EnterSleepMode()
1375 */
XMC_SCU_CLOCK_DisableFlashPowerDown(void)1376 __STATIC_INLINE void XMC_SCU_CLOCK_DisableFlashPowerDown(void)
1377 {
1378 SCU_CLK->PWRSVCR = 0;
1379 }
1380
1381 /**
1382 *
1383 * @return None
1384 *
1385 * \par<b>Description</b><br>
1386 * This function enables the watchdog on the DCO1 frequency
1387 * @note Only available for XMC1400 series
1388 */
XMC_SCU_CLOCK_EnableDCO1OscillatorWatchdog(void)1389 __STATIC_INLINE void XMC_SCU_CLOCK_EnableDCO1OscillatorWatchdog(void)
1390 {
1391 SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_OWDEN_Msk;
1392 }
1393
1394 /**
1395 *
1396 * @return None
1397 *
1398 * \par<b>Description</b><br>
1399 * This function disables the watchdog on the DCO1 frequency
1400 * @note Only available for XMC1400 series
1401 */
XMC_SCU_CLOCK_DisableDCO1OscillatorWatchdog(void)1402 __STATIC_INLINE void XMC_SCU_CLOCK_DisableDCO1OscillatorWatchdog(void)
1403 {
1404 SCU_CLK->OSCCSR &= ~SCU_CLK_OSCCSR_OWDEN_Msk;
1405 }
1406
1407 /**
1408 *
1409 * @return None
1410 *
1411 * \par<b>Description</b><br>
1412 * This function clears the status of the watchdog on the DCO1 frequency
1413 * @note Only available for XMC1400 series
1414 */
XMC_SCU_CLOCK_ClearDCO1OscillatorWatchdogStatus(void)1415 __STATIC_INLINE void XMC_SCU_CLOCK_ClearDCO1OscillatorWatchdogStatus(void)
1416 {
1417 SCU_CLK->OSCCSR |= SCU_CLK_OSCCSR_OWDRES_Msk;
1418 }
1419
1420 /*
1421 *
1422 * @return true The OSC frequency is usable
1423 * @return false The OSC frequency is not usable. Frequency is too high or too low
1424 *
1425 * \par<b>Description</b><br>
1426 * This function checks if the DCO1 frequency is in the limits of the watchdog
1427 * @note Only available for XMC1400 series
1428 */
XMC_SCU_CLOCK_IsDCO1ClockFrequencyUsable(void)1429 __STATIC_INLINE bool XMC_SCU_CLOCK_IsDCO1ClockFrequencyUsable(void)
1430 {
1431 return ((SCU_CLK->OSCCSR & (SCU_CLK_OSCCSR_OSC2L_Msk | SCU_CLK_OSCCSR_OSC2H_Msk)) == 0U);
1432 }
1433
1434 #ifdef __cplusplus
1435 }
1436 #endif
1437
1438 /**
1439 * @}
1440 */
1441
1442 /**
1443 * @}
1444 */
1445
1446 #endif /* UC_FAMILY == XMC1 */
1447
1448 #endif /* XMC1_SCU_H */
1449
