1 /**
2 * @file xmc_pau.h
3 * @date 2015-06-20
4 *
5 * @cond
6 *********************************************************************************************************************
7 * XMClib v2.1.24 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015-2019, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
22 * products derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
33 * Infineon Technologies AG dave@infineon.com).
34 *********************************************************************************************************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-02-20:
40 * - Initial version
41 *
42 * 2015-05-20:
43 * - Documentation updated
44 *
45 * 2015-06-20:
46 * - Removed version macros and declaration of GetDriverVersion API
47 * @endcond
48 *
49 */
50
51 #ifndef XMC_PAU_H
52 #define XMC_PAU_H
53
54 /*********************************************************************************************************************
55 * HEADER FILES
56 *********************************************************************************************************************/
57
58 #include "xmc_common.h"
59
60 #if defined(PAU)
61
62 /**
63 * @addtogroup XMClib XMC Peripheral Library
64 * @{
65 */
66
67 /**
68 * @addtogroup PAU
69 * @brief Peripheral Access Unit (PAU) driver for the XMC1000 microcontroller family
70 *
71 * The Peripheral Access Unit (PAU) supports access control of memories and peripherals.
72 * It allows user application to enable/disable the access to the registers of a peripheral.
73 * It generates a HardFault exception when there is an access to a disabled or unassigned
74 * address location. It also provides information on the availability of peripherals and
75 * sizes of memories.
76 *
77 * The PAU low level driver provides functions to check the availability of peripherals
78 * and to enable/disable peripheral access.
79 * @{
80 */
81
82 /*********************************************************************************************************************
83 * MACROS
84 *********************************************************************************************************************/
85
86 /**
87 * A convenient symbol for the PAU peripheral base address
88 */
89 #define XMC_PAU ((XMC_PAU_t *) PAU_BASE)
90
91 /*
92 * This macro is used in the LLD for assertion checks (XMC_ASSERT)
93 */
94 #define XMC_PAU_CHECK_MODULE_PTR(p) ((p) == XMC_PAU)
95
96 /*********************************************************************************************************************
97 * ENUMS
98 *********************************************************************************************************************/
99
100 /**
101 * Status return values for PAU low level driver
102 */
103 typedef enum XMC_PAU_STATUS
104 {
105 XMC_PAU_STATUS_OK = 0U, /**< Operation successful */
106 XMC_PAU_STATUS_BUSY = 1U, /**< Busy with a previous request */
107 XMC_PAU_STATUS_ERROR = 2U /**< Operation unsuccessful */
108 } XMC_PAU_STATUS_t;
109
110 /**
111 * PAU peripheral select
112 */
113 typedef enum XMC_PAU_PERIPHERAL
114 {
115 XMC_PAU_PERIPHERAL_FLASH = PAU_PRIVDIS0_PDIS2_Msk, /**< Flash SFRs Privilege Disable Flag */
116 XMC_PAU_PERIPHERAL_RAM_BLOCK1 = PAU_PRIVDIS0_PDIS5_Msk, /**< RAM Block 1 Privilege Disable Flag */
117 XMC_PAU_PERIPHERAL_RAM_BLOCK2 = PAU_PRIVDIS0_PDIS6_Msk, /**< RAM Block 2 Privilege Disable Flag */
118 XMC_PAU_PERIPHERAL_RAM_BLOCK3 = PAU_PRIVDIS0_PDIS7_Msk, /**< RAM Block 3 Privilege Disable Flag */
119 #if defined(WDT)
120 XMC_PAU_PERIPHERAL_WDT = PAU_PRIVDIS0_PDIS19_Msk, /**< WDT Privilege Disable Flag */
121 #endif
122 #if defined(MATH)
123 XMC_PAU_PERIPHERAL_MATH_GLOBAL_AND_DIV = PAU_PRIVDIS0_PDIS20_Msk, /**< MATH Global SFRs and Divider Privilege Disable Flag */
124 #endif
125 #if defined(MATH)
126 XMC_PAU_PERIPHERAL_MATH_CORDIC = PAU_PRIVDIS0_PDIS21_Msk, /**< MATH CORDIC Privilege Disable Flag */
127 #endif
128 #if defined(PORT0)
129 XMC_PAU_PERIPHERAL_PORT0 = PAU_PRIVDIS0_PDIS22_Msk, /**< Port 0 Privilege Disable Flag */
130 #endif
131 #if defined(PORT1)
132 XMC_PAU_PERIPHERAL_PORT1 = PAU_PRIVDIS0_PDIS23_Msk, /**< Port 1 Privilege Disable Flag */
133 #endif
134 #if defined(PORT2)
135 XMC_PAU_PERIPHERAL_PORT2 = PAU_PRIVDIS0_PDIS24_Msk, /**< Port 2 Privilege Disable Flag */
136 #endif
137 #if defined(PORT3)
138 XMC_PAU_PERIPHERAL_PORT3 = PAU_PRIVDIS0_PDIS25_Msk, /**< Port 3 Privilege Disable Flag */
139 #endif
140 #if defined(PORT4)
141 XMC_PAU_PERIPHERAL_PORT4 = PAU_PRIVDIS0_PDIS26_Msk, /**< Port 4 Privilege Disable Flag */
142 #endif
143 #if defined(USIC0)
144 XMC_PAU_PERIPHERAL_USIC0_CH0 = PAU_PRIVDIS1_PDIS0_Msk | 0x10000000U, /**< USIC0 Channel 0 Privilege Disable Flag */
145 XMC_PAU_PERIPHERAL_USIC0_CH1 = PAU_PRIVDIS1_PDIS1_Msk | 0x10000000U, /**< USIC0 Channel 1 Privilege Disable Flag */
146 #endif
147 #if defined(USIC1)
148 XMC_PAU_PERIPHERAL_USIC1_CH0 = PAU_PRIVDIS1_PDIS16_Msk | 0x10000000U, /**< USIC1 Channel 0 Privilege Disable Flag */
149 XMC_PAU_PERIPHERAL_USIC1_CH1 = PAU_PRIVDIS1_PDIS17_Msk | 0x10000000U, /**< USIC1 Channel 1 Privilege Disable Flag */
150 #endif
151 #if defined(PRNG)
152 XMC_PAU_PERIPHERAL_PRNG = PAU_AVAIL1_AVAIL4_Msk | 0x10000000U, /**< PRNG Availability Flag*/
153 #endif
154 #if defined(VADC)
155 XMC_PAU_PERIPHERAL_VADC_GLOBAL = PAU_PRIVDIS1_PDIS5_Msk | 0x10000000U, /**< VADC0 Basic SFRs Privilege Disable Flag */
156 #if defined(VADC_G0)
157 XMC_PAU_PERIPHERAL_VADC_GROUP0 = PAU_PRIVDIS1_PDIS6_Msk | 0x10000000U, /**< VADC0 Group 0 SFRs Privilege Disable Flag */
158 #endif
159 #if defined(VADC_G1)
160 XMC_PAU_PERIPHERAL_VADC_GROUP1 = PAU_PRIVDIS1_PDIS7_Msk | 0x10000000U, /**< VADC0 Group 1 SFRs Privilege Disable Flag */
161 #endif
162 #endif
163 #if defined(SHS0)
164 XMC_PAU_PERIPHERAL_VADC_SHS0 = PAU_PRIVDIS1_PDIS8_Msk | 0x10000000U, /**< SHS0 Privilege Disable Flag */
165 #endif
166 #if defined(CCU40)
167 XMC_PAU_PERIPHERAL_CCU40_CC40_AND_GLOBAL = PAU_PRIVDIS1_PDIS9_Msk | 0x10000000U, /**< CCU40_CC40 and CCU40 Kernel SFRs Privilege Disable Flag */
168 #if defined(CCU40_CC41)
169 XMC_PAU_PERIPHERAL_CCU40_CC41 = PAU_PRIVDIS1_PDIS10_Msk | 0x10000000U, /**< CCU40_CC41 Privilege Disable Flag */
170 #endif
171 #if defined(CCU40_CC42)
172 XMC_PAU_PERIPHERAL_CCU40_CC42 = PAU_PRIVDIS1_PDIS11_Msk | 0x10000000U, /**< CCU40_CC42 Privilege Disable Flag */
173 #endif
174 #if defined(CCU40_CC43)
175 XMC_PAU_PERIPHERAL_CCU40_CC43 = PAU_PRIVDIS1_PDIS12_Msk | 0x10000000U, /**< CCU40_CC43 Privilege Disable Flag */
176 #endif
177 #endif
178 #if defined(CCU41)
179 XMC_PAU_PERIPHERAL_CCU41_CC40_AND_GLOBAL = PAU_PRIVDIS1_PDIS25_Msk | 0x10000000U, /**< CCU41_CC40 and CCU41 Kernel SFRs Privilege Disable Flag */
180 #if defined(CCU41_CC41)
181 XMC_PAU_PERIPHERAL_CCU41_CC41 = PAU_PRIVDIS1_PDIS26_Msk | 0x10000000U, /**< CCU41_CC41 Privilege Disable Flag */
182 #endif
183 #if defined(CCU41_CC42)
184 XMC_PAU_PERIPHERAL_CCU41_CC42 = PAU_PRIVDIS1_PDIS27_Msk | 0x10000000U, /**< CCU41_CC42 Privilege Disable Flag */
185 #endif
186 #if defined(CCU41_CC43)
187 XMC_PAU_PERIPHERAL_CCU41_CC43 = PAU_PRIVDIS1_PDIS28_Msk | 0x10000000U, /**< CCU41_CC43 Privilege Disable Flag */
188 #endif
189 #endif
190 #if defined(CCU80)
191 XMC_PAU_PERIPHERAL_CCU80_CC80_AND_GLOBAL = PAU_PRIVDIS2_PDIS0_Msk | 0x20000000U, /**< CCU80_CC80 and CCU80 Kernel SFRs Privilege Disable Flag */
192 #if defined(CCU80_CC81)
193 XMC_PAU_PERIPHERAL_CCU80_CC81 = PAU_PRIVDIS2_PDIS1_Msk | 0x20000000U, /**< CCU80_CC81 Privilege Disable Flag */
194 #endif
195 #if defined(CCU80_CC82)
196 XMC_PAU_PERIPHERAL_CCU80_CC82 = PAU_PRIVDIS2_PDIS2_Msk | 0x20000000U, /**< CCU80_CC82 Privilege Disable Flag */
197 #endif
198 #if defined(CCU80_CC83)
199 XMC_PAU_PERIPHERAL_CCU80_CC83 = PAU_PRIVDIS2_PDIS3_Msk | 0x20000000U, /**< CCU80_CC83 Privilege Disable Flag */
200 #endif
201 #endif
202 #if defined(CCU81)
203 XMC_PAU_PERIPHERAL_CCU81_CC80_AND_GLOBAL = PAU_PRIVDIS2_PDIS16_Msk | 0x20000000U, /**< CCU81_CC80 and CCU81 Kernel SFRs Privilege Disable Flag */
204 #if defined(CCU81_CC81)
205 XMC_PAU_PERIPHERAL_CCU81_CC81 = PAU_PRIVDIS2_PDIS17_Msk | 0x20000000U, /**< CCU81_CC81 Privilege Disable Flag */
206 #endif
207 #if defined(CCU81_CC82)
208 XMC_PAU_PERIPHERAL_CCU81_CC82 = PAU_PRIVDIS2_PDIS18_Msk | 0x20000000U, /**< CCU81_CC82 Privilege Disable Flag */
209 #endif
210 #if defined(CCU81_CC83)
211 XMC_PAU_PERIPHERAL_CCU81_CC83 = PAU_PRIVDIS2_PDIS19_Msk | 0x20000000U, /**< CCU81_CC83 Privilege Disable Flag */
212 #endif
213 #endif
214 #if defined(POSIF0)
215 XMC_PAU_PERIPHERAL_POSIF0 = PAU_PRIVDIS2_PDIS12_Msk | 0x20000000U, /**< POSIF0 Privilege Disable Flag */
216 #endif
217 #if defined(POSIF1)
218 XMC_PAU_PERIPHERAL_POSIF1 = PAU_PRIVDIS2_PDIS28_Msk | 0x20000000U, /**< POSIF1 Privilege Disable Flag */
219 #endif
220 #if defined(LEDTS0)
221 XMC_PAU_PERIPHERAL_LEDTS0 = PAU_PRIVDIS2_PDIS13_Msk | 0x20000000U, /**< LEDTS0 Privilege Disable Flag */
222 #endif
223 #if defined(LEDTS1)
224 XMC_PAU_PERIPHERAL_LEDTS1 = PAU_PRIVDIS2_PDIS14_Msk | 0x20000000U, /**< LEDTS1 Privilege Disable Flag */
225 #endif
226 #if defined(LEDTS2)
227 XMC_PAU_PERIPHERAL_LEDTS2 = PAU_PRIVDIS2_PDIS29_Msk | 0x20000000U, /**< LEDTS2 Privilege Disable Flag */
228 #endif
229 #if defined(BCCU0)
230 XMC_PAU_PERIPHERAL_BCCU0 = PAU_PRIVDIS2_PDIS15_Msk | 0x20000000U, /**< BCCU0 Privilege Disable Flag */
231 #endif
232 #if defined(CAN)
233 #if defined(CAN_NODE0)
234 XMC_PAU_PERIPHERAL_MCAN_NODE0_AND_GLOBAL = PAU_PRIVDIS2_PDIS21_Msk | 0x20000000U, /**< MCAN NODE0 and Global SFRs Privilege */
235 #endif
236 #if defined(CAN_NODE1)
237 XMC_PAU_PERIPHERAL_MCAN_NODE1_AND_GLOBAL = PAU_PRIVDIS2_PDIS23_Msk | 0x20000000U, /**< MCAN NODE1 Privilege Disable Flag */
238 #endif
239 XMC_PAU_PERIPHERAL_MCAN_OBJECTS = PAU_PRIVDIS2_PDIS28_Msk | 0x20000000U, /**< MCAN Message Objects Privilege Disable Flag */
240 #endif
241 } XMC_PAU_PERIPHERAL_t;
242
243
244 /*********************************************************************************************************************
245 * DATA STRUCTURES
246 *********************************************************************************************************************/
247
248
249 /**
250 * External Peripheral Access Unit (PAU) device structure <br>
251 *
252 * The structure represents a collection of all hardware registers
253 * used to configure the PAU peripheral on the XMC microcontroller.
254 * The registers can be accessed with ::XMC_PAU.
255 */
256 typedef struct
257 {
258 __I uint32_t RESERVED0[16];
259 __I uint32_t AVAIL[3];
260 __I uint32_t RESERVED1[13];
261 __IO uint32_t PRIVDIS[3];
262 __I uint32_t RESERVED2[221];
263 __I uint32_t ROMSIZE;
264 __I uint32_t FLSIZE;
265 __I uint32_t RESERVED3[2];
266 __I uint32_t RAM0SIZE;
267 } XMC_PAU_t;
268
269 /*********************************************************************************************************************
270 * API PROTOTYPES
271 *********************************************************************************************************************/
272
273 #ifdef __cplusplus
274 extern "C" {
275 #endif
276
277 /**
278 * @param peripheral Peripheral of type ::XMC_PAU_PERIPHERAL_t for which access needs to be enabled
279 * @return None
280 *
281 * \par<b>Description: </b><br>
282 * Enable the peripheral access <br>
283 *
284 * \par
285 * The function resets the PRIVDISx.PDISy bit to enable the access to the registers of a peripheral
286 * during run time.
287 *
288 * \par<b>Related APIs:</b><br>
289 * XMC_PAU_DisablePeripheralAccess()
290 */
291 void XMC_PAU_EnablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral);
292
293 /**
294 * @param peripheral Peripheral of type ::XMC_PAU_PERIPHERAL_t for which access needs to be disabled
295 * @return None
296 *
297 * \par<b>Description: </b><br>
298 * Disable the peripheral access <br>
299 *
300 * \par
301 * The function sets the PRIVDISx.PDISy bit to disable the access to the registers of a peripheral
302 * during run time. An access to a disabled or unassigned address location generates a hardfault
303 * exception.
304 *
305 * \par<b>Related APIs:</b><br>
306 * XMC_PAU_EnablePeripheralAccess()
307 */
308 void XMC_PAU_DisablePeripheralAccess(XMC_PAU_PERIPHERAL_t peripheral);
309
310 /**
311 * @param peripheral Peripheral of type ::XMC_PAU_PERIPHERAL_t for which access enabled status to be checked
312 * @return bool "false" if peripheral access is enabled, "true" otherwise
313 *
314 * \par<b>Description: </b><br>
315 * Checks if the peripheral access is enabled or not <br>
316 *
317 * \par
318 * The function checks the PRIVDISx.PDISy bit to know whether the access to the registers of a peripheral
319 * during run time is enabled or not.
320 *
321 * \par<b>Related APIs:</b><br>
322 * XMC_PAU_DisablePeripheralAccess(), XMC_PAU_EnablePeripheralAccess()
323 */
324 bool XMC_PAU_IsPeripheralAccessEnabled(XMC_PAU_PERIPHERAL_t peripheral);
325
326 /**
327 * @param peripheral Peripheral of type ::XMC_PAU_PERIPHERAL_t for which access needs to be disabled
328 * @return bool Returns "true" if peripheral is available, "false" otherwise
329 *
330 * \par<b>Description: </b><br>
331 * Checks if a peripheral is available or not <br>
332 *
333 * \par
334 * The function checks the AVAILx.AVAILy bit to know whether the peripheral
335 * is available or not for the particular device variant.
336 */
337 bool XMC_PAU_IsPeripheralAvailable(XMC_PAU_PERIPHERAL_t peripheral);
338
339 /**
340 * @return uint32_t Returns ROM size
341 *
342 * \par<b>Description: </b><br>
343 * Gets the ROM size <br>
344 *
345 * \par
346 * The function checks the ROMSIZE.ADDR bitfield to indicate the available size of ROM in the device in bytes.
347 */
XMC_PAU_GetROMSize(void)348 __STATIC_INLINE uint32_t XMC_PAU_GetROMSize(void)
349 {
350 return (uint32_t)(((XMC_PAU->ROMSIZE & PAU_ROMSIZE_ADDR_Msk) >> PAU_ROMSIZE_ADDR_Pos) * 256U);
351 }
352
353 /**
354 * @return uint32_t Returns flash size
355 *
356 * \par<b>Description: </b><br>
357 * Gets the flash size <br>
358 *
359 * \par
360 * The function checks the FLSIZE.ADDR bitfield to indicate the available size of FLASH in the device in Kbytes.
361 */
XMC_PAU_GetFlashSize(void)362 __STATIC_INLINE uint32_t XMC_PAU_GetFlashSize(void)
363 {
364 return (uint32_t)((((XMC_PAU->FLSIZE & PAU_FLSIZE_ADDR_Msk) >> PAU_FLSIZE_ADDR_Pos) - 1U) * 4U);
365 }
366
367 /**
368 * @return uint32_t Returns RAM size
369 *
370 * \par<b>Description: </b><br>
371 * Gets RAM size <br>
372 *
373 * \par
374 * The function checks the RAM0SIZE.ADDR bitfield to indicate the available size of RAM in the device in bytes.
375 */
XMC_PAU_GetRAMSize(void)376 __STATIC_INLINE uint32_t XMC_PAU_GetRAMSize(void)
377 {
378 return (uint32_t)(((XMC_PAU->RAM0SIZE & PAU_RAM0SIZE_ADDR_Msk) >> PAU_RAM0SIZE_ADDR_Pos) * 256U);
379 }
380
381 #ifdef __cplusplus
382 }
383 #endif
384
385 /**
386 * @}
387 */
388
389 /**
390 * @}
391 */
392
393 #endif /* defined(PAU) */
394
395 #endif /* XMC_PAU_H */
396
397
