1 /**
2 * @file xmc_fce.h
3 * @date 2019-03-30
4 *
5 * @cond
6 *********************************************************************************************************************
7 * XMClib v2.1.24 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015-2019, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
22 * products derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
33 * Infineon Technologies AG dave@infineon.com).
34 *********************************************************************************************************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-02-20:
40 * - Initial
41 *
42 * 2015-05-20:
43 * - Description updated <br>
44 *
45 * 2015-06-20:
46 * - Removed version macros and declaration of GetDriverVersion API
47 *
48 * 2019-03-30:
49 * - Added XMC_FCE_CalculateCRC16Ex() and XMC_FCE_CalculateCRC32Ex()
50 *
51 * @endcond
52 *
53 */
54
55 #ifndef XMC_FCE_H
56 #define XMC_FCE_H
57
58 /**********************************************************************************************************************
59 * HEADER FILES
60 *********************************************************************************************************************/
61
62 #include <xmc_common.h>
63
64 #if defined (FCE)
65
66 /**
67 * @addtogroup XMClib
68 * @{
69 */
70
71 /**
72 * @addtogroup FCE
73 * @brief Flexible CRC Engine(FCE) driver for the XMC microcontroller family.
74 *
75 * The FCE provides a parallel implementation of Cyclic Redundancy Code (CRC)
76 * algorithms. The current FCE version for the XMC4000 microcontroller family implements the
77 * IEEE 802.3 ethernet CRC32, the CCITT CRC16 and the SAE J1850 CRC8 polynomials.
78 * The primary target of FCE is to be used as an hardware acceleration engine for software
79 * applications or operating systems services using CRC signatures.
80 *
81 * @image html fce_overview.png
82 * @image latex ../images/fce_overview.png
83 * FCE Features: <br>
84 * @image html fce_polynomials.png
85 * @image latex ../images/fce_polynomials.png
86 * * CRC kernel 0 and 1: IEEE 802.3 CRC32 ethernet polynomial: 0x04C11DB71 <br>
87 * * CRC kernel 2: CCITT CRC16 polynomial: 0x1021 <br>
88 * * CRC kernel 3: SAE J1850 CRC8 polynomial: 0x1D <br>
89 * * Configuration Registers enable to control the CRC operation and perform automatic checksum checks at
90 * the end of a message. <br>
91 * * Extended register interface to control reliability of FCE execution in safety applications. <br>
92 * * Error notification scheme via dedicated interrupt node for: <br>
93 a)Transient error detection: Error interrupt generation (maskable) with local status register
94 (cleared by software) <br>
95 b)Checksum failure: Error interrupt generation (maskable) with local status register (cleared by software) <br>
96
97 FCE provides one interrupt line to the interrupt system. Each CRC engine has its own set of flag registers. <br>
98
99 * @{
100 */
101
102 /**********************************************************************************************************************
103 * MACROS
104 *********************************************************************************************************************/
105
106 #define XMC_FCE_CRC32_0 FCE_KE0 /**< Kernel 0 <br> */
107 #define XMC_FCE_CRC32_1 FCE_KE1 /**< Kernel 1 <br> */
108 #define XMC_FCE_CRC16 FCE_KE2 /**< Kernel 2 <br> */
109 #define XMC_FCE_CRC8 FCE_KE3 /**< Kernel 3 <br> */
110
111 #define XMC_FCE_REFIN_SET (1U) /**< Enables input reflection */
112 #define XMC_FCE_REFIN_RESET (0U) /**< Disables input reflection */
113 #define XMC_FCE_REFOUT_SET (1U) /**< Enables output reflection */
114 #define XMC_FCE_REFOUT_RESET (0U) /**< Disables output reflection */
115 #define XMC_FCE_INVSEL_SET (1U) /**< Enables output inversion */
116 #define XMC_FCE_INVSEL_RESET (0U) /**< Disables output inversion */
117
118 /**********************************************************************************************************************
119 * ENUMS
120 *********************************************************************************************************************/
121
122 /**
123 * FCE interrupt configuration
124 */
125 typedef enum XMC_FCE_CONFIG_INTERRUPT
126 {
127 XMC_FCE_CFG_CONFIG_CMI = FCE_KE_CFG_CMI_Msk, /**< Enables CRC Mismatch interrupt \n*/
128 XMC_FCE_CFG_CONFIG_CEI = FCE_KE_CFG_CEI_Msk, /**< Enables Configuration error interrupt \n*/
129 XMC_FCE_CFG_CONFIG_LEI = FCE_KE_CFG_LEI_Msk, /**< Enables Length error interrupt \n*/
130 XMC_FCE_CFG_CONFIG_BEI = FCE_KE_CFG_BEI_Msk /**< Enables Bus error interrupt \n*/
131 } XMC_FCE_CONFIG_INTERRUPT_t;
132
133 /**
134 * FCE operation configuration
135 */
136 typedef enum XMC_FCE_CONFIG_OPERATION
137 {
138 XMC_FCE_CFG_CONFIG_CCE = FCE_KE_CFG_CCE_Msk, /**< Enables CRC check */
139 XMC_FCE_CFG_CONFIG_ALR = FCE_KE_CFG_ALR_Msk /**< Enables Automatic length reload */
140 } XMC_FCE_CONFIG_OPERATION_t;
141
142 /**
143 * FCE algorithm configuration
144 */
145 typedef enum XMC_FCE_CONFIG_ALGO
146 {
147 XMC_FCE_CFG_CONFIG_REFIN = FCE_KE_CFG_REFIN_Msk, /**< Enables input byte reflection */
148 XMC_FCE_CFG_CONFIG_REFOUT = FCE_KE_CFG_REFOUT_Msk, /**< Enables Final CRC reflection */
149 XMC_FCE_CFG_CONFIG_XSEL = FCE_KE_CFG_XSEL_Msk /**< Enables output inversion */
150 } XMC_FCE_CONFIG_ALGO_t;
151
152 /**
153 * FCE status flag configuration
154 */
155 typedef enum XMC_FCE_STS_FLAG
156 {
157 XMC_FCE_STS_MISMATCH_CRC = FCE_KE_STS_CMF_Msk, /**< CRC Mismatch flag */
158 XMC_FCE_STS_CONFIG_ERROR = FCE_KE_STS_CEF_Msk, /**< Configuration Error flag */
159 XMC_FCE_STS_LENGTH_ERROR = FCE_KE_STS_LEF_Msk, /**< Length Error flag */
160 XMC_FCE_STS_BUS_ERROR = FCE_KE_STS_BEF_Msk /**< Bus Error flag */
161 } XMC_FCE_STS_FLAG_t;
162
163 /**
164 * FCE control configuration
165 */
166 typedef enum XMC_FCE_CTR_TEST
167 {
168 XMC_FCE_CTR_MISMATCH_CRC = FCE_KE_CTR_FCM_Msk, /**< Forces CRC mismatch */
169 XMC_FCE_CTR_MISMATCH_CFG = FCE_KE_CTR_FRM_CFG_Msk, /**< Forces CFG Register mismatch */
170 XMC_FCE_CTR_MISMATCH_CHECK = FCE_KE_CTR_FRM_CHECK_Msk /**< Forces CRC Check Register mismatch */
171 } XMC_FCE_CTR_TEST_t;
172
173 /**
174 * FCE status enumeration
175 */
176 typedef enum XMC_FCE_STATUS
177 {
178 XMC_FCE_STATUS_OK = 0, /**< Returns OK on success */
179 XMC_FCE_STATUS_BUSY, /**< Returns BUSY when API is busy with a previous request */
180 XMC_FCE_STATUS_ERROR /**< Returns ERROR when API cannot fulfil request */
181 } XMC_FCE_STATUS_t;
182
183 /**********************************************************************************************************************
184 * DATA STRUCTURES
185 *********************************************************************************************************************/
186
187 /**
188 * FCE kernel
189 */
190 typedef FCE_KE_TypeDef XMC_FCE_Kernel_t;
191
192 /* Anonymous structure/union guard start */
193 #if defined (__CC_ARM)
194 #pragma push
195 #pragma anon_unions
196 #elif defined (__TASKING__)
197 #pragma warning 586
198 #endif
199
200 /**
201 * @brief XMC_FCE configuration structure
202 */
203 typedef struct XMC_FCE_CONFIG
204 {
205 union
206 {
207 uint32_t regval;
208 struct
209 {
210 uint32_t : 8;
211 uint32_t config_refin : 1; /**< Enables byte-wise reflection */
212 uint32_t config_refout : 1; /**< Enables bit-wise reflection */
213 uint32_t config_xsel : 1; /**< Enables output inversion */
214 uint32_t : 21; /**< Reserved bits */
215 };
216 };
217 } XMC_FCE_CONFIG_t;
218
219 /* Anonymous structure/union guard end */
220 #if defined (__CC_ARM)
221 #pragma pop
222 #elif defined (__TASKING__)
223 #pragma warning restore
224 #endif
225
226 /**
227 * FCE handler
228 */
229 typedef struct XMC_FCE
230 {
231 XMC_FCE_Kernel_t *kernel_ptr; /**< FCE Kernel Pointer */
232 XMC_FCE_CONFIG_t fce_cfg_update; /**< FCE CFG register update */
233 uint32_t seedvalue; /**< CRC seed value to be used */
234 } XMC_FCE_t;
235
236 /**********************************************************************************************************************
237 * API PROTOTYPES
238 *********************************************************************************************************************/
239
240 #ifdef __cplusplus
241 extern "C" {
242 #endif
243
244 /**
245 * @param None
246 * @return uint32_t Module revision number
247 *
248 * \par<b>Description: </b><br>
249 * Read FCE module revision number <br>
250 *
251 * \par
252 * The value of a module revision starts with 0x01 (first revision). The current revision
253 * number is 0x01.
254 */
XMC_FCE_ReadModuleRev(void)255 __STATIC_INLINE uint32_t XMC_FCE_ReadModuleRev(void)
256 {
257 return (uint32_t)(FCE->ID & FCE_ID_MOD_REV_Msk);
258 }
259
260 /**
261 * @param None
262 * @return uint32_t Module type
263 *
264 * \par<b>Description: </b><br>
265 * Read the FCE module type <br>
266 *
267 * \par
268 * The return value is currently 0xC0. It defines the module as a 32-bit module.
269 */
XMC_FCE_ReadModuleType(void)270 __STATIC_INLINE uint32_t XMC_FCE_ReadModuleType(void)
271 {
272 return (uint32_t)((FCE->ID & FCE_ID_MOD_TYPE_Msk) >> FCE_ID_MOD_TYPE_Pos);
273 }
274
275 /**
276 * @param None
277 * @return uint32_t Module number
278 *
279 * \par<b>Description: </b><br>
280 * Read FCE module number <br>
281 *
282 * \par
283 * The return value for FCE module is currently 0x00CA.
284 */
XMC_FCE_ReadModuleNumber(void)285 __STATIC_INLINE uint32_t XMC_FCE_ReadModuleNumber(void)
286 {
287 return ((uint32_t)((FCE->ID & FCE_ID_MOD_NUMBER_Msk) >> FCE_ID_MOD_NUMBER_Pos));
288 }
289
290 /**
291 * @param None
292 * @return bool Disable status
293 *
294 *
295 * \par<b>Description: </b><br>
296 * Return the disable status <br>
297 *
298 * \par
299 * The function reads the FCE module disable status (DISS) bit. It returns "true" if
300 * set, "false" otherwise.
301 */
XMC_FCE_Get_DisableStatus(void)302 __STATIC_INLINE bool XMC_FCE_Get_DisableStatus(void)
303 {
304 return (bool)(FCE->CLC &= (uint32_t)~FCE_CLC_DISS_Msk);
305 }
306
307 /**
308 * @param None
309 * @return None
310 *
311 * \par<b>Description: </b><br>
312 * Disable the FCE module <br>
313 *
314 * \par
315 * The function asserts the FCE peripheral reset and sets the DISR bit in the CLC
316 * register.
317 *
318 * \par<b>Note: </b><br>
319 * All pending transactions running on the bus slave interface must be completed before
320 * entering the disabled state.
321 */
322 void XMC_FCE_Disable(void);
323
324 /**
325 * @param None
326 * @return None
327 *
328 * \par<b>Description: </b><br>
329 * Enable the FCE module <br>
330 *
331 * \par
332 * The function de-asserts the peripheral reset and clears the DISR bit CLC register.
333 */
334 void XMC_FCE_Enable(void);
335
336 /**
337 * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
338 * @return ::XMC_FCE_STATUS_t
339 *
340 * \par<b>Description: </b><br>
341 * Initialize the FCE engine <br>
342 *
343 * \par
344 * The function sets to the CFG and CRC registers with the FCE configuration and
345 * seeds values. The function always returns XMC_FCE_STATUS_SUCCESS.
346 *
347 * \par<b>Note: </b><br>
348 * The software must first ensure that the CRC kernel is properly configured with the
349 * initial CRC value (seed value).
350 */
351 XMC_FCE_STATUS_t XMC_FCE_Init(const XMC_FCE_t *const engine);
352
353 /**
354 * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
355 * @param seedvalue Initial CRC value
356 * @return None
357 *
358 * \par<b>Description: </b><br>
359 * Initialize FCE seed value
360 *
361 * \par
362 * The function sets the initial CRC (seed) value in the CRC register.
363 */
XMC_FCE_InitializeSeedValue(const XMC_FCE_t * const engine,uint32_t seedvalue)364 __STATIC_INLINE void XMC_FCE_InitializeSeedValue(const XMC_FCE_t *const engine, uint32_t seedvalue)
365 {
366 engine->kernel_ptr->CRC = seedvalue;
367 }
368
369 /**
370 * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
371 * @param event OR'd values of ::XMC_FCE_CONFIG_INTERRUPT_t enumeration values
372 * @return None
373 *
374 * \par<b>Description: </b><br>
375 * Enable FCE event(s) <br>
376 *
377 * \par
378 * The function sets the CFG register to enable FCE event(s).
379 */
XMC_FCE_EnableEvent(const XMC_FCE_t * const engine,uint32_t event)380 __STATIC_INLINE void XMC_FCE_EnableEvent(const XMC_FCE_t *const engine, uint32_t event)
381 {
382 engine->kernel_ptr->CFG |= (uint32_t)event;
383 }
384
385 /**
386 * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
387 * @param event OR'd values of ::XMC_FCE_CONFIG_INTERRUPT_t enumeration values
388 * @return None
389 *
390 * \par<b>Description: </b><br>
391 * Disable FCE event(s) <br>
392 *
393 * \par
394 * The function clears the CFG register to disable FCE event(s).
395 */
XMC_FCE_DisableEvent(const XMC_FCE_t * const engine,uint32_t event)396 __STATIC_INLINE void XMC_FCE_DisableEvent(const XMC_FCE_t *const engine, uint32_t event)
397 {
398 engine->kernel_ptr->CFG &= ~(uint32_t)event;
399 }
400
401 /**
402 * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
403 * @param event Event of type ::XMC_FCE_STS_FLAG_t
404 * @return bool
405 *
406 * \par<b>Description: </b><br>
407 * Return the event status of FCE event <br>
408 *
409 * \par
410 * The function returns the status of a single requested FCE event by reading the
411 * appropriate bit-fields of the STS register.
412 */
XMC_FCE_GetEventStatus(const XMC_FCE_t * const engine,XMC_FCE_STS_FLAG_t event)413 __STATIC_INLINE bool XMC_FCE_GetEventStatus(const XMC_FCE_t *const engine, XMC_FCE_STS_FLAG_t event)
414 {
415 return (bool) (engine->kernel_ptr->STS & (uint32_t)event);
416 }
417
418 /**
419 * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
420 * @param event Event of type ::XMC_FCE_STS_FLAG_t
421 * @return None
422 *
423 * \par<b>Description: </b><br>
424 * Clear an FCE event <br>
425 *
426 * \par
427 * The function clears requested FCE events by setting the bit-fields of the STS
428 * register.
429 */
XMC_FCE_ClearEvent(const XMC_FCE_t * const engine,XMC_FCE_STS_FLAG_t event)430 __STATIC_INLINE void XMC_FCE_ClearEvent(const XMC_FCE_t *const engine, XMC_FCE_STS_FLAG_t event)
431 {
432 engine->kernel_ptr->STS |= (uint32_t)event;
433 }
434
435 /**
436 * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
437 * @param operation FCE operation of type ::XMC_FCE_CONFIG_OPERATION_t
438 * @return None
439 *
440 * \par<b>Description: </b><br>
441 * Enable CRC operations <br>
442 *
443 * \par
444 * The function enables FRC operations by writing to the CFG register.
445 *
446 * \par<b>Note: </b><br>
447 * CRC comparison check (at the end of message) can be enabled using the CCE bit-field.
448 * Automatic reload of LENGTH field (at the end of message) can be enabled using the
449 * ALR bit field.
450 */
XMC_FCE_EnableOperation(const XMC_FCE_t * const engine,uint32_t operation)451 __STATIC_INLINE void XMC_FCE_EnableOperation(const XMC_FCE_t *const engine, uint32_t operation)
452 {
453 engine->kernel_ptr->CFG |= operation;
454 }
455
456 /**
457 * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
458 * @param operation FCE operation of type ::XMC_FCE_CONFIG_OPERATION_t
459 * @return None
460 *
461 * \par<b>Description: </b><br>
462 * Disable CRC operations <br>
463 *
464 * \par
465 * The function disables FRC operations by writing to the CFG register.
466 *
467 * \par<b>Note: </b><br>
468 * CRC comparison check (at the end of message) can be disabled using the CCE bit-field.
469 * Automatic reload of LENGTH field (at the end of message) can be disabled using the
470 * ALR bit field.
471 */
XMC_FCE_DisableOperation(const XMC_FCE_t * const engine,uint32_t operation)472 __STATIC_INLINE void XMC_FCE_DisableOperation(const XMC_FCE_t *const engine, uint32_t operation)
473 {
474 engine->kernel_ptr->CFG &= ~(uint32_t)operation;
475 }
476
477 /**
478 * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
479 * @param algo A valid algorithm of type ::XMC_FCE_CONFIG_ALGO_t or a valid combination
480 * of logically OR'd algorithms
481 * @return None
482 *
483 * \par<b>Description: </b><br>
484 * Enables CRC algorithm(s) <br>
485 *
486 * \par<b>Note: </b><br>
487 * Options for enabling CRC algorithm: <br>
488 * REFIN: Input byte wise reflection <br>
489 * REFOUT: Output bit wise reflection <br>
490 * XSEL: Value to be XORed with final CRC <br>
491 */
XMC_FCE_EnableCRCAlgorithm(const XMC_FCE_t * const engine,uint32_t algo)492 __STATIC_INLINE void XMC_FCE_EnableCRCAlgorithm(const XMC_FCE_t *const engine, uint32_t algo)
493 {
494 engine->kernel_ptr->CFG |= (uint32_t)algo;
495 }
496
497 /**
498 * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
499 * @param algo A valid algorithm of type ::XMC_FCE_CONFIG_ALGO_t or a valid combination
500 * of logically OR'd algorithms
501 * @return None
502 *
503 * \par<b>Description: </b><br>
504 * Disable CRC algorithm(s) <br>
505 *
506 * \par<b>Note: </b><br>
507 * Options for disabling CRC algorithm: <br>
508 * REFIN: Input byte wise reflection <br>
509 * REFOUT: Output bit wise reflection <br>
510 * XSEL: Value to be XORed with final CRC <br>
511 */
XMC_FCE_DisableCRCAlgorithm(const XMC_FCE_t * const engine,uint32_t algo)512 __STATIC_INLINE void XMC_FCE_DisableCRCAlgorithm(const XMC_FCE_t *const engine, uint32_t algo)
513 {
514 engine->kernel_ptr->CFG &= ~(uint32_t)algo;
515 }
516
517 /**
518 * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
519 * @param checkvalue Checksum value
520 * @return None
521 *
522 * \par<b>Description: </b><br>
523 * Updates CRC check value <br>
524 *
525 * \par
526 * When the CFG.CCE bit field is set, every time the IR register is written, the
527 * LENGTH register is decremented by one until it reaches zero. The hardware monitors
528 * the transition of the LENGTH register from 1 to 0 to detect the end of the
529 * message and proceed with the comparison of the result register (RES) value with
530 * the CHECK register value.
531 */
XMC_FCE_UpdateCRCCheck(const XMC_FCE_t * const engine,const uint32_t checkvalue)532 __STATIC_INLINE void XMC_FCE_UpdateCRCCheck(const XMC_FCE_t *const engine, const uint32_t checkvalue)
533 {
534 engine->kernel_ptr->CHECK = 0xFACECAFEU;
535 engine->kernel_ptr->CHECK = checkvalue;
536 }
537
538 /**
539 * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
540 * @param checklength Checksum length
541 * @return None <br>
542 *
543 * \par<b>Description: </b><br>
544 * Updates CRC length specified in the input parameter <br>
545 *
546 * \par
547 * When the ALR bit field is set to 1, every write to the IR register decrements
548 * the value of the LENGTH bit field. The LENGTH field shall be reloaded with its
549 * configuration value at the end of the cycle where LENGTH reaches 0.
550 */
XMC_FCE_UpdateLength(const XMC_FCE_t * const engine,const uint32_t checklength)551 __STATIC_INLINE void XMC_FCE_UpdateLength(const XMC_FCE_t *const engine, const uint32_t checklength)
552 {
553 engine->kernel_ptr->LENGTH = 0xFACECAFEU;
554 engine->kernel_ptr->LENGTH = checklength;
555 }
556
557 /**
558 * @param engine Constant pointer to @ref XMC_FCE_t, pointing to the FCE base address
559 * @param data Pointer to the data buffer
560 * @param length Total number of bytes of data buffer
561 * @param result Pointer to computed CRC result
562 * @return XMC_FCE_STATUS_ERROR on error
563 * @return XMC_FCE_STATUS_SUCCESS otherwise.
564 *
565 * \par<b>Description: </b><br>
566 * Calculate and updates the CRC8 checksum in the result pointer <br>
567 *
568 * \par<b>Note: </b><br>
569 * A write to IRm (m = 3) triggers the CRC kernel to update the message checksum
570 * according to the IR and current CRC register contents. Any write transaction
571 * is allowed to this IRm register. Only the lower 8-bit of the write transactions
572 * will be used. ::XMC_FCE_GetCRCResult() should be called after invoking
573 * ::XMC_FCE_CalculateCRC8() to get final CRC value.
574 */
575 XMC_FCE_STATUS_t XMC_FCE_CalculateCRC8(const XMC_FCE_t *const engine,
576 const uint8_t *data,
577 uint32_t length,
578 uint8_t *result);
579
580 /**
581 * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
582 * @param data Pointer to the data buffer
583 * @param length Length of data buffer
584 * @param result Pointer to computed CRC result
585 * @return XMC_FCE_STATUS_ERROR on error
586 * @return XMC_FCE_STATUS_SUCCESS otherwise.
587 *
588 * \par<b>Description: </b><br>
589 * Calculate and update the RC16 checksum in the result pointer <br>
590 *
591 * \par<b>Note: </b><br>
592 * A write to Internal Register (IRm m = 2) triggers the CRC kernel to update the
593 * message checksum according to the IR and current CRC register contents. Only 32-bit
594 * or 16-bit write transactions are permitted. Any other bus write transaction will
595 * lead to a bus error. Only the lower 16-bit of the write transactions will be used.
596 * ::XMC_FCE_GetCRCResult() should be called after ::XMC_FCE_CalculateCRC16() to get
597 * final CRC value.
598 */
599 XMC_FCE_STATUS_t XMC_FCE_CalculateCRC16(const XMC_FCE_t *const engine,
600 const uint16_t *data,
601 uint32_t length,
602 uint16_t *result);
603
604 /**
605 * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
606 * @param data Pointer to the data buffer
607 * @param length Length of data buffer
608 * @param result Pointer to computed CRC result
609 * @return XMC_FCE_STATUS_ERROR on error
610 * @return XMC_FCE_STATUS_SUCCESS otherwise.
611 *
612 * \par<b>Description: </b><br>
613 * Calculate and update the RC16 checksum in the result pointer <br>
614 *
615 * \par<b>Note: </b><br>
616 * Alternative to XMC_FCE_CalculateCRC16() where a uint8_t data array can be used
617 */
618 XMC_FCE_STATUS_t XMC_FCE_CalculateCRC16Ex(const XMC_FCE_t *const engine,
619 const uint8_t *data,
620 uint32_t length,
621 uint16_t *const result);
622
623 /**
624 * @param engine Constant pointer to @ref XMC_FCE_t, pointing to the FCE base address
625 * @param data Pointer to the data buffer
626 * @param length Total number of bytes of data buffer
627 * @param result Pointer to computed CRC result
628 * @return XMC_FCE_STATUS_ERROR on error
629 * @return XMC_FCE_STATUS_SUCCESS otherwise.
630 *
631 * \par<b>Description</b><br>
632 * Calculate and update the calculated CRC32 checksum in the result pointer <br>
633 *
634 * \par<b>Note:</b><br>
635 * A write to Internal Register (IRm, m = 0-1) triggers the CRC kernel to update
636 * the message checksum according to the IR and current CRC register contents. Only
637 * 32-bit write transactions are permitted. Any other bus write transaction will
638 * lead to a bus error. ::XMC_FCE_GetCRCResult() should be called after
639 * ::XMC_FCE_CalculateCRC32() to get final CRC value.
640 */
641 XMC_FCE_STATUS_t XMC_FCE_CalculateCRC32(const XMC_FCE_t *const engine,
642 const uint32_t *data,
643 uint32_t length,
644 uint32_t *result);
645
646 /**
647 * @param engine Constant pointer to @ref XMC_FCE_t, pointing to the FCE base address
648 * @param data Pointer to the data buffer
649 * @param length Total number of bytes of data buffer
650 * @param result Pointer to computed CRC result
651 * @return XMC_FCE_STATUS_ERROR on error
652 * @return XMC_FCE_STATUS_SUCCESS otherwise.
653 *
654 * \par<b>Description</b><br>
655 * Calculate and update the calculated CRC32 checksum in the result pointer <br>
656 *
657 * \par<b>Note:</b><br>
658 * Alternative to XMC_FCE_CalculateCRC32() where a uint8_t data array can be used
659 */
660 XMC_FCE_STATUS_t XMC_FCE_CalculateCRC32Ex(const XMC_FCE_t *const engine,
661 const uint8_t *data,
662 uint32_t length,
663 uint32_t *const result);
664
665 /**
666 * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
667 * @param result Pointer to CRC result
668 * @return None
669 *
670 * \par<b>Description: </b><br>
671 * Read the final CRC value from RES register <br>
672 */
XMC_FCE_GetCRCResult(const XMC_FCE_t * const engine,uint32_t * result)673 __STATIC_INLINE void XMC_FCE_GetCRCResult(const XMC_FCE_t *const engine, uint32_t *result)
674 {
675 *result= engine->kernel_ptr->RES;
676 }
677
678 /**
679 * @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
680 * @param test values of type ::XMC_FCE_CTR_TEST_t
681 * @return None
682 *
683 * \par<b>Description: </b><br>
684 * Trigger the CTR register to generate a CRC mismatch/register mismatch/check register
685 * mismatch interrupt <br>
686 */
687 void XMC_FCE_TriggerMismatch(const XMC_FCE_t *const engine, XMC_FCE_CTR_TEST_t test);
688
689 /**
690 * @param inbuffer Pointer to input data buffer
691 * @param outbuffer Pointer to the output data buffer
692 * @param length Length of the input buffer
693 * @return None
694 *
695 * \par<b>Description: </b><br>
696 * Convert input data buffer's endianness from big endian to little endian <br>
697 *
698 * \par
699 * The function stores the converted data in output data buffer.
700 *
701 * \par<b>Note: </b><br>
702 * This function should be invoked before using ::XMC_FCE_CalculateCRC16() to compute
703 * the CRC value.
704 */
705 void XMC_FCE_LittleEndian16bit(uint8_t* inbuffer, uint16_t* outbuffer, uint16_t length);
706
707 /**
708 * @param inbuffer Pointer to input data buffer
709 * @param outbuffer Pointer to the output data buffer
710 * @param length Length of the input buffer
711 * @return None
712 *
713 * \par<b>Description: </b><br>
714 * Convert input data buffer's endianness from big endian to little endian <br>
715 *
716 * \par
717 * The function stores the converted data in output data buffer.
718 *
719 * \par<b>Note: </b><br>
720 * This function should be invoked before using ::XMC_FCE_CalculateCRC32() to compute
721 * the CRC value.
722 */
723 void XMC_FCE_LittleEndian32bit(uint8_t* inbuffer, uint32_t* outbuffer, uint16_t length);
724
725 #ifdef __cplusplus
726 }
727 #endif
728
729 /**
730 * @}
731 */
732
733 /**
734 * @}
735 */
736
737 #endif /* defined (FCE) */
738
739 #endif /* XMC_FCE_H */
740
