1 /**
2 * @file xmc_ccu4.h
3 * @date 2019-03-30
4 *
5 * @cond
6 *********************************************************************************************************************
7 * XMClib v2.1.24 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015-2019, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
22 * products derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
33 * Infineon Technologies AG dave@infineon.com).
34 *********************************************************************************************************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-02-20:
40 * - Initial <br>
41 * - Documentation updates <br>
42 *
43 * 2015-06-20:
44 * - Removed version macros and declaration of GetDriverVersion API <br>
45 *
46 * 2015-07-22:
47 * - XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent() is updated to support XMC14 device. <br>
48 *
49 * 2015-08-17:
50 * - XMC_CCU4_SLICE_PRESCALER_t enum is added to set the prescaler divider. <br>
51 * - XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t enum item names are updated according to the guidelines. <br>
52 * - XMC_CCU4_EnableShadowTransfer() API is made as inline, to improve the speed. <br>
53 *
54 * 2015-09-29:
55 * - In XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_t, two more enum items are added to support external count direction
56 * settings.
57 *
58 * 2015-10-07:
59 * - XMC_CCU4_SLICE_GetEvent() is made as inline.
60 * - XMC_CCU4_SLICE_MULTI_IRQ_ID_t is added to support the XMC_CCU4_SLICE_EnableMultipleEvents() and
61 * XMC_CCU4_SLICE_DisableMultipleEvents() APIs.
62 * - DOC updates for the newly added APIs.
63 *
64 * 2016-03-09:
65 * - Optimization of write only registers
66 *
67 * 2016-05-20:
68 * - Added XMC_CCU4_SLICE_StopClearTimer()
69 * - Changed implementation of XMC_CCU4_SLICE_StopTimer() and XMC_CCU4_SLICE_ClearTimer() to avoid RMW access
70 *
71 * 2017-04-27:
72 * - XMC_CCU4_SLICE_SetPrescaler() changed div_val parameter to type XMC_CCU4_SLICE_PRESCALER_t
73 *
74 * 2017-09-15:
75 * - Fix XMC_CCU4_SLICE_SetShadowTransferMode()
76 *
77 * 2019-03-30:
78 * - Changed XMC_CCU4_StartPrescaler(), XMC_CCU4_StopPrescaler(), XMC_CCU4_EnableMultipleClocks(), XMC_CCU4_EnableClock(), XMC_CCU4_DisableClock() to avoid RMW access
79 * - Changed XMC_CCU4_SLICE_SetEvent(), XMC_CCU4_SLICE_ClearEvent() to avoid RMW access
80 * - Added XMC_CCU4_SetSuspendMode(), XMC_CCU4_SLICE_GetPrescaler()
81 *
82 * 2019-07-29:
83 * - Added XMC_CCU4_SLICE_GetStatus()
84 *
85 * @endcond
86 */
87
88 #ifndef XMC_CCU4_H
89 #define XMC_CCU4_H
90
91 /*********************************************************************************************************************
92 * HEADER FILES
93 ********************************************************************************************************************/
94 #include "xmc_common.h"
95 #if defined(CCU40)
96
97 #if UC_FAMILY == XMC1
98 #include "xmc1_ccu4_map.h"
99 #endif
100
101 #if UC_FAMILY == XMC4
102 #include "xmc4_ccu4_map.h"
103 #endif
104
105 /**
106 * @addtogroup XMClib XMC Peripheral Library
107 * @{
108 */
109
110 /**
111 * @addtogroup CCU4
112 * @brief Capture Compare Unit 4 (CCU4) low level driver for XMC family of microcontrollers<br>
113 *
114 * The CCU4 peripheral is a major component for systems that need general purpose timers for signal
115 * monitoring/conditioning and Pulse Width Modulation (PWM) signal generation. Power electronic control systems like
116 * switched mode power supplies or interruptible power supplies, can easily be implemented with the functions inside the
117 * CCU4 peripheral.\n
118 * Each CCU4 module is comprised of four identical 16 bit Capture/Compare Timer slices, CC4y (where y = [0..4]). Each
119 * timer slice can work in compare mode or in capture mode.
120 *
121 * APIs provided in this file cover the following functional blocks of CCU4:\n
122 * -- Timer configuration, Capture configuration, Function/Event configuration, Interrupt configuration\n
123 * \par Note:
124 * 1. SLICE (APIs prefixed with e.g. XMC_CCU4_SLICE_)
125 * 2. Module (APIs are not having any prefix e.g. XMC_CCU4_)
126 *
127 * \par Timer(Compare mode) configuration:
128 * This section of the LLD provides the configuration structure XMC_CCU4_SLICE_COMPARE_CONFIG_t and the initialization
129 * function XMC_CCU4_SLICE_CompareInit().
130 *
131 * It can be used to:
132 * -# Start and Stop the timer. (XMC_CCU4_SLICE_StartTimer(), XMC_CCU4_SLICE_StopTimer())
133 * -# Update the period, compare, Dither, Prescaler and Passive values. (XMC_CCU4_SLICE_SetTimerPeriodMatch(),
134 * XMC_CCU4_SLICE_SetTimerCompareMatch(), XMC_CCU4_SLICE_SetPrescaler(), XMC_CCU4_SLICE_SetDitherCompareValue(),
135 * XMC_CCU4_SLICE_SetPassiveLevel())
136 * -# Enable the slices to support multichannel mode. (XMC_CCU4_SLICE_EnableMultiChannelMode())
137 *
138 * \par Capture configuration:
139 * This section of the LLD provides the configuration structure XMC_CCU4_SLICE_CAPTURE_CONFIG_t and the initialization
140 * function XMC_CCU4_SLICE_CaptureInit().
141 *
142 * It can be used to:
143 * -# Configure the capture functionality. (XMC_CCU4_SLICE_Capture0Config(), XMC_CCU4_SLICE_Capture1Config())
144 * -# Read the captured values along with the status, which indicate the value is latest or not.
145 * (XMC_CCU4_SLICE_GetCaptureRegisterValue())
146 *
147 * \par Function/Event configuration:
148 * This section of the LLD provides the configuration structure XMC_CCU4_SLICE_EVENT_CONFIG_t.\n
149 *
150 * It can be used to:
151 * -# Enable and Disable the events. (XMC_CCU4_SLICE_EnableEvent(), XMC_CCU4_SLICE_DisableEvent())
152 * -# Configure to start and stop the timer on external events.(XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_StopConfig())
153 * -# Modulation, external load and Gating of the timer output.(XMC_CCU4_SLICE_ModulationConfig(),
154 * XMC_CCU4_SLICE_LoadConfig(), XMC_CCU4_SLICE_GateConfig())
155 * -# Control the count direction of the timer based on the external event. (XMC_CCU4_SLICE_DirectionConfig())
156 * -# Count the external events.(XMC_CCU4_SLICE_CountConfig())
157 * -# External Trap. Which can be used as protective feature.(XMC_CCU4_SLICE_EnableTrap(), XMC_CCU4_SLICE_DisableTrap(),
158 * XMC_CCU4_SLICE_TrapConfig())
159 *
160 * \par Interrupt configuration:
161 * This section of the LLD provides the function to configure the interrupt node to each event (XMC_CCU4_SLICE_SetInterruptNode())
162 * @{
163 */
164
165 /*********************************************************************************************************************
166 * MACROS
167 ********************************************************************************************************************/
168 /* Macro to check if the interrupt enum passed is valid */
169 #define XMC_CCU4_SLICE_CHECK_INTERRUPT(interrupt) \
170 ((interrupt == XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH) || \
171 (interrupt == XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH) || \
172 (interrupt == XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP) || \
173 (interrupt == XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN)|| \
174 (interrupt == XMC_CCU4_SLICE_IRQ_ID_EVENT0) || \
175 (interrupt == XMC_CCU4_SLICE_IRQ_ID_EVENT1) || \
176 (interrupt == XMC_CCU4_SLICE_IRQ_ID_EVENT2) || \
177 (interrupt == XMC_CCU4_SLICE_IRQ_ID_TRAP))
178
179 /*********************************************************************************************************************
180 * ENUMS
181 ********************************************************************************************************************/
182
183 /**
184 * Typedef for CCU4 Global data structure
185 */
186 typedef CCU4_GLOBAL_TypeDef XMC_CCU4_MODULE_t;
187
188 /**
189 * Typedef for CCU4 Slice data structure
190 */
191 typedef CCU4_CC4_TypeDef XMC_CCU4_SLICE_t;
192
193 /**
194 * Return Value of an API
195 */
196 typedef enum XMC_CCU4_STATUS
197 {
198 XMC_CCU4_STATUS_OK = 0U, /**< API fulfils request */
199 XMC_CCU4_STATUS_ERROR , /**< API cannot fulfil the request */
200 XMC_CCU4_STATUS_RUNNING , /**< The timer slice is currently running */
201 XMC_CCU4_STATUS_IDLE /**< The timer slice is currently idle */
202 } XMC_CCU4_STATUS_t;
203
204 /**
205 * CCU4 module clock
206 */
207 typedef enum XMC_CCU4_CLOCK
208 {
209 XMC_CCU4_CLOCK_SCU = 0U, /**< Select the fCCU as the clock */
210 XMC_CCU4_CLOCK_EXTERNAL_A , /**< External clock-A */
211 XMC_CCU4_CLOCK_EXTERNAL_B , /**< External clock-B */
212 XMC_CCU4_CLOCK_EXTERNAL_C /**< External clock-C */
213 } XMC_CCU4_CLOCK_t;
214
215 /**
216 * CCU4 set the shadow transfer type for multichannel mode
217 */
218 typedef enum XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER
219 {
220 XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE0 = (uint32_t)0x4000000, /**< Shadow transfer through software
221 only for slice 0*/
222 XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE0 = (uint32_t)0x4000400, /**< Shadow transfer through software
223 and hardware for slice 0 */
224 XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE1 = (uint32_t)0x8000000, /**< Shadow transfer through software
225 only for slice 1*/
226 XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE1 = (uint32_t)0x8000800, /**< Shadow transfer through software
227 and hardware for slice 1 */
228 XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE2 = (uint32_t)0x10000000, /**< Shadow transfer through software
229 only for slice 2 */
230 XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE2 = (uint32_t)0x10001000, /**< Shadow transfer through software
231 and hardware for slice 2 */
232 XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE3 = (uint32_t)0x20000000, /**< Shadow transfer through software
233 only for slice 3*/
234 XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE3 = (uint32_t)0x20002000 /**< Shadow transfer through software
235 and hardware for slice 3 */
236 } XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_t;
237
238 /**
239 * Operational modes of CCU4 slice
240 */
241 typedef enum XMC_CCU4_SLICE_MODE
242 {
243 XMC_CCU4_SLICE_MODE_COMPARE = 0U, /**< slice(CC4y) operates in Compare Mode */
244 XMC_CCU4_SLICE_MODE_CAPTURE /**< slice(CC4y) operates in Capture Mode */
245 } XMC_CCU4_SLICE_MODE_t;
246
247 /**
248 * Timer counting modes for the slice
249 */
250 typedef enum XMC_CCU4_SLICE_TIMER_COUNT_MODE
251 {
252 XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA = 0U, /**< Edge Aligned Mode */
253 XMC_CCU4_SLICE_TIMER_COUNT_MODE_CA /**< Center Aligned Mode */
254 } XMC_CCU4_SLICE_TIMER_COUNT_MODE_t;
255
256 /**
257 * Timer repetition mode for the slice
258 */
259 typedef enum XMC_CCU4_SLICE_TIMER_REPEAT_MODE
260 {
261 XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT = 0U, /**< Repetitive mode: continuous mode of operation */
262 XMC_CCU4_SLICE_TIMER_REPEAT_MODE_SINGLE /**< Single shot mode: Once a Period match/One match
263 occurs timer goes to idle state */
264 } XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t;
265
266 /**
267 * Timer counting direction for the CCU4 slice
268 */
269 typedef enum XMC_CCU4_SLICE_TIMER_COUNT_DIR
270 {
271 XMC_CCU4_SLICE_TIMER_COUNT_DIR_UP = 0U, /**< Counting up */
272 XMC_CCU4_SLICE_TIMER_COUNT_DIR_DOWN /**< Counting down */
273 } XMC_CCU4_SLICE_TIMER_COUNT_DIR_t;
274
275 /**
276 * Capture mode register sets
277 */
278 typedef enum XMC_CCU4_SLICE_CAP_REG_SET
279 {
280 XMC_CCU4_SLICE_CAP_REG_SET_LOW = 0U, /**< Capture register-0, Capture register-1 used */
281 XMC_CCU4_SLICE_CAP_REG_SET_HIGH /**< Capture register-2, Capture register-3 used */
282 } XMC_CCU4_SLICE_CAP_REG_SET_t;
283
284 /**
285 * Prescaler mode
286 */
287 typedef enum XMC_CCU4_SLICE_PRESCALER_MODE
288 {
289 XMC_CCU4_SLICE_PRESCALER_MODE_NORMAL = 0U, /**< Fixed division of module clock */
290 XMC_CCU4_SLICE_PRESCALER_MODE_FLOAT /**< Floating divider. */
291 } XMC_CCU4_SLICE_PRESCALER_MODE_t;
292
293 /**
294 * Timer output passive level
295 */
296 typedef enum XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL
297 {
298 XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW = 0U, /**< Passive level = Low */
299 XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH /**< Passive level = High */
300 } XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t;
301
302 /**
303 * Timer clock Divider
304 */
305 typedef enum XMC_CCU4_SLICE_PRESCALER
306 {
307 XMC_CCU4_SLICE_PRESCALER_1 = 0U, /**< Slice Clock = fccu4 */
308 XMC_CCU4_SLICE_PRESCALER_2 , /**< Slice Clock = fccu4/2 */
309 XMC_CCU4_SLICE_PRESCALER_4 , /**< Slice Clock = fccu4/4 */
310 XMC_CCU4_SLICE_PRESCALER_8 , /**< Slice Clock = fccu4/8 */
311 XMC_CCU4_SLICE_PRESCALER_16 , /**< Slice Clock = fccu4/16 */
312 XMC_CCU4_SLICE_PRESCALER_32 , /**< Slice Clock = fccu4/32 */
313 XMC_CCU4_SLICE_PRESCALER_64 , /**< Slice Clock = fccu4/64 */
314 XMC_CCU4_SLICE_PRESCALER_128 , /**< Slice Clock = fccu4/128 */
315 XMC_CCU4_SLICE_PRESCALER_256 , /**< Slice Clock = fccu4/256 */
316 XMC_CCU4_SLICE_PRESCALER_512 , /**< Slice Clock = fccu4/512 */
317 XMC_CCU4_SLICE_PRESCALER_1024 , /**< Slice Clock = fccu4/1024 */
318 XMC_CCU4_SLICE_PRESCALER_2048 , /**< Slice Clock = fccu4/2048 */
319 XMC_CCU4_SLICE_PRESCALER_4096 , /**< Slice Clock = fccu4/4096 */
320 XMC_CCU4_SLICE_PRESCALER_8192 , /**< Slice Clock = fccu4/8192 */
321 XMC_CCU4_SLICE_PRESCALER_16384 , /**< Slice Clock = fccu4/16384 */
322 XMC_CCU4_SLICE_PRESCALER_32768 /**< Slice Clock = fccu4/32768 */
323 } XMC_CCU4_SLICE_PRESCALER_t;
324
325 /**
326 * External Function list
327 */
328 typedef enum XMC_CCU4_SLICE_FUNCTION
329 {
330 XMC_CCU4_SLICE_FUNCTION_START = 0U, /**< Start function */
331 XMC_CCU4_SLICE_FUNCTION_STOP , /**< Stop function */
332 XMC_CCU4_SLICE_FUNCTION_CAPTURE_EVENT0 , /**< Capture Event-0 function, CCycapt0 signal is used for event
333 generation */
334 XMC_CCU4_SLICE_FUNCTION_CAPTURE_EVENT1 , /**< Capture Event-1 function, CCycapt1 signal is used for event
335 generation */
336 XMC_CCU4_SLICE_FUNCTION_GATING , /**< Gating function */
337 XMC_CCU4_SLICE_FUNCTION_DIRECTION , /**< Direction function */
338 XMC_CCU4_SLICE_FUNCTION_LOAD , /**< Load function */
339 XMC_CCU4_SLICE_FUNCTION_COUNT , /**< Counting function */
340 XMC_CCU4_SLICE_FUNCTION_OVERRIDE , /**< Override function */
341 XMC_CCU4_SLICE_FUNCTION_MODULATION , /**< Modulation function */
342 XMC_CCU4_SLICE_FUNCTION_TRAP /**< Trap function */
343 } XMC_CCU4_SLICE_FUNCTION_t;
344
345 /**
346 * External Event list
347 */
348 typedef enum XMC_CCU4_SLICE_EVENT
349 {
350 XMC_CCU4_SLICE_EVENT_NONE = 0U, /**< None */
351 XMC_CCU4_SLICE_EVENT_0 , /**< Event-0 */
352 XMC_CCU4_SLICE_EVENT_1 , /**< Event-1 */
353 XMC_CCU4_SLICE_EVENT_2 /**< Event-2 */
354 } XMC_CCU4_SLICE_EVENT_t;
355
356 /**
357 * External Event trigger criteria - Edge sensitivity
358 */
359 typedef enum XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY
360 {
361 XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE = 0U, /**< None */
362 XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE , /**< Rising Edge of the input signal generates event trigger*/
363 XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE , /**< Falling Edge of the input signal generates event
364 trigger */
365 XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE /**< Both Rising and Falling edges cause an event trigger*/
366 } XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_t;
367
368 /**
369 * External Event trigger criteria - Level sensitivity
370 */
371 typedef enum XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY
372 {
373 XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH = 0U, /**< Level sensitive functions react to a high signal level*/
374 XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW = 1U, /**< Level sensitive functions react to a low signal level*/
375 /* Below enum items can be utilised specific to the functionality */
376 XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_LOW = 0U, /**< Timer counts up, during Low state of the control signal */
377 XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_HIGH = 1U /**< Timer counts up, during High state of the control signal */
378 } XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_t;
379
380 /**
381 * Low pass filter Configuration. The External Event input should be stable for a selected number of clock cycles.
382 */
383 typedef enum XMC_CCU4_SLICE_EVENT_FILTER
384 {
385 XMC_CCU4_SLICE_EVENT_FILTER_DISABLED = 0U, /**< No Low Pass Filter */
386 XMC_CCU4_SLICE_EVENT_FILTER_3_CYCLES , /**< 3 clock cycles */
387 XMC_CCU4_SLICE_EVENT_FILTER_5_CYCLES , /**< 5 clock cycles */
388 XMC_CCU4_SLICE_EVENT_FILTER_7_CYCLES /**< 7 clock cycles */
389 } XMC_CCU4_SLICE_EVENT_FILTER_t;
390
391 /**
392 * External Event Input list. This list depicts the possible input connections to the CCU4 slice.
393 * Interconnects are specific to each device.
394 */
395 typedef uint8_t XMC_CCU4_SLICE_INPUT_t;
396
397 /**
398 * Actions that can be performed upon detection of an external Timer STOP event
399 */
400 typedef enum XMC_CCU4_SLICE_END_MODE
401 {
402 XMC_CCU4_SLICE_END_MODE_TIMER_STOP = 0U, /**< Stops the timer, without clearing TIMER register */
403 XMC_CCU4_SLICE_END_MODE_TIMER_CLEAR , /**< Without stopping timer, clears the TIMER register */
404 XMC_CCU4_SLICE_END_MODE_TIMER_STOP_CLEAR /**< Stops the timer and clears the TIMER register */
405 } XMC_CCU4_SLICE_END_MODE_t;
406
407 /**
408 * Actions that can be performed upon detection of an external Timer START event
409 */
410 typedef enum XMC_CCU4_SLICE_START_MODE
411 {
412 XMC_CCU4_SLICE_START_MODE_TIMER_START = 0U, /**< Start the timer from the current count of TIMER register */
413 XMC_CCU4_SLICE_START_MODE_TIMER_START_CLEAR /**< Clears the TIMER register and start the timer */
414 } XMC_CCU4_SLICE_START_MODE_t;
415
416 /**
417 * Modulation of timer output signals
418 */
419 typedef enum XMC_CCU4_SLICE_MODULATION_MODE
420 {
421 XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_ST_OUT = 0U, /**< Clear ST and OUT signals */
422 XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_OUT /**< Clear only the OUT signal */
423 } XMC_CCU4_SLICE_MODULATION_MODE_t;
424
425 /**
426 * Trap exit mode
427 */
428 typedef enum XMC_CCU4_SLICE_TRAP_EXIT_MODE
429 {
430 XMC_CCU4_SLICE_TRAP_EXIT_MODE_AUTOMATIC = 0U, /**< Clear trap state as soon as the trap signal is de-asserted */
431 XMC_CCU4_SLICE_TRAP_EXIT_MODE_SW /**< Clear only when acknowledged by software */
432 } XMC_CCU4_SLICE_TRAP_EXIT_MODE_t;
433
434 /**
435 * Timer clear on capture
436 */
437 typedef enum XMC_CCU4_SLICE_TIMER_CLEAR_MODE
438 {
439 XMC_CCU4_SLICE_TIMER_CLEAR_MODE_NEVER = 0U, /**< Never clear the timer on any capture event */
440 XMC_CCU4_SLICE_TIMER_CLEAR_MODE_CAP_HIGH , /**< Clear only when timer value has been captured in C3V and C2V */
441 XMC_CCU4_SLICE_TIMER_CLEAR_MODE_CAP_LOW , /**< Clear only when timer value has been captured in C1V and C0V */
442 XMC_CCU4_SLICE_TIMER_CLEAR_MODE_ALWAYS /**< Always clear the timer upon detection of any capture event */
443 } XMC_CCU4_SLICE_TIMER_CLEAR_MODE_t;
444
445 /**
446 * Multi Channel Shadow transfer request configuration options
447 */
448 typedef enum XMC_CCU4_SLICE_MCMS_ACTION
449 {
450 XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR = 0U, /**< Transfer Compare and Period Shadow register values to
451 the actual registers upon MCS xfer request */
452 XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP = 1U, /**< Transfer Compare, Period and Prescaler Compare Shadow
453 register values to the actual registers upon MCS xfer
454 request */
455 XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT = 3U /**< Transfer Compare, Period ,Prescaler Compare and Dither
456 Compare register values to the actual registers upon
457 MCS xfer request */
458 } XMC_CCU4_SLICE_MCMS_ACTION_t;
459
460 /**
461 * Available Interrupt Event Ids
462 */
463 typedef enum XMC_CCU4_SLICE_IRQ_ID
464 {
465 XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH = 0U , /**< Period match counting up */
466 XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH = 1U , /**< Period match -> One match counting down */
467 XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP = 2U , /**< Compare match counting up */
468 XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN = 3U , /**< Compare match counting down */
469 XMC_CCU4_SLICE_IRQ_ID_EVENT0 = 8U , /**< Event-0 occurrence */
470 XMC_CCU4_SLICE_IRQ_ID_EVENT1 = 9U , /**< Event-1 occurrence */
471 XMC_CCU4_SLICE_IRQ_ID_EVENT2 = 10U, /**< Event-2 occurrence */
472 XMC_CCU4_SLICE_IRQ_ID_TRAP = 11U /**< Trap occurrence */
473 } XMC_CCU4_SLICE_IRQ_ID_t;
474
475 /**
476 * Available Interrupt Event Ids, which is added to support multi event APIs
477 */
478 typedef enum XMC_CCU4_SLICE_MULTI_IRQ_ID
479 {
480 XMC_CCU4_SLICE_MULTI_IRQ_ID_PERIOD_MATCH = 0x1U, /**< Period match counting up */
481 XMC_CCU4_SLICE_MULTI_IRQ_ID_ONE_MATCH = 0x2U, /**< Period match -> One match counting down */
482 XMC_CCU4_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_UP = 0x4U, /**< Compare match counting up */
483 XMC_CCU4_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_DOWN = 0x8U, /**< Compare match counting down */
484 XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT0 = 0x100U, /**< Event-0 occurrence */
485 XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT1 = 0x200U, /**< Event-1 occurrence */
486 XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT2 = 0x400U, /**< Event-2 occurrence */
487 } XMC_CCU4_SLICE_MULTI_IRQ_ID_t;
488
489 /**
490 * Service Request Lines for CCU4. Event are mapped to these SR lines and these are used to generate the interrupt.
491 */
492 typedef enum XMC_CCU4_SLICE_SR_ID
493 {
494 XMC_CCU4_SLICE_SR_ID_0 = 0U, /**< Service Request Line-0 selected */
495 XMC_CCU4_SLICE_SR_ID_1 , /**< Service Request Line-1 selected */
496 XMC_CCU4_SLICE_SR_ID_2 , /**< Service Request Line-2 selected */
497 XMC_CCU4_SLICE_SR_ID_3 /**< Service Request Line-3 selected */
498 } XMC_CCU4_SLICE_SR_ID_t;
499
500 /**
501 * Slice shadow transfer options.
502 */
503 typedef enum XMC_CCU4_SHADOW_TRANSFER
504 {
505 XMC_CCU4_SHADOW_TRANSFER_SLICE_0 = CCU4_GCSS_S0SE_Msk, /**< Transfer Period, Compare and Passive Level
506 shadow register values to actual registers for
507 SLICE-0 */
508 XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_0 = CCU4_GCSS_S0DSE_Msk, /**< Transfer Dither compare shadow register value
509 to actual register for SLICE-0 */
510 XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_0 = CCU4_GCSS_S0PSE_Msk, /**< Transfer Prescaler shadow register value to
511 actual register for SLICE-0 */
512 XMC_CCU4_SHADOW_TRANSFER_SLICE_1 = CCU4_GCSS_S1SE_Msk, /**< Transfer Period, Compare and Passive Level
513 shadow register values to actual registers for
514 SLICE-1 */
515 XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_1 = CCU4_GCSS_S1DSE_Msk, /**< Transfer Dither compare shadow register value
516 to actual registers for SLICE-1 */
517 XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_1 = CCU4_GCSS_S1PSE_Msk, /**< Transfer Prescaler shadow register value to
518 actual register for SLICE-1 */
519 XMC_CCU4_SHADOW_TRANSFER_SLICE_2 = CCU4_GCSS_S2SE_Msk, /**< Transfer Period, Compare and Passive Level
520 shadow register values to actual registers for
521 SLICE-2 */
522 XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_2 = CCU4_GCSS_S2DSE_Msk, /**< Transfer Dither compare shadow register value
523 to actual register for SLICE-2 */
524 XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_2 = CCU4_GCSS_S2PSE_Msk, /**< Transfer Prescaler shadow register value to
525 actual register for SLICE-2 */
526 XMC_CCU4_SHADOW_TRANSFER_SLICE_3 = CCU4_GCSS_S3SE_Msk, /**< Transfer Period, Compare and Passive Level
527 shadow register values to actual registers for
528 SLICE-3 */
529 XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_3 = CCU4_GCSS_S3DSE_Msk, /**< Transfer Dither compare shadow register value
530 to actual register for SLICE-3 */
531 XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_3 = CCU4_GCSS_S3PSE_Msk /**< Transfer Prescaler shadow register value to
532 actual register for SLICE-3 */
533 } XMC_CCU4_SHADOW_TRANSFER_t;
534
535 #if defined(CCU4V3) || defined(DOXYGEN)/* Defined for XMC1400 devices only */
536 /**
537 * Slice shadow transfer mode options.
538 * @note Only available for XMC1400 series
539 */
540 typedef enum XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE
541 {
542 XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_IN_PERIOD_MATCH_AND_ONE_MATCH = 0U, /**< Shadow transfer is done in Period Match and
543 One match. */
544 XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_PERIOD_MATCH = 1U, /**< Shadow transfer is done only in Period Match. */
545 XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_ONE_MATCH = 2U /**< Shadow transfer is done only in One Match. */
546 } XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t;
547
548
549 /**
550 * Immediate write into configuration register
551 * @note Only available for XMC1400 series
552 */
553 typedef enum XMC_CCU4_SLICE_WRITE_INTO
554 {
555 XMC_CCU4_SLICE_WRITE_INTO_PERIOD_CONFIGURATION = CCU4_CC4_STC_IRPC_Msk, /**< Immediate or Coherent
556 Write into Period
557 Configuration */
558 XMC_CCU4_SLICE_WRITE_INTO_COMPARE_CONFIGURATION = CCU4_CC4_STC_IRCC_Msk, /**< Immediate or Coherent
559 Write into Compare
560 Configuration */
561 XMC_CCU4_SLICE_WRITE_INTO_PASSIVE_LEVEL_CONFIGURATION = CCU4_CC4_STC_IRLC_Msk, /**< Immediate or Coherent
562 Write into Passive Level
563 Configuration */
564 XMC_CCU4_SLICE_WRITE_INTO_DITHER_VALUE_CONFIGURATION = CCU4_CC4_STC_IRDC_Msk, /**< Immediate or Coherent
565 Write into Dither Value
566 Configuration */
567 XMC_CCU4_SLICE_WRITE_INTO_FLOATING_PRESCALER_VALUE_CONFIGURATION = CCU4_CC4_STC_IRFC_Msk /**< Immediate or Coherent
568 Write into Floating Prescaler
569 Value Configuration */
570 } XMC_CCU4_SLICE_WRITE_INTO_t;
571
572
573 /**
574 * Automatic Shadow Transfer request when writing into shadow register
575 * @note Only available for XMC1400 series
576 */
577 typedef enum XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO
578 {
579 XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_PERIOD_SHADOW = CCU4_CC4_STC_ASPC_Msk, /**< Automatic Shadow
580 Transfer request when
581 writing into Period
582 Shadow Register */
583 XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_COMPARE_SHADOW = CCU4_CC4_STC_ASCC_Msk, /**< Automatic Shadow
584 transfer request
585 when writing into
586 Compare Shadow Register */
587 XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_PASSIVE_LEVEL = CCU4_CC4_STC_ASLC_Msk, /**< Automatic Shadow transfer
588 request when writing
589 into Passive Level Register*/
590 XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_DITHER_SHADOW = CCU4_CC4_STC_ASDC_Msk, /**< Automatic Shadow transfer
591 request when writing
592 into Dither Shadow Register */
593 XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_FLOATING_PRESCALER_SHADOW = CCU4_CC4_STC_ASFC_Msk /**< Automatic Shadow transfer
594 request when writing
595 into Floating Prescaler Shadow
596 register */
597
598 } XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t;
599 #endif
600 /**
601 * Used to create Mask needed for Multi-channel Shadow transfer enable/disable
602 */
603 typedef enum XMC_CCU4_SLICE_MASK
604 {
605 XMC_CCU4_SLICE_MASK_SLICE_0 = 1U , /**< SLICE-0 */
606 XMC_CCU4_SLICE_MASK_SLICE_1 = 2U , /**< SLICE-1 */
607 XMC_CCU4_SLICE_MASK_SLICE_2 = 4U , /**< SLICE-2 */
608 XMC_CCU4_SLICE_MASK_SLICE_3 = 8U /**< SLICE-3 */
609 } XMC_CCU4_SLICE_MASK_t;
610
611 /**
612 * Selects suspend mode
613 */
614 typedef enum XMC_CCU4_SUSPEND_MODE
615 {
616 XMC_CCU4_SUSPEND_MODE_IGNORE = 0 << CCU4_GCTRL_SUSCFG_Pos, /**< Suspend request ignored. The module never enters in suspend */
617 XMC_CCU4_SUSPEND_MODE_STOPS_INMEDIATELLY = 1 << CCU4_GCTRL_SUSCFG_Pos, /**< Stops all the running slices immediately. Safe stop is not applied. */
618 XMC_CCU4_SUSPEND_MODE_SAFE_STOP = 2 << CCU4_GCTRL_SUSCFG_Pos, /**< Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied. */
619 XMC_CCU4_SUSPEND_MODE_WAIT_ROLL_OVER = 3 << CCU4_GCTRL_SUSCFG_Pos /**< Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied. */
620 } XMC_CCU4_SUSPEND_MODE_t;
621
622
623 /**
624 * CCU4 slice status bit
625 */
626 typedef enum XMC_CCU4_SLICE_STATUS_BIT
627 {
628 XMC_CCU4_SLICE_STATUS_BIT_PASSIVE = false, /**< Passive */
629 XMC_CCU4_SLICE_STATUS_BIT_ACTIVE = true /**< Active */
630 } XMC_CCU4_SLICE_STATUS_BIT_t;
631
632
633 /*********************************************************************************************************************
634 * DATA STRUCTURES
635 ********************************************************************************************************************/
636
637 /**
638 * Configuration data structure of an External Event(Event-0/1/2).
639 * Needed to configure the various aspects of an External Event.
640 * This structure will not connect the external event with an external function.
641 */
642 typedef struct XMC_CCU4_SLICE_EVENT_CONFIG
643 {
644 XMC_CCU4_SLICE_INPUT_t mapped_input; /**< Required input signal for the Event */
645 XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_t edge; /**< Select the event edge of the input signal.
646 This is needed for an edge sensitive External function.*/
647 XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_t level; /**< Select the event level of the input signal.
648 This is needed for an level sensitive External function.*/
649 XMC_CCU4_SLICE_EVENT_FILTER_t duration; /**< Low Pass filter duration in terms of fCCU clock cycles */
650 } XMC_CCU4_SLICE_EVENT_CONFIG_t;
651
652 /*Anonymous structure/union guard start*/
653 #if defined(__CC_ARM)
654 #pragma push
655 #pragma anon_unions
656 #elif defined(__TASKING__)
657 #pragma warning 586
658 #endif
659
660 /**
661 * Configuration data structure for CCU4 slice. Specifically configures the CCU4 slice to compare mode operation.
662 * This excludes event and function configuration.
663 */
664 typedef struct XMC_CCU4_SLICE_COMPARE_CONFIG
665 {
666 union
667 {
668 struct
669 {
670 uint32_t timer_mode : 1; /**< Edge aligned or Centre Aligned.
671 Accepts enum ::XMC_CCU4_SLICE_TIMER_COUNT_MODE_t */
672 uint32_t monoshot : 1; /**< Single shot or Continuous mode .
673 Accepts enum :: XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t*/
674 uint32_t shadow_xfer_clear : 1; /**< Should PR and CR shadow xfer happen when timer is cleared? */
675 uint32_t : 10;
676 uint32_t dither_timer_period: 1; /**< Can the period of the timer dither? */
677 uint32_t dither_duty_cycle : 1; /**< Can the compare match of the timer dither? */
678 uint32_t : 1;
679 uint32_t prescaler_mode: 1; /**< Normal or floating prescaler mode.
680 Accepts enum :: XMC_CCU4_SLICE_PRESCALER_MODE_t*/
681 uint32_t : 8;
682 uint32_t mcm_enable : 1; /**< Multi-Channel mode enable? */
683 uint32_t : 6;
684 };
685 uint32_t tc;
686 };
687 uint32_t prescaler_initval : 4; /**< Initial prescaler divider value
688 Accepts enum :: XMC_CCU4_SLICE_PRESCALER_t */
689 uint32_t float_limit : 4; /**< The max value which the prescaler divider can increment to */
690 uint32_t dither_limit : 4; /**< The value that determines the spreading of dithering */
691 uint32_t passive_level : 1; /**< Configuration of ST and OUT passive levels.
692 Accepts enum :: XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t*/
693 uint32_t timer_concatenation : 1; /**< Enables the concatenation of the timer if true.*/
694 } XMC_CCU4_SLICE_COMPARE_CONFIG_t;
695
696 /**
697 * Configuration data structure for CCU4 slice. Specifically configures the CCU4 slice to capture mode operation.
698 * This excludes event and function configuration.
699 */
700 typedef struct XMC_CCU4_SLICE_CAPTURE_CONFIG
701 {
702 union
703 {
704 struct
705 {
706 uint32_t : 4;
707 uint32_t fifo_enable : 1; /**< Should the capture registers be setup as a FIFO?(Extended capture mode)*/
708 uint32_t timer_clear_mode : 2; /**< How should the timer register be cleared upon detection of capture event?
709 Accepts enum ::XMC_CCU4_SLICE_TIMER_CLEAR_MODE_t*/
710 uint32_t : 4;
711 uint32_t same_event : 1; /**< Should the capture event for C1V/C0V and C3V/C2V be same capture edge? */
712 uint32_t ignore_full_flag : 1; /**< Should updates to capture registers follow full flag rules? */
713 uint32_t : 3;
714 uint32_t prescaler_mode: 1; /**< Normal or floating prescaler Accepts enum :: XMC_CCU4_SLICE_PRESCALER_MODE_t*/
715 uint32_t : 15;
716 };
717 uint32_t tc;
718 };
719 uint32_t prescaler_initval : 4; /**< Prescaler divider value */
720 uint32_t float_limit : 4; /**< The max value which the prescaler divider can increment to */
721 uint32_t timer_concatenation : 1; /**< Enables the concatenation of the timer */
722 } XMC_CCU4_SLICE_CAPTURE_CONFIG_t;
723 /*Anonymous structure/union guard end*/
724 #if defined(__CC_ARM)
725 #pragma pop
726 #elif defined(__TASKING__)
727 #pragma warning restore
728 #endif
729 /*********************************************************************************************************************
730 * API Prototypes
731 ********************************************************************************************************************/
732
733 #ifdef __cplusplus
734 extern "C" {
735 #endif
736
XMC_CCU4_IsValidModule(const XMC_CCU4_MODULE_t * const module)737 __STATIC_INLINE bool XMC_CCU4_IsValidModule(const XMC_CCU4_MODULE_t *const module)
738 {
739 bool tmp = false;
740
741 tmp = (module == CCU40);
742
743 #if defined(CCU41)
744 tmp = tmp || (module == CCU41);
745 #endif
746
747 #if defined(CCU42)
748 tmp = tmp || (module == CCU42);
749 #endif
750
751 #if defined(CCU43)
752 tmp = tmp || (module == CCU43);
753 #endif
754
755 return tmp;
756 }
757
XMC_CCU4_IsValidSlice(const XMC_CCU4_SLICE_t * const slice)758 __STATIC_INLINE bool XMC_CCU4_IsValidSlice(const XMC_CCU4_SLICE_t *const slice)
759 {
760 bool tmp = false;
761
762 tmp = (slice == CCU40_CC40);
763 #if defined(CCU40_CC41)
764 tmp = tmp || (slice == CCU40_CC41);
765 #endif
766 #if defined(CCU40_CC42)
767 tmp = tmp || (slice == CCU40_CC42);
768 #endif
769 #if defined(CCU40_CC43)
770 tmp = tmp || (slice == CCU40_CC43);
771 #endif
772 #if defined(CCU41)
773 tmp = tmp || (slice == CCU41_CC40);
774 #if defined(CCU41_CC41)
775 tmp = tmp || (slice == CCU41_CC41);
776 #endif
777 #if defined(CCU41_CC42)
778 tmp = tmp || (slice == CCU41_CC42);
779 #endif
780 #if defined(CCU41_CC43)
781 tmp = tmp || (slice == CCU41_CC43);
782 #endif
783 #endif
784 #if defined(CCU42)
785 tmp = tmp || (slice == CCU42_CC40);
786 #if defined(CCU42_CC41)
787 tmp = tmp || (slice == CCU42_CC41);
788 #endif
789 #if defined(CCU42_CC42)
790 tmp = tmp || (slice == CCU42_CC42);
791 #endif
792 #if defined(CCU42_CC43)
793 tmp = tmp || (slice == CCU42_CC43);
794 #endif
795 #endif
796 #if defined(CCU43)
797 tmp = tmp || (slice == CCU43_CC40);
798 #if defined(CCU43_CC41)
799 tmp = tmp || (slice == CCU43_CC41);
800 #endif
801 #if defined(CCU43_CC42)
802 tmp = tmp || (slice == CCU43_CC42);
803 #endif
804 #if defined(CCU43_CC43)
805 tmp = tmp || (slice == CCU43_CC43);
806 #endif
807 #endif
808
809 return tmp;
810 }
811
812 /**
813 * @param module Constant pointer to CCU4 module
814 * @param mcs_action multi-channel shadow transfer request configuration
815 * @return <BR>
816 * None<BR>
817 *
818 * \par<b>Description:</b><br>
819 * Initialization of global register GCTRL.<br>\n
820 * As part of module initialization, behaviour of the module upon detection
821 * Multi-Channel Mode trigger is configured. Will also invoke the XMC_CCU4_EnableModule().
822 * The API call would bring up the required CCU4 module and also initialize the module for
823 * the required multi-channel shadow transfer.
824 *
825 * \par<b>Related APIs:</b><br>
826 * XMC_CCU4_SLICE_CompareInit()<BR> XMC_CCU4_SLICE_CaptureInit().
827 */
828 void XMC_CCU4_Init(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_SLICE_MCMS_ACTION_t mcs_action);
829
830 /**
831 * @param module Constant pointer to CCU4 module
832 * @param clock Choice of input clock to the module
833 * @return <BR>
834 * None<BR>
835 *
836 * \par<b>Description:</b><br>
837 * Selects the Module Clock by configuring GCTRL.PCIS bits.<BR>\n
838 * There are 3 potential clock sources. This API helps to select the required clock source.
839 * Call to this API is valid after the XMC_CCU4_Init().
840 *
841 * \par<b>Related APIs:</b><br>
842 * None.<BR>
843 */
844 void XMC_CCU4_SetModuleClock(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_CLOCK_t clock);
845
846 /**
847 * @param module Constant pointer to CCU4 module
848 * @return <BR>
849 * None<BR>
850 *
851 * \par<b>Description:</b><br>
852 * Enables the CCU4 module and brings it to active state.<BR>\n
853 * Also disables the gating of the clock signal (if applicable depending on the device being selected).
854 * Invoke this API before any operations are done on the CCU4 module. Invoked from XMC_CCU4_Init().
855 *
856 * \par<b>Related APIs:</b><br>
857 * XMC_CCU4_SetModuleClock()<BR> XMC_CCU4_DisableModule()<BR> XMC_CCU4_StartPrescaler().
858 */
859 void XMC_CCU4_EnableModule(XMC_CCU4_MODULE_t *const module);
860
861 /**
862 * @param module Constant pointer to CCU4 module
863 * @return <BR>
864 * None<BR>
865 *
866 * \par<b>Description:</b><br>
867 * Brings the CCU4 module to reset state and enables gating of the clock signal(if applicable depending
868 * on the device being selected).<BR>\n
869 * Invoke this API when a CCU4 module needs to be disabled completely.
870 * Any operation on the CCU4 module will have no effect after this API is called.
871 *
872 * \par<b>Related APIs:</b><br>
873 * XMC_CCU4_EnableModule()<BR> XMC_CCU4_DisableModule().
874 */
875 void XMC_CCU4_DisableModule(XMC_CCU4_MODULE_t *const module);
876
877 /**
878 * @param module Constant pointer to CCU4 module
879 * @return <BR>
880 * None<BR>
881 *
882 * \par<b>Description:</b><br>
883 * Starts the prescaler and restores clocks to the timer slices, by setting GIDLC.SPRB bit.<BR>\n
884 * Once the input to the prescaler has been chosen and the prescaler divider of all slices programmed,
885 * the prescaler itself may be started. Invoke this API after XMC_CCU4_Init()
886 * (Mandatory to fully initialize the module).Directly accessed register is GIDLC.
887 *
888 * \par<b>Related APIs:</b><br>
889 * XMC_CCU4_Init()<BR> XMC_CCU4_EnableClock()<BR> XMC_CCU4_DisableClock()<BR> XMC_CCU4_StartPrescaler()<BR>
890 * XMC_CCU4_StopPrescaler().
891 */
XMC_CCU4_StartPrescaler(XMC_CCU4_MODULE_t * const module)892 __STATIC_INLINE void XMC_CCU4_StartPrescaler(XMC_CCU4_MODULE_t *const module)
893 {
894 XMC_ASSERT("XMC_CCU4_StartPrescaler:Invalid Module Pointer", XMC_CCU4_IsValidModule(module));
895 module->GIDLC = (uint32_t) CCU4_GIDLC_SPRB_Msk;
896 }
897
898 /**
899 * @param module Constant pointer to CCU4 module
900 * @return <BR>
901 * None<BR>
902 *
903 * \par<b>Description:</b><br>
904 * Stops the prescaler and blocks clocks to the timer slices, by setting GIDLS.CPRB bit.<BR>\n
905 * Opposite of the StartPrescaler routine.
906 * Clears the run bit of the prescaler. Ensures that the module clock is not supplied to
907 * the slices of the module.Registers directly accessed is GIDLS.
908 *
909 * \par<b>Related APIs:</b><br>
910 * XMC_CCU4_EnableClock()<BR> XMC_CCU4_DisableClock()<BR> XMC_CCU4_StartPrescaler()<BR> XMC_CCU4_StopPrescaler().
911 */
XMC_CCU4_StopPrescaler(XMC_CCU4_MODULE_t * const module)912 __STATIC_INLINE void XMC_CCU4_StopPrescaler(XMC_CCU4_MODULE_t *const module)
913 {
914 XMC_ASSERT("XMC_CCU4_StopPrescaler:Invalid Module Pointer", XMC_CCU4_IsValidModule(module));
915 module->GIDLS = (uint32_t) CCU4_GIDLS_CPRB_Msk;
916 }
917
918 /**
919 * @param module Constant pointer to CCU4 module
920 * @return <BR>
921 * None<BR>
922 *
923 * \par<b>Description:</b><br>
924 * Returns the state of the prescaler, by reading GSTAT.PRB bit.<BR>\n
925 * This will return true if the prescaler is running. If clock is being supplied to the slices of the
926 * module then returns as true.
927 *
928 * \par<b>Related APIs:</b><br>
929 * XMC_CCU4_StartPrescaler()<BR> XMC_CCU4_StopPrescaler()<BR> XMC_CCU4_EnableClock()<BR> XMC_CCU4_DisableClock().
930 */
XMC_CCU4_IsPrescalerRunning(XMC_CCU4_MODULE_t * const module)931 __STATIC_INLINE bool XMC_CCU4_IsPrescalerRunning(XMC_CCU4_MODULE_t *const module)
932 {
933 XMC_ASSERT("XMC_CCU4_IsPrescalerRunning:Invalid Module Pointer", XMC_CCU4_IsValidModule(module));
934 return((bool)((module->GSTAT & (uint32_t) CCU4_GSTAT_PRB_Msk) == (uint32_t)CCU4_GSTAT_PRB_Msk));
935 }
936
937 /**
938 * @param module Constant pointer to CCU4 module
939 * @param clock_mask Slices whose clocks are to be enabled simultaneously.
940 * Bit location 0/1/2/3 represents slice-0/1/2/3 respectively.
941 * Range: [0x1 to 0xF]
942 * @return <BR>
943 * None<BR>
944 *
945 * \par<b>Description:</b><br>
946 * Enables clocks of multiple slices at a time, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I,
947 * GIDLC.CS3I bits.\n\n
948 * Takes an input clock_mask, which determines the slices that would receive the clock. Bring them out
949 * of the idle state simultaneously.
950 *
951 * \par<b>Related APIs:</b><br>
952 * XMC_CCU4_EnableClock()<BR> XMC_CCU4_DisableClock().
953 */
XMC_CCU4_EnableMultipleClocks(XMC_CCU4_MODULE_t * const module,const uint8_t clock_mask)954 __STATIC_INLINE void XMC_CCU4_EnableMultipleClocks(XMC_CCU4_MODULE_t *const module, const uint8_t clock_mask)
955 {
956 XMC_ASSERT("XMC_CCU4_EnableMultipleClocks:Invalid Module Pointer", XMC_CCU4_IsValidModule(module));
957 XMC_ASSERT("XMC_CCU4_EnableMultipleClocks:Wrong clock mask", (clock_mask < 16U));
958
959 module->GIDLC = (uint32_t) clock_mask;
960 }
961
962 /**
963 * @param module Constant pointer to CCU4 module
964 * @param slice_number Slice for which the clock should be Enabled.
965 * Range: [0x0 to 0x3]
966 * @return <BR>
967 * None<BR>
968 *
969 * \par<b>Description:</b><br>
970 * Enables the slice timer clock, by configuring GIDLC.CS0I, GIDLC.CS1I, GIDLC.CS2I,
971 * GIDLC.CS3I bits according to the selected \a slice_number.\n\n
972 * It is possible to enable/disable clock at slice level. This uses the \b slice_number to indicate the
973 * slice whose clock needs to be enabled.
974 *
975 * \par<b>Related APIs:</b><br>
976 * XMC_CCU4_DisableClock()<BR> XMC_CCU4_EnableMultipleClocks()<BR> XMC_CCU4_StartPrescaler()<BR> XMC_CCU4_StopPrescaler().
977 */
XMC_CCU4_EnableClock(XMC_CCU4_MODULE_t * const module,const uint8_t slice_number)978 __STATIC_INLINE void XMC_CCU4_EnableClock(XMC_CCU4_MODULE_t *const module, const uint8_t slice_number)
979 {
980 XMC_ASSERT("XMC_CCU4_EnableClock:Invalid Module Pointer", XMC_CCU4_IsValidModule(module));
981 XMC_ASSERT("XMC_CCU4_EnableClock:Invalid Slice Number", (slice_number < 4U));
982
983 module->GIDLC = ((uint32_t) 1) << slice_number;
984 }
985
986 /**
987 * @param module Constant pointer to CCU4 module
988 * @param slice_number Slice for which the clock should be disabled.
989 * Range: [0x0 to 0x3]
990 * @return <BR>
991 * None<BR>
992 *
993 * \par<b>Description:</b><br>
994 * Disables the slice timer clock, by configuring GIDLS.SS0I, GIDLS.SSS1I, GIDLS.SSS2I,
995 * GIDLS.SSS3I bits according to the selected \a slice_number .\n\n
996 * It is possible to disable clock at slice level using the module pointer.
997 * \b slice_number is used to disable the clock to a given slice of the module.
998 * Directly accessed Register is GIDLS.
999 *
1000 * \par<b>Related APIs:</b><br>
1001 * XMC_CCU4_EnableClock()<BR> XMC_CCU4_EnableMultipleClocks()<BR> XMC_CCU4_StartPrescaler()<BR> XMC_CCU4_StopPrescaler().
1002 */
XMC_CCU4_DisableClock(XMC_CCU4_MODULE_t * const module,const uint8_t slice_number)1003 __STATIC_INLINE void XMC_CCU4_DisableClock(XMC_CCU4_MODULE_t *const module, const uint8_t slice_number)
1004 {
1005 XMC_ASSERT("XMC_CCU4_DisableClock:Invalid Module Pointer", XMC_CCU4_IsValidModule(module));
1006 XMC_ASSERT("XMC_CCU4_DisableClock:Invalid Slice Number", (slice_number < 4U));
1007
1008 module->GIDLS = ((uint32_t) 1) << slice_number;
1009 }
1010
1011 /**
1012 * @param module Constant pointer to CCU8 module
1013 * @param mode Selects suspend mode
1014 * @return <BR>
1015 * None<BR>
1016 *
1017 * \par<b>Description:</b><br>
1018 * Configures the entering in suspend mode for all the CCU8 slices.
1019 *
1020 * \par<b>Related APIs:</b><br>
1021 * None.
1022 */
XMC_CCU4_SetSuspendMode(XMC_CCU4_MODULE_t * const module,const XMC_CCU4_SUSPEND_MODE_t mode)1023 __STATIC_INLINE void XMC_CCU4_SetSuspendMode(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_SUSPEND_MODE_t mode)
1024 {
1025 XMC_ASSERT("XMC_CCU4_EnableMultipleClocks:Invalid Module Pointer", XMC_CCU4_IsValidModule(module));
1026 module->GCTRL = (module->GCTRL & (uint32_t)~CCU4_GCTRL_SUSCFG_Msk) | mode;
1027 }
1028
1029 /**
1030 * @param slice Constant pointer to CC4 Slice
1031 * @param compare_init Pointer to slice configuration structure
1032 * @return <BR>
1033 * None<BR>
1034 *
1035 * \par<b>Description:</b><br>
1036 * Initialization of a CC4 slice to compare mode, by configuring CC4yTC, CC4yCMC, CC4yPSC, CC4yDITH, CC4yPSL,
1037 * CC4yFPCS, CC4yCHC registers.\n\n
1038 * CC4 slice is configured with Timer configurations in this routine.
1039 * After initialization user has to explicitly enable the shadow transfer for the required values by calling
1040 * XMC_CCU4_EnableShadowTransfer() with appropriate mask.
1041 *
1042 * \par<b>Related APIs:</b><br>
1043 * None.
1044 */
1045 void XMC_CCU4_SLICE_CompareInit(XMC_CCU4_SLICE_t *const slice,
1046 const XMC_CCU4_SLICE_COMPARE_CONFIG_t *const compare_init);
1047
1048 /**
1049 * @param slice Constant pointer to CC4 Slice
1050 * @param capture_init Pointer to slice configuration structure
1051 * @return <BR>
1052 * None<BR>
1053 *
1054 * \par<b>Description:</b><br>
1055 * Initialization of a CC4 slice to capture mode, by configuring CC4yTC, CC4yCMC, CC4yPSC,CC4yFPCS registers.\n\n
1056 * CC4 slice is configured with Capture configurations in this routine.After initialization user has to explicitly
1057 * enable the shadow transfer for the required values by calling XMC_CCU4_EnableShadowTransfer()
1058 * with appropriate mask.
1059 *
1060 * \par<b>Related APIs:</b><br>
1061 * XMC_CCU4_SLICE_Capture0Config()<BR> XMC_CCU4_SLICE_Capture1Config().
1062 */
1063 void XMC_CCU4_SLICE_CaptureInit(XMC_CCU4_SLICE_t *const slice,
1064 const XMC_CCU4_SLICE_CAPTURE_CONFIG_t *const capture_init);
1065
1066
1067 /**
1068 * @param slice Constant pointer to CC4 Slice
1069 * @param event Map an External event to the External Start Function
1070 * @param start_mode Behavior of slice when the start function is activated
1071 * @return <BR>
1072 * None<BR>
1073 *
1074 * \par<b>Description:</b><br>
1075 * Configures the Start Function of the slice, by configuring CC4yCMC.ENDS and CC4yTC.ENDM bits.\n\n
1076 * Start function is mapped with one of the 3 events. An external signal can control when a CC4 timer should start.
1077 * Additionally, the behaviour of the slice upon activation of the start function is configured as well.
1078 *
1079 * \par<b>Related APIs:</b><br>
1080 * XMC_CCU4_SLICE_StopConfig()<BR> XMC_CCU4_SLICE_ConfigureEvent()<BR> XMC_CCU4_SLICE_SetInput().
1081 */
1082 void XMC_CCU4_SLICE_StartConfig(XMC_CCU4_SLICE_t *const slice,
1083 const XMC_CCU4_SLICE_EVENT_t event,
1084 const XMC_CCU4_SLICE_START_MODE_t start_mode);
1085
1086 /**
1087 * @param slice Constant pointer to CC4 Slice
1088 * @param event Map an External event to the External Stop Function
1089 * @param end_mode Behavior of slice when the stop function is activated
1090 * @return <BR>
1091 * None<BR>
1092 *
1093 * \par<b>Description:</b><br>
1094 * Configures the Stop function for the slice, by configuring CC4yCMC.STRTS and CC4yTC.STRM bits.\n\n
1095 * Stop function is mapped with one of the 3 events. An external signal can control when a CCU4 timer should stop.
1096 * Additionally, the behaviour of the slice upon activation of the stop function is configured as well.
1097 *
1098 * \par<b>Related APIs:</b><br>
1099 * XMC_CCU4_SLICE_StartConfig()<BR> XMC_CCU4_SLICE_ConfigureEvent()<BR> XMC_CCU4_SLICE_SetInput().
1100 */
1101 void XMC_CCU4_SLICE_StopConfig(XMC_CCU4_SLICE_t *const slice,
1102 const XMC_CCU4_SLICE_EVENT_t event,
1103 const XMC_CCU4_SLICE_END_MODE_t end_mode);
1104
1105 /**
1106 * @param slice Constant pointer to CC4 Slice
1107 * @param event Map an External event to the External load Function
1108 * @return <BR>
1109 * None<BR>
1110 *
1111 * \par<b>Description:</b><br>
1112 * Configures the Load Function for the slice, by configuring CC4yCMC.LDS bit.\n\n
1113 * Load function is mapped with one of the 3 events. Up on occurrence of the event,\n
1114 * if CC4yTCST.CDIR set to 0,CC4yTIMER register is reloaded with the value from compare register\n
1115 * if CC4yTCST.CDIR set to 1,CC4yTIMER register is reloaded with the value from period register\n
1116 *
1117 * \par<b>Related APIs:</b><br>
1118 * XMC_CCU4_SLICE_ConfigureEvent()<BR> XMC_CCU4_SLICE_SetInput().
1119 */
1120 void XMC_CCU4_SLICE_LoadConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);
1121
1122
1123 /**
1124 * @param slice Constant pointer to CC4 Slice
1125 * @param event Map an External event to the External Modulation Function
1126 * @param mod_mode Desired Modulation mode
1127 * @param synch_with_pwm Option to synchronize modulation with PWM start
1128 * Pass \b true if the modulation needs to be synchronized with PWM signal.
1129 * @return <BR>
1130 * None<BR>
1131 *
1132 * \par<b>Description:</b><br>
1133 * Configures the Output Modulation Function of the slice, by configuring CCeyCMC.MOS, CC4yTC.EMT and
1134 * CC4yTC.EMS bits.\n\n
1135 * Modulation function is mapped with one of the 3 events. The output signal of the CCU can
1136 * be modulated according to a external input. Additionally, the behaviour of the slice upon activation
1137 * of the modulation function is configured as well.
1138 *
1139 * \par<b>Related APIs:</b><br>
1140 * XMC_CCU4_SLICE_ConfigureEvent()<BR> XMC_CCU4_SLICE_SetInput().
1141 */
1142 void XMC_CCU4_SLICE_ModulationConfig(XMC_CCU4_SLICE_t *const slice,
1143 const XMC_CCU4_SLICE_EVENT_t event,
1144 const XMC_CCU4_SLICE_MODULATION_MODE_t mod_mode,
1145 const bool synch_with_pwm);
1146
1147 /**
1148 * @param slice Constant pointer to CC4 Slice
1149 * @param event Map an External event to the External Count Function
1150 * @return <BR>
1151 * None<BR>
1152 *
1153 * \par<b>Description:</b><br>
1154 * Configures the Count Function of the slice, by configuring CC4yCMC.CNTS bit.\n\n
1155 * Count function is mapped with one of the 3 events. CCU4 slice can take an external
1156 * signal to act as the counting event. The CCU4 slice would count the
1157 * edges present on the \b event selected.
1158 *
1159 * \par<b>Related APIs:</b><br>
1160 * XMC_CCU4_SLICE_ConfigureEvent()<BR> XMC_CCU4_SLICE_SetInput().
1161 */
1162 void XMC_CCU4_SLICE_CountConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);
1163
1164 /**
1165 * @param slice Constant pointer to CC4 Slice
1166 * @param event Map an External event to the External Gating Function
1167 * @return <BR>
1168 * None<BR>
1169 *
1170 * \par<b>Description:</b><br>
1171 * Configures the Gating Function of the slice, by configuring CC4yCMC.GATES bit.\n\n
1172 * Gating function is mapped with one of the 3 events. A CCU4 slice can use an input signal that would
1173 * operate as counter gating. If the configured Active level is detected the counter will gate all the pulses.
1174 *
1175 * \par<b>Related APIs:</b><br>
1176 * XMC_CCU4_SLICE_ConfigureEvent()<BR> XMC_CCU4_SLICE_SetInput().
1177 */
1178 void XMC_CCU4_SLICE_GateConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);
1179
1180 /**
1181 * @param slice Constant pointer to CC4 Slice
1182 * @param event Map an External event to the Capture-0 Function
1183 * @return <BR>
1184 * None<BR>
1185 *
1186 * \par<b>Description:</b><br>
1187 * Configures the Capture-0 Function of the slice, by configuring CC4yCMC.CAP0S bit.\n\n
1188 * Capture function is mapped with one of the 3 events. A CCU4 slice can be configured into capture-0 mode
1189 * with the selected \b event. In this mode the CCU4 will capture the timer value into CC4yC0V and CC4yC1V.
1190 *
1191 * \par<b>Related APIs:</b><br>
1192 * XMC_CCU4_SLICE_ConfigureEvent()<BR> XMC_CCU4_SLICE_SetInput().
1193 */
1194 void XMC_CCU4_SLICE_Capture0Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);
1195
1196 /**
1197 * @param slice Constant pointer to CC4 Slice
1198 * @param event Map an External event to the Capture-1 Function
1199 * @return <BR>
1200 * None<BR>
1201 *
1202 * \par<b>Description:</b><br>
1203 * Configures the Capture-1 Function of the slice, by configuring CC4yCMC.CAP1S bit.\n\n
1204 * Capture function is mapped with one of the 3 events. A CCU4 slice can be configured into capture-1
1205 * mode with the selected \b event. In this mode the CCU4 will capture the timer value into CC4yC2V and CC4yC3V.
1206 *
1207 * \par<b>Related APIs:</b><br>
1208 * XMC_CCU4_SLICE_ConfigureEvent()<BR> XMC_CCU4_SLICE_SetInput().
1209 */
1210 void XMC_CCU4_SLICE_Capture1Config(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);
1211
1212 /**
1213 * @param slice Constant pointer to CC4 Slice
1214 * @return <BR>
1215 * bool would return true if the extended capture read back mode is enabled<BR>
1216 *
1217 * \par<b>Description:</b><br>
1218 * Checks if Extended capture mode read is enabled for particular slice or not, by reading CC4yTC.ECM bit.\n\n
1219 * In this mode the there is only one associated read address for all the capture registers.
1220 * Individual capture registers can still be accessed in this mode.
1221 *
1222 * \par<b>Related APIs:</b><br>
1223 * XMC_CCU4_GetCapturedValueFromFifo().
1224 */
XMC_CCU4_SLICE_IsExtendedCapReadEnabled(const XMC_CCU4_SLICE_t * const slice)1225 __STATIC_INLINE bool XMC_CCU4_SLICE_IsExtendedCapReadEnabled(const XMC_CCU4_SLICE_t *const slice)
1226 {
1227 XMC_ASSERT("XMC_CCU4_SLICE_IsExtendedCapReadEnabled:Invalid Module Pointer", XMC_CCU4_IsValidSlice(slice));
1228 return((bool)((slice->TC & (uint32_t) CCU4_CC4_TC_ECM_Msk) == (uint32_t)CCU4_CC4_TC_ECM_Msk));
1229 }
1230
1231 #if defined(CCU4V1) /* Defined for XMC4500, XMC4400, XMC4200, XMC4100 devices only */
1232 /**
1233 * @param module Constant pointer to CCU4 module
1234 * @param slice_number to check whether read value belongs to required slice or not
1235 * @return <BR>
1236 * int32_t Returns -1 if the FIFO value being retrieved is not from the \b slice_number.
1237 * Returns the value captured in the \b slice_number, if captured value is from the correct slice.
1238 * Range: [0x0 to 0xFFFF]
1239 *
1240 * \par<b>Description:</b><br>
1241 * Read captured value from FIFO(ECRD register).\n\n
1242 * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured
1243 * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the
1244 * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be
1245 * derived/inferred from the captured values.
1246 *
1247 * \par<b>Related APIs:</b><br>
1248 * XMC_CCU4_SLICE_IsExtendedCapReadEnabled().
1249 * @note Only available for XMC4500, XMC4400, XMC4200 and XMC4100 series
1250 */
1251 int32_t XMC_CCU4_GetCapturedValueFromFifo(const XMC_CCU4_MODULE_t *const module, const uint8_t slice_number);
1252 #else
1253 /**
1254 * @param slice Constant pointer to CC4 Slice
1255 * @param set The capture register set from which the captured value is to be retrieved
1256 * @return <BR>
1257 * uint32_t Returns the value captured in the \b slice_number
1258 * Range: [0x0 to 0xFFFF]
1259 *
1260 * \par<b>Description:</b><br>
1261 * Read captured value from FIFO(CC4yECRD0 and CC4yECRD1).\n\n
1262 * This is applicable only in the Capture mode of operation. The signal whose timing characteristics are to be measured
1263 * must be mapped to an event which in turn must be mapped to the capture function. Based on the capture criteria, the
1264 * instant timer values are captured into capture registers. Timing characteristics of the input signal may then be
1265 * derived/inferred from the captured values.
1266 *
1267 * \par<b>Related APIs:</b><br>
1268 * XMC_CCU4_SLICE_IsExtendedCapReadEnabled().
1269 * @note Defined for XMC4800, XMC4700, XMC4500, XMC4400, XMC4200, XMC4100 devices only. For other devices use XMC_CCU4_GetCapturedValueFromFifo() API
1270 */
1271 uint32_t XMC_CCU4_SLICE_GetCapturedValueFromFifo(const XMC_CCU4_SLICE_t *const slice,
1272 const XMC_CCU4_SLICE_CAP_REG_SET_t set);
1273 #endif
1274
1275 /**
1276 * @param slice Constant pointer to CC4 Slice
1277 * @param event Map an External event to the External Count Direction Function
1278 * @return <BR>
1279 * None<BR>
1280 *
1281 * \par<b>Description:</b><br>
1282 * Configures the Count Direction of the slice, by configuring CC4yCMC.UDS bit.\n\n
1283 * Count direction function is mapped with one of the 3 events. A slice can be configured to change the
1284 * CC4yTIMER count direction depending on an external signal.
1285 *
1286 * \par<b>Related APIs:</b><br>
1287 * XMC_CCU4_SLICE_ConfigureEvent()<BR> XMC_CCU4_SLICE_SetInput().
1288 */
1289 void XMC_CCU4_SLICE_DirectionConfig(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_EVENT_t event);
1290
1291 /**
1292 * @param slice Constant pointer to CC4 Slice
1293 * @return <BR>
1294 * None<BR>
1295 *
1296 * \par<b>Description:</b><br>
1297 * Configures the status bit override Function of the slice, by configuring CC4yCMC.OFS bit.\n\n
1298 * Status bit override function is mapped with one of the 3 events. A slice can be configured to change the
1299 * output of the timer's CC4yST signal depending on an external signal.
1300 *
1301 * \par<b>Related APIs:</b><br>
1302 * XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent().
1303 */
1304 void XMC_CCU4_SLICE_StatusBitOverrideConfig(XMC_CCU4_SLICE_t *const slice);
1305
1306 /**
1307 * @param slice Constant pointer to CC4 Slice
1308 * @param exit_mode How should a previously logged trap state be exited?
1309 * @param synch_with_pwm Should exit of trap state be synchronized with PWM cycle start?
1310 * @return <BR>
1311 * None<BR>
1312 *
1313 * \par<b>Description:</b><br>
1314 * Configures the Trap Function of the slice, by configuring CC4yCMC.TS, CC4yTC.TRPSE, and CC4yTC.TRPSW bits.\n\n
1315 * Trap function is mapped with Event-2. Criteria for exiting the trap state is configured.
1316 * This trap function allows PWM outputs to react on the state of an input pin.
1317 * Thus PWM output can be forced to inactive state upon detection of a trap.
1318 * It is also possible to synchronize the trap function with the PWM signal using the \b synch_with_pwm.
1319 *
1320 * \par<b>Related APIs:</b><br>
1321 * XMC_CCU4_SLICE_ConfigureEvent()<BR> XMC_CCU4_SLICE_SetInput().
1322 */
1323 void XMC_CCU4_SLICE_TrapConfig(XMC_CCU4_SLICE_t *const slice,
1324 const XMC_CCU4_SLICE_TRAP_EXIT_MODE_t exit_mode,
1325 bool synch_with_pwm);
1326
1327
1328 /**
1329 * @param slice Constant pointer to CC4 Slice
1330 * @param ev1_config Pointer to event 1 configuration data
1331 * @param ev2_config Pointer to event 2 configuration data
1332 * @return <BR>
1333 * None<BR>
1334 *
1335 *
1336 * \par<b>Description:</b><br>
1337 * Map Status bit override function with an Event1 & Event 2 of the slice and configure CC4yINS register.\n\n
1338 * Details such as the input mapped to the event, event detection criteria and Low Pass filter options are programmed
1339 * by this routine for the events 1 & 2. Event-1 input would be the trigger to override the value.
1340 * Event-2 input would be the override value.
1341 *
1342 * \par<b>Related APIs:</b><br>
1343 * XMC_CCU4_SLICE_StatusBitOverrideConfig().
1344 */
1345 void XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent(XMC_CCU4_SLICE_t *const slice,
1346 const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev1_config,
1347 const XMC_CCU4_SLICE_EVENT_CONFIG_t *const ev2_config);
1348
1349 /**
1350 * @param slice Constant pointer to CC4 Slice
1351 * @param event The External Event which needs to be configured.
1352 * @param config Pointer to event configuration data.
1353 * @return <BR>
1354 * None<BR>
1355 *
1356 * \par<b>Description:</b><br>
1357 * Configures an External Event of the slice, by updating CC4yINS register .\n\n
1358 * Details such as the input mapped to the event, event detection criteria and low pass filter
1359 * options are programmed by this routine. The Event \b config will configure the input selection,
1360 * the edge selection, the level selection and the Low pass filter for the event.
1361 *
1362 * \par<b>Related APIs:</b><br>
1363 * XMC_CCU4_SLICE_StartConfig()<BR> XMC_CCU4_SLICE_StopConfig()<BR> XMC_CCU4_SLICE_LoadConfig()<BR>
1364 * XMC_CCU4_SLICE_ModulationConfig()<BR> XMC_CCU4_SLICE_CountConfig()<BR> XMC_CCU4_SLICE_GateConfig()<BR>
1365 * XMC_CCU4_SLICE_Capture0Config()<BR> XMC_CCU4_SLICE_Capture1Config()<BR> XMC_CCU4_SLICE_DirectionConfig()<BR>
1366 * XMC_CCU4_SLICE_StatusBitOverrideConfig()<BR> XMC_CCU4_SLICE_TrapConfig().
1367 */
1368 void XMC_CCU4_SLICE_ConfigureEvent(XMC_CCU4_SLICE_t *const slice,
1369 const XMC_CCU4_SLICE_EVENT_t event,
1370 const XMC_CCU4_SLICE_EVENT_CONFIG_t *const config);
1371
1372 /**
1373 * @param slice Constant pointer to CC4 Slice
1374 * @param event The External Event which needs to be configured.
1375 * @param input One of the 16 inputs meant to be mapped to the desired event
1376 * @return <BR>
1377 * None<BR>
1378 *
1379 *
1380 * \par<b>Description:</b><br>
1381 * Selects an input for an external event, by configuring CC4yINS register.\n\n
1382 * It is possible to select one of the possible 16 input signals for a given Event.
1383 * This configures the CC4yINS.EVxIS for the selected event.
1384 *
1385 * \par<b>Related APIs:</b><br>
1386 * XMC_CCU4_SLICE_StartConfig()<BR> XMC_CCU4_SLICE_StopConfig()<BR> XMC_CCU4_SLICE_LoadConfig()<BR>
1387 * XMC_CCU4_SLICE_ModulationConfig()<BR> XMC_CCU4_SLICE_CountConfig()<BR> XMC_CCU4_SLICE_GateConfig()<BR>
1388 * XMC_CCU4_SLICE_Capture0Config()<BR> XMC_CCU4_SLICE_Capture1Config()<BR> XMC_CCU4_SLICE_DirectionConfig()<BR>
1389 * XMC_CCU4_SLICE_StatusBitOverrideConfig()<BR> XMC_CCU4_SLICE_TrapConfig().
1390 */
1391 void XMC_CCU4_SLICE_SetInput(XMC_CCU4_SLICE_t *const slice,
1392 const XMC_CCU4_SLICE_EVENT_t event,
1393 const XMC_CCU4_SLICE_INPUT_t input);
1394
1395 /**
1396 * @param slice Constant pointer to CC4 Slice
1397 * @return <BR>
1398 * None<BR>
1399 *
1400 * \par<b>Description:</b><br>
1401 * Enables the trap feature, by setting CC4yTC.TRAPE0, CC4yTC.TRAPE1, CC4yTC.TRAPE2 and CC4yTC.TRAPE3 bit based on the
1402 * \a out_mask.\n\n
1403 * A particularly useful feature where the PWM output can be forced inactive upon detection of a trap. The trap signal
1404 * can be the output of a sensing element which has just detected an abnormal electrical condition.
1405 *
1406 * \par<b>Related APIs:</b><br>
1407 * XMC_CCU4_SLICE_TrapConfig()<BR> XMC_CCU4_SLICE_DisableTrap()<BR> XMC_CCU4_SLICE_ConfigureEvent()<BR>
1408 * XMC_CCU4_SLICE_SetInput().
1409 */
XMC_CCU4_SLICE_EnableTrap(XMC_CCU4_SLICE_t * const slice)1410 __STATIC_INLINE void XMC_CCU4_SLICE_EnableTrap(XMC_CCU4_SLICE_t *const slice)
1411 {
1412 XMC_ASSERT("XMC_CCU4_SLICE_EnableTrap:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1413 slice->TC |= (uint32_t) CCU4_CC4_TC_TRAPE_Msk;
1414 }
1415
1416 /**
1417 * @param slice Constant pointer to CC4 Slice
1418 * @return <BR>
1419 * None<BR>
1420 *
1421 * \par<b>Description:</b><br>
1422 * Disables the trap feature, by clearing CC4yTC.TRAPE0, CC4yTC.TRAPE1, CC4yTC.TRAPE2 and CC4yTC.TRAPE3 bit based on the
1423 * \a out_mask.\n\n.\n\n
1424 * This API will revert the changes done by XMC_CCU4_SLICE_EnableTrap().
1425 * This Ensures that the TRAP function has no effect on the output of the CCU4 slice.
1426 *
1427 * \par<b>Related APIs:</b><br>
1428 * XMC_CCU4_SLICE_EnableTrap().
1429 */
XMC_CCU4_SLICE_DisableTrap(XMC_CCU4_SLICE_t * const slice)1430 __STATIC_INLINE void XMC_CCU4_SLICE_DisableTrap(XMC_CCU4_SLICE_t *const slice)
1431 {
1432 XMC_ASSERT("XMC_CCU4_SLICE_DisableTrap:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1433 slice->TC &= ~((uint32_t) CCU4_CC4_TC_TRAPE_Msk);
1434 }
1435
1436 /**
1437 * @param slice Constant pointer to CC4 Slice
1438 * @return <BR>
1439 * bool returns \b true if the Timer is running else it returns \b false.
1440 *
1441 * \par<b>Description:</b><br>
1442 * Returns the state of the timer (Either Running or stopped(idle)), by reading CC4yTCST.TRB bit.
1443 *
1444 * \par<b>Related APIs:</b><br>
1445 * XMC_CCU4_SLICE_StartTimer()<BR> XMC_CCU4_SLICE_StopTimer().
1446 */
XMC_CCU4_SLICE_IsTimerRunning(const XMC_CCU4_SLICE_t * const slice)1447 __STATIC_INLINE bool XMC_CCU4_SLICE_IsTimerRunning(const XMC_CCU4_SLICE_t *const slice)
1448 {
1449 XMC_ASSERT("XMC_CCU4_SLICE_GetTimerStatus:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1450 return (bool)(((slice->TCST) & CCU4_CC4_TCST_TRB_Msk) == CCU4_CC4_TCST_TRB_Msk);
1451 }
1452
1453 /**
1454 * @param slice Constant pointer to CC4 Slice
1455 * @return <BR>
1456 * ::XMC_CCU4_SLICE_TIMER_COUNT_DIR_t returns the direction in which the timer is counting.
1457 *
1458 * \par<b>Description:</b><br>
1459 * Returns the timer counting direction, by reading CC4yTCST.CDIR bit.\n\n
1460 * This API will return the direction in which the timer is currently
1461 * incrementing(XMC_CCU4_SLICE_TIMER_COUNT_DIR_UP) or decrementing (XMC_CCU4_SLICE_TIMER_COUNT_DIR_DOWN).
1462 *
1463 * \par<b>Related APIs:</b><br>
1464 * None.
1465 */
XMC_CCU4_SLICE_GetCountingDir(const XMC_CCU4_SLICE_t * const slice)1466 __STATIC_INLINE XMC_CCU4_SLICE_TIMER_COUNT_DIR_t XMC_CCU4_SLICE_GetCountingDir(const XMC_CCU4_SLICE_t *const slice)
1467 {
1468 XMC_ASSERT("XMC_CCU4_SLICE_GetCountingDir:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1469 return((XMC_CCU4_SLICE_TIMER_COUNT_DIR_t)(((slice->TCST) & CCU4_CC4_TCST_CDIR_Msk) >> CCU4_CC4_TCST_CDIR_Pos));
1470 }
1471
1472 /**
1473 * @param slice Constant pointer to CC4 Slice
1474 * @return <BR>
1475 * None<BR>
1476 *
1477 * \par<b>Description:</b><br>
1478 * Starts the timer counting operation, by setting CC4yTCSET.TRBS bit.\n\n
1479 * It is necessary to have configured the CC4 slice before starting its timer.
1480 * Before the Timer is started ensure that the clock is provided to the slice.
1481 *
1482 * \par<b>Related APIs:</b><br>
1483 * XMC_CCU4_SLICE_StopTimer().
1484 */
XMC_CCU4_SLICE_StartTimer(XMC_CCU4_SLICE_t * const slice)1485 __STATIC_INLINE void XMC_CCU4_SLICE_StartTimer(XMC_CCU4_SLICE_t *const slice)
1486 {
1487 XMC_ASSERT("XMC_CCU4_SLICE_StartTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1488 slice->TCSET = CCU4_CC4_TCSET_TRBS_Msk;
1489 }
1490
1491 /**
1492 * @param slice Constant pointer to CC4 Slice
1493 * @return <BR>
1494 * None<BR>
1495 *
1496 * \par<b>Description:</b><br>
1497 * Stops the Timer.<BR>\n
1498 * Timer counting operation can be stopped by invoking this API, by setting CC4yTCCLR.TRBC bit.
1499 *
1500 * \par<b>Related APIs:</b><br>
1501 * XMC_CCU4_SLICE_StartTimer().
1502 */
XMC_CCU4_SLICE_StopTimer(XMC_CCU4_SLICE_t * const slice)1503 __STATIC_INLINE void XMC_CCU4_SLICE_StopTimer(XMC_CCU4_SLICE_t *const slice)
1504 {
1505 XMC_ASSERT("XMC_CCU4_SLICE_StopTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1506 slice->TCCLR = (uint32_t) CCU4_CC4_TCCLR_TRBC_Msk;
1507 }
1508
1509 /**
1510 * @param slice Constant pointer to CC4 Slice
1511 * @return <BR>
1512 * None<BR>
1513 *
1514 * \par<b>Description:</b><br>
1515 * Resets the timer count to zero, by setting CC4yTCCLR.TCC bit.\n\n
1516 * A timer which has been stopped can still retain the last counted value.
1517 * After invoking this API the timer value will be cleared.
1518 *
1519 * \par<b>Related APIs:</b><br>
1520 * XMC_CCU4_SLICE_StartTimer().
1521 */
XMC_CCU4_SLICE_ClearTimer(XMC_CCU4_SLICE_t * const slice)1522 __STATIC_INLINE void XMC_CCU4_SLICE_ClearTimer(XMC_CCU4_SLICE_t *const slice)
1523 {
1524 XMC_ASSERT("XMC_CCU4_SLICE_ClearTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1525 slice->TCCLR = (uint32_t) CCU4_CC4_TCCLR_TCC_Msk;
1526 }
1527
1528 /**
1529 * @param slice Constant pointer to CC4 Slice
1530 * @return <BR>
1531 * None<BR>
1532 *
1533 * \par<b>Description:</b><br>
1534 * Stops and resets the timer count to zero, by setting CC4yTCCLR.TCC and CC4yTCCLR.TRBC bit.\n\n
1535 *
1536 * \par<b>Related APIs:</b><br>
1537 * XMC_CCU4_SLICE_StartTimer().
1538 */
XMC_CCU4_SLICE_StopClearTimer(XMC_CCU4_SLICE_t * const slice)1539 __STATIC_INLINE void XMC_CCU4_SLICE_StopClearTimer(XMC_CCU4_SLICE_t *const slice)
1540 {
1541 XMC_ASSERT("XMC_CCU4_SLICE_StopClearTimer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1542 slice->TCCLR = CCU4_CC4_TCCLR_TRBC_Msk | CCU4_CC4_TCCLR_TCC_Msk;
1543 }
1544
1545 /**
1546 * @param slice Constant pointer to CC4 Slice
1547 * @return <BR>
1548 * ::XMC_CCU4_SLICE_MODE_t returns XMC_CCU4_SLICE_MODE_COMPARE if the slice is operating in compare mode
1549 * returns XMC_CCU4_SLICE_MODE_CAPTURE if the slice is operating in capture mode
1550 *
1551 * \par<b>Description:</b><br>
1552 * Retrieves the current mode of operation in the slice (either Capture mode or Compare mode), by reading
1553 * CC4yTC.CMOD bit.\n\n
1554 * Ensure that before invoking this API the CCU4 slice should be configured otherwise the output of this API is
1555 * invalid.
1556 *
1557 * \par<b>Related APIs:</b><br>
1558 * None.
1559 */
XMC_CCU4_SLICE_GetSliceMode(const XMC_CCU4_SLICE_t * const slice)1560 __STATIC_INLINE XMC_CCU4_SLICE_MODE_t XMC_CCU4_SLICE_GetSliceMode(const XMC_CCU4_SLICE_t *const slice)
1561 {
1562 XMC_ASSERT("XMC_CCU4_SLICE_GetSliceMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1563 return((XMC_CCU4_SLICE_MODE_t)(((slice->TC) & CCU4_CC4_TC_CMOD_Msk) >> CCU4_CC4_TC_CMOD_Pos));
1564 }
1565 /**
1566 * @param slice Constant pointer to CC4 Slice
1567 * @param mode Desired repetition mode (Either single shot or Continuous)
1568 * @return <BR>
1569 * None<BR>
1570 *
1571 * \par<b>Description:</b><br>
1572 * Configures the Timer to either Single shot mode or continuous mode, by configuring CC4yTC.TSSM bit.\n\n
1573 * The timer will count up to the terminal count as specified in the period register and stops immediately if the repeat
1574 * mode has been set to single shot. In the continuous mode of operation, the timer starts counting all over again after
1575 * reaching the terminal count.
1576 *
1577 * \par<b>Related APIs:</b><br>
1578 * XMC_CCU4_SLICE_GetTimerRepeatMode().
1579 */
1580 void XMC_CCU4_SLICE_SetTimerRepeatMode(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t mode);
1581
1582 /**
1583 * @param slice Constant pointer to CC4 Slice
1584 * @return <br>
1585 * ::XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t returns XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT if continuous mode is selected
1586 * returns XMC_CCU4_SLICE_TIMER_REPEAT_MODE_SINGLE if single shot mode is selected
1587 *
1588 * \par<b>Description:</b><br>
1589 * Retrieves the Timer repeat mode, either Single shot mode or continuous mode, by reading CC4yTC.TSSM bit.\n\n
1590 * The timer will count up to the terminal count as specified in the period register and stops immediately if the repeat
1591 * mode has been set to single shot mode. In the continuous mode of operation, the timer starts counting
1592 * all over again after reaching the terminal count.
1593 *
1594 * \par<b>Related APIs:</b><br>
1595 * XMC_CCU4_SLICE_SetTimerRepeatMode().
1596 */
XMC_CCU4_SLICE_GetTimerRepeatMode(const XMC_CCU4_SLICE_t * const slice)1597 __STATIC_INLINE XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t XMC_CCU4_SLICE_GetTimerRepeatMode(
1598 const XMC_CCU4_SLICE_t *const slice)
1599 {
1600 XMC_ASSERT("XMC_CCU4_SLICE_GetTimerRepeatMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1601 return((XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t)(((slice->TC) & CCU4_CC4_TC_TSSM_Msk) >> CCU4_CC4_TC_TSSM_Pos));
1602 }
1603 /**
1604 * @param slice Constant pointer to CC4 Slice
1605 * @param mode Desired counting mode (Either Edge Aligned or Center Aligned)
1606 * @return <BR>
1607 * None<BR>
1608 *
1609 * \par<b>Description:</b><br>
1610 * Configures the timer counting mode either Edge Aligned or Center Aligned, by configuring CC4yTC.TCM bit.\n\n
1611 * In the edge aligned mode, the timer counts from 0 to the terminal count. Once the timer count has reached a preset
1612 * compare value, the timer status output asserts itself. It will now deassert only after the timer count reaches the
1613 * terminal count.\n In the center aligned mode, the timer first counts from 0 to the terminal count and then back to 0.
1614 * During this upward and downward counting, the timer status output stays asserted as long as the timer value is
1615 * greater than the compare value.
1616 *
1617 * \par<b>Related APIs:</b><br>
1618 * XMC_CCU4_SLICE_GetTimerCountingMode().
1619 */
1620 void XMC_CCU4_SLICE_SetTimerCountingMode(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_TIMER_COUNT_MODE_t mode);
1621
1622 /**
1623 * @param slice Constant pointer to CC4 Slice
1624 * @return <br>
1625 * ::XMC_CCU4_SLICE_TIMER_COUNT_MODE_t returns XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA if edge aligned mode is selected
1626 * returns XMC_CCU4_SLICE_TIMER_COUNT_MODE_CA if center aligned mode is selected
1627 *
1628 * \par<b>Description:</b><br>
1629 * Retrieves timer counting mode either Edge aligned or Center Aligned, by reading CC4yTC.TCM bit.\n\n
1630 *
1631 * \par<b>Related APIs:</b><br>
1632 * XMC_CCU4_SLICE_SetTimerCountingMode().
1633 */
XMC_CCU4_SLICE_GetTimerCountingMode(const XMC_CCU4_SLICE_t * const slice)1634 __STATIC_INLINE XMC_CCU4_SLICE_TIMER_COUNT_MODE_t XMC_CCU4_SLICE_GetTimerCountingMode(
1635 const XMC_CCU4_SLICE_t *const slice)
1636 {
1637 XMC_ASSERT("XMC_CCU4_SLICE_GetTimerCountingMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1638 return((XMC_CCU4_SLICE_TIMER_COUNT_MODE_t)(((slice->TC) & CCU4_CC4_TC_TCM_Msk) >> CCU4_CC4_TC_TCM_Pos));
1639 }
1640 /**
1641 * @param slice Constant pointer to CC4 Slice
1642 * @param period_val Timer period value
1643 * Range: [0x0 to 0xFFFF]
1644 * @return <BR>
1645 * None<BR>
1646 *
1647 * \par<b>Description:</b><br>
1648 * Programs the timer period, by writing CC4yPRS register.\n\n
1649 * The frequency of counting/ PWM frequency is determined by this value. The period value is written to a shadow
1650 * register. Explicitly enable the shadow transfer for the the period value by calling
1651 * XMC_CCU4_EnableShadowTransfer() with appropriate mask. If shadow transfer is enabled and the timer is running,
1652 * a period match transfers the value from the shadow register to the actual period register.
1653 *
1654 * \par<b>Related APIs:</b><br>
1655 * XMC_CCU4_SLICE_GetTimerPeriodMatch().
1656 */
XMC_CCU4_SLICE_SetTimerPeriodMatch(XMC_CCU4_SLICE_t * const slice,const uint16_t period_val)1657 __STATIC_INLINE void XMC_CCU4_SLICE_SetTimerPeriodMatch(XMC_CCU4_SLICE_t *const slice, const uint16_t period_val)
1658 {
1659 XMC_ASSERT("XMC_CCU4_SLICE_SetTimerPeriodMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1660 slice->PRS = (uint32_t) period_val;
1661 }
1662
1663 /**
1664 * @param slice Constant pointer to CC4 Slice
1665 * @return <BR>
1666 * uint16_t returns the current timer period value
1667 * Range: [0x0 to 0xFFFF]
1668 *
1669 * \par<b>Description:</b><br>
1670 * Retrieves the timer period value currently effective, by reading CC4yPR register.\n\n
1671 * If the timer is active then the value being returned is currently being used for the PWM period.
1672 *
1673 * \par<b>Note:</b><br>
1674 * The XMC_CCU4_SLICE_SetTimerPeriodMatch() would set the new period value to a shadow register.
1675 * This would only transfer the new values into the actual period register if the shadow transfer request
1676 * is enabled and if a period match occurs. Hence a consecutive call to XMC_CCU4_SLICE_GetTimerPeriodMatch()
1677 * would not reflect the new values until the shadow transfer completes.
1678 *
1679 * \par<b>Related APIs:</b><br>
1680 * XMC_CCU4_SLICE_SetTimerPeriodMatch().
1681 */
XMC_CCU4_SLICE_GetTimerPeriodMatch(const XMC_CCU4_SLICE_t * const slice)1682 __STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerPeriodMatch(const XMC_CCU4_SLICE_t *const slice)
1683 {
1684 XMC_ASSERT("XMC_CCU4_SLICE_SetTimerPeriodMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1685 return((uint16_t)slice->PR);
1686 }
1687
1688 /**
1689 * @param slice Constant pointer to CC4 Slice
1690 * @param compare_val Timer compare value
1691 * @return <BR>
1692 * None<BR>
1693 *
1694 * \par<b>Description:</b><br>
1695 * Programs the timer compare value, by writing CC4yCRS register.<BR>\n
1696 * The PWM duty cycle is determined by this value.
1697 * The compare value is written to a shadow register. Explicitly enable the shadow transfer for
1698 * the the period/compare value by calling XMC_CCU4_EnableShadowTransfer() with
1699 * appropriate mask.If shadow transfer is enabled and the timer is running,
1700 * a period match transfers the value from the shadow register to the actual compare register.
1701 *
1702 * \par<b>Related APIs:</b><br>
1703 * XMC_CCU4_SLICE_GetTimerPeriodMatch().
1704 */
XMC_CCU4_SLICE_SetTimerCompareMatch(XMC_CCU4_SLICE_t * const slice,const uint16_t compare_val)1705 __STATIC_INLINE void XMC_CCU4_SLICE_SetTimerCompareMatch(XMC_CCU4_SLICE_t *const slice, const uint16_t compare_val)
1706 {
1707 XMC_ASSERT("XMC_CCU4_SLICE_SetTimerCompareMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1708 slice->CRS = (uint32_t) compare_val;
1709 }
1710
1711 /**
1712 * @param slice Constant pointer to CC4 Slice
1713 * @return <BR>
1714 * uint16_t returns the current timer compare value
1715 * Range: [0x0 to 0xFFFF]
1716 *
1717 * \par<b>Description:</b><br>
1718 * Retrieves the timer compare value currently effective, by reading CC4yCRS register.\n\n
1719 * If the timer is active then the value being returned is currently being for the PWM duty cycle( timer compare value).
1720 *
1721 * \par<b>Note:</b><br>
1722 * The XMC_CCU4_SLICE_SetTimerCompareMatch() would set the new compare value to a shadow register.
1723 * This would only transfer the new values into the actual compare register if the shadow transfer request
1724 * is enabled and if a period match occurs. Hence a consecutive call to XMC_CCU4_SLICE_GetTimerCompareMatch()
1725 * would not reflect the new values until the shadow transfer completes.
1726 * Directly accessed Register is CC4yCR.
1727 *
1728 * \par<b>Related APIs:</b><br>
1729 * XMC_CCU4_SLICE_SetTimerCompareMatch().
1730 */
XMC_CCU4_SLICE_GetTimerCompareMatch(const XMC_CCU4_SLICE_t * const slice)1731 __STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerCompareMatch(const XMC_CCU4_SLICE_t *const slice)
1732 {
1733 XMC_ASSERT("XMC_CCU4_SLICE_GetTimerCompareMatch:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1734 return((uint16_t)slice->CR);
1735 }
1736
1737 /**
1738 * @param module Constant pointer to CCU4 module
1739 * @param shadow_transfer_msk Shadow transfer request mask for various transfers.
1740 * Use ::XMC_CCU4_SHADOW_TRANSFER_t enum items to create a mask of choice,
1741 * using a bit wise OR operation.
1742 * @return <BR>
1743 * None<BR>
1744 *
1745 * \par<b>Description:</b><br>
1746 * Requests of shadow transfer for Period, Compare, Passive level, dither and prescaler, by configuring
1747 * the GCSS register.\n\n
1748 * The transfer from the shadow registers to the actual registers is done in the immediate next occurrence of the
1749 * shadow transfer trigger after the API is called.
1750 *
1751 * Any call to XMC_CCU4_SLICE_SetTimerPeriodMatch()<BR> XMC_CCU4_SLICE_SetTimerCompareMatch()<BR>
1752 * XMC_CCU4_SLICE_SetPrescaler()<BR> XMC_CCU4_SLICE_CompareInit()<BR> XMC_CCU4_SLICE_CaptureInit().
1753 * must be succeeded by this API.
1754 * Directly accessed Register is GCSS.
1755 *
1756 * \par<b>Related APIs:</b><br>
1757 * None.
1758 */
XMC_CCU4_EnableShadowTransfer(XMC_CCU4_MODULE_t * const module,const uint32_t shadow_transfer_msk)1759 __STATIC_INLINE void XMC_CCU4_EnableShadowTransfer(XMC_CCU4_MODULE_t *const module, const uint32_t shadow_transfer_msk)
1760 {
1761 XMC_ASSERT("XMC_CCU4_EnableShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidModule(module));
1762 module->GCSS = (uint32_t)shadow_transfer_msk;
1763 }
1764
1765 /**
1766 * @param slice Constant pointer to CC4 Slice
1767 * @return <BR>
1768 * uint16_t returns the current timer value
1769 * Range: [0x0 to 0xFFFF]
1770 *
1771 * \par<b>Description:</b><br>
1772 * Retrieves the latest timer value, from CC4yTIMER register.\n\n
1773 *
1774 * \par<b>Related APIs:</b><br>
1775 * XMC_CCU4_SLICE_SetTimerValue().
1776 */
XMC_CCU4_SLICE_GetTimerValue(const XMC_CCU4_SLICE_t * const slice)1777 __STATIC_INLINE uint16_t XMC_CCU4_SLICE_GetTimerValue(const XMC_CCU4_SLICE_t *const slice)
1778 {
1779 XMC_ASSERT("XMC_CCU4_SLICE_GetTimerValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1780 return((uint16_t)slice->TIMER);
1781 }
1782 /**
1783 * @param slice Constant pointer to CC4 Slice
1784 * @param timer_val The new timer value that has to be loaded into the TIMER register.
1785 * Range: [0x0 to 0xFFFF]
1786 * @return <BR>
1787 * None<BR>
1788 *
1789 * \par<b>Description:</b><br>
1790 * Loads a new timer value, by setting CC4yTIMER register.\n\n
1791 *
1792 * \par<b>Note:</b><br>
1793 * Request to load is ignored if the timer is running.
1794 *
1795 * \par<b>Related APIs:</b><br>
1796 * XMC_CCU4_SLICE_GetTimerValue().
1797 */
XMC_CCU4_SLICE_SetTimerValue(XMC_CCU4_SLICE_t * const slice,const uint16_t timer_val)1798 __STATIC_INLINE void XMC_CCU4_SLICE_SetTimerValue(XMC_CCU4_SLICE_t *const slice, const uint16_t timer_val)
1799 {
1800 XMC_ASSERT("XMC_CCU4_SLICE_SetTimerValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1801 slice->TIMER = (uint32_t) timer_val;
1802 }
1803 /**
1804 * @param slice Constant pointer to CC4 Slice
1805 * @param period_dither Boolean instruction on dithering of period match
1806 * @param duty_dither Boolean instruction on dithering of compare match
1807 * @param spread Dither compare value
1808 * @return <BR>
1809 * None<BR>
1810 *
1811 * \par<b>Description:</b><br>
1812 * Enables dithering of PWM frequency and duty cycle, by configuring CC4yTC.DITHE and CC4yDITS bits.\n\n
1813 * Some control loops are slow in updating PWM frequency and duty cycle. In such a case, a Bresenham style dithering
1814 * can help reduce long term errors. Dithering can be applied to period and duty individually,
1815 * this can be selected using the parameter \b period_dither and \b duty_dither.
1816 * The \b spread would provide the dither compare value. If the dither counter value is less than this \b spread then
1817 * the period/compare values would be dithered according to the dither mode selected. This API would invoke
1818 * XMC_CCU4_SLICE_SetDitherCompareValue().
1819 *
1820 * \par<b>Note:</b><br>
1821 * After this API call, XMC_CCU4_EnableShadowTransfer() has to be called with appropriate mask
1822 * to transfer the dither value.
1823 *
1824 * \par<b>Related APIs:</b><br>
1825 * XMC_CCU4_SLICE_DisableDithering().
1826 */
1827 void XMC_CCU4_SLICE_EnableDithering(XMC_CCU4_SLICE_t *const slice,
1828 const bool period_dither,
1829 const bool duty_dither,
1830 const uint8_t spread);
1831
1832 /**
1833 * @param slice Constant pointer to CC4 Slice
1834 * @return <BR>
1835 * None<BR>
1836 *
1837 * \par<b>Description:</b><br>
1838 * Disables dithering of PWM frequency and duty cycle, by clearing CC4yTC.DITHE bits.\n\n
1839 * This disables the Dither mode that was set in XMC_CCU4_SLICE_EnableDithering().
1840 * This API will not clear the dither compare value.
1841 *
1842 * \par<b>Related APIs:</b><br>
1843 * XMC_CCU4_SLICE_EnableDithering().
1844 */
XMC_CCU4_SLICE_DisableDithering(XMC_CCU4_SLICE_t * const slice)1845 __STATIC_INLINE void XMC_CCU4_SLICE_DisableDithering(XMC_CCU4_SLICE_t *const slice)
1846 {
1847 XMC_ASSERT("XMC_CCU4_SLICE_DisableDithering:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1848 slice->TC &= ~((uint32_t) CCU4_CC4_TC_DITHE_Msk);
1849 }
1850
1851 /**
1852 * @param slice Constant pointer to CC4 Slice
1853 * @return <BR>
1854 * None<BR>
1855 *
1856 * \par<b>Description:</b><br>
1857 * Enables the floating prescaler, by setting CC4yTC.FPE bit.\n\n
1858 * The prescaler divider starts with an initial value and increments upon every period match. It keeps incrementing
1859 * until a ceiling (prescaler compare value) is hit and thereafter rolls back to the original prescaler divider value.\n
1860 * It is necessary to have programmed an initial divider value and a compare value before the feature is enabled.
1861 *
1862 * \par<b>Related APIs:</b><br>
1863 * XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue()<BR> XMC_CCU4_SLICE_DisableFloatingPrescaler()<BR>
1864 * XMC_CCU4_SLICE_SetPrescaler().
1865 */
XMC_CCU4_SLICE_EnableFloatingPrescaler(XMC_CCU4_SLICE_t * const slice)1866 __STATIC_INLINE void XMC_CCU4_SLICE_EnableFloatingPrescaler(XMC_CCU4_SLICE_t *const slice)
1867 {
1868 XMC_ASSERT("XMC_CCU4_SLICE_EnableFloatingPrescaler:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1869 slice->TC |= (uint32_t) CCU4_CC4_TC_FPE_Msk;
1870 }
1871
1872 /**
1873 * @param slice Constant pointer to CC4 Slice
1874 * @return <BR>
1875 * None<BR>
1876 *
1877 * \par<b>Description:</b><br>
1878 * Disables the floating prescaler, by clearing CC4yTC.FPE bit.\n\n
1879 * This would return the prescaler to the normal mode.
1880 * The prescaler that would be applied is the value present in CC4yPSC.
1881 *
1882 * \par<b>Related APIs:</b><br>
1883 * XMC_CCU4_SLICE_EnableFloatingPrescaler().
1884 */
XMC_CCU4_SLICE_DisableFloatingPrescaler(XMC_CCU4_SLICE_t * const slice)1885 __STATIC_INLINE void XMC_CCU4_SLICE_DisableFloatingPrescaler(XMC_CCU4_SLICE_t *const slice)
1886 {
1887 XMC_ASSERT("XMC_CCU4_SLICE_DisableFloatingPrescaler:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1888 slice->TC &= ~((uint32_t) CCU4_CC4_TC_FPE_Msk);
1889 }
1890
1891 /**
1892 * @param slice Constant pointer to CC4 Slice
1893 * @param comp_val Dither compare value
1894 * Range: [0x0 to 0xF]
1895 * @return <BR>
1896 * None<BR>
1897 *
1898 * \par<b>Description:</b><br>
1899 * Sets the dither spread/compare value, by setting CC4yDITS.DCVS bits.\n\n
1900 * This value is the cornerstone of PWM dithering feature. Dithering is applied/done when the value in the
1901 * dithering counter is less than this compare/spread value. For all dithering counter values greater than
1902 * the spread value, there is no dithering. After setting the value XMC_CCU4_EnableShadowTransfer() has to be
1903 * called with appropriate mask.
1904 *
1905 * \par<b>Related APIs:</b><br>
1906 * XMC_CCU4_SLICE_EnableDithering().
1907 */
XMC_CCU4_SLICE_SetDitherCompareValue(XMC_CCU4_SLICE_t * const slice,const uint8_t comp_val)1908 __STATIC_INLINE void XMC_CCU4_SLICE_SetDitherCompareValue(XMC_CCU4_SLICE_t *const slice, const uint8_t comp_val)
1909 {
1910 XMC_ASSERT("XMC_CCU4_SLICE_SetDitherCompareValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1911 slice->DITS = comp_val;
1912 }
1913
1914 /**
1915 * @param slice Constant pointer to CC4 Slice
1916 * @param div_val Prescaler divider value. Accepts enum :: XMC_CCU4_SLICE_PRESCALER_t
1917 * Range: [0x0 to 0xF]
1918 * @return <BR>
1919 * None<BR>
1920 *
1921 * \par<b>Description:</b><br>
1922 * Programs the slice specific prescaler divider, by configuring the CC4yPSC and CC4yFPC registers.\n\n
1923 * The prescaler divider may only be programmed after the prescaler run bit has been cleared
1924 * by calling XMC_CCU4_StopPrescaler().
1925 *
1926 * \par<b>Related APIs:</b><br>
1927 * XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue().
1928 */
1929 void XMC_CCU4_SLICE_SetPrescaler(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_PRESCALER_t div_val);
1930
1931 /**
1932 * @param slice Constant pointer to CC4 Slice
1933 * @return <BR>
1934 * XMC_CCU4_SLICE_PRESCALER_t Prescaler divider value.<BR>
1935 *
1936 * \par<b>Description:</b><br>
1937 * Returns current prescaler value.\n\n
1938 * Used to detrmine the clock frequency of the CCU8 slice XMC_SCU_CLOCK_GetCcuClockFrequency() / XMC_CCU4_SLICE_GetPrescaler()
1939 *
1940 * \par<b>Related APIs:</b><br>
1941 * XMC_CCU4_SLICE_SetPrescaler().
1942 */
XMC_CCU4_SLICE_GetPrescaler(XMC_CCU4_SLICE_t * const slice)1943 __STATIC_INLINE XMC_CCU4_SLICE_PRESCALER_t XMC_CCU4_SLICE_GetPrescaler(XMC_CCU4_SLICE_t *const slice)
1944 {
1945 XMC_ASSERT("XMC_CCU8_SLICE_SetPrescaler:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1946
1947 return (XMC_CCU4_SLICE_PRESCALER_t)slice->PSC;
1948 }
1949
1950 /**
1951 * @param slice Constant pointer to CC4 Slice
1952 * @param cmp_val Prescaler divider compare value
1953 * Range: [0x0 to 0xF]
1954 * @return <BR>
1955 * None<BR>
1956 *
1957 * \par<b>Description:</b><br>
1958 * Programs the slice specific prescaler divider compare value, by configuring CC4yFPCS register.\n\n
1959 * The compare value is applicable only in floating mode of operation. The prescaler divider starts with an initial
1960 * value and increments to the compare value steadily upon every period match. Once prescaler divider
1961 * equals the prescaler divider compare value, the value in the former resets back to the PVAL (from FPC). After setting
1962 * the value, XMC_CCU4_EnableShadowTransfer() has to be called with appropriate mask.
1963 *
1964 * \par<b>Related APIs:</b><br>
1965 * XMC_CCU4_SLICE_SetPrescaler().
1966 */
XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue(XMC_CCU4_SLICE_t * const slice,const uint8_t cmp_val)1967 __STATIC_INLINE void XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue(XMC_CCU4_SLICE_t *const slice,
1968 const uint8_t cmp_val)
1969 {
1970 XMC_ASSERT("XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1971 /* write to the shadow register */
1972 slice->FPCS = (uint32_t) cmp_val;
1973 }
1974 /**
1975 * @param slice Constant pointer to CC4 Slice
1976 * @return <BR>
1977 * None<BR>
1978 *
1979 * \par<b>Description:</b><br>
1980 * Enables the multichannel mode, by setting CC4yTC.MCME bit.<BR>\n
1981 * The output state of the Timer slices can be controlled in parallel by a single input signal.
1982 * A particularly useful feature in motor control applications where the PWM output of multiple slices of a module can
1983 * be gated and ungated by multi-channel gating inputs connected to the slices. A peripheral like POSIF connected to the
1984 * motor knows exactly which of the power drive switches are to be turned on and off at any instant. It can thus through
1985 * a gating bus (known as multi-channel inputs) control which of the slices output stays gated/ungated.
1986 *
1987 * \par<b>Related APIs:</b><br>
1988 * XMC_CCU4_SLICE_DisableMultiChannelMode()<BR> XMC_CCU4_SetMultiChannelShadowTransferMode().
1989 */
XMC_CCU4_SLICE_EnableMultiChannelMode(XMC_CCU4_SLICE_t * const slice)1990 __STATIC_INLINE void XMC_CCU4_SLICE_EnableMultiChannelMode(XMC_CCU4_SLICE_t *const slice)
1991 {
1992 XMC_ASSERT("XMC_CCU4_SLICE_EnableMultiChannelMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
1993 slice->TC |= (uint32_t) CCU4_CC4_TC_MCME_Msk;
1994 }
1995
1996 /**
1997 * @param slice Constant pointer to CC4 Slice
1998 * @return <BR>
1999 * None<BR>
2000 *
2001 * \par<b>Description:</b><br>
2002 * Disables the multichannel mode, by clearing CC4yTC.MCME bit.<BR>\n
2003 * This would return the slices to the normal operation mode.
2004 *
2005 * \par<b>Related APIs:</b><br>
2006 * XMC_CCU4_SLICE_EnableMultiChannelMode().
2007 */
XMC_CCU4_SLICE_DisableMultiChannelMode(XMC_CCU4_SLICE_t * const slice)2008 __STATIC_INLINE void XMC_CCU4_SLICE_DisableMultiChannelMode(XMC_CCU4_SLICE_t *const slice)
2009 {
2010 XMC_ASSERT("XMC_CCU4_SLICE_DisableMultiChannelMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
2011 slice->TC &= ~((uint32_t) CCU4_CC4_TC_MCME_Msk);
2012 }
2013
2014 /**
2015 * @param module Constant pointer to CCU4 module
2016 * @param slice_mode_msk Slices for which the configuration has to be applied.
2017 * Use ::XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_t enum items to create a mask of choice,
2018 * using a bit wise OR operation.
2019 * @return <BR>
2020 * None<BR>
2021 *
2022 * \par<b>Description:</b><br>
2023 * Enables the Multi-channel shadow transfer request trigger signal either by software or hardware by configuring
2024 * GCTRL.MSE0, GCTRL.MSE1, GCTRL.MSE2, and GCTRL.MSE3 based on the mask.\n\n
2025 * The shadow transfer would take place either if it was requested by software or by the CCU4x.MCSS input.
2026 *
2027 * \par<b>Related APIs:</b><br>
2028 * None.
2029 */
2030 void XMC_CCU4_SetMultiChannelShadowTransferMode(XMC_CCU4_MODULE_t *const module, const uint32_t slice_mode_msk);
2031
2032 /**
2033 * @param slice Constant pointer to CC4 Slice
2034 * @param reg_num The capture register from which the captured value is to be retrieved
2035 * Range: [0,3]
2036 * @return <BR>
2037 * uint32_t Returns the Capture register value.
2038 * Range: [0 to 0x1FFFFF]
2039 *
2040 * \par<b>Description:</b><br>
2041 * Retrieves timer value which has been captured in the Capture registers, by reading CC4yCV[\b reg_num] register.\n\n
2042 * The signal whose timing characteristics are to be measured must be mapped to an event which in turn must be mapped
2043 * to the capture function. Based on the capture criteria, the timer values are captured into capture registers. Timing
2044 * characteristics of the input signal may then be derived/inferred from the captured values. The full flag will help
2045 * to find out if there is a new captured value present.
2046 *
2047 * \par<b>Related APIs:</b><br>
2048 * XMC_CCU4_SLICE_GetLastCapturedTimerValue().
2049 */
2050 uint32_t XMC_CCU4_SLICE_GetCaptureRegisterValue(const XMC_CCU4_SLICE_t *const slice, const uint8_t reg_num);
2051
2052 /**
2053 * @param slice Constant pointer to CC4 Slice
2054 * @param set The capture register set, which must be evaluated
2055 * @param val_ptr Out Parameter of the API.Stores the captured timer value into this out parameter.
2056 * @return <BR>
2057 * ::XMC_CCU4_STATUS_t Returns XMC_CCU4_STATUS_OK if there was new value present in the capture registers.
2058 * returns XMC_CCU4_STATUS_ERROR if there was no new value present in the capture registers.
2059 *
2060 * \par<b>Description:</b><br>
2061 * Retrieves the latest captured timer value, by reading CC4yCV registers.\n\n
2062 * Retrieve the timer value last stored by the slice. When separate capture events are used,
2063 * users must specify the capture set to evaluate. If single capture event mode is used, all 4 capture registers are
2064 * evaluated.\n
2065 * The lowest register is evaluated first followed by the next higher ordered register and this continues until all
2066 * capture registers have been evaluated.
2067 *
2068 * \par<b>Related APIs:</b><br>
2069 * XMC_CCU4_SLICE_GetCaptureRegisterValue().
2070 */
2071 XMC_CCU4_STATUS_t XMC_CCU4_SLICE_GetLastCapturedTimerValue(const XMC_CCU4_SLICE_t *const slice,
2072 const XMC_CCU4_SLICE_CAP_REG_SET_t set,
2073 uint32_t *val_ptr);
2074
2075 /**
2076 * @param slice Constant pointer to CC4 Slice
2077 * @param event Event whose assertion can potentially lead to an interrupt
2078 * @return <BR>
2079 * None<BR>
2080 *
2081 * \par<b>Description:</b><br>
2082 * Enables the generation of an interrupt pulse for the event, by configuring CC4yINTE register.\n\n
2083 * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding
2084 * NVIC node must be enabled as well. This API merely enables the event. Binding with SR is performed by another API.
2085 *
2086 * \par<b>Related APIs:</b><br>
2087 * XMC_CCU4_SLICE_SetInterruptNode()<BR> XMC_CCU4_SLICE_EnableMultipleEvents()<BR> XMC_CCU4_SLICE_DisableEvent()<BR>
2088 * XMC_CCU4_SLICE_DisableMultipleEvents().
2089 */
XMC_CCU4_SLICE_EnableEvent(XMC_CCU4_SLICE_t * const slice,const XMC_CCU4_SLICE_IRQ_ID_t event)2090 __STATIC_INLINE void XMC_CCU4_SLICE_EnableEvent(XMC_CCU4_SLICE_t *const slice,
2091 const XMC_CCU4_SLICE_IRQ_ID_t event)
2092 {
2093 XMC_ASSERT("XMC_CCU4_SLICE_EnableEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
2094 XMC_ASSERT("XMC_CCU4_SLICE_EnableEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event));
2095 slice->INTE |= ((uint32_t) 1) << ((uint32_t) event);
2096 }
2097
2098 /**
2099 * @param slice Constant pointer to CC4 Slice
2100 * @param intr_mask Event mask such that multiple events can be enabled.
2101 * Use ::XMC_CCU4_SLICE_MULTI_IRQ_ID_t enum items to create a mask of choice,
2102 * using a bit wise OR operation.
2103 * @return <BR>
2104 * None<BR>
2105 *
2106 * \par<b>Description:</b><br>
2107 * Enables the generation of an interrupt pulse for the required events, by configuring CC4yINTE register.\n\n
2108 * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding
2109 * NVIC node must be enabled as well. This API merely enables the events. Binding with SR is performed by another API.
2110 *
2111 * \par<b>Related APIs:</b><br>
2112 * XMC_CCU4_SLICE_SetInterruptNode()<BR> XMC_CCU4_SLICE_EnableEvent()<BR> XMC_CCU4_SLICE_DisableEvent()<BR>
2113 * XMC_CCU4_SLICE_DisableMultipleEvents().
2114 */
XMC_CCU4_SLICE_EnableMultipleEvents(XMC_CCU4_SLICE_t * const slice,const uint16_t intr_mask)2115 __STATIC_INLINE void XMC_CCU4_SLICE_EnableMultipleEvents(XMC_CCU4_SLICE_t *const slice, const uint16_t intr_mask)
2116 {
2117 XMC_ASSERT("XMC_CCU4_SLICE_EnableMultipleEvents:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
2118 slice->INTE |= (uint32_t)intr_mask;
2119 }
2120
2121 /**
2122 * @param slice Constant pointer to CC4 Slice
2123 * @param event Event whose assertion can potentially lead to an interrupt
2124 * @return <BR>
2125 * None<BR>
2126 *
2127 * \par<b>Description:</b><br>
2128 * Disables the generation of an interrupt pulse for the event, by clearing CC4yINTE register.\n\n
2129 * Prevents the event from being asserted
2130 *
2131 * \par<b>Related APIs:</b><br>
2132 * XMC_CCU4_SLICE_SetInterruptNode()<BR> XMC_CCU4_SLICE_EnableEvent()<BR> XMC_CCU4_SLICE_EnableMultipleEvents()<BR>
2133 * XMC_CCU4_SLICE_DisableMultipleEvents().
2134 */
XMC_CCU4_SLICE_DisableEvent(XMC_CCU4_SLICE_t * const slice,const XMC_CCU4_SLICE_IRQ_ID_t event)2135 __STATIC_INLINE void XMC_CCU4_SLICE_DisableEvent(XMC_CCU4_SLICE_t *const slice,
2136 const XMC_CCU4_SLICE_IRQ_ID_t event)
2137 {
2138 XMC_ASSERT("XMC_CCU4_SLICE_DisableEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
2139 XMC_ASSERT("XMC_CCU4_SLICE_DisableEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event));
2140 slice->INTE &= ~(((uint32_t) 1) << ((uint32_t) event));
2141 }
2142
2143 /**
2144 * @param slice Constant pointer to CC4 Slice
2145 * @param mask Event mask such that multiple events can be enabled.
2146 * Use ::XMC_CCU4_SLICE_MULTI_IRQ_ID_t enum items to create a mask of choice,
2147 * using a bit wise OR operation.
2148 * @return <BR>
2149 * None<BR>
2150 *
2151 * \par<b>Description:</b><br>
2152 * Disables the generation of an interrupt pulse for the required events, by clearing CC4yINTE register.\n\n
2153 * Prevents selected events of the slice from being asserted.
2154 *
2155 * \par<b>Related APIs:</b><br>
2156 * XMC_CCU4_SLICE_SetInterruptNode()<BR> XMC_CCU4_SLICE_EnableEvent()<BR> XMC_CCU4_SLICE_EnableMultipleEvents()<BR>
2157 * XMC_CCU4_SLICE_DisableEvent().
2158 */
XMC_CCU4_SLICE_DisableMultipleEvents(XMC_CCU4_SLICE_t * const slice,const uint16_t mask)2159 __STATIC_INLINE void XMC_CCU4_SLICE_DisableMultipleEvents(XMC_CCU4_SLICE_t *const slice, const uint16_t mask)
2160 {
2161 XMC_ASSERT("XMC_CCU4_SLICE_DisableMultipleEvents:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
2162 slice->INTE &= ~((uint32_t) mask);
2163 }
2164
2165 /**
2166 * @param slice Constant pointer to CC4 Slice
2167 * @param event Event whose assertion can potentially lead to an interrupt
2168 * @return <BR>
2169 * None<BR>
2170 *
2171 * \par<b>Description:</b><br>
2172 * Manually asserts the requested event, by setting CC4ySWS register.\n\n
2173 * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding
2174 * NVIC node must be enabled as well. This API manually asserts the requested event.
2175 *
2176 * \par<b>Related APIs:</b><br>
2177 * XMC_CCU4_SLICE_SetInterruptNode()<BR> XMC_CCU4_SLICE_EnableEvent()<BR> XMC_CCU4_SLICE_EnableMultipleEvents().
2178 */
XMC_CCU4_SLICE_SetEvent(XMC_CCU4_SLICE_t * const slice,const XMC_CCU4_SLICE_IRQ_ID_t event)2179 __STATIC_INLINE void XMC_CCU4_SLICE_SetEvent(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_IRQ_ID_t event)
2180 {
2181 XMC_ASSERT("XMC_CCU4_SLICE_SetEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
2182 XMC_ASSERT("XMC_CCU4_SLICE_SetEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event));
2183 slice->SWS = ((uint32_t) 1) << ((uint32_t) event);
2184 }
2185
2186 /**
2187 * @param slice Constant pointer to CC4 Slice
2188 * @param event Asserted event which must be acknowledged.
2189 * @return <BR>
2190 * None<BR>
2191 *
2192 * \par<b>Description:</b><br>
2193 * Acknowledges an asserted event, by setting CC4ySWR with respective event flag.\n\n
2194 *
2195 * \par<b>Related APIs:</b><br>
2196 * XMC_CCU4_SLICE_EnableEvent()<BR> XMC_CCU4_SLICE_SetEvent()<BR> XMC_CCU4_SLICE_GetEvent().
2197 */
XMC_CCU4_SLICE_ClearEvent(XMC_CCU4_SLICE_t * const slice,const XMC_CCU4_SLICE_IRQ_ID_t event)2198 __STATIC_INLINE void XMC_CCU4_SLICE_ClearEvent(XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_IRQ_ID_t event)
2199 {
2200 XMC_ASSERT("XMC_CCU4_SLICE_ClearEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
2201 XMC_ASSERT("XMC_CCU4_SLICE_ClearEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event));
2202 slice->SWR = ((uint32_t) 1) << ((uint32_t) event);
2203 }
2204
2205 /**
2206 * @param slice Constant pointer to CC4 Slice
2207 * @param event Event to be evaluated for assertion
2208 * @return <br>
2209 * bool Returns true if event is set else false is returned.
2210 *
2211 * \par<b>Description:</b><br>
2212 * Evaluates if a given event is asserted or not, by reading CC4yINTS register.\n\n
2213 * Return true if the event is asserted. For a event to be asserted it has to be
2214 * first enabled. Only if that event is enabled the call to this API is valid.
2215 * If the Event is enabled and has not yet occurred then a false is returned.
2216 *
2217 * \par<b>Related APIs:</b><br>
2218 * XMC_CCU4_SLICE_EnableEvent()<BR> XMC_CCU4_SLICE_SetEvent().
2219 */
XMC_CCU4_SLICE_GetEvent(const XMC_CCU4_SLICE_t * const slice,const XMC_CCU4_SLICE_IRQ_ID_t event)2220 __STATIC_INLINE bool XMC_CCU4_SLICE_GetEvent(const XMC_CCU4_SLICE_t *const slice, const XMC_CCU4_SLICE_IRQ_ID_t event)
2221 {
2222 XMC_ASSERT("XMC_CCU4_SLICE_GetEvent:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
2223 XMC_ASSERT("XMC_CCU4_SLICE_GetEvent:Invalid SR event", XMC_CCU4_SLICE_CHECK_INTERRUPT(event));
2224
2225 return(((uint32_t)(slice->INTS & ((uint32_t)1 << (uint32_t)event))) != 0U);
2226 }
2227 /**
2228 * @param slice Constant pointer to CC4 Slice
2229 * @param event Event which must be bound to a service request line
2230 * @param sr The Service request line which is bound to the \b event
2231 * @return <BR>
2232 * None<BR>
2233 *
2234 * \par<b>Description:</b><br>
2235 * Binds requested event to a service request line, by configuring CC4ySRS register with respective event.\n\n
2236 * For an event to lead to an interrupt, it must first be enabled and bound to a service request line. The corresponding
2237 * NVIC node must be enabled as well. This API binds the requested event with the requested service request line(\b sr).
2238 *
2239 * \par<b>Related APIs:</b><br>
2240 * XMC_CCU4_SLICE_EnableEvent()<BR> XMC_CCU4_SLICE_SetEvent().
2241 */
2242 void XMC_CCU4_SLICE_SetInterruptNode(XMC_CCU4_SLICE_t *const slice,
2243 const XMC_CCU4_SLICE_IRQ_ID_t event,
2244 const XMC_CCU4_SLICE_SR_ID_t sr);
2245
2246 /**
2247 * @param slice Constant pointer to CC4 Slice
2248 * @param level Slice output passive level
2249 * @return <BR>
2250 * None<BR>
2251 *
2252 * \par<b>Description:</b><br>
2253 * Configures the passive level for the slice output, by setting CC4yPSL register.\n\n
2254 * Defines the passive level for the timer slice output pin. Selects either level high is passive
2255 * or level low is passive. This is the level of the output before the compare match is value changes it.
2256 *
2257 * \par<b>Related APIs:</b><br>
2258 * XMC_CCU4_SLICE_EnableEvent()<BR> XMC_CCU4_SLICE_SetEvent().
2259 */
2260 void XMC_CCU4_SLICE_SetPassiveLevel(XMC_CCU4_SLICE_t *const slice,
2261 const XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t level);
2262
2263 #if defined(CCU4V3) || defined(DOXYGEN) /* Defined for XMC1400 devices only */
2264 /**
2265 * @param slice Constant pointer to CC4 Slice
2266 *
2267 * @return <BR>
2268 * None<BR>
2269 *
2270 * \par<b>Description:</b><br>
2271 * Cascades the shadow transfer operation throughout the CCU4 timer slices, by setting CSE bit in STC register.\n\n
2272 *
2273 * The shadow transfer enable bits needs to be set in all timer slices, that are being used in the cascaded architecture,
2274 * at the same time. The shadow transfer enable bits, also need to be set for all slices even if the shadow values of
2275 * some slices were not updated. It is possible to to cascade with the adjacent slices only. CC40 slice is a
2276 * master to start the operation.
2277 *
2278 * \par<b>Note:</b><br>
2279 * XMC_CCU4_EnableShadowTransfer() must be called to enable the shadow transfer of the all the slices, which needs to be
2280 * cascaded.
2281 *
2282 * \par<b>Related APIs:</b><br>
2283 * XMC_CCU4_EnableShadowTransfer(), XMC_CCU4_SLICE_DisableCascadedShadowTransfer()<BR>.
2284 * @note Only available for XMC1400 series
2285 */
XMC_CCU4_SLICE_EnableCascadedShadowTransfer(XMC_CCU4_SLICE_t * const slice)2286 __STATIC_INLINE void XMC_CCU4_SLICE_EnableCascadedShadowTransfer(XMC_CCU4_SLICE_t *const slice)
2287 {
2288 XMC_ASSERT("XMC_CCU4_SLICE_EnableCascadedShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
2289 slice->STC |= (uint32_t) CCU4_CC4_STC_CSE_Msk;
2290 }
2291
2292 /**
2293 * @param slice Constant pointer to CC4 Slice
2294 *
2295 * @return <BR>
2296 * None<BR>
2297 *
2298 * \par<b>Description:</b><br>
2299 * Disables the cascaded the shadow transfer operation, by clearing CSE bit in STC register.\n\n
2300 *
2301 * If in any slice the cascaded mode disabled, other slices from there onwards does not update the values in cascaded mode.
2302 *
2303 * \par<b>Related APIs:</b><br>
2304 * XMC_CCU4_SLICE_EnableCascadedShadowTransfer()<BR>.
2305 * @note Only available for XMC1400 series
2306 */
XMC_CCU4_SLICE_DisableCascadedShadowTransfer(XMC_CCU4_SLICE_t * const slice)2307 __STATIC_INLINE void XMC_CCU4_SLICE_DisableCascadedShadowTransfer(XMC_CCU4_SLICE_t *const slice)
2308 {
2309 XMC_ASSERT("XMC_CCU4_SLICE_DisableCascadedShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
2310 slice->STC &= ~(uint32_t) CCU4_CC4_STC_CSE_Msk;
2311 }
2312
2313 /**
2314 * @param slice Constant pointer to CC4 Slice
2315 * @param shadow_transfer_mode mode to be configured
2316 * Use :: XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t enum items for mode
2317 * @return <BR>
2318 * None<BR>
2319 *
2320 * \par<b>Description:</b><br>
2321 * Configures when the shadow transfer has to occur, by setting STM bit in STC register.\n\n
2322 *
2323 * After requesting for shadow transfer mode using XMC_CCU4_EnableShadowTransfer(), actual transfer occurs based on the
2324 * selection done using this API (i.e. on period and One match, on Period match only, on One match only).
2325 *
2326 * \par<b>Note:</b><br>
2327 * This is effective when the timer is configured in centre aligned mode.
2328 *
2329 * \par<b>Related APIs:</b><br>
2330 * XMC_CCU4_EnableShadowTransfer()<BR>
2331 * @note Only available for XMC1400 series
2332 */
XMC_CCU4_SLICE_SetShadowTransferMode(XMC_CCU4_SLICE_t * const slice,const XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t shadow_transfer_mode)2333 __STATIC_INLINE void XMC_CCU4_SLICE_SetShadowTransferMode(XMC_CCU4_SLICE_t *const slice,
2334 const XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t shadow_transfer_mode)
2335 {
2336 XMC_ASSERT("XMC_CCU4_SLICE_SetShadowTransferMode:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
2337 slice->STC = ((slice->STC) & (uint32_t)~CCU4_CC4_STC_STM_Msk) |
2338 ((shadow_transfer_mode << CCU4_CC4_STC_STM_Pos) & (uint32_t)CCU4_CC4_STC_STM_Msk);
2339 }
2340
2341 /**
2342 * @param slice Constant pointer to CC4 Slice
2343 * @param coherent_write specifies for what fields this mode has to be applied
2344 * Use :: XMC_CCU4_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation.
2345 * @return <BR>
2346 * None<BR>
2347 *
2348 * \par<b>Description:</b><br>
2349 * Configures the specified fields shadow value to be updated in synchronous with PWM after shadow transfer request, by
2350 * clearing IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n
2351 *
2352 * When coherent shadow is enabled, after calling XMC_CCU4_EnableShadowTransfer(), the value which are written in the
2353 * respective shadow registers get updated according the configuration done using XMC_CCU4_SLICE_SetShadowTransferMode()
2354 * API. \par<b>Note:</b><br>
2355 *
2356 * \par<b>Related APIs:</b><br>
2357 * XMC_CCU4_EnableShadowTransfer(), XMC_CCU4_SLICE_SetShadowTransferMode()<BR>
2358 * @note Only available for XMC1400 series
2359 */
XMC_CCU4_SLICE_WriteCoherentlyWithPWMCycle(XMC_CCU4_SLICE_t * const slice,const uint32_t coherent_write)2360 __STATIC_INLINE void XMC_CCU4_SLICE_WriteCoherentlyWithPWMCycle(XMC_CCU4_SLICE_t *const slice,
2361 const uint32_t coherent_write)
2362 {
2363 XMC_ASSERT("XMC_CCU4_SLICE_WriteCoherentlyWithPWMCycle:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
2364 slice->STC &= ~(uint32_t)coherent_write;
2365 }
2366
2367 /**
2368 * @param slice Constant pointer to CC4 Slice
2369 * @param immediate_write specifies for what fields this mode has to be applied
2370 * Use :: XMC_CCU4_SLICE_WRITE_INTO_t enum items to create a mask of choice, using a bit wise OR operation.
2371 * @return <BR>
2372 * None<BR>
2373 *
2374 * \par<b>Description:</b><br>
2375 * Configures the specified fields shadow value to be updated immediately after shadow transfer request, by setting
2376 * IRPC, IRCC1, IRCC2, IRLC, IRDC, IRFC bits in STC register.\n\n
2377 *
2378 * When immediate shadow is enabled, by calling XMC_CCU4_EnableShadowTransfer() the value which are written in the
2379 * shadow registers get updated to the actual registers immediately. \par<b>Note:</b><br>
2380 *
2381 * \par<b>Related APIs:</b><br>
2382 * XMC_CCU4_EnableShadowTransfer()<BR>
2383 * @note Only available for XMC1400 series
2384 */
XMC_CCU4_SLICE_WriteImmediateAfterShadowTransfer(XMC_CCU4_SLICE_t * const slice,const uint32_t immediate_write)2385 __STATIC_INLINE void XMC_CCU4_SLICE_WriteImmediateAfterShadowTransfer(XMC_CCU4_SLICE_t *const slice,
2386 const uint32_t immediate_write)
2387 {
2388 XMC_ASSERT("XMC_CCU4_SLICE_WriteImmediateAfterShadowTransfer:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
2389 slice->STC |= immediate_write;
2390 }
2391
2392 /**
2393 * @param slice Constant pointer to CC4 Slice
2394 * @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request is generated
2395 * Use :: XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a
2396 * bit wise OR operation.
2397 * @return <BR>
2398 * None<BR>
2399 *
2400 * \par<b>Description:</b><br>
2401 * Configure on which shadow register update, automatic shadow transfer request generation has to be enabled. By setting
2402 * ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n
2403 *
2404 * By updating the configured shadow register, the shadow transfer request is generated to update all the shadow registers.
2405 * \par<b>Note:</b><br>
2406 *
2407 * \par<b>Related APIs:</b><br>
2408 * XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest().
2409 * @note Only available for XMC1400 series
2410 */
XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest(XMC_CCU4_SLICE_t * const slice,const uint32_t automatic_shadow_transfer)2411 __STATIC_INLINE void XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest(XMC_CCU4_SLICE_t *const slice,
2412 const uint32_t automatic_shadow_transfer)
2413 {
2414 XMC_ASSERT("XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
2415 slice->STC |= automatic_shadow_transfer;
2416 }
2417
2418 /**
2419 * @param slice Constant pointer to CC4 Slice
2420 * @param automatic_shadow_transfer specify upon which register update, automatic shadow transfer request should not be
2421 * generated
2422 * Use :: XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t enum items to create a mask of choice, using a
2423 * bit wise OR operation.
2424 * @return <BR>
2425 * None<BR>
2426 *
2427 * \par<b>Description:</b><br>
2428 * Configure on which shadow register update, automatic shadow transfer request generation has to be disabled. By
2429 * clearing ASPC, ASCC1, ASCC2, ASLC, ASDC, ASFC bits in STC register.\n\n
2430 *
2431 * This disables the generation of automatic shadow transfer request for the specified register update.
2432 * \par<b>Note:</b><br>
2433 *
2434 * \par<b>Related APIs:</b><br>
2435 * XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest().
2436 * @note Only available for XMC1400 series
2437 */
XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest(XMC_CCU4_SLICE_t * const slice,const uint32_t automatic_shadow_transfer)2438 __STATIC_INLINE void XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest(XMC_CCU4_SLICE_t *const slice,
2439 const uint32_t automatic_shadow_transfer)
2440 {
2441 XMC_ASSERT("XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest:Invalid Slice Pointer", XMC_CCU4_IsValidSlice(slice));
2442 slice->STC &= ~(uint32_t)automatic_shadow_transfer;
2443 }
2444 #endif
2445
2446 /**
2447 * @param module Constant pointer to CCU4 module
2448 * @param slice_number Slice for which the clock should be disabled.
2449 * Range: [0x0 to 0x3]
2450 * @return status bit of slice passive (false) or active (true)
2451 *
2452 * \par<b>Description:</b><br>
2453 * Returns CCU4 slice status bit (passive or active)
2454 *
2455 */
XMC_CCU4_GetSliceStatusBit(XMC_CCU4_MODULE_t * const module,uint8_t slice_number)2456 __STATIC_INLINE XMC_CCU4_SLICE_STATUS_BIT_t XMC_CCU4_GetSliceStatusBit(XMC_CCU4_MODULE_t *const module, uint8_t slice_number)
2457 {
2458 return (XMC_CCU4_SLICE_STATUS_BIT_t)((module->GCST & (CCU4_GCST_CC40ST_Msk << slice_number)) ? 1 : 0);
2459 }
2460
2461 #ifdef __cplusplus
2462 }
2463 #endif
2464
2465 /**
2466 * @}
2467 */
2468
2469 /**
2470 * @}
2471 */
2472
2473 #endif /* defined(CCU40) */
2474
2475 #endif /* CCU4_H */
2476
