1 /***************************************************************************//** 2 * \file cyip_usbfs.h 3 * 4 * \brief 5 * USBFS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_USBFS_H_ 28 #define _CYIP_USBFS_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * USBFS 34 *******************************************************************************/ 35 36 #define USBFS_USBDEV_SECTION_SIZE 0x00002000UL 37 #define USBFS_USBLPM_SECTION_SIZE 0x00001000UL 38 #define USBFS_USBHOST_SECTION_SIZE 0x00002000UL 39 #define USBFS_SECTION_SIZE 0x00010000UL 40 41 /** 42 * \brief USB Device (USBFS_USBDEV) 43 */ 44 typedef struct { 45 __IOM uint32_t EP0_DR[8]; /*!< 0x00000000 Control End point EP0 Data Register */ 46 __IOM uint32_t CR0; /*!< 0x00000020 USB control 0 Register */ 47 __IOM uint32_t CR1; /*!< 0x00000024 USB control 1 Register */ 48 __IOM uint32_t SIE_EP_INT_EN; /*!< 0x00000028 USB SIE Data Endpoints Interrupt Enable Register */ 49 __IOM uint32_t SIE_EP_INT_SR; /*!< 0x0000002C USB SIE Data Endpoint Interrupt Status */ 50 __IOM uint32_t SIE_EP1_CNT0; /*!< 0x00000030 Non-control endpoint count register */ 51 __IOM uint32_t SIE_EP1_CNT1; /*!< 0x00000034 Non-control endpoint count register */ 52 __IOM uint32_t SIE_EP1_CR0; /*!< 0x00000038 Non-control endpoint's control Register */ 53 __IM uint32_t RESERVED; 54 __IOM uint32_t USBIO_CR0; /*!< 0x00000040 USBIO Control 0 Register */ 55 __IOM uint32_t USBIO_CR2; /*!< 0x00000044 USBIO control 2 Register */ 56 __IOM uint32_t USBIO_CR1; /*!< 0x00000048 USBIO control 1 Register */ 57 __IM uint32_t RESERVED1; 58 __IOM uint32_t DYN_RECONFIG; /*!< 0x00000050 USB Dynamic reconfiguration register */ 59 __IM uint32_t RESERVED2[3]; 60 __IM uint32_t SOF0; /*!< 0x00000060 Start Of Frame Register */ 61 __IM uint32_t SOF1; /*!< 0x00000064 Start Of Frame Register */ 62 __IM uint32_t RESERVED3[2]; 63 __IOM uint32_t SIE_EP2_CNT0; /*!< 0x00000070 Non-control endpoint count register */ 64 __IOM uint32_t SIE_EP2_CNT1; /*!< 0x00000074 Non-control endpoint count register */ 65 __IOM uint32_t SIE_EP2_CR0; /*!< 0x00000078 Non-control endpoint's control Register */ 66 __IM uint32_t RESERVED4; 67 __IM uint32_t OSCLK_DR0; /*!< 0x00000080 Oscillator lock data register 0 */ 68 __IM uint32_t OSCLK_DR1; /*!< 0x00000084 Oscillator lock data register 1 */ 69 __IM uint32_t RESERVED5[6]; 70 __IOM uint32_t EP0_CR; /*!< 0x000000A0 Endpoint0 control Register */ 71 __IOM uint32_t EP0_CNT; /*!< 0x000000A4 Endpoint0 count Register */ 72 __IM uint32_t RESERVED6[2]; 73 __IOM uint32_t SIE_EP3_CNT0; /*!< 0x000000B0 Non-control endpoint count register */ 74 __IOM uint32_t SIE_EP3_CNT1; /*!< 0x000000B4 Non-control endpoint count register */ 75 __IOM uint32_t SIE_EP3_CR0; /*!< 0x000000B8 Non-control endpoint's control Register */ 76 __IM uint32_t RESERVED7[13]; 77 __IOM uint32_t SIE_EP4_CNT0; /*!< 0x000000F0 Non-control endpoint count register */ 78 __IOM uint32_t SIE_EP4_CNT1; /*!< 0x000000F4 Non-control endpoint count register */ 79 __IOM uint32_t SIE_EP4_CR0; /*!< 0x000000F8 Non-control endpoint's control Register */ 80 __IM uint32_t RESERVED8[13]; 81 __IOM uint32_t SIE_EP5_CNT0; /*!< 0x00000130 Non-control endpoint count register */ 82 __IOM uint32_t SIE_EP5_CNT1; /*!< 0x00000134 Non-control endpoint count register */ 83 __IOM uint32_t SIE_EP5_CR0; /*!< 0x00000138 Non-control endpoint's control Register */ 84 __IM uint32_t RESERVED9[13]; 85 __IOM uint32_t SIE_EP6_CNT0; /*!< 0x00000170 Non-control endpoint count register */ 86 __IOM uint32_t SIE_EP6_CNT1; /*!< 0x00000174 Non-control endpoint count register */ 87 __IOM uint32_t SIE_EP6_CR0; /*!< 0x00000178 Non-control endpoint's control Register */ 88 __IM uint32_t RESERVED10[13]; 89 __IOM uint32_t SIE_EP7_CNT0; /*!< 0x000001B0 Non-control endpoint count register */ 90 __IOM uint32_t SIE_EP7_CNT1; /*!< 0x000001B4 Non-control endpoint count register */ 91 __IOM uint32_t SIE_EP7_CR0; /*!< 0x000001B8 Non-control endpoint's control Register */ 92 __IM uint32_t RESERVED11[13]; 93 __IOM uint32_t SIE_EP8_CNT0; /*!< 0x000001F0 Non-control endpoint count register */ 94 __IOM uint32_t SIE_EP8_CNT1; /*!< 0x000001F4 Non-control endpoint count register */ 95 __IOM uint32_t SIE_EP8_CR0; /*!< 0x000001F8 Non-control endpoint's control Register */ 96 __IM uint32_t RESERVED12; 97 __IOM uint32_t ARB_EP1_CFG; /*!< 0x00000200 Endpoint Configuration Register *1 */ 98 __IOM uint32_t ARB_EP1_INT_EN; /*!< 0x00000204 Endpoint Interrupt Enable Register *1 */ 99 __IOM uint32_t ARB_EP1_SR; /*!< 0x00000208 Endpoint Interrupt Enable Register *1 */ 100 __IM uint32_t RESERVED13; 101 __IOM uint32_t ARB_RW1_WA; /*!< 0x00000210 Endpoint Write Address value *1, *2 */ 102 __IOM uint32_t ARB_RW1_WA_MSB; /*!< 0x00000214 Endpoint Write Address value *1, *2 */ 103 __IOM uint32_t ARB_RW1_RA; /*!< 0x00000218 Endpoint Read Address value *1, *2 */ 104 __IOM uint32_t ARB_RW1_RA_MSB; /*!< 0x0000021C Endpoint Read Address value *1, *2 */ 105 __IOM uint32_t ARB_RW1_DR; /*!< 0x00000220 Endpoint Data Register */ 106 __IM uint32_t RESERVED14[3]; 107 __IOM uint32_t BUF_SIZE; /*!< 0x00000230 Dedicated Endpoint Buffer Size Register *1 */ 108 __IM uint32_t RESERVED15; 109 __IOM uint32_t EP_ACTIVE; /*!< 0x00000238 Endpoint Active Indication Register *1 */ 110 __IOM uint32_t EP_TYPE; /*!< 0x0000023C Endpoint Type (IN/OUT) Indication *1 */ 111 __IOM uint32_t ARB_EP2_CFG; /*!< 0x00000240 Endpoint Configuration Register *1 */ 112 __IOM uint32_t ARB_EP2_INT_EN; /*!< 0x00000244 Endpoint Interrupt Enable Register *1 */ 113 __IOM uint32_t ARB_EP2_SR; /*!< 0x00000248 Endpoint Interrupt Enable Register *1 */ 114 __IM uint32_t RESERVED16; 115 __IOM uint32_t ARB_RW2_WA; /*!< 0x00000250 Endpoint Write Address value *1, *2 */ 116 __IOM uint32_t ARB_RW2_WA_MSB; /*!< 0x00000254 Endpoint Write Address value *1, *2 */ 117 __IOM uint32_t ARB_RW2_RA; /*!< 0x00000258 Endpoint Read Address value *1, *2 */ 118 __IOM uint32_t ARB_RW2_RA_MSB; /*!< 0x0000025C Endpoint Read Address value *1, *2 */ 119 __IOM uint32_t ARB_RW2_DR; /*!< 0x00000260 Endpoint Data Register */ 120 __IM uint32_t RESERVED17[3]; 121 __IOM uint32_t ARB_CFG; /*!< 0x00000270 Arbiter Configuration Register *1 */ 122 __IOM uint32_t USB_CLK_EN; /*!< 0x00000274 USB Block Clock Enable Register */ 123 __IOM uint32_t ARB_INT_EN; /*!< 0x00000278 Arbiter Interrupt Enable *1 */ 124 __IM uint32_t ARB_INT_SR; /*!< 0x0000027C Arbiter Interrupt Status *1 */ 125 __IOM uint32_t ARB_EP3_CFG; /*!< 0x00000280 Endpoint Configuration Register *1 */ 126 __IOM uint32_t ARB_EP3_INT_EN; /*!< 0x00000284 Endpoint Interrupt Enable Register *1 */ 127 __IOM uint32_t ARB_EP3_SR; /*!< 0x00000288 Endpoint Interrupt Enable Register *1 */ 128 __IM uint32_t RESERVED18; 129 __IOM uint32_t ARB_RW3_WA; /*!< 0x00000290 Endpoint Write Address value *1, *2 */ 130 __IOM uint32_t ARB_RW3_WA_MSB; /*!< 0x00000294 Endpoint Write Address value *1, *2 */ 131 __IOM uint32_t ARB_RW3_RA; /*!< 0x00000298 Endpoint Read Address value *1, *2 */ 132 __IOM uint32_t ARB_RW3_RA_MSB; /*!< 0x0000029C Endpoint Read Address value *1, *2 */ 133 __IOM uint32_t ARB_RW3_DR; /*!< 0x000002A0 Endpoint Data Register */ 134 __IM uint32_t RESERVED19[3]; 135 __IOM uint32_t CWA; /*!< 0x000002B0 Common Area Write Address *1 */ 136 __IOM uint32_t CWA_MSB; /*!< 0x000002B4 Endpoint Read Address value *1 */ 137 __IM uint32_t RESERVED20[2]; 138 __IOM uint32_t ARB_EP4_CFG; /*!< 0x000002C0 Endpoint Configuration Register *1 */ 139 __IOM uint32_t ARB_EP4_INT_EN; /*!< 0x000002C4 Endpoint Interrupt Enable Register *1 */ 140 __IOM uint32_t ARB_EP4_SR; /*!< 0x000002C8 Endpoint Interrupt Enable Register *1 */ 141 __IM uint32_t RESERVED21; 142 __IOM uint32_t ARB_RW4_WA; /*!< 0x000002D0 Endpoint Write Address value *1, *2 */ 143 __IOM uint32_t ARB_RW4_WA_MSB; /*!< 0x000002D4 Endpoint Write Address value *1, *2 */ 144 __IOM uint32_t ARB_RW4_RA; /*!< 0x000002D8 Endpoint Read Address value *1, *2 */ 145 __IOM uint32_t ARB_RW4_RA_MSB; /*!< 0x000002DC Endpoint Read Address value *1, *2 */ 146 __IOM uint32_t ARB_RW4_DR; /*!< 0x000002E0 Endpoint Data Register */ 147 __IM uint32_t RESERVED22[3]; 148 __IOM uint32_t DMA_THRES; /*!< 0x000002F0 DMA Burst / Threshold Configuration */ 149 __IOM uint32_t DMA_THRES_MSB; /*!< 0x000002F4 DMA Burst / Threshold Configuration */ 150 __IM uint32_t RESERVED23[2]; 151 __IOM uint32_t ARB_EP5_CFG; /*!< 0x00000300 Endpoint Configuration Register *1 */ 152 __IOM uint32_t ARB_EP5_INT_EN; /*!< 0x00000304 Endpoint Interrupt Enable Register *1 */ 153 __IOM uint32_t ARB_EP5_SR; /*!< 0x00000308 Endpoint Interrupt Enable Register *1 */ 154 __IM uint32_t RESERVED24; 155 __IOM uint32_t ARB_RW5_WA; /*!< 0x00000310 Endpoint Write Address value *1, *2 */ 156 __IOM uint32_t ARB_RW5_WA_MSB; /*!< 0x00000314 Endpoint Write Address value *1, *2 */ 157 __IOM uint32_t ARB_RW5_RA; /*!< 0x00000318 Endpoint Read Address value *1, *2 */ 158 __IOM uint32_t ARB_RW5_RA_MSB; /*!< 0x0000031C Endpoint Read Address value *1, *2 */ 159 __IOM uint32_t ARB_RW5_DR; /*!< 0x00000320 Endpoint Data Register */ 160 __IM uint32_t RESERVED25[3]; 161 __IOM uint32_t BUS_RST_CNT; /*!< 0x00000330 Bus Reset Count Register */ 162 __IM uint32_t RESERVED26[3]; 163 __IOM uint32_t ARB_EP6_CFG; /*!< 0x00000340 Endpoint Configuration Register *1 */ 164 __IOM uint32_t ARB_EP6_INT_EN; /*!< 0x00000344 Endpoint Interrupt Enable Register *1 */ 165 __IOM uint32_t ARB_EP6_SR; /*!< 0x00000348 Endpoint Interrupt Enable Register *1 */ 166 __IM uint32_t RESERVED27; 167 __IOM uint32_t ARB_RW6_WA; /*!< 0x00000350 Endpoint Write Address value *1, *2 */ 168 __IOM uint32_t ARB_RW6_WA_MSB; /*!< 0x00000354 Endpoint Write Address value *1, *2 */ 169 __IOM uint32_t ARB_RW6_RA; /*!< 0x00000358 Endpoint Read Address value *1, *2 */ 170 __IOM uint32_t ARB_RW6_RA_MSB; /*!< 0x0000035C Endpoint Read Address value *1, *2 */ 171 __IOM uint32_t ARB_RW6_DR; /*!< 0x00000360 Endpoint Data Register */ 172 __IM uint32_t RESERVED28[7]; 173 __IOM uint32_t ARB_EP7_CFG; /*!< 0x00000380 Endpoint Configuration Register *1 */ 174 __IOM uint32_t ARB_EP7_INT_EN; /*!< 0x00000384 Endpoint Interrupt Enable Register *1 */ 175 __IOM uint32_t ARB_EP7_SR; /*!< 0x00000388 Endpoint Interrupt Enable Register *1 */ 176 __IM uint32_t RESERVED29; 177 __IOM uint32_t ARB_RW7_WA; /*!< 0x00000390 Endpoint Write Address value *1, *2 */ 178 __IOM uint32_t ARB_RW7_WA_MSB; /*!< 0x00000394 Endpoint Write Address value *1, *2 */ 179 __IOM uint32_t ARB_RW7_RA; /*!< 0x00000398 Endpoint Read Address value *1, *2 */ 180 __IOM uint32_t ARB_RW7_RA_MSB; /*!< 0x0000039C Endpoint Read Address value *1, *2 */ 181 __IOM uint32_t ARB_RW7_DR; /*!< 0x000003A0 Endpoint Data Register */ 182 __IM uint32_t RESERVED30[7]; 183 __IOM uint32_t ARB_EP8_CFG; /*!< 0x000003C0 Endpoint Configuration Register *1 */ 184 __IOM uint32_t ARB_EP8_INT_EN; /*!< 0x000003C4 Endpoint Interrupt Enable Register *1 */ 185 __IOM uint32_t ARB_EP8_SR; /*!< 0x000003C8 Endpoint Interrupt Enable Register *1 */ 186 __IM uint32_t RESERVED31; 187 __IOM uint32_t ARB_RW8_WA; /*!< 0x000003D0 Endpoint Write Address value *1, *2 */ 188 __IOM uint32_t ARB_RW8_WA_MSB; /*!< 0x000003D4 Endpoint Write Address value *1, *2 */ 189 __IOM uint32_t ARB_RW8_RA; /*!< 0x000003D8 Endpoint Read Address value *1, *2 */ 190 __IOM uint32_t ARB_RW8_RA_MSB; /*!< 0x000003DC Endpoint Read Address value *1, *2 */ 191 __IOM uint32_t ARB_RW8_DR; /*!< 0x000003E0 Endpoint Data Register */ 192 __IM uint32_t RESERVED32[7]; 193 __IOM uint32_t MEM_DATA[512]; /*!< 0x00000400 DATA */ 194 __IM uint32_t RESERVED33[280]; 195 __IM uint32_t SOF16; /*!< 0x00001060 Start Of Frame Register */ 196 __IM uint32_t RESERVED34[7]; 197 __IM uint32_t OSCLK_DR16; /*!< 0x00001080 Oscillator lock data register */ 198 __IM uint32_t RESERVED35[99]; 199 __IOM uint32_t ARB_RW1_WA16; /*!< 0x00001210 Endpoint Write Address value *3 */ 200 __IM uint32_t RESERVED36; 201 __IOM uint32_t ARB_RW1_RA16; /*!< 0x00001218 Endpoint Read Address value *3 */ 202 __IM uint32_t RESERVED37; 203 __IOM uint32_t ARB_RW1_DR16; /*!< 0x00001220 Endpoint Data Register */ 204 __IM uint32_t RESERVED38[11]; 205 __IOM uint32_t ARB_RW2_WA16; /*!< 0x00001250 Endpoint Write Address value *3 */ 206 __IM uint32_t RESERVED39; 207 __IOM uint32_t ARB_RW2_RA16; /*!< 0x00001258 Endpoint Read Address value *3 */ 208 __IM uint32_t RESERVED40; 209 __IOM uint32_t ARB_RW2_DR16; /*!< 0x00001260 Endpoint Data Register */ 210 __IM uint32_t RESERVED41[11]; 211 __IOM uint32_t ARB_RW3_WA16; /*!< 0x00001290 Endpoint Write Address value *3 */ 212 __IM uint32_t RESERVED42; 213 __IOM uint32_t ARB_RW3_RA16; /*!< 0x00001298 Endpoint Read Address value *3 */ 214 __IM uint32_t RESERVED43; 215 __IOM uint32_t ARB_RW3_DR16; /*!< 0x000012A0 Endpoint Data Register */ 216 __IM uint32_t RESERVED44[3]; 217 __IOM uint32_t CWA16; /*!< 0x000012B0 Common Area Write Address */ 218 __IM uint32_t RESERVED45[7]; 219 __IOM uint32_t ARB_RW4_WA16; /*!< 0x000012D0 Endpoint Write Address value *3 */ 220 __IM uint32_t RESERVED46; 221 __IOM uint32_t ARB_RW4_RA16; /*!< 0x000012D8 Endpoint Read Address value *3 */ 222 __IM uint32_t RESERVED47; 223 __IOM uint32_t ARB_RW4_DR16; /*!< 0x000012E0 Endpoint Data Register */ 224 __IM uint32_t RESERVED48[3]; 225 __IOM uint32_t DMA_THRES16; /*!< 0x000012F0 DMA Burst / Threshold Configuration */ 226 __IM uint32_t RESERVED49[7]; 227 __IOM uint32_t ARB_RW5_WA16; /*!< 0x00001310 Endpoint Write Address value *3 */ 228 __IM uint32_t RESERVED50; 229 __IOM uint32_t ARB_RW5_RA16; /*!< 0x00001318 Endpoint Read Address value *3 */ 230 __IM uint32_t RESERVED51; 231 __IOM uint32_t ARB_RW5_DR16; /*!< 0x00001320 Endpoint Data Register */ 232 __IM uint32_t RESERVED52[11]; 233 __IOM uint32_t ARB_RW6_WA16; /*!< 0x00001350 Endpoint Write Address value *3 */ 234 __IM uint32_t RESERVED53; 235 __IOM uint32_t ARB_RW6_RA16; /*!< 0x00001358 Endpoint Read Address value *3 */ 236 __IM uint32_t RESERVED54; 237 __IOM uint32_t ARB_RW6_DR16; /*!< 0x00001360 Endpoint Data Register */ 238 __IM uint32_t RESERVED55[11]; 239 __IOM uint32_t ARB_RW7_WA16; /*!< 0x00001390 Endpoint Write Address value *3 */ 240 __IM uint32_t RESERVED56; 241 __IOM uint32_t ARB_RW7_RA16; /*!< 0x00001398 Endpoint Read Address value *3 */ 242 __IM uint32_t RESERVED57; 243 __IOM uint32_t ARB_RW7_DR16; /*!< 0x000013A0 Endpoint Data Register */ 244 __IM uint32_t RESERVED58[11]; 245 __IOM uint32_t ARB_RW8_WA16; /*!< 0x000013D0 Endpoint Write Address value *3 */ 246 __IM uint32_t RESERVED59; 247 __IOM uint32_t ARB_RW8_RA16; /*!< 0x000013D8 Endpoint Read Address value *3 */ 248 __IM uint32_t RESERVED60; 249 __IOM uint32_t ARB_RW8_DR16; /*!< 0x000013E0 Endpoint Data Register */ 250 __IM uint32_t RESERVED61[775]; 251 } USBFS_USBDEV_V1_Type; /*!< Size = 8192 (0x2000) */ 252 253 /** 254 * \brief USB Device LPM and PHY Test (USBFS_USBLPM) 255 */ 256 typedef struct { 257 __IOM uint32_t POWER_CTL; /*!< 0x00000000 Power Control Register */ 258 __IM uint32_t RESERVED; 259 __IOM uint32_t USBIO_CTL; /*!< 0x00000008 USB IO Control Register */ 260 __IOM uint32_t FLOW_CTL; /*!< 0x0000000C Flow Control Register */ 261 __IOM uint32_t LPM_CTL; /*!< 0x00000010 LPM Control Register */ 262 __IM uint32_t LPM_STAT; /*!< 0x00000014 LPM Status register */ 263 __IM uint32_t RESERVED1[2]; 264 __IOM uint32_t INTR_SIE; /*!< 0x00000020 USB SOF, BUS RESET and EP0 Interrupt Status */ 265 __IOM uint32_t INTR_SIE_SET; /*!< 0x00000024 USB SOF, BUS RESET and EP0 Interrupt Set */ 266 __IOM uint32_t INTR_SIE_MASK; /*!< 0x00000028 USB SOF, BUS RESET and EP0 Interrupt Mask */ 267 __IM uint32_t INTR_SIE_MASKED; /*!< 0x0000002C USB SOF, BUS RESET and EP0 Interrupt Masked */ 268 __IOM uint32_t INTR_LVL_SEL; /*!< 0x00000030 Select interrupt level for each interrupt source */ 269 __IM uint32_t INTR_CAUSE_HI; /*!< 0x00000034 High priority interrupt Cause register */ 270 __IM uint32_t INTR_CAUSE_MED; /*!< 0x00000038 Medium priority interrupt Cause register */ 271 __IM uint32_t INTR_CAUSE_LO; /*!< 0x0000003C Low priority interrupt Cause register */ 272 __IM uint32_t RESERVED2[12]; 273 __IOM uint32_t DFT_CTL; /*!< 0x00000070 DFT control */ 274 __IM uint32_t RESERVED3[995]; 275 } USBFS_USBLPM_V1_Type; /*!< Size = 4096 (0x1000) */ 276 277 /** 278 * \brief USB Host Controller (USBFS_USBHOST) 279 */ 280 typedef struct { 281 __IOM uint32_t HOST_CTL0; /*!< 0x00000000 Host Control 0 Register. */ 282 __IM uint32_t RESERVED[3]; 283 __IOM uint32_t HOST_CTL1; /*!< 0x00000010 Host Control 1 Register. */ 284 __IM uint32_t RESERVED1[59]; 285 __IOM uint32_t HOST_CTL2; /*!< 0x00000100 Host Control 2 Register. */ 286 __IOM uint32_t HOST_ERR; /*!< 0x00000104 Host Error Status Register. */ 287 __IOM uint32_t HOST_STATUS; /*!< 0x00000108 Host Status Register. */ 288 __IOM uint32_t HOST_FCOMP; /*!< 0x0000010C Host SOF Interrupt Frame Compare Register */ 289 __IOM uint32_t HOST_RTIMER; /*!< 0x00000110 Host Retry Timer Setup Register */ 290 __IOM uint32_t HOST_ADDR; /*!< 0x00000114 Host Address Register */ 291 __IOM uint32_t HOST_EOF; /*!< 0x00000118 Host EOF Setup Register */ 292 __IOM uint32_t HOST_FRAME; /*!< 0x0000011C Host Frame Setup Register */ 293 __IOM uint32_t HOST_TOKEN; /*!< 0x00000120 Host Token Endpoint Register */ 294 __IM uint32_t RESERVED2[183]; 295 __IOM uint32_t HOST_EP1_CTL; /*!< 0x00000400 Host Endpoint 1 Control Register */ 296 __IM uint32_t HOST_EP1_STATUS; /*!< 0x00000404 Host Endpoint 1 Status Register */ 297 __IOM uint32_t HOST_EP1_RW1_DR; /*!< 0x00000408 Host Endpoint 1 Data 1-Byte Register */ 298 __IOM uint32_t HOST_EP1_RW2_DR; /*!< 0x0000040C Host Endpoint 1 Data 2-Byte Register */ 299 __IM uint32_t RESERVED3[60]; 300 __IOM uint32_t HOST_EP2_CTL; /*!< 0x00000500 Host Endpoint 2 Control Register */ 301 __IM uint32_t HOST_EP2_STATUS; /*!< 0x00000504 Host Endpoint 2 Status Register */ 302 __IOM uint32_t HOST_EP2_RW1_DR; /*!< 0x00000508 Host Endpoint 2 Data 1-Byte Register */ 303 __IOM uint32_t HOST_EP2_RW2_DR; /*!< 0x0000050C Host Endpoint 2 Data 2-Byte Register */ 304 __IM uint32_t RESERVED4[188]; 305 __IOM uint32_t HOST_LVL1_SEL; /*!< 0x00000800 Host Interrupt Level 1 Selection Register */ 306 __IOM uint32_t HOST_LVL2_SEL; /*!< 0x00000804 Host Interrupt Level 2 Selection Register */ 307 __IM uint32_t RESERVED5[62]; 308 __IM uint32_t INTR_USBHOST_CAUSE_HI; /*!< 0x00000900 Interrupt USB Host Cause High Register */ 309 __IM uint32_t INTR_USBHOST_CAUSE_MED; /*!< 0x00000904 Interrupt USB Host Cause Medium Register */ 310 __IM uint32_t INTR_USBHOST_CAUSE_LO; /*!< 0x00000908 Interrupt USB Host Cause Low Register */ 311 __IM uint32_t RESERVED6[5]; 312 __IM uint32_t INTR_HOST_EP_CAUSE_HI; /*!< 0x00000920 Interrupt USB Host Endpoint Cause High Register */ 313 __IM uint32_t INTR_HOST_EP_CAUSE_MED; /*!< 0x00000924 Interrupt USB Host Endpoint Cause Medium Register */ 314 __IM uint32_t INTR_HOST_EP_CAUSE_LO; /*!< 0x00000928 Interrupt USB Host Endpoint Cause Low Register */ 315 __IM uint32_t RESERVED7[5]; 316 __IOM uint32_t INTR_USBHOST; /*!< 0x00000940 Interrupt USB Host Register */ 317 __IOM uint32_t INTR_USBHOST_SET; /*!< 0x00000944 Interrupt USB Host Set Register */ 318 __IOM uint32_t INTR_USBHOST_MASK; /*!< 0x00000948 Interrupt USB Host Mask Register */ 319 __IM uint32_t INTR_USBHOST_MASKED; /*!< 0x0000094C Interrupt USB Host Masked Register */ 320 __IM uint32_t RESERVED8[44]; 321 __IOM uint32_t INTR_HOST_EP; /*!< 0x00000A00 Interrupt USB Host Endpoint Register */ 322 __IOM uint32_t INTR_HOST_EP_SET; /*!< 0x00000A04 Interrupt USB Host Endpoint Set Register */ 323 __IOM uint32_t INTR_HOST_EP_MASK; /*!< 0x00000A08 Interrupt USB Host Endpoint Mask Register */ 324 __IM uint32_t INTR_HOST_EP_MASKED; /*!< 0x00000A0C Interrupt USB Host Endpoint Masked Register */ 325 __IM uint32_t RESERVED9[60]; 326 __IOM uint32_t HOST_DMA_ENBL; /*!< 0x00000B00 Host DMA Enable Register */ 327 __IM uint32_t RESERVED10[7]; 328 __IOM uint32_t HOST_EP1_BLK; /*!< 0x00000B20 Host Endpoint 1 Block Register */ 329 __IM uint32_t RESERVED11[3]; 330 __IOM uint32_t HOST_EP2_BLK; /*!< 0x00000B30 Host Endpoint 2 Block Register */ 331 __IM uint32_t RESERVED12[1331]; 332 } USBFS_USBHOST_V1_Type; /*!< Size = 8192 (0x2000) */ 333 334 /** 335 * \brief USB Host and Device Controller (USBFS) 336 */ 337 typedef struct { 338 USBFS_USBDEV_V1_Type USBDEV; /*!< 0x00000000 USB Device */ 339 USBFS_USBLPM_V1_Type USBLPM; /*!< 0x00002000 USB Device LPM and PHY Test */ 340 __IM uint32_t RESERVED[1024]; 341 USBFS_USBHOST_V1_Type USBHOST; /*!< 0x00004000 USB Host Controller */ 342 } USBFS_V1_Type; /*!< Size = 24576 (0x6000) */ 343 344 345 /* USBFS_USBDEV.EP0_DR */ 346 #define USBFS_USBDEV_EP0_DR_DATA_BYTE_Pos 0UL 347 #define USBFS_USBDEV_EP0_DR_DATA_BYTE_Msk 0xFFUL 348 /* USBFS_USBDEV.CR0 */ 349 #define USBFS_USBDEV_CR0_DEVICE_ADDRESS_Pos 0UL 350 #define USBFS_USBDEV_CR0_DEVICE_ADDRESS_Msk 0x7FUL 351 #define USBFS_USBDEV_CR0_USB_ENABLE_Pos 7UL 352 #define USBFS_USBDEV_CR0_USB_ENABLE_Msk 0x80UL 353 /* USBFS_USBDEV.CR1 */ 354 #define USBFS_USBDEV_CR1_REG_ENABLE_Pos 0UL 355 #define USBFS_USBDEV_CR1_REG_ENABLE_Msk 0x1UL 356 #define USBFS_USBDEV_CR1_ENABLE_LOCK_Pos 1UL 357 #define USBFS_USBDEV_CR1_ENABLE_LOCK_Msk 0x2UL 358 #define USBFS_USBDEV_CR1_BUS_ACTIVITY_Pos 2UL 359 #define USBFS_USBDEV_CR1_BUS_ACTIVITY_Msk 0x4UL 360 #define USBFS_USBDEV_CR1_RESERVED_3_Pos 3UL 361 #define USBFS_USBDEV_CR1_RESERVED_3_Msk 0x8UL 362 /* USBFS_USBDEV.SIE_EP_INT_EN */ 363 #define USBFS_USBDEV_SIE_EP_INT_EN_EP1_INTR_EN_Pos 0UL 364 #define USBFS_USBDEV_SIE_EP_INT_EN_EP1_INTR_EN_Msk 0x1UL 365 #define USBFS_USBDEV_SIE_EP_INT_EN_EP2_INTR_EN_Pos 1UL 366 #define USBFS_USBDEV_SIE_EP_INT_EN_EP2_INTR_EN_Msk 0x2UL 367 #define USBFS_USBDEV_SIE_EP_INT_EN_EP3_INTR_EN_Pos 2UL 368 #define USBFS_USBDEV_SIE_EP_INT_EN_EP3_INTR_EN_Msk 0x4UL 369 #define USBFS_USBDEV_SIE_EP_INT_EN_EP4_INTR_EN_Pos 3UL 370 #define USBFS_USBDEV_SIE_EP_INT_EN_EP4_INTR_EN_Msk 0x8UL 371 #define USBFS_USBDEV_SIE_EP_INT_EN_EP5_INTR_EN_Pos 4UL 372 #define USBFS_USBDEV_SIE_EP_INT_EN_EP5_INTR_EN_Msk 0x10UL 373 #define USBFS_USBDEV_SIE_EP_INT_EN_EP6_INTR_EN_Pos 5UL 374 #define USBFS_USBDEV_SIE_EP_INT_EN_EP6_INTR_EN_Msk 0x20UL 375 #define USBFS_USBDEV_SIE_EP_INT_EN_EP7_INTR_EN_Pos 6UL 376 #define USBFS_USBDEV_SIE_EP_INT_EN_EP7_INTR_EN_Msk 0x40UL 377 #define USBFS_USBDEV_SIE_EP_INT_EN_EP8_INTR_EN_Pos 7UL 378 #define USBFS_USBDEV_SIE_EP_INT_EN_EP8_INTR_EN_Msk 0x80UL 379 /* USBFS_USBDEV.SIE_EP_INT_SR */ 380 #define USBFS_USBDEV_SIE_EP_INT_SR_EP1_INTR_Pos 0UL 381 #define USBFS_USBDEV_SIE_EP_INT_SR_EP1_INTR_Msk 0x1UL 382 #define USBFS_USBDEV_SIE_EP_INT_SR_EP2_INTR_Pos 1UL 383 #define USBFS_USBDEV_SIE_EP_INT_SR_EP2_INTR_Msk 0x2UL 384 #define USBFS_USBDEV_SIE_EP_INT_SR_EP3_INTR_Pos 2UL 385 #define USBFS_USBDEV_SIE_EP_INT_SR_EP3_INTR_Msk 0x4UL 386 #define USBFS_USBDEV_SIE_EP_INT_SR_EP4_INTR_Pos 3UL 387 #define USBFS_USBDEV_SIE_EP_INT_SR_EP4_INTR_Msk 0x8UL 388 #define USBFS_USBDEV_SIE_EP_INT_SR_EP5_INTR_Pos 4UL 389 #define USBFS_USBDEV_SIE_EP_INT_SR_EP5_INTR_Msk 0x10UL 390 #define USBFS_USBDEV_SIE_EP_INT_SR_EP6_INTR_Pos 5UL 391 #define USBFS_USBDEV_SIE_EP_INT_SR_EP6_INTR_Msk 0x20UL 392 #define USBFS_USBDEV_SIE_EP_INT_SR_EP7_INTR_Pos 6UL 393 #define USBFS_USBDEV_SIE_EP_INT_SR_EP7_INTR_Msk 0x40UL 394 #define USBFS_USBDEV_SIE_EP_INT_SR_EP8_INTR_Pos 7UL 395 #define USBFS_USBDEV_SIE_EP_INT_SR_EP8_INTR_Msk 0x80UL 396 /* USBFS_USBDEV.SIE_EP1_CNT0 */ 397 #define USBFS_USBDEV_SIE_EP1_CNT0_DATA_COUNT_MSB_Pos 0UL 398 #define USBFS_USBDEV_SIE_EP1_CNT0_DATA_COUNT_MSB_Msk 0x7UL 399 #define USBFS_USBDEV_SIE_EP1_CNT0_DATA_VALID_Pos 6UL 400 #define USBFS_USBDEV_SIE_EP1_CNT0_DATA_VALID_Msk 0x40UL 401 #define USBFS_USBDEV_SIE_EP1_CNT0_DATA_TOGGLE_Pos 7UL 402 #define USBFS_USBDEV_SIE_EP1_CNT0_DATA_TOGGLE_Msk 0x80UL 403 /* USBFS_USBDEV.SIE_EP1_CNT1 */ 404 #define USBFS_USBDEV_SIE_EP1_CNT1_DATA_COUNT_Pos 0UL 405 #define USBFS_USBDEV_SIE_EP1_CNT1_DATA_COUNT_Msk 0xFFUL 406 /* USBFS_USBDEV.SIE_EP1_CR0 */ 407 #define USBFS_USBDEV_SIE_EP1_CR0_MODE_Pos 0UL 408 #define USBFS_USBDEV_SIE_EP1_CR0_MODE_Msk 0xFUL 409 #define USBFS_USBDEV_SIE_EP1_CR0_ACKED_TXN_Pos 4UL 410 #define USBFS_USBDEV_SIE_EP1_CR0_ACKED_TXN_Msk 0x10UL 411 #define USBFS_USBDEV_SIE_EP1_CR0_NAK_INT_EN_Pos 5UL 412 #define USBFS_USBDEV_SIE_EP1_CR0_NAK_INT_EN_Msk 0x20UL 413 #define USBFS_USBDEV_SIE_EP1_CR0_ERR_IN_TXN_Pos 6UL 414 #define USBFS_USBDEV_SIE_EP1_CR0_ERR_IN_TXN_Msk 0x40UL 415 #define USBFS_USBDEV_SIE_EP1_CR0_STALL_Pos 7UL 416 #define USBFS_USBDEV_SIE_EP1_CR0_STALL_Msk 0x80UL 417 /* USBFS_USBDEV.USBIO_CR0 */ 418 #define USBFS_USBDEV_USBIO_CR0_RD_Pos 0UL 419 #define USBFS_USBDEV_USBIO_CR0_RD_Msk 0x1UL 420 #define USBFS_USBDEV_USBIO_CR0_TD_Pos 5UL 421 #define USBFS_USBDEV_USBIO_CR0_TD_Msk 0x20UL 422 #define USBFS_USBDEV_USBIO_CR0_TSE0_Pos 6UL 423 #define USBFS_USBDEV_USBIO_CR0_TSE0_Msk 0x40UL 424 #define USBFS_USBDEV_USBIO_CR0_TEN_Pos 7UL 425 #define USBFS_USBDEV_USBIO_CR0_TEN_Msk 0x80UL 426 /* USBFS_USBDEV.USBIO_CR2 */ 427 #define USBFS_USBDEV_USBIO_CR2_RESERVED_5_0_Pos 0UL 428 #define USBFS_USBDEV_USBIO_CR2_RESERVED_5_0_Msk 0x3FUL 429 #define USBFS_USBDEV_USBIO_CR2_TEST_PKT_Pos 6UL 430 #define USBFS_USBDEV_USBIO_CR2_TEST_PKT_Msk 0x40UL 431 #define USBFS_USBDEV_USBIO_CR2_RESERVED_7_Pos 7UL 432 #define USBFS_USBDEV_USBIO_CR2_RESERVED_7_Msk 0x80UL 433 /* USBFS_USBDEV.USBIO_CR1 */ 434 #define USBFS_USBDEV_USBIO_CR1_DMO_Pos 0UL 435 #define USBFS_USBDEV_USBIO_CR1_DMO_Msk 0x1UL 436 #define USBFS_USBDEV_USBIO_CR1_DPO_Pos 1UL 437 #define USBFS_USBDEV_USBIO_CR1_DPO_Msk 0x2UL 438 #define USBFS_USBDEV_USBIO_CR1_RESERVED_2_Pos 2UL 439 #define USBFS_USBDEV_USBIO_CR1_RESERVED_2_Msk 0x4UL 440 #define USBFS_USBDEV_USBIO_CR1_IOMODE_Pos 5UL 441 #define USBFS_USBDEV_USBIO_CR1_IOMODE_Msk 0x20UL 442 /* USBFS_USBDEV.DYN_RECONFIG */ 443 #define USBFS_USBDEV_DYN_RECONFIG_DYN_CONFIG_EN_Pos 0UL 444 #define USBFS_USBDEV_DYN_RECONFIG_DYN_CONFIG_EN_Msk 0x1UL 445 #define USBFS_USBDEV_DYN_RECONFIG_DYN_RECONFIG_EPNO_Pos 1UL 446 #define USBFS_USBDEV_DYN_RECONFIG_DYN_RECONFIG_EPNO_Msk 0xEUL 447 #define USBFS_USBDEV_DYN_RECONFIG_DYN_RECONFIG_RDY_STS_Pos 4UL 448 #define USBFS_USBDEV_DYN_RECONFIG_DYN_RECONFIG_RDY_STS_Msk 0x10UL 449 /* USBFS_USBDEV.SOF0 */ 450 #define USBFS_USBDEV_SOF0_FRAME_NUMBER_Pos 0UL 451 #define USBFS_USBDEV_SOF0_FRAME_NUMBER_Msk 0xFFUL 452 /* USBFS_USBDEV.SOF1 */ 453 #define USBFS_USBDEV_SOF1_FRAME_NUMBER_MSB_Pos 0UL 454 #define USBFS_USBDEV_SOF1_FRAME_NUMBER_MSB_Msk 0x7UL 455 /* USBFS_USBDEV.SIE_EP2_CNT0 */ 456 #define USBFS_USBDEV_SIE_EP2_CNT0_DATA_COUNT_MSB_Pos 0UL 457 #define USBFS_USBDEV_SIE_EP2_CNT0_DATA_COUNT_MSB_Msk 0x7UL 458 #define USBFS_USBDEV_SIE_EP2_CNT0_DATA_VALID_Pos 6UL 459 #define USBFS_USBDEV_SIE_EP2_CNT0_DATA_VALID_Msk 0x40UL 460 #define USBFS_USBDEV_SIE_EP2_CNT0_DATA_TOGGLE_Pos 7UL 461 #define USBFS_USBDEV_SIE_EP2_CNT0_DATA_TOGGLE_Msk 0x80UL 462 /* USBFS_USBDEV.SIE_EP2_CNT1 */ 463 #define USBFS_USBDEV_SIE_EP2_CNT1_DATA_COUNT_Pos 0UL 464 #define USBFS_USBDEV_SIE_EP2_CNT1_DATA_COUNT_Msk 0xFFUL 465 /* USBFS_USBDEV.SIE_EP2_CR0 */ 466 #define USBFS_USBDEV_SIE_EP2_CR0_MODE_Pos 0UL 467 #define USBFS_USBDEV_SIE_EP2_CR0_MODE_Msk 0xFUL 468 #define USBFS_USBDEV_SIE_EP2_CR0_ACKED_TXN_Pos 4UL 469 #define USBFS_USBDEV_SIE_EP2_CR0_ACKED_TXN_Msk 0x10UL 470 #define USBFS_USBDEV_SIE_EP2_CR0_NAK_INT_EN_Pos 5UL 471 #define USBFS_USBDEV_SIE_EP2_CR0_NAK_INT_EN_Msk 0x20UL 472 #define USBFS_USBDEV_SIE_EP2_CR0_ERR_IN_TXN_Pos 6UL 473 #define USBFS_USBDEV_SIE_EP2_CR0_ERR_IN_TXN_Msk 0x40UL 474 #define USBFS_USBDEV_SIE_EP2_CR0_STALL_Pos 7UL 475 #define USBFS_USBDEV_SIE_EP2_CR0_STALL_Msk 0x80UL 476 /* USBFS_USBDEV.OSCLK_DR0 */ 477 #define USBFS_USBDEV_OSCLK_DR0_ADDER_Pos 0UL 478 #define USBFS_USBDEV_OSCLK_DR0_ADDER_Msk 0xFFUL 479 /* USBFS_USBDEV.OSCLK_DR1 */ 480 #define USBFS_USBDEV_OSCLK_DR1_ADDER_MSB_Pos 0UL 481 #define USBFS_USBDEV_OSCLK_DR1_ADDER_MSB_Msk 0x7FUL 482 /* USBFS_USBDEV.EP0_CR */ 483 #define USBFS_USBDEV_EP0_CR_MODE_Pos 0UL 484 #define USBFS_USBDEV_EP0_CR_MODE_Msk 0xFUL 485 #define USBFS_USBDEV_EP0_CR_ACKED_TXN_Pos 4UL 486 #define USBFS_USBDEV_EP0_CR_ACKED_TXN_Msk 0x10UL 487 #define USBFS_USBDEV_EP0_CR_OUT_RCVD_Pos 5UL 488 #define USBFS_USBDEV_EP0_CR_OUT_RCVD_Msk 0x20UL 489 #define USBFS_USBDEV_EP0_CR_IN_RCVD_Pos 6UL 490 #define USBFS_USBDEV_EP0_CR_IN_RCVD_Msk 0x40UL 491 #define USBFS_USBDEV_EP0_CR_SETUP_RCVD_Pos 7UL 492 #define USBFS_USBDEV_EP0_CR_SETUP_RCVD_Msk 0x80UL 493 /* USBFS_USBDEV.EP0_CNT */ 494 #define USBFS_USBDEV_EP0_CNT_BYTE_COUNT_Pos 0UL 495 #define USBFS_USBDEV_EP0_CNT_BYTE_COUNT_Msk 0xFUL 496 #define USBFS_USBDEV_EP0_CNT_DATA_VALID_Pos 6UL 497 #define USBFS_USBDEV_EP0_CNT_DATA_VALID_Msk 0x40UL 498 #define USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Pos 7UL 499 #define USBFS_USBDEV_EP0_CNT_DATA_TOGGLE_Msk 0x80UL 500 /* USBFS_USBDEV.SIE_EP3_CNT0 */ 501 #define USBFS_USBDEV_SIE_EP3_CNT0_DATA_COUNT_MSB_Pos 0UL 502 #define USBFS_USBDEV_SIE_EP3_CNT0_DATA_COUNT_MSB_Msk 0x7UL 503 #define USBFS_USBDEV_SIE_EP3_CNT0_DATA_VALID_Pos 6UL 504 #define USBFS_USBDEV_SIE_EP3_CNT0_DATA_VALID_Msk 0x40UL 505 #define USBFS_USBDEV_SIE_EP3_CNT0_DATA_TOGGLE_Pos 7UL 506 #define USBFS_USBDEV_SIE_EP3_CNT0_DATA_TOGGLE_Msk 0x80UL 507 /* USBFS_USBDEV.SIE_EP3_CNT1 */ 508 #define USBFS_USBDEV_SIE_EP3_CNT1_DATA_COUNT_Pos 0UL 509 #define USBFS_USBDEV_SIE_EP3_CNT1_DATA_COUNT_Msk 0xFFUL 510 /* USBFS_USBDEV.SIE_EP3_CR0 */ 511 #define USBFS_USBDEV_SIE_EP3_CR0_MODE_Pos 0UL 512 #define USBFS_USBDEV_SIE_EP3_CR0_MODE_Msk 0xFUL 513 #define USBFS_USBDEV_SIE_EP3_CR0_ACKED_TXN_Pos 4UL 514 #define USBFS_USBDEV_SIE_EP3_CR0_ACKED_TXN_Msk 0x10UL 515 #define USBFS_USBDEV_SIE_EP3_CR0_NAK_INT_EN_Pos 5UL 516 #define USBFS_USBDEV_SIE_EP3_CR0_NAK_INT_EN_Msk 0x20UL 517 #define USBFS_USBDEV_SIE_EP3_CR0_ERR_IN_TXN_Pos 6UL 518 #define USBFS_USBDEV_SIE_EP3_CR0_ERR_IN_TXN_Msk 0x40UL 519 #define USBFS_USBDEV_SIE_EP3_CR0_STALL_Pos 7UL 520 #define USBFS_USBDEV_SIE_EP3_CR0_STALL_Msk 0x80UL 521 /* USBFS_USBDEV.SIE_EP4_CNT0 */ 522 #define USBFS_USBDEV_SIE_EP4_CNT0_DATA_COUNT_MSB_Pos 0UL 523 #define USBFS_USBDEV_SIE_EP4_CNT0_DATA_COUNT_MSB_Msk 0x7UL 524 #define USBFS_USBDEV_SIE_EP4_CNT0_DATA_VALID_Pos 6UL 525 #define USBFS_USBDEV_SIE_EP4_CNT0_DATA_VALID_Msk 0x40UL 526 #define USBFS_USBDEV_SIE_EP4_CNT0_DATA_TOGGLE_Pos 7UL 527 #define USBFS_USBDEV_SIE_EP4_CNT0_DATA_TOGGLE_Msk 0x80UL 528 /* USBFS_USBDEV.SIE_EP4_CNT1 */ 529 #define USBFS_USBDEV_SIE_EP4_CNT1_DATA_COUNT_Pos 0UL 530 #define USBFS_USBDEV_SIE_EP4_CNT1_DATA_COUNT_Msk 0xFFUL 531 /* USBFS_USBDEV.SIE_EP4_CR0 */ 532 #define USBFS_USBDEV_SIE_EP4_CR0_MODE_Pos 0UL 533 #define USBFS_USBDEV_SIE_EP4_CR0_MODE_Msk 0xFUL 534 #define USBFS_USBDEV_SIE_EP4_CR0_ACKED_TXN_Pos 4UL 535 #define USBFS_USBDEV_SIE_EP4_CR0_ACKED_TXN_Msk 0x10UL 536 #define USBFS_USBDEV_SIE_EP4_CR0_NAK_INT_EN_Pos 5UL 537 #define USBFS_USBDEV_SIE_EP4_CR0_NAK_INT_EN_Msk 0x20UL 538 #define USBFS_USBDEV_SIE_EP4_CR0_ERR_IN_TXN_Pos 6UL 539 #define USBFS_USBDEV_SIE_EP4_CR0_ERR_IN_TXN_Msk 0x40UL 540 #define USBFS_USBDEV_SIE_EP4_CR0_STALL_Pos 7UL 541 #define USBFS_USBDEV_SIE_EP4_CR0_STALL_Msk 0x80UL 542 /* USBFS_USBDEV.SIE_EP5_CNT0 */ 543 #define USBFS_USBDEV_SIE_EP5_CNT0_DATA_COUNT_MSB_Pos 0UL 544 #define USBFS_USBDEV_SIE_EP5_CNT0_DATA_COUNT_MSB_Msk 0x7UL 545 #define USBFS_USBDEV_SIE_EP5_CNT0_DATA_VALID_Pos 6UL 546 #define USBFS_USBDEV_SIE_EP5_CNT0_DATA_VALID_Msk 0x40UL 547 #define USBFS_USBDEV_SIE_EP5_CNT0_DATA_TOGGLE_Pos 7UL 548 #define USBFS_USBDEV_SIE_EP5_CNT0_DATA_TOGGLE_Msk 0x80UL 549 /* USBFS_USBDEV.SIE_EP5_CNT1 */ 550 #define USBFS_USBDEV_SIE_EP5_CNT1_DATA_COUNT_Pos 0UL 551 #define USBFS_USBDEV_SIE_EP5_CNT1_DATA_COUNT_Msk 0xFFUL 552 /* USBFS_USBDEV.SIE_EP5_CR0 */ 553 #define USBFS_USBDEV_SIE_EP5_CR0_MODE_Pos 0UL 554 #define USBFS_USBDEV_SIE_EP5_CR0_MODE_Msk 0xFUL 555 #define USBFS_USBDEV_SIE_EP5_CR0_ACKED_TXN_Pos 4UL 556 #define USBFS_USBDEV_SIE_EP5_CR0_ACKED_TXN_Msk 0x10UL 557 #define USBFS_USBDEV_SIE_EP5_CR0_NAK_INT_EN_Pos 5UL 558 #define USBFS_USBDEV_SIE_EP5_CR0_NAK_INT_EN_Msk 0x20UL 559 #define USBFS_USBDEV_SIE_EP5_CR0_ERR_IN_TXN_Pos 6UL 560 #define USBFS_USBDEV_SIE_EP5_CR0_ERR_IN_TXN_Msk 0x40UL 561 #define USBFS_USBDEV_SIE_EP5_CR0_STALL_Pos 7UL 562 #define USBFS_USBDEV_SIE_EP5_CR0_STALL_Msk 0x80UL 563 /* USBFS_USBDEV.SIE_EP6_CNT0 */ 564 #define USBFS_USBDEV_SIE_EP6_CNT0_DATA_COUNT_MSB_Pos 0UL 565 #define USBFS_USBDEV_SIE_EP6_CNT0_DATA_COUNT_MSB_Msk 0x7UL 566 #define USBFS_USBDEV_SIE_EP6_CNT0_DATA_VALID_Pos 6UL 567 #define USBFS_USBDEV_SIE_EP6_CNT0_DATA_VALID_Msk 0x40UL 568 #define USBFS_USBDEV_SIE_EP6_CNT0_DATA_TOGGLE_Pos 7UL 569 #define USBFS_USBDEV_SIE_EP6_CNT0_DATA_TOGGLE_Msk 0x80UL 570 /* USBFS_USBDEV.SIE_EP6_CNT1 */ 571 #define USBFS_USBDEV_SIE_EP6_CNT1_DATA_COUNT_Pos 0UL 572 #define USBFS_USBDEV_SIE_EP6_CNT1_DATA_COUNT_Msk 0xFFUL 573 /* USBFS_USBDEV.SIE_EP6_CR0 */ 574 #define USBFS_USBDEV_SIE_EP6_CR0_MODE_Pos 0UL 575 #define USBFS_USBDEV_SIE_EP6_CR0_MODE_Msk 0xFUL 576 #define USBFS_USBDEV_SIE_EP6_CR0_ACKED_TXN_Pos 4UL 577 #define USBFS_USBDEV_SIE_EP6_CR0_ACKED_TXN_Msk 0x10UL 578 #define USBFS_USBDEV_SIE_EP6_CR0_NAK_INT_EN_Pos 5UL 579 #define USBFS_USBDEV_SIE_EP6_CR0_NAK_INT_EN_Msk 0x20UL 580 #define USBFS_USBDEV_SIE_EP6_CR0_ERR_IN_TXN_Pos 6UL 581 #define USBFS_USBDEV_SIE_EP6_CR0_ERR_IN_TXN_Msk 0x40UL 582 #define USBFS_USBDEV_SIE_EP6_CR0_STALL_Pos 7UL 583 #define USBFS_USBDEV_SIE_EP6_CR0_STALL_Msk 0x80UL 584 /* USBFS_USBDEV.SIE_EP7_CNT0 */ 585 #define USBFS_USBDEV_SIE_EP7_CNT0_DATA_COUNT_MSB_Pos 0UL 586 #define USBFS_USBDEV_SIE_EP7_CNT0_DATA_COUNT_MSB_Msk 0x7UL 587 #define USBFS_USBDEV_SIE_EP7_CNT0_DATA_VALID_Pos 6UL 588 #define USBFS_USBDEV_SIE_EP7_CNT0_DATA_VALID_Msk 0x40UL 589 #define USBFS_USBDEV_SIE_EP7_CNT0_DATA_TOGGLE_Pos 7UL 590 #define USBFS_USBDEV_SIE_EP7_CNT0_DATA_TOGGLE_Msk 0x80UL 591 /* USBFS_USBDEV.SIE_EP7_CNT1 */ 592 #define USBFS_USBDEV_SIE_EP7_CNT1_DATA_COUNT_Pos 0UL 593 #define USBFS_USBDEV_SIE_EP7_CNT1_DATA_COUNT_Msk 0xFFUL 594 /* USBFS_USBDEV.SIE_EP7_CR0 */ 595 #define USBFS_USBDEV_SIE_EP7_CR0_MODE_Pos 0UL 596 #define USBFS_USBDEV_SIE_EP7_CR0_MODE_Msk 0xFUL 597 #define USBFS_USBDEV_SIE_EP7_CR0_ACKED_TXN_Pos 4UL 598 #define USBFS_USBDEV_SIE_EP7_CR0_ACKED_TXN_Msk 0x10UL 599 #define USBFS_USBDEV_SIE_EP7_CR0_NAK_INT_EN_Pos 5UL 600 #define USBFS_USBDEV_SIE_EP7_CR0_NAK_INT_EN_Msk 0x20UL 601 #define USBFS_USBDEV_SIE_EP7_CR0_ERR_IN_TXN_Pos 6UL 602 #define USBFS_USBDEV_SIE_EP7_CR0_ERR_IN_TXN_Msk 0x40UL 603 #define USBFS_USBDEV_SIE_EP7_CR0_STALL_Pos 7UL 604 #define USBFS_USBDEV_SIE_EP7_CR0_STALL_Msk 0x80UL 605 /* USBFS_USBDEV.SIE_EP8_CNT0 */ 606 #define USBFS_USBDEV_SIE_EP8_CNT0_DATA_COUNT_MSB_Pos 0UL 607 #define USBFS_USBDEV_SIE_EP8_CNT0_DATA_COUNT_MSB_Msk 0x7UL 608 #define USBFS_USBDEV_SIE_EP8_CNT0_DATA_VALID_Pos 6UL 609 #define USBFS_USBDEV_SIE_EP8_CNT0_DATA_VALID_Msk 0x40UL 610 #define USBFS_USBDEV_SIE_EP8_CNT0_DATA_TOGGLE_Pos 7UL 611 #define USBFS_USBDEV_SIE_EP8_CNT0_DATA_TOGGLE_Msk 0x80UL 612 /* USBFS_USBDEV.SIE_EP8_CNT1 */ 613 #define USBFS_USBDEV_SIE_EP8_CNT1_DATA_COUNT_Pos 0UL 614 #define USBFS_USBDEV_SIE_EP8_CNT1_DATA_COUNT_Msk 0xFFUL 615 /* USBFS_USBDEV.SIE_EP8_CR0 */ 616 #define USBFS_USBDEV_SIE_EP8_CR0_MODE_Pos 0UL 617 #define USBFS_USBDEV_SIE_EP8_CR0_MODE_Msk 0xFUL 618 #define USBFS_USBDEV_SIE_EP8_CR0_ACKED_TXN_Pos 4UL 619 #define USBFS_USBDEV_SIE_EP8_CR0_ACKED_TXN_Msk 0x10UL 620 #define USBFS_USBDEV_SIE_EP8_CR0_NAK_INT_EN_Pos 5UL 621 #define USBFS_USBDEV_SIE_EP8_CR0_NAK_INT_EN_Msk 0x20UL 622 #define USBFS_USBDEV_SIE_EP8_CR0_ERR_IN_TXN_Pos 6UL 623 #define USBFS_USBDEV_SIE_EP8_CR0_ERR_IN_TXN_Msk 0x40UL 624 #define USBFS_USBDEV_SIE_EP8_CR0_STALL_Pos 7UL 625 #define USBFS_USBDEV_SIE_EP8_CR0_STALL_Msk 0x80UL 626 /* USBFS_USBDEV.ARB_EP1_CFG */ 627 #define USBFS_USBDEV_ARB_EP1_CFG_IN_DATA_RDY_Pos 0UL 628 #define USBFS_USBDEV_ARB_EP1_CFG_IN_DATA_RDY_Msk 0x1UL 629 #define USBFS_USBDEV_ARB_EP1_CFG_DMA_REQ_Pos 1UL 630 #define USBFS_USBDEV_ARB_EP1_CFG_DMA_REQ_Msk 0x2UL 631 #define USBFS_USBDEV_ARB_EP1_CFG_CRC_BYPASS_Pos 2UL 632 #define USBFS_USBDEV_ARB_EP1_CFG_CRC_BYPASS_Msk 0x4UL 633 #define USBFS_USBDEV_ARB_EP1_CFG_RESET_PTR_Pos 3UL 634 #define USBFS_USBDEV_ARB_EP1_CFG_RESET_PTR_Msk 0x8UL 635 /* USBFS_USBDEV.ARB_EP1_INT_EN */ 636 #define USBFS_USBDEV_ARB_EP1_INT_EN_IN_BUF_FULL_EN_Pos 0UL 637 #define USBFS_USBDEV_ARB_EP1_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL 638 #define USBFS_USBDEV_ARB_EP1_INT_EN_DMA_GNT_EN_Pos 1UL 639 #define USBFS_USBDEV_ARB_EP1_INT_EN_DMA_GNT_EN_Msk 0x2UL 640 #define USBFS_USBDEV_ARB_EP1_INT_EN_BUF_OVER_EN_Pos 2UL 641 #define USBFS_USBDEV_ARB_EP1_INT_EN_BUF_OVER_EN_Msk 0x4UL 642 #define USBFS_USBDEV_ARB_EP1_INT_EN_BUF_UNDER_EN_Pos 3UL 643 #define USBFS_USBDEV_ARB_EP1_INT_EN_BUF_UNDER_EN_Msk 0x8UL 644 #define USBFS_USBDEV_ARB_EP1_INT_EN_ERR_INT_EN_Pos 4UL 645 #define USBFS_USBDEV_ARB_EP1_INT_EN_ERR_INT_EN_Msk 0x10UL 646 #define USBFS_USBDEV_ARB_EP1_INT_EN_DMA_TERMIN_EN_Pos 5UL 647 #define USBFS_USBDEV_ARB_EP1_INT_EN_DMA_TERMIN_EN_Msk 0x20UL 648 /* USBFS_USBDEV.ARB_EP1_SR */ 649 #define USBFS_USBDEV_ARB_EP1_SR_IN_BUF_FULL_Pos 0UL 650 #define USBFS_USBDEV_ARB_EP1_SR_IN_BUF_FULL_Msk 0x1UL 651 #define USBFS_USBDEV_ARB_EP1_SR_DMA_GNT_Pos 1UL 652 #define USBFS_USBDEV_ARB_EP1_SR_DMA_GNT_Msk 0x2UL 653 #define USBFS_USBDEV_ARB_EP1_SR_BUF_OVER_Pos 2UL 654 #define USBFS_USBDEV_ARB_EP1_SR_BUF_OVER_Msk 0x4UL 655 #define USBFS_USBDEV_ARB_EP1_SR_BUF_UNDER_Pos 3UL 656 #define USBFS_USBDEV_ARB_EP1_SR_BUF_UNDER_Msk 0x8UL 657 #define USBFS_USBDEV_ARB_EP1_SR_DMA_TERMIN_Pos 5UL 658 #define USBFS_USBDEV_ARB_EP1_SR_DMA_TERMIN_Msk 0x20UL 659 /* USBFS_USBDEV.ARB_RW1_WA */ 660 #define USBFS_USBDEV_ARB_RW1_WA_WA_Pos 0UL 661 #define USBFS_USBDEV_ARB_RW1_WA_WA_Msk 0xFFUL 662 /* USBFS_USBDEV.ARB_RW1_WA_MSB */ 663 #define USBFS_USBDEV_ARB_RW1_WA_MSB_WA_MSB_Pos 0UL 664 #define USBFS_USBDEV_ARB_RW1_WA_MSB_WA_MSB_Msk 0x1UL 665 /* USBFS_USBDEV.ARB_RW1_RA */ 666 #define USBFS_USBDEV_ARB_RW1_RA_RA_Pos 0UL 667 #define USBFS_USBDEV_ARB_RW1_RA_RA_Msk 0xFFUL 668 /* USBFS_USBDEV.ARB_RW1_RA_MSB */ 669 #define USBFS_USBDEV_ARB_RW1_RA_MSB_RA_MSB_Pos 0UL 670 #define USBFS_USBDEV_ARB_RW1_RA_MSB_RA_MSB_Msk 0x1UL 671 /* USBFS_USBDEV.ARB_RW1_DR */ 672 #define USBFS_USBDEV_ARB_RW1_DR_DR_Pos 0UL 673 #define USBFS_USBDEV_ARB_RW1_DR_DR_Msk 0xFFUL 674 /* USBFS_USBDEV.BUF_SIZE */ 675 #define USBFS_USBDEV_BUF_SIZE_IN_BUF_Pos 0UL 676 #define USBFS_USBDEV_BUF_SIZE_IN_BUF_Msk 0xFUL 677 #define USBFS_USBDEV_BUF_SIZE_OUT_BUF_Pos 4UL 678 #define USBFS_USBDEV_BUF_SIZE_OUT_BUF_Msk 0xF0UL 679 /* USBFS_USBDEV.EP_ACTIVE */ 680 #define USBFS_USBDEV_EP_ACTIVE_EP1_ACT_Pos 0UL 681 #define USBFS_USBDEV_EP_ACTIVE_EP1_ACT_Msk 0x1UL 682 #define USBFS_USBDEV_EP_ACTIVE_EP2_ACT_Pos 1UL 683 #define USBFS_USBDEV_EP_ACTIVE_EP2_ACT_Msk 0x2UL 684 #define USBFS_USBDEV_EP_ACTIVE_EP3_ACT_Pos 2UL 685 #define USBFS_USBDEV_EP_ACTIVE_EP3_ACT_Msk 0x4UL 686 #define USBFS_USBDEV_EP_ACTIVE_EP4_ACT_Pos 3UL 687 #define USBFS_USBDEV_EP_ACTIVE_EP4_ACT_Msk 0x8UL 688 #define USBFS_USBDEV_EP_ACTIVE_EP5_ACT_Pos 4UL 689 #define USBFS_USBDEV_EP_ACTIVE_EP5_ACT_Msk 0x10UL 690 #define USBFS_USBDEV_EP_ACTIVE_EP6_ACT_Pos 5UL 691 #define USBFS_USBDEV_EP_ACTIVE_EP6_ACT_Msk 0x20UL 692 #define USBFS_USBDEV_EP_ACTIVE_EP7_ACT_Pos 6UL 693 #define USBFS_USBDEV_EP_ACTIVE_EP7_ACT_Msk 0x40UL 694 #define USBFS_USBDEV_EP_ACTIVE_EP8_ACT_Pos 7UL 695 #define USBFS_USBDEV_EP_ACTIVE_EP8_ACT_Msk 0x80UL 696 /* USBFS_USBDEV.EP_TYPE */ 697 #define USBFS_USBDEV_EP_TYPE_EP1_TYP_Pos 0UL 698 #define USBFS_USBDEV_EP_TYPE_EP1_TYP_Msk 0x1UL 699 #define USBFS_USBDEV_EP_TYPE_EP2_TYP_Pos 1UL 700 #define USBFS_USBDEV_EP_TYPE_EP2_TYP_Msk 0x2UL 701 #define USBFS_USBDEV_EP_TYPE_EP3_TYP_Pos 2UL 702 #define USBFS_USBDEV_EP_TYPE_EP3_TYP_Msk 0x4UL 703 #define USBFS_USBDEV_EP_TYPE_EP4_TYP_Pos 3UL 704 #define USBFS_USBDEV_EP_TYPE_EP4_TYP_Msk 0x8UL 705 #define USBFS_USBDEV_EP_TYPE_EP5_TYP_Pos 4UL 706 #define USBFS_USBDEV_EP_TYPE_EP5_TYP_Msk 0x10UL 707 #define USBFS_USBDEV_EP_TYPE_EP6_TYP_Pos 5UL 708 #define USBFS_USBDEV_EP_TYPE_EP6_TYP_Msk 0x20UL 709 #define USBFS_USBDEV_EP_TYPE_EP7_TYP_Pos 6UL 710 #define USBFS_USBDEV_EP_TYPE_EP7_TYP_Msk 0x40UL 711 #define USBFS_USBDEV_EP_TYPE_EP8_TYP_Pos 7UL 712 #define USBFS_USBDEV_EP_TYPE_EP8_TYP_Msk 0x80UL 713 /* USBFS_USBDEV.ARB_EP2_CFG */ 714 #define USBFS_USBDEV_ARB_EP2_CFG_IN_DATA_RDY_Pos 0UL 715 #define USBFS_USBDEV_ARB_EP2_CFG_IN_DATA_RDY_Msk 0x1UL 716 #define USBFS_USBDEV_ARB_EP2_CFG_DMA_REQ_Pos 1UL 717 #define USBFS_USBDEV_ARB_EP2_CFG_DMA_REQ_Msk 0x2UL 718 #define USBFS_USBDEV_ARB_EP2_CFG_CRC_BYPASS_Pos 2UL 719 #define USBFS_USBDEV_ARB_EP2_CFG_CRC_BYPASS_Msk 0x4UL 720 #define USBFS_USBDEV_ARB_EP2_CFG_RESET_PTR_Pos 3UL 721 #define USBFS_USBDEV_ARB_EP2_CFG_RESET_PTR_Msk 0x8UL 722 /* USBFS_USBDEV.ARB_EP2_INT_EN */ 723 #define USBFS_USBDEV_ARB_EP2_INT_EN_IN_BUF_FULL_EN_Pos 0UL 724 #define USBFS_USBDEV_ARB_EP2_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL 725 #define USBFS_USBDEV_ARB_EP2_INT_EN_DMA_GNT_EN_Pos 1UL 726 #define USBFS_USBDEV_ARB_EP2_INT_EN_DMA_GNT_EN_Msk 0x2UL 727 #define USBFS_USBDEV_ARB_EP2_INT_EN_BUF_OVER_EN_Pos 2UL 728 #define USBFS_USBDEV_ARB_EP2_INT_EN_BUF_OVER_EN_Msk 0x4UL 729 #define USBFS_USBDEV_ARB_EP2_INT_EN_BUF_UNDER_EN_Pos 3UL 730 #define USBFS_USBDEV_ARB_EP2_INT_EN_BUF_UNDER_EN_Msk 0x8UL 731 #define USBFS_USBDEV_ARB_EP2_INT_EN_ERR_INT_EN_Pos 4UL 732 #define USBFS_USBDEV_ARB_EP2_INT_EN_ERR_INT_EN_Msk 0x10UL 733 #define USBFS_USBDEV_ARB_EP2_INT_EN_DMA_TERMIN_EN_Pos 5UL 734 #define USBFS_USBDEV_ARB_EP2_INT_EN_DMA_TERMIN_EN_Msk 0x20UL 735 /* USBFS_USBDEV.ARB_EP2_SR */ 736 #define USBFS_USBDEV_ARB_EP2_SR_IN_BUF_FULL_Pos 0UL 737 #define USBFS_USBDEV_ARB_EP2_SR_IN_BUF_FULL_Msk 0x1UL 738 #define USBFS_USBDEV_ARB_EP2_SR_DMA_GNT_Pos 1UL 739 #define USBFS_USBDEV_ARB_EP2_SR_DMA_GNT_Msk 0x2UL 740 #define USBFS_USBDEV_ARB_EP2_SR_BUF_OVER_Pos 2UL 741 #define USBFS_USBDEV_ARB_EP2_SR_BUF_OVER_Msk 0x4UL 742 #define USBFS_USBDEV_ARB_EP2_SR_BUF_UNDER_Pos 3UL 743 #define USBFS_USBDEV_ARB_EP2_SR_BUF_UNDER_Msk 0x8UL 744 #define USBFS_USBDEV_ARB_EP2_SR_DMA_TERMIN_Pos 5UL 745 #define USBFS_USBDEV_ARB_EP2_SR_DMA_TERMIN_Msk 0x20UL 746 /* USBFS_USBDEV.ARB_RW2_WA */ 747 #define USBFS_USBDEV_ARB_RW2_WA_WA_Pos 0UL 748 #define USBFS_USBDEV_ARB_RW2_WA_WA_Msk 0xFFUL 749 /* USBFS_USBDEV.ARB_RW2_WA_MSB */ 750 #define USBFS_USBDEV_ARB_RW2_WA_MSB_WA_MSB_Pos 0UL 751 #define USBFS_USBDEV_ARB_RW2_WA_MSB_WA_MSB_Msk 0x1UL 752 /* USBFS_USBDEV.ARB_RW2_RA */ 753 #define USBFS_USBDEV_ARB_RW2_RA_RA_Pos 0UL 754 #define USBFS_USBDEV_ARB_RW2_RA_RA_Msk 0xFFUL 755 /* USBFS_USBDEV.ARB_RW2_RA_MSB */ 756 #define USBFS_USBDEV_ARB_RW2_RA_MSB_RA_MSB_Pos 0UL 757 #define USBFS_USBDEV_ARB_RW2_RA_MSB_RA_MSB_Msk 0x1UL 758 /* USBFS_USBDEV.ARB_RW2_DR */ 759 #define USBFS_USBDEV_ARB_RW2_DR_DR_Pos 0UL 760 #define USBFS_USBDEV_ARB_RW2_DR_DR_Msk 0xFFUL 761 /* USBFS_USBDEV.ARB_CFG */ 762 #define USBFS_USBDEV_ARB_CFG_AUTO_MEM_Pos 4UL 763 #define USBFS_USBDEV_ARB_CFG_AUTO_MEM_Msk 0x10UL 764 #define USBFS_USBDEV_ARB_CFG_DMA_CFG_Pos 5UL 765 #define USBFS_USBDEV_ARB_CFG_DMA_CFG_Msk 0x60UL 766 #define USBFS_USBDEV_ARB_CFG_CFG_CMP_Pos 7UL 767 #define USBFS_USBDEV_ARB_CFG_CFG_CMP_Msk 0x80UL 768 /* USBFS_USBDEV.USB_CLK_EN */ 769 #define USBFS_USBDEV_USB_CLK_EN_CSR_CLK_EN_Pos 0UL 770 #define USBFS_USBDEV_USB_CLK_EN_CSR_CLK_EN_Msk 0x1UL 771 /* USBFS_USBDEV.ARB_INT_EN */ 772 #define USBFS_USBDEV_ARB_INT_EN_EP1_INTR_EN_Pos 0UL 773 #define USBFS_USBDEV_ARB_INT_EN_EP1_INTR_EN_Msk 0x1UL 774 #define USBFS_USBDEV_ARB_INT_EN_EP2_INTR_EN_Pos 1UL 775 #define USBFS_USBDEV_ARB_INT_EN_EP2_INTR_EN_Msk 0x2UL 776 #define USBFS_USBDEV_ARB_INT_EN_EP3_INTR_EN_Pos 2UL 777 #define USBFS_USBDEV_ARB_INT_EN_EP3_INTR_EN_Msk 0x4UL 778 #define USBFS_USBDEV_ARB_INT_EN_EP4_INTR_EN_Pos 3UL 779 #define USBFS_USBDEV_ARB_INT_EN_EP4_INTR_EN_Msk 0x8UL 780 #define USBFS_USBDEV_ARB_INT_EN_EP5_INTR_EN_Pos 4UL 781 #define USBFS_USBDEV_ARB_INT_EN_EP5_INTR_EN_Msk 0x10UL 782 #define USBFS_USBDEV_ARB_INT_EN_EP6_INTR_EN_Pos 5UL 783 #define USBFS_USBDEV_ARB_INT_EN_EP6_INTR_EN_Msk 0x20UL 784 #define USBFS_USBDEV_ARB_INT_EN_EP7_INTR_EN_Pos 6UL 785 #define USBFS_USBDEV_ARB_INT_EN_EP7_INTR_EN_Msk 0x40UL 786 #define USBFS_USBDEV_ARB_INT_EN_EP8_INTR_EN_Pos 7UL 787 #define USBFS_USBDEV_ARB_INT_EN_EP8_INTR_EN_Msk 0x80UL 788 /* USBFS_USBDEV.ARB_INT_SR */ 789 #define USBFS_USBDEV_ARB_INT_SR_EP1_INTR_Pos 0UL 790 #define USBFS_USBDEV_ARB_INT_SR_EP1_INTR_Msk 0x1UL 791 #define USBFS_USBDEV_ARB_INT_SR_EP2_INTR_Pos 1UL 792 #define USBFS_USBDEV_ARB_INT_SR_EP2_INTR_Msk 0x2UL 793 #define USBFS_USBDEV_ARB_INT_SR_EP3_INTR_Pos 2UL 794 #define USBFS_USBDEV_ARB_INT_SR_EP3_INTR_Msk 0x4UL 795 #define USBFS_USBDEV_ARB_INT_SR_EP4_INTR_Pos 3UL 796 #define USBFS_USBDEV_ARB_INT_SR_EP4_INTR_Msk 0x8UL 797 #define USBFS_USBDEV_ARB_INT_SR_EP5_INTR_Pos 4UL 798 #define USBFS_USBDEV_ARB_INT_SR_EP5_INTR_Msk 0x10UL 799 #define USBFS_USBDEV_ARB_INT_SR_EP6_INTR_Pos 5UL 800 #define USBFS_USBDEV_ARB_INT_SR_EP6_INTR_Msk 0x20UL 801 #define USBFS_USBDEV_ARB_INT_SR_EP7_INTR_Pos 6UL 802 #define USBFS_USBDEV_ARB_INT_SR_EP7_INTR_Msk 0x40UL 803 #define USBFS_USBDEV_ARB_INT_SR_EP8_INTR_Pos 7UL 804 #define USBFS_USBDEV_ARB_INT_SR_EP8_INTR_Msk 0x80UL 805 /* USBFS_USBDEV.ARB_EP3_CFG */ 806 #define USBFS_USBDEV_ARB_EP3_CFG_IN_DATA_RDY_Pos 0UL 807 #define USBFS_USBDEV_ARB_EP3_CFG_IN_DATA_RDY_Msk 0x1UL 808 #define USBFS_USBDEV_ARB_EP3_CFG_DMA_REQ_Pos 1UL 809 #define USBFS_USBDEV_ARB_EP3_CFG_DMA_REQ_Msk 0x2UL 810 #define USBFS_USBDEV_ARB_EP3_CFG_CRC_BYPASS_Pos 2UL 811 #define USBFS_USBDEV_ARB_EP3_CFG_CRC_BYPASS_Msk 0x4UL 812 #define USBFS_USBDEV_ARB_EP3_CFG_RESET_PTR_Pos 3UL 813 #define USBFS_USBDEV_ARB_EP3_CFG_RESET_PTR_Msk 0x8UL 814 /* USBFS_USBDEV.ARB_EP3_INT_EN */ 815 #define USBFS_USBDEV_ARB_EP3_INT_EN_IN_BUF_FULL_EN_Pos 0UL 816 #define USBFS_USBDEV_ARB_EP3_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL 817 #define USBFS_USBDEV_ARB_EP3_INT_EN_DMA_GNT_EN_Pos 1UL 818 #define USBFS_USBDEV_ARB_EP3_INT_EN_DMA_GNT_EN_Msk 0x2UL 819 #define USBFS_USBDEV_ARB_EP3_INT_EN_BUF_OVER_EN_Pos 2UL 820 #define USBFS_USBDEV_ARB_EP3_INT_EN_BUF_OVER_EN_Msk 0x4UL 821 #define USBFS_USBDEV_ARB_EP3_INT_EN_BUF_UNDER_EN_Pos 3UL 822 #define USBFS_USBDEV_ARB_EP3_INT_EN_BUF_UNDER_EN_Msk 0x8UL 823 #define USBFS_USBDEV_ARB_EP3_INT_EN_ERR_INT_EN_Pos 4UL 824 #define USBFS_USBDEV_ARB_EP3_INT_EN_ERR_INT_EN_Msk 0x10UL 825 #define USBFS_USBDEV_ARB_EP3_INT_EN_DMA_TERMIN_EN_Pos 5UL 826 #define USBFS_USBDEV_ARB_EP3_INT_EN_DMA_TERMIN_EN_Msk 0x20UL 827 /* USBFS_USBDEV.ARB_EP3_SR */ 828 #define USBFS_USBDEV_ARB_EP3_SR_IN_BUF_FULL_Pos 0UL 829 #define USBFS_USBDEV_ARB_EP3_SR_IN_BUF_FULL_Msk 0x1UL 830 #define USBFS_USBDEV_ARB_EP3_SR_DMA_GNT_Pos 1UL 831 #define USBFS_USBDEV_ARB_EP3_SR_DMA_GNT_Msk 0x2UL 832 #define USBFS_USBDEV_ARB_EP3_SR_BUF_OVER_Pos 2UL 833 #define USBFS_USBDEV_ARB_EP3_SR_BUF_OVER_Msk 0x4UL 834 #define USBFS_USBDEV_ARB_EP3_SR_BUF_UNDER_Pos 3UL 835 #define USBFS_USBDEV_ARB_EP3_SR_BUF_UNDER_Msk 0x8UL 836 #define USBFS_USBDEV_ARB_EP3_SR_DMA_TERMIN_Pos 5UL 837 #define USBFS_USBDEV_ARB_EP3_SR_DMA_TERMIN_Msk 0x20UL 838 /* USBFS_USBDEV.ARB_RW3_WA */ 839 #define USBFS_USBDEV_ARB_RW3_WA_WA_Pos 0UL 840 #define USBFS_USBDEV_ARB_RW3_WA_WA_Msk 0xFFUL 841 /* USBFS_USBDEV.ARB_RW3_WA_MSB */ 842 #define USBFS_USBDEV_ARB_RW3_WA_MSB_WA_MSB_Pos 0UL 843 #define USBFS_USBDEV_ARB_RW3_WA_MSB_WA_MSB_Msk 0x1UL 844 /* USBFS_USBDEV.ARB_RW3_RA */ 845 #define USBFS_USBDEV_ARB_RW3_RA_RA_Pos 0UL 846 #define USBFS_USBDEV_ARB_RW3_RA_RA_Msk 0xFFUL 847 /* USBFS_USBDEV.ARB_RW3_RA_MSB */ 848 #define USBFS_USBDEV_ARB_RW3_RA_MSB_RA_MSB_Pos 0UL 849 #define USBFS_USBDEV_ARB_RW3_RA_MSB_RA_MSB_Msk 0x1UL 850 /* USBFS_USBDEV.ARB_RW3_DR */ 851 #define USBFS_USBDEV_ARB_RW3_DR_DR_Pos 0UL 852 #define USBFS_USBDEV_ARB_RW3_DR_DR_Msk 0xFFUL 853 /* USBFS_USBDEV.CWA */ 854 #define USBFS_USBDEV_CWA_CWA_Pos 0UL 855 #define USBFS_USBDEV_CWA_CWA_Msk 0xFFUL 856 /* USBFS_USBDEV.CWA_MSB */ 857 #define USBFS_USBDEV_CWA_MSB_CWA_MSB_Pos 0UL 858 #define USBFS_USBDEV_CWA_MSB_CWA_MSB_Msk 0x1UL 859 /* USBFS_USBDEV.ARB_EP4_CFG */ 860 #define USBFS_USBDEV_ARB_EP4_CFG_IN_DATA_RDY_Pos 0UL 861 #define USBFS_USBDEV_ARB_EP4_CFG_IN_DATA_RDY_Msk 0x1UL 862 #define USBFS_USBDEV_ARB_EP4_CFG_DMA_REQ_Pos 1UL 863 #define USBFS_USBDEV_ARB_EP4_CFG_DMA_REQ_Msk 0x2UL 864 #define USBFS_USBDEV_ARB_EP4_CFG_CRC_BYPASS_Pos 2UL 865 #define USBFS_USBDEV_ARB_EP4_CFG_CRC_BYPASS_Msk 0x4UL 866 #define USBFS_USBDEV_ARB_EP4_CFG_RESET_PTR_Pos 3UL 867 #define USBFS_USBDEV_ARB_EP4_CFG_RESET_PTR_Msk 0x8UL 868 /* USBFS_USBDEV.ARB_EP4_INT_EN */ 869 #define USBFS_USBDEV_ARB_EP4_INT_EN_IN_BUF_FULL_EN_Pos 0UL 870 #define USBFS_USBDEV_ARB_EP4_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL 871 #define USBFS_USBDEV_ARB_EP4_INT_EN_DMA_GNT_EN_Pos 1UL 872 #define USBFS_USBDEV_ARB_EP4_INT_EN_DMA_GNT_EN_Msk 0x2UL 873 #define USBFS_USBDEV_ARB_EP4_INT_EN_BUF_OVER_EN_Pos 2UL 874 #define USBFS_USBDEV_ARB_EP4_INT_EN_BUF_OVER_EN_Msk 0x4UL 875 #define USBFS_USBDEV_ARB_EP4_INT_EN_BUF_UNDER_EN_Pos 3UL 876 #define USBFS_USBDEV_ARB_EP4_INT_EN_BUF_UNDER_EN_Msk 0x8UL 877 #define USBFS_USBDEV_ARB_EP4_INT_EN_ERR_INT_EN_Pos 4UL 878 #define USBFS_USBDEV_ARB_EP4_INT_EN_ERR_INT_EN_Msk 0x10UL 879 #define USBFS_USBDEV_ARB_EP4_INT_EN_DMA_TERMIN_EN_Pos 5UL 880 #define USBFS_USBDEV_ARB_EP4_INT_EN_DMA_TERMIN_EN_Msk 0x20UL 881 /* USBFS_USBDEV.ARB_EP4_SR */ 882 #define USBFS_USBDEV_ARB_EP4_SR_IN_BUF_FULL_Pos 0UL 883 #define USBFS_USBDEV_ARB_EP4_SR_IN_BUF_FULL_Msk 0x1UL 884 #define USBFS_USBDEV_ARB_EP4_SR_DMA_GNT_Pos 1UL 885 #define USBFS_USBDEV_ARB_EP4_SR_DMA_GNT_Msk 0x2UL 886 #define USBFS_USBDEV_ARB_EP4_SR_BUF_OVER_Pos 2UL 887 #define USBFS_USBDEV_ARB_EP4_SR_BUF_OVER_Msk 0x4UL 888 #define USBFS_USBDEV_ARB_EP4_SR_BUF_UNDER_Pos 3UL 889 #define USBFS_USBDEV_ARB_EP4_SR_BUF_UNDER_Msk 0x8UL 890 #define USBFS_USBDEV_ARB_EP4_SR_DMA_TERMIN_Pos 5UL 891 #define USBFS_USBDEV_ARB_EP4_SR_DMA_TERMIN_Msk 0x20UL 892 /* USBFS_USBDEV.ARB_RW4_WA */ 893 #define USBFS_USBDEV_ARB_RW4_WA_WA_Pos 0UL 894 #define USBFS_USBDEV_ARB_RW4_WA_WA_Msk 0xFFUL 895 /* USBFS_USBDEV.ARB_RW4_WA_MSB */ 896 #define USBFS_USBDEV_ARB_RW4_WA_MSB_WA_MSB_Pos 0UL 897 #define USBFS_USBDEV_ARB_RW4_WA_MSB_WA_MSB_Msk 0x1UL 898 /* USBFS_USBDEV.ARB_RW4_RA */ 899 #define USBFS_USBDEV_ARB_RW4_RA_RA_Pos 0UL 900 #define USBFS_USBDEV_ARB_RW4_RA_RA_Msk 0xFFUL 901 /* USBFS_USBDEV.ARB_RW4_RA_MSB */ 902 #define USBFS_USBDEV_ARB_RW4_RA_MSB_RA_MSB_Pos 0UL 903 #define USBFS_USBDEV_ARB_RW4_RA_MSB_RA_MSB_Msk 0x1UL 904 /* USBFS_USBDEV.ARB_RW4_DR */ 905 #define USBFS_USBDEV_ARB_RW4_DR_DR_Pos 0UL 906 #define USBFS_USBDEV_ARB_RW4_DR_DR_Msk 0xFFUL 907 /* USBFS_USBDEV.DMA_THRES */ 908 #define USBFS_USBDEV_DMA_THRES_DMA_THS_Pos 0UL 909 #define USBFS_USBDEV_DMA_THRES_DMA_THS_Msk 0xFFUL 910 /* USBFS_USBDEV.DMA_THRES_MSB */ 911 #define USBFS_USBDEV_DMA_THRES_MSB_DMA_THS_MSB_Pos 0UL 912 #define USBFS_USBDEV_DMA_THRES_MSB_DMA_THS_MSB_Msk 0x1UL 913 /* USBFS_USBDEV.ARB_EP5_CFG */ 914 #define USBFS_USBDEV_ARB_EP5_CFG_IN_DATA_RDY_Pos 0UL 915 #define USBFS_USBDEV_ARB_EP5_CFG_IN_DATA_RDY_Msk 0x1UL 916 #define USBFS_USBDEV_ARB_EP5_CFG_DMA_REQ_Pos 1UL 917 #define USBFS_USBDEV_ARB_EP5_CFG_DMA_REQ_Msk 0x2UL 918 #define USBFS_USBDEV_ARB_EP5_CFG_CRC_BYPASS_Pos 2UL 919 #define USBFS_USBDEV_ARB_EP5_CFG_CRC_BYPASS_Msk 0x4UL 920 #define USBFS_USBDEV_ARB_EP5_CFG_RESET_PTR_Pos 3UL 921 #define USBFS_USBDEV_ARB_EP5_CFG_RESET_PTR_Msk 0x8UL 922 /* USBFS_USBDEV.ARB_EP5_INT_EN */ 923 #define USBFS_USBDEV_ARB_EP5_INT_EN_IN_BUF_FULL_EN_Pos 0UL 924 #define USBFS_USBDEV_ARB_EP5_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL 925 #define USBFS_USBDEV_ARB_EP5_INT_EN_DMA_GNT_EN_Pos 1UL 926 #define USBFS_USBDEV_ARB_EP5_INT_EN_DMA_GNT_EN_Msk 0x2UL 927 #define USBFS_USBDEV_ARB_EP5_INT_EN_BUF_OVER_EN_Pos 2UL 928 #define USBFS_USBDEV_ARB_EP5_INT_EN_BUF_OVER_EN_Msk 0x4UL 929 #define USBFS_USBDEV_ARB_EP5_INT_EN_BUF_UNDER_EN_Pos 3UL 930 #define USBFS_USBDEV_ARB_EP5_INT_EN_BUF_UNDER_EN_Msk 0x8UL 931 #define USBFS_USBDEV_ARB_EP5_INT_EN_ERR_INT_EN_Pos 4UL 932 #define USBFS_USBDEV_ARB_EP5_INT_EN_ERR_INT_EN_Msk 0x10UL 933 #define USBFS_USBDEV_ARB_EP5_INT_EN_DMA_TERMIN_EN_Pos 5UL 934 #define USBFS_USBDEV_ARB_EP5_INT_EN_DMA_TERMIN_EN_Msk 0x20UL 935 /* USBFS_USBDEV.ARB_EP5_SR */ 936 #define USBFS_USBDEV_ARB_EP5_SR_IN_BUF_FULL_Pos 0UL 937 #define USBFS_USBDEV_ARB_EP5_SR_IN_BUF_FULL_Msk 0x1UL 938 #define USBFS_USBDEV_ARB_EP5_SR_DMA_GNT_Pos 1UL 939 #define USBFS_USBDEV_ARB_EP5_SR_DMA_GNT_Msk 0x2UL 940 #define USBFS_USBDEV_ARB_EP5_SR_BUF_OVER_Pos 2UL 941 #define USBFS_USBDEV_ARB_EP5_SR_BUF_OVER_Msk 0x4UL 942 #define USBFS_USBDEV_ARB_EP5_SR_BUF_UNDER_Pos 3UL 943 #define USBFS_USBDEV_ARB_EP5_SR_BUF_UNDER_Msk 0x8UL 944 #define USBFS_USBDEV_ARB_EP5_SR_DMA_TERMIN_Pos 5UL 945 #define USBFS_USBDEV_ARB_EP5_SR_DMA_TERMIN_Msk 0x20UL 946 /* USBFS_USBDEV.ARB_RW5_WA */ 947 #define USBFS_USBDEV_ARB_RW5_WA_WA_Pos 0UL 948 #define USBFS_USBDEV_ARB_RW5_WA_WA_Msk 0xFFUL 949 /* USBFS_USBDEV.ARB_RW5_WA_MSB */ 950 #define USBFS_USBDEV_ARB_RW5_WA_MSB_WA_MSB_Pos 0UL 951 #define USBFS_USBDEV_ARB_RW5_WA_MSB_WA_MSB_Msk 0x1UL 952 /* USBFS_USBDEV.ARB_RW5_RA */ 953 #define USBFS_USBDEV_ARB_RW5_RA_RA_Pos 0UL 954 #define USBFS_USBDEV_ARB_RW5_RA_RA_Msk 0xFFUL 955 /* USBFS_USBDEV.ARB_RW5_RA_MSB */ 956 #define USBFS_USBDEV_ARB_RW5_RA_MSB_RA_MSB_Pos 0UL 957 #define USBFS_USBDEV_ARB_RW5_RA_MSB_RA_MSB_Msk 0x1UL 958 /* USBFS_USBDEV.ARB_RW5_DR */ 959 #define USBFS_USBDEV_ARB_RW5_DR_DR_Pos 0UL 960 #define USBFS_USBDEV_ARB_RW5_DR_DR_Msk 0xFFUL 961 /* USBFS_USBDEV.BUS_RST_CNT */ 962 #define USBFS_USBDEV_BUS_RST_CNT_BUS_RST_CNT_Pos 0UL 963 #define USBFS_USBDEV_BUS_RST_CNT_BUS_RST_CNT_Msk 0xFUL 964 /* USBFS_USBDEV.ARB_EP6_CFG */ 965 #define USBFS_USBDEV_ARB_EP6_CFG_IN_DATA_RDY_Pos 0UL 966 #define USBFS_USBDEV_ARB_EP6_CFG_IN_DATA_RDY_Msk 0x1UL 967 #define USBFS_USBDEV_ARB_EP6_CFG_DMA_REQ_Pos 1UL 968 #define USBFS_USBDEV_ARB_EP6_CFG_DMA_REQ_Msk 0x2UL 969 #define USBFS_USBDEV_ARB_EP6_CFG_CRC_BYPASS_Pos 2UL 970 #define USBFS_USBDEV_ARB_EP6_CFG_CRC_BYPASS_Msk 0x4UL 971 #define USBFS_USBDEV_ARB_EP6_CFG_RESET_PTR_Pos 3UL 972 #define USBFS_USBDEV_ARB_EP6_CFG_RESET_PTR_Msk 0x8UL 973 /* USBFS_USBDEV.ARB_EP6_INT_EN */ 974 #define USBFS_USBDEV_ARB_EP6_INT_EN_IN_BUF_FULL_EN_Pos 0UL 975 #define USBFS_USBDEV_ARB_EP6_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL 976 #define USBFS_USBDEV_ARB_EP6_INT_EN_DMA_GNT_EN_Pos 1UL 977 #define USBFS_USBDEV_ARB_EP6_INT_EN_DMA_GNT_EN_Msk 0x2UL 978 #define USBFS_USBDEV_ARB_EP6_INT_EN_BUF_OVER_EN_Pos 2UL 979 #define USBFS_USBDEV_ARB_EP6_INT_EN_BUF_OVER_EN_Msk 0x4UL 980 #define USBFS_USBDEV_ARB_EP6_INT_EN_BUF_UNDER_EN_Pos 3UL 981 #define USBFS_USBDEV_ARB_EP6_INT_EN_BUF_UNDER_EN_Msk 0x8UL 982 #define USBFS_USBDEV_ARB_EP6_INT_EN_ERR_INT_EN_Pos 4UL 983 #define USBFS_USBDEV_ARB_EP6_INT_EN_ERR_INT_EN_Msk 0x10UL 984 #define USBFS_USBDEV_ARB_EP6_INT_EN_DMA_TERMIN_EN_Pos 5UL 985 #define USBFS_USBDEV_ARB_EP6_INT_EN_DMA_TERMIN_EN_Msk 0x20UL 986 /* USBFS_USBDEV.ARB_EP6_SR */ 987 #define USBFS_USBDEV_ARB_EP6_SR_IN_BUF_FULL_Pos 0UL 988 #define USBFS_USBDEV_ARB_EP6_SR_IN_BUF_FULL_Msk 0x1UL 989 #define USBFS_USBDEV_ARB_EP6_SR_DMA_GNT_Pos 1UL 990 #define USBFS_USBDEV_ARB_EP6_SR_DMA_GNT_Msk 0x2UL 991 #define USBFS_USBDEV_ARB_EP6_SR_BUF_OVER_Pos 2UL 992 #define USBFS_USBDEV_ARB_EP6_SR_BUF_OVER_Msk 0x4UL 993 #define USBFS_USBDEV_ARB_EP6_SR_BUF_UNDER_Pos 3UL 994 #define USBFS_USBDEV_ARB_EP6_SR_BUF_UNDER_Msk 0x8UL 995 #define USBFS_USBDEV_ARB_EP6_SR_DMA_TERMIN_Pos 5UL 996 #define USBFS_USBDEV_ARB_EP6_SR_DMA_TERMIN_Msk 0x20UL 997 /* USBFS_USBDEV.ARB_RW6_WA */ 998 #define USBFS_USBDEV_ARB_RW6_WA_WA_Pos 0UL 999 #define USBFS_USBDEV_ARB_RW6_WA_WA_Msk 0xFFUL 1000 /* USBFS_USBDEV.ARB_RW6_WA_MSB */ 1001 #define USBFS_USBDEV_ARB_RW6_WA_MSB_WA_MSB_Pos 0UL 1002 #define USBFS_USBDEV_ARB_RW6_WA_MSB_WA_MSB_Msk 0x1UL 1003 /* USBFS_USBDEV.ARB_RW6_RA */ 1004 #define USBFS_USBDEV_ARB_RW6_RA_RA_Pos 0UL 1005 #define USBFS_USBDEV_ARB_RW6_RA_RA_Msk 0xFFUL 1006 /* USBFS_USBDEV.ARB_RW6_RA_MSB */ 1007 #define USBFS_USBDEV_ARB_RW6_RA_MSB_RA_MSB_Pos 0UL 1008 #define USBFS_USBDEV_ARB_RW6_RA_MSB_RA_MSB_Msk 0x1UL 1009 /* USBFS_USBDEV.ARB_RW6_DR */ 1010 #define USBFS_USBDEV_ARB_RW6_DR_DR_Pos 0UL 1011 #define USBFS_USBDEV_ARB_RW6_DR_DR_Msk 0xFFUL 1012 /* USBFS_USBDEV.ARB_EP7_CFG */ 1013 #define USBFS_USBDEV_ARB_EP7_CFG_IN_DATA_RDY_Pos 0UL 1014 #define USBFS_USBDEV_ARB_EP7_CFG_IN_DATA_RDY_Msk 0x1UL 1015 #define USBFS_USBDEV_ARB_EP7_CFG_DMA_REQ_Pos 1UL 1016 #define USBFS_USBDEV_ARB_EP7_CFG_DMA_REQ_Msk 0x2UL 1017 #define USBFS_USBDEV_ARB_EP7_CFG_CRC_BYPASS_Pos 2UL 1018 #define USBFS_USBDEV_ARB_EP7_CFG_CRC_BYPASS_Msk 0x4UL 1019 #define USBFS_USBDEV_ARB_EP7_CFG_RESET_PTR_Pos 3UL 1020 #define USBFS_USBDEV_ARB_EP7_CFG_RESET_PTR_Msk 0x8UL 1021 /* USBFS_USBDEV.ARB_EP7_INT_EN */ 1022 #define USBFS_USBDEV_ARB_EP7_INT_EN_IN_BUF_FULL_EN_Pos 0UL 1023 #define USBFS_USBDEV_ARB_EP7_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL 1024 #define USBFS_USBDEV_ARB_EP7_INT_EN_DMA_GNT_EN_Pos 1UL 1025 #define USBFS_USBDEV_ARB_EP7_INT_EN_DMA_GNT_EN_Msk 0x2UL 1026 #define USBFS_USBDEV_ARB_EP7_INT_EN_BUF_OVER_EN_Pos 2UL 1027 #define USBFS_USBDEV_ARB_EP7_INT_EN_BUF_OVER_EN_Msk 0x4UL 1028 #define USBFS_USBDEV_ARB_EP7_INT_EN_BUF_UNDER_EN_Pos 3UL 1029 #define USBFS_USBDEV_ARB_EP7_INT_EN_BUF_UNDER_EN_Msk 0x8UL 1030 #define USBFS_USBDEV_ARB_EP7_INT_EN_ERR_INT_EN_Pos 4UL 1031 #define USBFS_USBDEV_ARB_EP7_INT_EN_ERR_INT_EN_Msk 0x10UL 1032 #define USBFS_USBDEV_ARB_EP7_INT_EN_DMA_TERMIN_EN_Pos 5UL 1033 #define USBFS_USBDEV_ARB_EP7_INT_EN_DMA_TERMIN_EN_Msk 0x20UL 1034 /* USBFS_USBDEV.ARB_EP7_SR */ 1035 #define USBFS_USBDEV_ARB_EP7_SR_IN_BUF_FULL_Pos 0UL 1036 #define USBFS_USBDEV_ARB_EP7_SR_IN_BUF_FULL_Msk 0x1UL 1037 #define USBFS_USBDEV_ARB_EP7_SR_DMA_GNT_Pos 1UL 1038 #define USBFS_USBDEV_ARB_EP7_SR_DMA_GNT_Msk 0x2UL 1039 #define USBFS_USBDEV_ARB_EP7_SR_BUF_OVER_Pos 2UL 1040 #define USBFS_USBDEV_ARB_EP7_SR_BUF_OVER_Msk 0x4UL 1041 #define USBFS_USBDEV_ARB_EP7_SR_BUF_UNDER_Pos 3UL 1042 #define USBFS_USBDEV_ARB_EP7_SR_BUF_UNDER_Msk 0x8UL 1043 #define USBFS_USBDEV_ARB_EP7_SR_DMA_TERMIN_Pos 5UL 1044 #define USBFS_USBDEV_ARB_EP7_SR_DMA_TERMIN_Msk 0x20UL 1045 /* USBFS_USBDEV.ARB_RW7_WA */ 1046 #define USBFS_USBDEV_ARB_RW7_WA_WA_Pos 0UL 1047 #define USBFS_USBDEV_ARB_RW7_WA_WA_Msk 0xFFUL 1048 /* USBFS_USBDEV.ARB_RW7_WA_MSB */ 1049 #define USBFS_USBDEV_ARB_RW7_WA_MSB_WA_MSB_Pos 0UL 1050 #define USBFS_USBDEV_ARB_RW7_WA_MSB_WA_MSB_Msk 0x1UL 1051 /* USBFS_USBDEV.ARB_RW7_RA */ 1052 #define USBFS_USBDEV_ARB_RW7_RA_RA_Pos 0UL 1053 #define USBFS_USBDEV_ARB_RW7_RA_RA_Msk 0xFFUL 1054 /* USBFS_USBDEV.ARB_RW7_RA_MSB */ 1055 #define USBFS_USBDEV_ARB_RW7_RA_MSB_RA_MSB_Pos 0UL 1056 #define USBFS_USBDEV_ARB_RW7_RA_MSB_RA_MSB_Msk 0x1UL 1057 /* USBFS_USBDEV.ARB_RW7_DR */ 1058 #define USBFS_USBDEV_ARB_RW7_DR_DR_Pos 0UL 1059 #define USBFS_USBDEV_ARB_RW7_DR_DR_Msk 0xFFUL 1060 /* USBFS_USBDEV.ARB_EP8_CFG */ 1061 #define USBFS_USBDEV_ARB_EP8_CFG_IN_DATA_RDY_Pos 0UL 1062 #define USBFS_USBDEV_ARB_EP8_CFG_IN_DATA_RDY_Msk 0x1UL 1063 #define USBFS_USBDEV_ARB_EP8_CFG_DMA_REQ_Pos 1UL 1064 #define USBFS_USBDEV_ARB_EP8_CFG_DMA_REQ_Msk 0x2UL 1065 #define USBFS_USBDEV_ARB_EP8_CFG_CRC_BYPASS_Pos 2UL 1066 #define USBFS_USBDEV_ARB_EP8_CFG_CRC_BYPASS_Msk 0x4UL 1067 #define USBFS_USBDEV_ARB_EP8_CFG_RESET_PTR_Pos 3UL 1068 #define USBFS_USBDEV_ARB_EP8_CFG_RESET_PTR_Msk 0x8UL 1069 /* USBFS_USBDEV.ARB_EP8_INT_EN */ 1070 #define USBFS_USBDEV_ARB_EP8_INT_EN_IN_BUF_FULL_EN_Pos 0UL 1071 #define USBFS_USBDEV_ARB_EP8_INT_EN_IN_BUF_FULL_EN_Msk 0x1UL 1072 #define USBFS_USBDEV_ARB_EP8_INT_EN_DMA_GNT_EN_Pos 1UL 1073 #define USBFS_USBDEV_ARB_EP8_INT_EN_DMA_GNT_EN_Msk 0x2UL 1074 #define USBFS_USBDEV_ARB_EP8_INT_EN_BUF_OVER_EN_Pos 2UL 1075 #define USBFS_USBDEV_ARB_EP8_INT_EN_BUF_OVER_EN_Msk 0x4UL 1076 #define USBFS_USBDEV_ARB_EP8_INT_EN_BUF_UNDER_EN_Pos 3UL 1077 #define USBFS_USBDEV_ARB_EP8_INT_EN_BUF_UNDER_EN_Msk 0x8UL 1078 #define USBFS_USBDEV_ARB_EP8_INT_EN_ERR_INT_EN_Pos 4UL 1079 #define USBFS_USBDEV_ARB_EP8_INT_EN_ERR_INT_EN_Msk 0x10UL 1080 #define USBFS_USBDEV_ARB_EP8_INT_EN_DMA_TERMIN_EN_Pos 5UL 1081 #define USBFS_USBDEV_ARB_EP8_INT_EN_DMA_TERMIN_EN_Msk 0x20UL 1082 /* USBFS_USBDEV.ARB_EP8_SR */ 1083 #define USBFS_USBDEV_ARB_EP8_SR_IN_BUF_FULL_Pos 0UL 1084 #define USBFS_USBDEV_ARB_EP8_SR_IN_BUF_FULL_Msk 0x1UL 1085 #define USBFS_USBDEV_ARB_EP8_SR_DMA_GNT_Pos 1UL 1086 #define USBFS_USBDEV_ARB_EP8_SR_DMA_GNT_Msk 0x2UL 1087 #define USBFS_USBDEV_ARB_EP8_SR_BUF_OVER_Pos 2UL 1088 #define USBFS_USBDEV_ARB_EP8_SR_BUF_OVER_Msk 0x4UL 1089 #define USBFS_USBDEV_ARB_EP8_SR_BUF_UNDER_Pos 3UL 1090 #define USBFS_USBDEV_ARB_EP8_SR_BUF_UNDER_Msk 0x8UL 1091 #define USBFS_USBDEV_ARB_EP8_SR_DMA_TERMIN_Pos 5UL 1092 #define USBFS_USBDEV_ARB_EP8_SR_DMA_TERMIN_Msk 0x20UL 1093 /* USBFS_USBDEV.ARB_RW8_WA */ 1094 #define USBFS_USBDEV_ARB_RW8_WA_WA_Pos 0UL 1095 #define USBFS_USBDEV_ARB_RW8_WA_WA_Msk 0xFFUL 1096 /* USBFS_USBDEV.ARB_RW8_WA_MSB */ 1097 #define USBFS_USBDEV_ARB_RW8_WA_MSB_WA_MSB_Pos 0UL 1098 #define USBFS_USBDEV_ARB_RW8_WA_MSB_WA_MSB_Msk 0x1UL 1099 /* USBFS_USBDEV.ARB_RW8_RA */ 1100 #define USBFS_USBDEV_ARB_RW8_RA_RA_Pos 0UL 1101 #define USBFS_USBDEV_ARB_RW8_RA_RA_Msk 0xFFUL 1102 /* USBFS_USBDEV.ARB_RW8_RA_MSB */ 1103 #define USBFS_USBDEV_ARB_RW8_RA_MSB_RA_MSB_Pos 0UL 1104 #define USBFS_USBDEV_ARB_RW8_RA_MSB_RA_MSB_Msk 0x1UL 1105 /* USBFS_USBDEV.ARB_RW8_DR */ 1106 #define USBFS_USBDEV_ARB_RW8_DR_DR_Pos 0UL 1107 #define USBFS_USBDEV_ARB_RW8_DR_DR_Msk 0xFFUL 1108 /* USBFS_USBDEV.MEM_DATA */ 1109 #define USBFS_USBDEV_MEM_DATA_DR_Pos 0UL 1110 #define USBFS_USBDEV_MEM_DATA_DR_Msk 0xFFUL 1111 /* USBFS_USBDEV.SOF16 */ 1112 #define USBFS_USBDEV_SOF16_FRAME_NUMBER16_Pos 0UL 1113 #define USBFS_USBDEV_SOF16_FRAME_NUMBER16_Msk 0x7FFUL 1114 /* USBFS_USBDEV.OSCLK_DR16 */ 1115 #define USBFS_USBDEV_OSCLK_DR16_ADDER16_Pos 0UL 1116 #define USBFS_USBDEV_OSCLK_DR16_ADDER16_Msk 0x7FFFUL 1117 /* USBFS_USBDEV.ARB_RW1_WA16 */ 1118 #define USBFS_USBDEV_ARB_RW1_WA16_WA16_Pos 0UL 1119 #define USBFS_USBDEV_ARB_RW1_WA16_WA16_Msk 0x1FFUL 1120 /* USBFS_USBDEV.ARB_RW1_RA16 */ 1121 #define USBFS_USBDEV_ARB_RW1_RA16_RA16_Pos 0UL 1122 #define USBFS_USBDEV_ARB_RW1_RA16_RA16_Msk 0x1FFUL 1123 /* USBFS_USBDEV.ARB_RW1_DR16 */ 1124 #define USBFS_USBDEV_ARB_RW1_DR16_DR16_Pos 0UL 1125 #define USBFS_USBDEV_ARB_RW1_DR16_DR16_Msk 0xFFFFUL 1126 /* USBFS_USBDEV.ARB_RW2_WA16 */ 1127 #define USBFS_USBDEV_ARB_RW2_WA16_WA16_Pos 0UL 1128 #define USBFS_USBDEV_ARB_RW2_WA16_WA16_Msk 0x1FFUL 1129 /* USBFS_USBDEV.ARB_RW2_RA16 */ 1130 #define USBFS_USBDEV_ARB_RW2_RA16_RA16_Pos 0UL 1131 #define USBFS_USBDEV_ARB_RW2_RA16_RA16_Msk 0x1FFUL 1132 /* USBFS_USBDEV.ARB_RW2_DR16 */ 1133 #define USBFS_USBDEV_ARB_RW2_DR16_DR16_Pos 0UL 1134 #define USBFS_USBDEV_ARB_RW2_DR16_DR16_Msk 0xFFFFUL 1135 /* USBFS_USBDEV.ARB_RW3_WA16 */ 1136 #define USBFS_USBDEV_ARB_RW3_WA16_WA16_Pos 0UL 1137 #define USBFS_USBDEV_ARB_RW3_WA16_WA16_Msk 0x1FFUL 1138 /* USBFS_USBDEV.ARB_RW3_RA16 */ 1139 #define USBFS_USBDEV_ARB_RW3_RA16_RA16_Pos 0UL 1140 #define USBFS_USBDEV_ARB_RW3_RA16_RA16_Msk 0x1FFUL 1141 /* USBFS_USBDEV.ARB_RW3_DR16 */ 1142 #define USBFS_USBDEV_ARB_RW3_DR16_DR16_Pos 0UL 1143 #define USBFS_USBDEV_ARB_RW3_DR16_DR16_Msk 0xFFFFUL 1144 /* USBFS_USBDEV.CWA16 */ 1145 #define USBFS_USBDEV_CWA16_CWA16_Pos 0UL 1146 #define USBFS_USBDEV_CWA16_CWA16_Msk 0x1FFUL 1147 /* USBFS_USBDEV.ARB_RW4_WA16 */ 1148 #define USBFS_USBDEV_ARB_RW4_WA16_WA16_Pos 0UL 1149 #define USBFS_USBDEV_ARB_RW4_WA16_WA16_Msk 0x1FFUL 1150 /* USBFS_USBDEV.ARB_RW4_RA16 */ 1151 #define USBFS_USBDEV_ARB_RW4_RA16_RA16_Pos 0UL 1152 #define USBFS_USBDEV_ARB_RW4_RA16_RA16_Msk 0x1FFUL 1153 /* USBFS_USBDEV.ARB_RW4_DR16 */ 1154 #define USBFS_USBDEV_ARB_RW4_DR16_DR16_Pos 0UL 1155 #define USBFS_USBDEV_ARB_RW4_DR16_DR16_Msk 0xFFFFUL 1156 /* USBFS_USBDEV.DMA_THRES16 */ 1157 #define USBFS_USBDEV_DMA_THRES16_DMA_THS16_Pos 0UL 1158 #define USBFS_USBDEV_DMA_THRES16_DMA_THS16_Msk 0x1FFUL 1159 /* USBFS_USBDEV.ARB_RW5_WA16 */ 1160 #define USBFS_USBDEV_ARB_RW5_WA16_WA16_Pos 0UL 1161 #define USBFS_USBDEV_ARB_RW5_WA16_WA16_Msk 0x1FFUL 1162 /* USBFS_USBDEV.ARB_RW5_RA16 */ 1163 #define USBFS_USBDEV_ARB_RW5_RA16_RA16_Pos 0UL 1164 #define USBFS_USBDEV_ARB_RW5_RA16_RA16_Msk 0x1FFUL 1165 /* USBFS_USBDEV.ARB_RW5_DR16 */ 1166 #define USBFS_USBDEV_ARB_RW5_DR16_DR16_Pos 0UL 1167 #define USBFS_USBDEV_ARB_RW5_DR16_DR16_Msk 0xFFFFUL 1168 /* USBFS_USBDEV.ARB_RW6_WA16 */ 1169 #define USBFS_USBDEV_ARB_RW6_WA16_WA16_Pos 0UL 1170 #define USBFS_USBDEV_ARB_RW6_WA16_WA16_Msk 0x1FFUL 1171 /* USBFS_USBDEV.ARB_RW6_RA16 */ 1172 #define USBFS_USBDEV_ARB_RW6_RA16_RA16_Pos 0UL 1173 #define USBFS_USBDEV_ARB_RW6_RA16_RA16_Msk 0x1FFUL 1174 /* USBFS_USBDEV.ARB_RW6_DR16 */ 1175 #define USBFS_USBDEV_ARB_RW6_DR16_DR16_Pos 0UL 1176 #define USBFS_USBDEV_ARB_RW6_DR16_DR16_Msk 0xFFFFUL 1177 /* USBFS_USBDEV.ARB_RW7_WA16 */ 1178 #define USBFS_USBDEV_ARB_RW7_WA16_WA16_Pos 0UL 1179 #define USBFS_USBDEV_ARB_RW7_WA16_WA16_Msk 0x1FFUL 1180 /* USBFS_USBDEV.ARB_RW7_RA16 */ 1181 #define USBFS_USBDEV_ARB_RW7_RA16_RA16_Pos 0UL 1182 #define USBFS_USBDEV_ARB_RW7_RA16_RA16_Msk 0x1FFUL 1183 /* USBFS_USBDEV.ARB_RW7_DR16 */ 1184 #define USBFS_USBDEV_ARB_RW7_DR16_DR16_Pos 0UL 1185 #define USBFS_USBDEV_ARB_RW7_DR16_DR16_Msk 0xFFFFUL 1186 /* USBFS_USBDEV.ARB_RW8_WA16 */ 1187 #define USBFS_USBDEV_ARB_RW8_WA16_WA16_Pos 0UL 1188 #define USBFS_USBDEV_ARB_RW8_WA16_WA16_Msk 0x1FFUL 1189 /* USBFS_USBDEV.ARB_RW8_RA16 */ 1190 #define USBFS_USBDEV_ARB_RW8_RA16_RA16_Pos 0UL 1191 #define USBFS_USBDEV_ARB_RW8_RA16_RA16_Msk 0x1FFUL 1192 /* USBFS_USBDEV.ARB_RW8_DR16 */ 1193 #define USBFS_USBDEV_ARB_RW8_DR16_DR16_Pos 0UL 1194 #define USBFS_USBDEV_ARB_RW8_DR16_DR16_Msk 0xFFFFUL 1195 1196 1197 /* USBFS_USBLPM.POWER_CTL */ 1198 #define USBFS_USBLPM_POWER_CTL_SUSPEND_Pos 2UL 1199 #define USBFS_USBLPM_POWER_CTL_SUSPEND_Msk 0x4UL 1200 #define USBFS_USBLPM_POWER_CTL_DP_UP_EN_Pos 16UL 1201 #define USBFS_USBLPM_POWER_CTL_DP_UP_EN_Msk 0x10000UL 1202 #define USBFS_USBLPM_POWER_CTL_DP_BIG_Pos 17UL 1203 #define USBFS_USBLPM_POWER_CTL_DP_BIG_Msk 0x20000UL 1204 #define USBFS_USBLPM_POWER_CTL_DP_DOWN_EN_Pos 18UL 1205 #define USBFS_USBLPM_POWER_CTL_DP_DOWN_EN_Msk 0x40000UL 1206 #define USBFS_USBLPM_POWER_CTL_DM_UP_EN_Pos 19UL 1207 #define USBFS_USBLPM_POWER_CTL_DM_UP_EN_Msk 0x80000UL 1208 #define USBFS_USBLPM_POWER_CTL_DM_BIG_Pos 20UL 1209 #define USBFS_USBLPM_POWER_CTL_DM_BIG_Msk 0x100000UL 1210 #define USBFS_USBLPM_POWER_CTL_DM_DOWN_EN_Pos 21UL 1211 #define USBFS_USBLPM_POWER_CTL_DM_DOWN_EN_Msk 0x200000UL 1212 #define USBFS_USBLPM_POWER_CTL_ENABLE_DPO_Pos 28UL 1213 #define USBFS_USBLPM_POWER_CTL_ENABLE_DPO_Msk 0x10000000UL 1214 #define USBFS_USBLPM_POWER_CTL_ENABLE_DMO_Pos 29UL 1215 #define USBFS_USBLPM_POWER_CTL_ENABLE_DMO_Msk 0x20000000UL 1216 /* USBFS_USBLPM.USBIO_CTL */ 1217 #define USBFS_USBLPM_USBIO_CTL_DM_P_Pos 0UL 1218 #define USBFS_USBLPM_USBIO_CTL_DM_P_Msk 0x7UL 1219 #define USBFS_USBLPM_USBIO_CTL_DM_M_Pos 3UL 1220 #define USBFS_USBLPM_USBIO_CTL_DM_M_Msk 0x38UL 1221 /* USBFS_USBLPM.FLOW_CTL */ 1222 #define USBFS_USBLPM_FLOW_CTL_EP1_ERR_RESP_Pos 0UL 1223 #define USBFS_USBLPM_FLOW_CTL_EP1_ERR_RESP_Msk 0x1UL 1224 #define USBFS_USBLPM_FLOW_CTL_EP2_ERR_RESP_Pos 1UL 1225 #define USBFS_USBLPM_FLOW_CTL_EP2_ERR_RESP_Msk 0x2UL 1226 #define USBFS_USBLPM_FLOW_CTL_EP3_ERR_RESP_Pos 2UL 1227 #define USBFS_USBLPM_FLOW_CTL_EP3_ERR_RESP_Msk 0x4UL 1228 #define USBFS_USBLPM_FLOW_CTL_EP4_ERR_RESP_Pos 3UL 1229 #define USBFS_USBLPM_FLOW_CTL_EP4_ERR_RESP_Msk 0x8UL 1230 #define USBFS_USBLPM_FLOW_CTL_EP5_ERR_RESP_Pos 4UL 1231 #define USBFS_USBLPM_FLOW_CTL_EP5_ERR_RESP_Msk 0x10UL 1232 #define USBFS_USBLPM_FLOW_CTL_EP6_ERR_RESP_Pos 5UL 1233 #define USBFS_USBLPM_FLOW_CTL_EP6_ERR_RESP_Msk 0x20UL 1234 #define USBFS_USBLPM_FLOW_CTL_EP7_ERR_RESP_Pos 6UL 1235 #define USBFS_USBLPM_FLOW_CTL_EP7_ERR_RESP_Msk 0x40UL 1236 #define USBFS_USBLPM_FLOW_CTL_EP8_ERR_RESP_Pos 7UL 1237 #define USBFS_USBLPM_FLOW_CTL_EP8_ERR_RESP_Msk 0x80UL 1238 /* USBFS_USBLPM.LPM_CTL */ 1239 #define USBFS_USBLPM_LPM_CTL_LPM_EN_Pos 0UL 1240 #define USBFS_USBLPM_LPM_CTL_LPM_EN_Msk 0x1UL 1241 #define USBFS_USBLPM_LPM_CTL_LPM_ACK_RESP_Pos 1UL 1242 #define USBFS_USBLPM_LPM_CTL_LPM_ACK_RESP_Msk 0x2UL 1243 #define USBFS_USBLPM_LPM_CTL_NYET_EN_Pos 2UL 1244 #define USBFS_USBLPM_LPM_CTL_NYET_EN_Msk 0x4UL 1245 #define USBFS_USBLPM_LPM_CTL_SUB_RESP_Pos 4UL 1246 #define USBFS_USBLPM_LPM_CTL_SUB_RESP_Msk 0x10UL 1247 /* USBFS_USBLPM.LPM_STAT */ 1248 #define USBFS_USBLPM_LPM_STAT_LPM_BESL_Pos 0UL 1249 #define USBFS_USBLPM_LPM_STAT_LPM_BESL_Msk 0xFUL 1250 #define USBFS_USBLPM_LPM_STAT_LPM_REMOTEWAKE_Pos 4UL 1251 #define USBFS_USBLPM_LPM_STAT_LPM_REMOTEWAKE_Msk 0x10UL 1252 /* USBFS_USBLPM.INTR_SIE */ 1253 #define USBFS_USBLPM_INTR_SIE_SOF_INTR_Pos 0UL 1254 #define USBFS_USBLPM_INTR_SIE_SOF_INTR_Msk 0x1UL 1255 #define USBFS_USBLPM_INTR_SIE_BUS_RESET_INTR_Pos 1UL 1256 #define USBFS_USBLPM_INTR_SIE_BUS_RESET_INTR_Msk 0x2UL 1257 #define USBFS_USBLPM_INTR_SIE_EP0_INTR_Pos 2UL 1258 #define USBFS_USBLPM_INTR_SIE_EP0_INTR_Msk 0x4UL 1259 #define USBFS_USBLPM_INTR_SIE_LPM_INTR_Pos 3UL 1260 #define USBFS_USBLPM_INTR_SIE_LPM_INTR_Msk 0x8UL 1261 #define USBFS_USBLPM_INTR_SIE_RESUME_INTR_Pos 4UL 1262 #define USBFS_USBLPM_INTR_SIE_RESUME_INTR_Msk 0x10UL 1263 /* USBFS_USBLPM.INTR_SIE_SET */ 1264 #define USBFS_USBLPM_INTR_SIE_SET_SOF_INTR_SET_Pos 0UL 1265 #define USBFS_USBLPM_INTR_SIE_SET_SOF_INTR_SET_Msk 0x1UL 1266 #define USBFS_USBLPM_INTR_SIE_SET_BUS_RESET_INTR_SET_Pos 1UL 1267 #define USBFS_USBLPM_INTR_SIE_SET_BUS_RESET_INTR_SET_Msk 0x2UL 1268 #define USBFS_USBLPM_INTR_SIE_SET_EP0_INTR_SET_Pos 2UL 1269 #define USBFS_USBLPM_INTR_SIE_SET_EP0_INTR_SET_Msk 0x4UL 1270 #define USBFS_USBLPM_INTR_SIE_SET_LPM_INTR_SET_Pos 3UL 1271 #define USBFS_USBLPM_INTR_SIE_SET_LPM_INTR_SET_Msk 0x8UL 1272 #define USBFS_USBLPM_INTR_SIE_SET_RESUME_INTR_SET_Pos 4UL 1273 #define USBFS_USBLPM_INTR_SIE_SET_RESUME_INTR_SET_Msk 0x10UL 1274 /* USBFS_USBLPM.INTR_SIE_MASK */ 1275 #define USBFS_USBLPM_INTR_SIE_MASK_SOF_INTR_MASK_Pos 0UL 1276 #define USBFS_USBLPM_INTR_SIE_MASK_SOF_INTR_MASK_Msk 0x1UL 1277 #define USBFS_USBLPM_INTR_SIE_MASK_BUS_RESET_INTR_MASK_Pos 1UL 1278 #define USBFS_USBLPM_INTR_SIE_MASK_BUS_RESET_INTR_MASK_Msk 0x2UL 1279 #define USBFS_USBLPM_INTR_SIE_MASK_EP0_INTR_MASK_Pos 2UL 1280 #define USBFS_USBLPM_INTR_SIE_MASK_EP0_INTR_MASK_Msk 0x4UL 1281 #define USBFS_USBLPM_INTR_SIE_MASK_LPM_INTR_MASK_Pos 3UL 1282 #define USBFS_USBLPM_INTR_SIE_MASK_LPM_INTR_MASK_Msk 0x8UL 1283 #define USBFS_USBLPM_INTR_SIE_MASK_RESUME_INTR_MASK_Pos 4UL 1284 #define USBFS_USBLPM_INTR_SIE_MASK_RESUME_INTR_MASK_Msk 0x10UL 1285 /* USBFS_USBLPM.INTR_SIE_MASKED */ 1286 #define USBFS_USBLPM_INTR_SIE_MASKED_SOF_INTR_MASKED_Pos 0UL 1287 #define USBFS_USBLPM_INTR_SIE_MASKED_SOF_INTR_MASKED_Msk 0x1UL 1288 #define USBFS_USBLPM_INTR_SIE_MASKED_BUS_RESET_INTR_MASKED_Pos 1UL 1289 #define USBFS_USBLPM_INTR_SIE_MASKED_BUS_RESET_INTR_MASKED_Msk 0x2UL 1290 #define USBFS_USBLPM_INTR_SIE_MASKED_EP0_INTR_MASKED_Pos 2UL 1291 #define USBFS_USBLPM_INTR_SIE_MASKED_EP0_INTR_MASKED_Msk 0x4UL 1292 #define USBFS_USBLPM_INTR_SIE_MASKED_LPM_INTR_MASKED_Pos 3UL 1293 #define USBFS_USBLPM_INTR_SIE_MASKED_LPM_INTR_MASKED_Msk 0x8UL 1294 #define USBFS_USBLPM_INTR_SIE_MASKED_RESUME_INTR_MASKED_Pos 4UL 1295 #define USBFS_USBLPM_INTR_SIE_MASKED_RESUME_INTR_MASKED_Msk 0x10UL 1296 /* USBFS_USBLPM.INTR_LVL_SEL */ 1297 #define USBFS_USBLPM_INTR_LVL_SEL_SOF_LVL_SEL_Pos 0UL 1298 #define USBFS_USBLPM_INTR_LVL_SEL_SOF_LVL_SEL_Msk 0x3UL 1299 #define USBFS_USBLPM_INTR_LVL_SEL_BUS_RESET_LVL_SEL_Pos 2UL 1300 #define USBFS_USBLPM_INTR_LVL_SEL_BUS_RESET_LVL_SEL_Msk 0xCUL 1301 #define USBFS_USBLPM_INTR_LVL_SEL_EP0_LVL_SEL_Pos 4UL 1302 #define USBFS_USBLPM_INTR_LVL_SEL_EP0_LVL_SEL_Msk 0x30UL 1303 #define USBFS_USBLPM_INTR_LVL_SEL_LPM_LVL_SEL_Pos 6UL 1304 #define USBFS_USBLPM_INTR_LVL_SEL_LPM_LVL_SEL_Msk 0xC0UL 1305 #define USBFS_USBLPM_INTR_LVL_SEL_RESUME_LVL_SEL_Pos 8UL 1306 #define USBFS_USBLPM_INTR_LVL_SEL_RESUME_LVL_SEL_Msk 0x300UL 1307 #define USBFS_USBLPM_INTR_LVL_SEL_ARB_EP_LVL_SEL_Pos 14UL 1308 #define USBFS_USBLPM_INTR_LVL_SEL_ARB_EP_LVL_SEL_Msk 0xC000UL 1309 #define USBFS_USBLPM_INTR_LVL_SEL_EP1_LVL_SEL_Pos 16UL 1310 #define USBFS_USBLPM_INTR_LVL_SEL_EP1_LVL_SEL_Msk 0x30000UL 1311 #define USBFS_USBLPM_INTR_LVL_SEL_EP2_LVL_SEL_Pos 18UL 1312 #define USBFS_USBLPM_INTR_LVL_SEL_EP2_LVL_SEL_Msk 0xC0000UL 1313 #define USBFS_USBLPM_INTR_LVL_SEL_EP3_LVL_SEL_Pos 20UL 1314 #define USBFS_USBLPM_INTR_LVL_SEL_EP3_LVL_SEL_Msk 0x300000UL 1315 #define USBFS_USBLPM_INTR_LVL_SEL_EP4_LVL_SEL_Pos 22UL 1316 #define USBFS_USBLPM_INTR_LVL_SEL_EP4_LVL_SEL_Msk 0xC00000UL 1317 #define USBFS_USBLPM_INTR_LVL_SEL_EP5_LVL_SEL_Pos 24UL 1318 #define USBFS_USBLPM_INTR_LVL_SEL_EP5_LVL_SEL_Msk 0x3000000UL 1319 #define USBFS_USBLPM_INTR_LVL_SEL_EP6_LVL_SEL_Pos 26UL 1320 #define USBFS_USBLPM_INTR_LVL_SEL_EP6_LVL_SEL_Msk 0xC000000UL 1321 #define USBFS_USBLPM_INTR_LVL_SEL_EP7_LVL_SEL_Pos 28UL 1322 #define USBFS_USBLPM_INTR_LVL_SEL_EP7_LVL_SEL_Msk 0x30000000UL 1323 #define USBFS_USBLPM_INTR_LVL_SEL_EP8_LVL_SEL_Pos 30UL 1324 #define USBFS_USBLPM_INTR_LVL_SEL_EP8_LVL_SEL_Msk 0xC0000000UL 1325 /* USBFS_USBLPM.INTR_CAUSE_HI */ 1326 #define USBFS_USBLPM_INTR_CAUSE_HI_SOF_INTR_Pos 0UL 1327 #define USBFS_USBLPM_INTR_CAUSE_HI_SOF_INTR_Msk 0x1UL 1328 #define USBFS_USBLPM_INTR_CAUSE_HI_BUS_RESET_INTR_Pos 1UL 1329 #define USBFS_USBLPM_INTR_CAUSE_HI_BUS_RESET_INTR_Msk 0x2UL 1330 #define USBFS_USBLPM_INTR_CAUSE_HI_EP0_INTR_Pos 2UL 1331 #define USBFS_USBLPM_INTR_CAUSE_HI_EP0_INTR_Msk 0x4UL 1332 #define USBFS_USBLPM_INTR_CAUSE_HI_LPM_INTR_Pos 3UL 1333 #define USBFS_USBLPM_INTR_CAUSE_HI_LPM_INTR_Msk 0x8UL 1334 #define USBFS_USBLPM_INTR_CAUSE_HI_RESUME_INTR_Pos 4UL 1335 #define USBFS_USBLPM_INTR_CAUSE_HI_RESUME_INTR_Msk 0x10UL 1336 #define USBFS_USBLPM_INTR_CAUSE_HI_ARB_EP_INTR_Pos 7UL 1337 #define USBFS_USBLPM_INTR_CAUSE_HI_ARB_EP_INTR_Msk 0x80UL 1338 #define USBFS_USBLPM_INTR_CAUSE_HI_EP1_INTR_Pos 8UL 1339 #define USBFS_USBLPM_INTR_CAUSE_HI_EP1_INTR_Msk 0x100UL 1340 #define USBFS_USBLPM_INTR_CAUSE_HI_EP2_INTR_Pos 9UL 1341 #define USBFS_USBLPM_INTR_CAUSE_HI_EP2_INTR_Msk 0x200UL 1342 #define USBFS_USBLPM_INTR_CAUSE_HI_EP3_INTR_Pos 10UL 1343 #define USBFS_USBLPM_INTR_CAUSE_HI_EP3_INTR_Msk 0x400UL 1344 #define USBFS_USBLPM_INTR_CAUSE_HI_EP4_INTR_Pos 11UL 1345 #define USBFS_USBLPM_INTR_CAUSE_HI_EP4_INTR_Msk 0x800UL 1346 #define USBFS_USBLPM_INTR_CAUSE_HI_EP5_INTR_Pos 12UL 1347 #define USBFS_USBLPM_INTR_CAUSE_HI_EP5_INTR_Msk 0x1000UL 1348 #define USBFS_USBLPM_INTR_CAUSE_HI_EP6_INTR_Pos 13UL 1349 #define USBFS_USBLPM_INTR_CAUSE_HI_EP6_INTR_Msk 0x2000UL 1350 #define USBFS_USBLPM_INTR_CAUSE_HI_EP7_INTR_Pos 14UL 1351 #define USBFS_USBLPM_INTR_CAUSE_HI_EP7_INTR_Msk 0x4000UL 1352 #define USBFS_USBLPM_INTR_CAUSE_HI_EP8_INTR_Pos 15UL 1353 #define USBFS_USBLPM_INTR_CAUSE_HI_EP8_INTR_Msk 0x8000UL 1354 /* USBFS_USBLPM.INTR_CAUSE_MED */ 1355 #define USBFS_USBLPM_INTR_CAUSE_MED_SOF_INTR_Pos 0UL 1356 #define USBFS_USBLPM_INTR_CAUSE_MED_SOF_INTR_Msk 0x1UL 1357 #define USBFS_USBLPM_INTR_CAUSE_MED_BUS_RESET_INTR_Pos 1UL 1358 #define USBFS_USBLPM_INTR_CAUSE_MED_BUS_RESET_INTR_Msk 0x2UL 1359 #define USBFS_USBLPM_INTR_CAUSE_MED_EP0_INTR_Pos 2UL 1360 #define USBFS_USBLPM_INTR_CAUSE_MED_EP0_INTR_Msk 0x4UL 1361 #define USBFS_USBLPM_INTR_CAUSE_MED_LPM_INTR_Pos 3UL 1362 #define USBFS_USBLPM_INTR_CAUSE_MED_LPM_INTR_Msk 0x8UL 1363 #define USBFS_USBLPM_INTR_CAUSE_MED_RESUME_INTR_Pos 4UL 1364 #define USBFS_USBLPM_INTR_CAUSE_MED_RESUME_INTR_Msk 0x10UL 1365 #define USBFS_USBLPM_INTR_CAUSE_MED_ARB_EP_INTR_Pos 7UL 1366 #define USBFS_USBLPM_INTR_CAUSE_MED_ARB_EP_INTR_Msk 0x80UL 1367 #define USBFS_USBLPM_INTR_CAUSE_MED_EP1_INTR_Pos 8UL 1368 #define USBFS_USBLPM_INTR_CAUSE_MED_EP1_INTR_Msk 0x100UL 1369 #define USBFS_USBLPM_INTR_CAUSE_MED_EP2_INTR_Pos 9UL 1370 #define USBFS_USBLPM_INTR_CAUSE_MED_EP2_INTR_Msk 0x200UL 1371 #define USBFS_USBLPM_INTR_CAUSE_MED_EP3_INTR_Pos 10UL 1372 #define USBFS_USBLPM_INTR_CAUSE_MED_EP3_INTR_Msk 0x400UL 1373 #define USBFS_USBLPM_INTR_CAUSE_MED_EP4_INTR_Pos 11UL 1374 #define USBFS_USBLPM_INTR_CAUSE_MED_EP4_INTR_Msk 0x800UL 1375 #define USBFS_USBLPM_INTR_CAUSE_MED_EP5_INTR_Pos 12UL 1376 #define USBFS_USBLPM_INTR_CAUSE_MED_EP5_INTR_Msk 0x1000UL 1377 #define USBFS_USBLPM_INTR_CAUSE_MED_EP6_INTR_Pos 13UL 1378 #define USBFS_USBLPM_INTR_CAUSE_MED_EP6_INTR_Msk 0x2000UL 1379 #define USBFS_USBLPM_INTR_CAUSE_MED_EP7_INTR_Pos 14UL 1380 #define USBFS_USBLPM_INTR_CAUSE_MED_EP7_INTR_Msk 0x4000UL 1381 #define USBFS_USBLPM_INTR_CAUSE_MED_EP8_INTR_Pos 15UL 1382 #define USBFS_USBLPM_INTR_CAUSE_MED_EP8_INTR_Msk 0x8000UL 1383 /* USBFS_USBLPM.INTR_CAUSE_LO */ 1384 #define USBFS_USBLPM_INTR_CAUSE_LO_SOF_INTR_Pos 0UL 1385 #define USBFS_USBLPM_INTR_CAUSE_LO_SOF_INTR_Msk 0x1UL 1386 #define USBFS_USBLPM_INTR_CAUSE_LO_BUS_RESET_INTR_Pos 1UL 1387 #define USBFS_USBLPM_INTR_CAUSE_LO_BUS_RESET_INTR_Msk 0x2UL 1388 #define USBFS_USBLPM_INTR_CAUSE_LO_EP0_INTR_Pos 2UL 1389 #define USBFS_USBLPM_INTR_CAUSE_LO_EP0_INTR_Msk 0x4UL 1390 #define USBFS_USBLPM_INTR_CAUSE_LO_LPM_INTR_Pos 3UL 1391 #define USBFS_USBLPM_INTR_CAUSE_LO_LPM_INTR_Msk 0x8UL 1392 #define USBFS_USBLPM_INTR_CAUSE_LO_RESUME_INTR_Pos 4UL 1393 #define USBFS_USBLPM_INTR_CAUSE_LO_RESUME_INTR_Msk 0x10UL 1394 #define USBFS_USBLPM_INTR_CAUSE_LO_ARB_EP_INTR_Pos 7UL 1395 #define USBFS_USBLPM_INTR_CAUSE_LO_ARB_EP_INTR_Msk 0x80UL 1396 #define USBFS_USBLPM_INTR_CAUSE_LO_EP1_INTR_Pos 8UL 1397 #define USBFS_USBLPM_INTR_CAUSE_LO_EP1_INTR_Msk 0x100UL 1398 #define USBFS_USBLPM_INTR_CAUSE_LO_EP2_INTR_Pos 9UL 1399 #define USBFS_USBLPM_INTR_CAUSE_LO_EP2_INTR_Msk 0x200UL 1400 #define USBFS_USBLPM_INTR_CAUSE_LO_EP3_INTR_Pos 10UL 1401 #define USBFS_USBLPM_INTR_CAUSE_LO_EP3_INTR_Msk 0x400UL 1402 #define USBFS_USBLPM_INTR_CAUSE_LO_EP4_INTR_Pos 11UL 1403 #define USBFS_USBLPM_INTR_CAUSE_LO_EP4_INTR_Msk 0x800UL 1404 #define USBFS_USBLPM_INTR_CAUSE_LO_EP5_INTR_Pos 12UL 1405 #define USBFS_USBLPM_INTR_CAUSE_LO_EP5_INTR_Msk 0x1000UL 1406 #define USBFS_USBLPM_INTR_CAUSE_LO_EP6_INTR_Pos 13UL 1407 #define USBFS_USBLPM_INTR_CAUSE_LO_EP6_INTR_Msk 0x2000UL 1408 #define USBFS_USBLPM_INTR_CAUSE_LO_EP7_INTR_Pos 14UL 1409 #define USBFS_USBLPM_INTR_CAUSE_LO_EP7_INTR_Msk 0x4000UL 1410 #define USBFS_USBLPM_INTR_CAUSE_LO_EP8_INTR_Pos 15UL 1411 #define USBFS_USBLPM_INTR_CAUSE_LO_EP8_INTR_Msk 0x8000UL 1412 /* USBFS_USBLPM.DFT_CTL */ 1413 #define USBFS_USBLPM_DFT_CTL_DDFT_OUT_SEL_Pos 0UL 1414 #define USBFS_USBLPM_DFT_CTL_DDFT_OUT_SEL_Msk 0x7UL 1415 #define USBFS_USBLPM_DFT_CTL_DDFT_IN_SEL_Pos 3UL 1416 #define USBFS_USBLPM_DFT_CTL_DDFT_IN_SEL_Msk 0x18UL 1417 1418 1419 /* USBFS_USBHOST.HOST_CTL0 */ 1420 #define USBFS_USBHOST_HOST_CTL0_HOST_Pos 0UL 1421 #define USBFS_USBHOST_HOST_CTL0_HOST_Msk 0x1UL 1422 #define USBFS_USBHOST_HOST_CTL0_ENABLE_Pos 31UL 1423 #define USBFS_USBHOST_HOST_CTL0_ENABLE_Msk 0x80000000UL 1424 /* USBFS_USBHOST.HOST_CTL1 */ 1425 #define USBFS_USBHOST_HOST_CTL1_CLKSEL_Pos 0UL 1426 #define USBFS_USBHOST_HOST_CTL1_CLKSEL_Msk 0x1UL 1427 #define USBFS_USBHOST_HOST_CTL1_USTP_Pos 1UL 1428 #define USBFS_USBHOST_HOST_CTL1_USTP_Msk 0x2UL 1429 #define USBFS_USBHOST_HOST_CTL1_RST_Pos 7UL 1430 #define USBFS_USBHOST_HOST_CTL1_RST_Msk 0x80UL 1431 /* USBFS_USBHOST.HOST_CTL2 */ 1432 #define USBFS_USBHOST_HOST_CTL2_RETRY_Pos 0UL 1433 #define USBFS_USBHOST_HOST_CTL2_RETRY_Msk 0x1UL 1434 #define USBFS_USBHOST_HOST_CTL2_CANCEL_Pos 1UL 1435 #define USBFS_USBHOST_HOST_CTL2_CANCEL_Msk 0x2UL 1436 #define USBFS_USBHOST_HOST_CTL2_SOFSTEP_Pos 2UL 1437 #define USBFS_USBHOST_HOST_CTL2_SOFSTEP_Msk 0x4UL 1438 #define USBFS_USBHOST_HOST_CTL2_ALIVE_Pos 3UL 1439 #define USBFS_USBHOST_HOST_CTL2_ALIVE_Msk 0x8UL 1440 #define USBFS_USBHOST_HOST_CTL2_RESERVED_4_Pos 4UL 1441 #define USBFS_USBHOST_HOST_CTL2_RESERVED_4_Msk 0x10UL 1442 #define USBFS_USBHOST_HOST_CTL2_RESERVED_5_Pos 5UL 1443 #define USBFS_USBHOST_HOST_CTL2_RESERVED_5_Msk 0x20UL 1444 #define USBFS_USBHOST_HOST_CTL2_TTEST_Pos 6UL 1445 #define USBFS_USBHOST_HOST_CTL2_TTEST_Msk 0xC0UL 1446 /* USBFS_USBHOST.HOST_ERR */ 1447 #define USBFS_USBHOST_HOST_ERR_HS_Pos 0UL 1448 #define USBFS_USBHOST_HOST_ERR_HS_Msk 0x3UL 1449 #define USBFS_USBHOST_HOST_ERR_STUFF_Pos 2UL 1450 #define USBFS_USBHOST_HOST_ERR_STUFF_Msk 0x4UL 1451 #define USBFS_USBHOST_HOST_ERR_TGERR_Pos 3UL 1452 #define USBFS_USBHOST_HOST_ERR_TGERR_Msk 0x8UL 1453 #define USBFS_USBHOST_HOST_ERR_CRC_Pos 4UL 1454 #define USBFS_USBHOST_HOST_ERR_CRC_Msk 0x10UL 1455 #define USBFS_USBHOST_HOST_ERR_TOUT_Pos 5UL 1456 #define USBFS_USBHOST_HOST_ERR_TOUT_Msk 0x20UL 1457 #define USBFS_USBHOST_HOST_ERR_RERR_Pos 6UL 1458 #define USBFS_USBHOST_HOST_ERR_RERR_Msk 0x40UL 1459 #define USBFS_USBHOST_HOST_ERR_LSTSOF_Pos 7UL 1460 #define USBFS_USBHOST_HOST_ERR_LSTSOF_Msk 0x80UL 1461 /* USBFS_USBHOST.HOST_STATUS */ 1462 #define USBFS_USBHOST_HOST_STATUS_CSTAT_Pos 0UL 1463 #define USBFS_USBHOST_HOST_STATUS_CSTAT_Msk 0x1UL 1464 #define USBFS_USBHOST_HOST_STATUS_TMODE_Pos 1UL 1465 #define USBFS_USBHOST_HOST_STATUS_TMODE_Msk 0x2UL 1466 #define USBFS_USBHOST_HOST_STATUS_SUSP_Pos 2UL 1467 #define USBFS_USBHOST_HOST_STATUS_SUSP_Msk 0x4UL 1468 #define USBFS_USBHOST_HOST_STATUS_SOFBUSY_Pos 3UL 1469 #define USBFS_USBHOST_HOST_STATUS_SOFBUSY_Msk 0x8UL 1470 #define USBFS_USBHOST_HOST_STATUS_URST_Pos 4UL 1471 #define USBFS_USBHOST_HOST_STATUS_URST_Msk 0x10UL 1472 #define USBFS_USBHOST_HOST_STATUS_RESERVED_5_Pos 5UL 1473 #define USBFS_USBHOST_HOST_STATUS_RESERVED_5_Msk 0x20UL 1474 #define USBFS_USBHOST_HOST_STATUS_RSTBUSY_Pos 6UL 1475 #define USBFS_USBHOST_HOST_STATUS_RSTBUSY_Msk 0x40UL 1476 #define USBFS_USBHOST_HOST_STATUS_CLKSEL_ST_Pos 7UL 1477 #define USBFS_USBHOST_HOST_STATUS_CLKSEL_ST_Msk 0x80UL 1478 #define USBFS_USBHOST_HOST_STATUS_HOST_ST_Pos 8UL 1479 #define USBFS_USBHOST_HOST_STATUS_HOST_ST_Msk 0x100UL 1480 /* USBFS_USBHOST.HOST_FCOMP */ 1481 #define USBFS_USBHOST_HOST_FCOMP_FRAMECOMP_Pos 0UL 1482 #define USBFS_USBHOST_HOST_FCOMP_FRAMECOMP_Msk 0xFFUL 1483 /* USBFS_USBHOST.HOST_RTIMER */ 1484 #define USBFS_USBHOST_HOST_RTIMER_RTIMER_Pos 0UL 1485 #define USBFS_USBHOST_HOST_RTIMER_RTIMER_Msk 0x3FFFFUL 1486 /* USBFS_USBHOST.HOST_ADDR */ 1487 #define USBFS_USBHOST_HOST_ADDR_ADDRESS_Pos 0UL 1488 #define USBFS_USBHOST_HOST_ADDR_ADDRESS_Msk 0x7FUL 1489 /* USBFS_USBHOST.HOST_EOF */ 1490 #define USBFS_USBHOST_HOST_EOF_EOF_Pos 0UL 1491 #define USBFS_USBHOST_HOST_EOF_EOF_Msk 0x3FFFUL 1492 /* USBFS_USBHOST.HOST_FRAME */ 1493 #define USBFS_USBHOST_HOST_FRAME_FRAME_Pos 0UL 1494 #define USBFS_USBHOST_HOST_FRAME_FRAME_Msk 0x7FFUL 1495 /* USBFS_USBHOST.HOST_TOKEN */ 1496 #define USBFS_USBHOST_HOST_TOKEN_ENDPT_Pos 0UL 1497 #define USBFS_USBHOST_HOST_TOKEN_ENDPT_Msk 0xFUL 1498 #define USBFS_USBHOST_HOST_TOKEN_TKNEN_Pos 4UL 1499 #define USBFS_USBHOST_HOST_TOKEN_TKNEN_Msk 0x70UL 1500 #define USBFS_USBHOST_HOST_TOKEN_TGGL_Pos 8UL 1501 #define USBFS_USBHOST_HOST_TOKEN_TGGL_Msk 0x100UL 1502 /* USBFS_USBHOST.HOST_EP1_CTL */ 1503 #define USBFS_USBHOST_HOST_EP1_CTL_PKS1_Pos 0UL 1504 #define USBFS_USBHOST_HOST_EP1_CTL_PKS1_Msk 0x1FFUL 1505 #define USBFS_USBHOST_HOST_EP1_CTL_NULLE_Pos 10UL 1506 #define USBFS_USBHOST_HOST_EP1_CTL_NULLE_Msk 0x400UL 1507 #define USBFS_USBHOST_HOST_EP1_CTL_DMAE_Pos 11UL 1508 #define USBFS_USBHOST_HOST_EP1_CTL_DMAE_Msk 0x800UL 1509 #define USBFS_USBHOST_HOST_EP1_CTL_DIR_Pos 12UL 1510 #define USBFS_USBHOST_HOST_EP1_CTL_DIR_Msk 0x1000UL 1511 #define USBFS_USBHOST_HOST_EP1_CTL_BFINI_Pos 15UL 1512 #define USBFS_USBHOST_HOST_EP1_CTL_BFINI_Msk 0x8000UL 1513 /* USBFS_USBHOST.HOST_EP1_STATUS */ 1514 #define USBFS_USBHOST_HOST_EP1_STATUS_SIZE1_Pos 0UL 1515 #define USBFS_USBHOST_HOST_EP1_STATUS_SIZE1_Msk 0x1FFUL 1516 #define USBFS_USBHOST_HOST_EP1_STATUS_VAL_DATA_Pos 16UL 1517 #define USBFS_USBHOST_HOST_EP1_STATUS_VAL_DATA_Msk 0x10000UL 1518 #define USBFS_USBHOST_HOST_EP1_STATUS_INI_ST_Pos 17UL 1519 #define USBFS_USBHOST_HOST_EP1_STATUS_INI_ST_Msk 0x20000UL 1520 #define USBFS_USBHOST_HOST_EP1_STATUS_RESERVED_18_Pos 18UL 1521 #define USBFS_USBHOST_HOST_EP1_STATUS_RESERVED_18_Msk 0x40000UL 1522 /* USBFS_USBHOST.HOST_EP1_RW1_DR */ 1523 #define USBFS_USBHOST_HOST_EP1_RW1_DR_BFDT8_Pos 0UL 1524 #define USBFS_USBHOST_HOST_EP1_RW1_DR_BFDT8_Msk 0xFFUL 1525 /* USBFS_USBHOST.HOST_EP1_RW2_DR */ 1526 #define USBFS_USBHOST_HOST_EP1_RW2_DR_BFDT16_Pos 0UL 1527 #define USBFS_USBHOST_HOST_EP1_RW2_DR_BFDT16_Msk 0xFFFFUL 1528 /* USBFS_USBHOST.HOST_EP2_CTL */ 1529 #define USBFS_USBHOST_HOST_EP2_CTL_PKS2_Pos 0UL 1530 #define USBFS_USBHOST_HOST_EP2_CTL_PKS2_Msk 0x7FUL 1531 #define USBFS_USBHOST_HOST_EP2_CTL_NULLE_Pos 10UL 1532 #define USBFS_USBHOST_HOST_EP2_CTL_NULLE_Msk 0x400UL 1533 #define USBFS_USBHOST_HOST_EP2_CTL_DMAE_Pos 11UL 1534 #define USBFS_USBHOST_HOST_EP2_CTL_DMAE_Msk 0x800UL 1535 #define USBFS_USBHOST_HOST_EP2_CTL_DIR_Pos 12UL 1536 #define USBFS_USBHOST_HOST_EP2_CTL_DIR_Msk 0x1000UL 1537 #define USBFS_USBHOST_HOST_EP2_CTL_BFINI_Pos 15UL 1538 #define USBFS_USBHOST_HOST_EP2_CTL_BFINI_Msk 0x8000UL 1539 /* USBFS_USBHOST.HOST_EP2_STATUS */ 1540 #define USBFS_USBHOST_HOST_EP2_STATUS_SIZE2_Pos 0UL 1541 #define USBFS_USBHOST_HOST_EP2_STATUS_SIZE2_Msk 0x7FUL 1542 #define USBFS_USBHOST_HOST_EP2_STATUS_VAL_DATA_Pos 16UL 1543 #define USBFS_USBHOST_HOST_EP2_STATUS_VAL_DATA_Msk 0x10000UL 1544 #define USBFS_USBHOST_HOST_EP2_STATUS_INI_ST_Pos 17UL 1545 #define USBFS_USBHOST_HOST_EP2_STATUS_INI_ST_Msk 0x20000UL 1546 #define USBFS_USBHOST_HOST_EP2_STATUS_RESERVED_18_Pos 18UL 1547 #define USBFS_USBHOST_HOST_EP2_STATUS_RESERVED_18_Msk 0x40000UL 1548 /* USBFS_USBHOST.HOST_EP2_RW1_DR */ 1549 #define USBFS_USBHOST_HOST_EP2_RW1_DR_BFDT8_Pos 0UL 1550 #define USBFS_USBHOST_HOST_EP2_RW1_DR_BFDT8_Msk 0xFFUL 1551 /* USBFS_USBHOST.HOST_EP2_RW2_DR */ 1552 #define USBFS_USBHOST_HOST_EP2_RW2_DR_BFDT16_Pos 0UL 1553 #define USBFS_USBHOST_HOST_EP2_RW2_DR_BFDT16_Msk 0xFFFFUL 1554 /* USBFS_USBHOST.HOST_LVL1_SEL */ 1555 #define USBFS_USBHOST_HOST_LVL1_SEL_SOFIRQ_SEL_Pos 0UL 1556 #define USBFS_USBHOST_HOST_LVL1_SEL_SOFIRQ_SEL_Msk 0x3UL 1557 #define USBFS_USBHOST_HOST_LVL1_SEL_DIRQ_SEL_Pos 2UL 1558 #define USBFS_USBHOST_HOST_LVL1_SEL_DIRQ_SEL_Msk 0xCUL 1559 #define USBFS_USBHOST_HOST_LVL1_SEL_CNNIRQ_SEL_Pos 4UL 1560 #define USBFS_USBHOST_HOST_LVL1_SEL_CNNIRQ_SEL_Msk 0x30UL 1561 #define USBFS_USBHOST_HOST_LVL1_SEL_CMPIRQ_SEL_Pos 6UL 1562 #define USBFS_USBHOST_HOST_LVL1_SEL_CMPIRQ_SEL_Msk 0xC0UL 1563 #define USBFS_USBHOST_HOST_LVL1_SEL_URIRQ_SEL_Pos 8UL 1564 #define USBFS_USBHOST_HOST_LVL1_SEL_URIRQ_SEL_Msk 0x300UL 1565 #define USBFS_USBHOST_HOST_LVL1_SEL_RWKIRQ_SEL_Pos 10UL 1566 #define USBFS_USBHOST_HOST_LVL1_SEL_RWKIRQ_SEL_Msk 0xC00UL 1567 #define USBFS_USBHOST_HOST_LVL1_SEL_RESERVED_13_12_Pos 12UL 1568 #define USBFS_USBHOST_HOST_LVL1_SEL_RESERVED_13_12_Msk 0x3000UL 1569 #define USBFS_USBHOST_HOST_LVL1_SEL_TCAN_SEL_Pos 14UL 1570 #define USBFS_USBHOST_HOST_LVL1_SEL_TCAN_SEL_Msk 0xC000UL 1571 /* USBFS_USBHOST.HOST_LVL2_SEL */ 1572 #define USBFS_USBHOST_HOST_LVL2_SEL_EP1_DRQ_SEL_Pos 4UL 1573 #define USBFS_USBHOST_HOST_LVL2_SEL_EP1_DRQ_SEL_Msk 0x30UL 1574 #define USBFS_USBHOST_HOST_LVL2_SEL_EP1_SPK_SEL_Pos 6UL 1575 #define USBFS_USBHOST_HOST_LVL2_SEL_EP1_SPK_SEL_Msk 0xC0UL 1576 #define USBFS_USBHOST_HOST_LVL2_SEL_EP2_DRQ_SEL_Pos 8UL 1577 #define USBFS_USBHOST_HOST_LVL2_SEL_EP2_DRQ_SEL_Msk 0x300UL 1578 #define USBFS_USBHOST_HOST_LVL2_SEL_EP2_SPK_SEL_Pos 10UL 1579 #define USBFS_USBHOST_HOST_LVL2_SEL_EP2_SPK_SEL_Msk 0xC00UL 1580 /* USBFS_USBHOST.INTR_USBHOST_CAUSE_HI */ 1581 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_SOFIRQ_INT_Pos 0UL 1582 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_SOFIRQ_INT_Msk 0x1UL 1583 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_DIRQ_INT_Pos 1UL 1584 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_DIRQ_INT_Msk 0x2UL 1585 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_CNNIRQ_INT_Pos 2UL 1586 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_CNNIRQ_INT_Msk 0x4UL 1587 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_CMPIRQ_INT_Pos 3UL 1588 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_CMPIRQ_INT_Msk 0x8UL 1589 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_URIRQ_INT_Pos 4UL 1590 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_URIRQ_INT_Msk 0x10UL 1591 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_RWKIRQ_INT_Pos 5UL 1592 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_RWKIRQ_INT_Msk 0x20UL 1593 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_RESERVED_6_Pos 6UL 1594 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_RESERVED_6_Msk 0x40UL 1595 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_TCAN_INT_Pos 7UL 1596 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_HI_TCAN_INT_Msk 0x80UL 1597 /* USBFS_USBHOST.INTR_USBHOST_CAUSE_MED */ 1598 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_SOFIRQ_INT_Pos 0UL 1599 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_SOFIRQ_INT_Msk 0x1UL 1600 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_DIRQ_INT_Pos 1UL 1601 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_DIRQ_INT_Msk 0x2UL 1602 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_CNNIRQ_INT_Pos 2UL 1603 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_CNNIRQ_INT_Msk 0x4UL 1604 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_CMPIRQ_INT_Pos 3UL 1605 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_CMPIRQ_INT_Msk 0x8UL 1606 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_URIRQ_INT_Pos 4UL 1607 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_URIRQ_INT_Msk 0x10UL 1608 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_RWKIRQ_INT_Pos 5UL 1609 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_RWKIRQ_INT_Msk 0x20UL 1610 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_RESERVED_6_Pos 6UL 1611 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_RESERVED_6_Msk 0x40UL 1612 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_TCAN_INT_Pos 7UL 1613 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_MED_TCAN_INT_Msk 0x80UL 1614 /* USBFS_USBHOST.INTR_USBHOST_CAUSE_LO */ 1615 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_SOFIRQ_INT_Pos 0UL 1616 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_SOFIRQ_INT_Msk 0x1UL 1617 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_DIRQ_INT_Pos 1UL 1618 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_DIRQ_INT_Msk 0x2UL 1619 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_CNNIRQ_INT_Pos 2UL 1620 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_CNNIRQ_INT_Msk 0x4UL 1621 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_CMPIRQ_INT_Pos 3UL 1622 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_CMPIRQ_INT_Msk 0x8UL 1623 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_URIRQ_INT_Pos 4UL 1624 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_URIRQ_INT_Msk 0x10UL 1625 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_RWKIRQ_INT_Pos 5UL 1626 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_RWKIRQ_INT_Msk 0x20UL 1627 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_RESERVED_6_Pos 6UL 1628 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_RESERVED_6_Msk 0x40UL 1629 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_TCAN_INT_Pos 7UL 1630 #define USBFS_USBHOST_INTR_USBHOST_CAUSE_LO_TCAN_INT_Msk 0x80UL 1631 /* USBFS_USBHOST.INTR_HOST_EP_CAUSE_HI */ 1632 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP1DRQ_INT_Pos 2UL 1633 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP1DRQ_INT_Msk 0x4UL 1634 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP1SPK_INT_Pos 3UL 1635 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP1SPK_INT_Msk 0x8UL 1636 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP2DRQ_INT_Pos 4UL 1637 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP2DRQ_INT_Msk 0x10UL 1638 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP2SPK_INT_Pos 5UL 1639 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_HI_EP2SPK_INT_Msk 0x20UL 1640 /* USBFS_USBHOST.INTR_HOST_EP_CAUSE_MED */ 1641 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP1DRQ_INT_Pos 2UL 1642 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP1DRQ_INT_Msk 0x4UL 1643 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP1SPK_INT_Pos 3UL 1644 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP1SPK_INT_Msk 0x8UL 1645 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP2DRQ_INT_Pos 4UL 1646 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP2DRQ_INT_Msk 0x10UL 1647 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP2SPK_INT_Pos 5UL 1648 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_MED_EP2SPK_INT_Msk 0x20UL 1649 /* USBFS_USBHOST.INTR_HOST_EP_CAUSE_LO */ 1650 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP1DRQ_INT_Pos 2UL 1651 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP1DRQ_INT_Msk 0x4UL 1652 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP1SPK_INT_Pos 3UL 1653 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP1SPK_INT_Msk 0x8UL 1654 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP2DRQ_INT_Pos 4UL 1655 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP2DRQ_INT_Msk 0x10UL 1656 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP2SPK_INT_Pos 5UL 1657 #define USBFS_USBHOST_INTR_HOST_EP_CAUSE_LO_EP2SPK_INT_Msk 0x20UL 1658 /* USBFS_USBHOST.INTR_USBHOST */ 1659 #define USBFS_USBHOST_INTR_USBHOST_SOFIRQ_Pos 0UL 1660 #define USBFS_USBHOST_INTR_USBHOST_SOFIRQ_Msk 0x1UL 1661 #define USBFS_USBHOST_INTR_USBHOST_DIRQ_Pos 1UL 1662 #define USBFS_USBHOST_INTR_USBHOST_DIRQ_Msk 0x2UL 1663 #define USBFS_USBHOST_INTR_USBHOST_CNNIRQ_Pos 2UL 1664 #define USBFS_USBHOST_INTR_USBHOST_CNNIRQ_Msk 0x4UL 1665 #define USBFS_USBHOST_INTR_USBHOST_CMPIRQ_Pos 3UL 1666 #define USBFS_USBHOST_INTR_USBHOST_CMPIRQ_Msk 0x8UL 1667 #define USBFS_USBHOST_INTR_USBHOST_URIRQ_Pos 4UL 1668 #define USBFS_USBHOST_INTR_USBHOST_URIRQ_Msk 0x10UL 1669 #define USBFS_USBHOST_INTR_USBHOST_RWKIRQ_Pos 5UL 1670 #define USBFS_USBHOST_INTR_USBHOST_RWKIRQ_Msk 0x20UL 1671 #define USBFS_USBHOST_INTR_USBHOST_RESERVED_6_Pos 6UL 1672 #define USBFS_USBHOST_INTR_USBHOST_RESERVED_6_Msk 0x40UL 1673 #define USBFS_USBHOST_INTR_USBHOST_TCAN_Pos 7UL 1674 #define USBFS_USBHOST_INTR_USBHOST_TCAN_Msk 0x80UL 1675 /* USBFS_USBHOST.INTR_USBHOST_SET */ 1676 #define USBFS_USBHOST_INTR_USBHOST_SET_SOFIRQS_Pos 0UL 1677 #define USBFS_USBHOST_INTR_USBHOST_SET_SOFIRQS_Msk 0x1UL 1678 #define USBFS_USBHOST_INTR_USBHOST_SET_DIRQS_Pos 1UL 1679 #define USBFS_USBHOST_INTR_USBHOST_SET_DIRQS_Msk 0x2UL 1680 #define USBFS_USBHOST_INTR_USBHOST_SET_CNNIRQS_Pos 2UL 1681 #define USBFS_USBHOST_INTR_USBHOST_SET_CNNIRQS_Msk 0x4UL 1682 #define USBFS_USBHOST_INTR_USBHOST_SET_CMPIRQS_Pos 3UL 1683 #define USBFS_USBHOST_INTR_USBHOST_SET_CMPIRQS_Msk 0x8UL 1684 #define USBFS_USBHOST_INTR_USBHOST_SET_URIRQS_Pos 4UL 1685 #define USBFS_USBHOST_INTR_USBHOST_SET_URIRQS_Msk 0x10UL 1686 #define USBFS_USBHOST_INTR_USBHOST_SET_RWKIRQS_Pos 5UL 1687 #define USBFS_USBHOST_INTR_USBHOST_SET_RWKIRQS_Msk 0x20UL 1688 #define USBFS_USBHOST_INTR_USBHOST_SET_RESERVED_6_Pos 6UL 1689 #define USBFS_USBHOST_INTR_USBHOST_SET_RESERVED_6_Msk 0x40UL 1690 #define USBFS_USBHOST_INTR_USBHOST_SET_TCANS_Pos 7UL 1691 #define USBFS_USBHOST_INTR_USBHOST_SET_TCANS_Msk 0x80UL 1692 /* USBFS_USBHOST.INTR_USBHOST_MASK */ 1693 #define USBFS_USBHOST_INTR_USBHOST_MASK_SOFIRQM_Pos 0UL 1694 #define USBFS_USBHOST_INTR_USBHOST_MASK_SOFIRQM_Msk 0x1UL 1695 #define USBFS_USBHOST_INTR_USBHOST_MASK_DIRQM_Pos 1UL 1696 #define USBFS_USBHOST_INTR_USBHOST_MASK_DIRQM_Msk 0x2UL 1697 #define USBFS_USBHOST_INTR_USBHOST_MASK_CNNIRQM_Pos 2UL 1698 #define USBFS_USBHOST_INTR_USBHOST_MASK_CNNIRQM_Msk 0x4UL 1699 #define USBFS_USBHOST_INTR_USBHOST_MASK_CMPIRQM_Pos 3UL 1700 #define USBFS_USBHOST_INTR_USBHOST_MASK_CMPIRQM_Msk 0x8UL 1701 #define USBFS_USBHOST_INTR_USBHOST_MASK_URIRQM_Pos 4UL 1702 #define USBFS_USBHOST_INTR_USBHOST_MASK_URIRQM_Msk 0x10UL 1703 #define USBFS_USBHOST_INTR_USBHOST_MASK_RWKIRQM_Pos 5UL 1704 #define USBFS_USBHOST_INTR_USBHOST_MASK_RWKIRQM_Msk 0x20UL 1705 #define USBFS_USBHOST_INTR_USBHOST_MASK_RESERVED_6_Pos 6UL 1706 #define USBFS_USBHOST_INTR_USBHOST_MASK_RESERVED_6_Msk 0x40UL 1707 #define USBFS_USBHOST_INTR_USBHOST_MASK_TCANM_Pos 7UL 1708 #define USBFS_USBHOST_INTR_USBHOST_MASK_TCANM_Msk 0x80UL 1709 /* USBFS_USBHOST.INTR_USBHOST_MASKED */ 1710 #define USBFS_USBHOST_INTR_USBHOST_MASKED_SOFIRQED_Pos 0UL 1711 #define USBFS_USBHOST_INTR_USBHOST_MASKED_SOFIRQED_Msk 0x1UL 1712 #define USBFS_USBHOST_INTR_USBHOST_MASKED_DIRQED_Pos 1UL 1713 #define USBFS_USBHOST_INTR_USBHOST_MASKED_DIRQED_Msk 0x2UL 1714 #define USBFS_USBHOST_INTR_USBHOST_MASKED_CNNIRQED_Pos 2UL 1715 #define USBFS_USBHOST_INTR_USBHOST_MASKED_CNNIRQED_Msk 0x4UL 1716 #define USBFS_USBHOST_INTR_USBHOST_MASKED_CMPIRQED_Pos 3UL 1717 #define USBFS_USBHOST_INTR_USBHOST_MASKED_CMPIRQED_Msk 0x8UL 1718 #define USBFS_USBHOST_INTR_USBHOST_MASKED_URIRQED_Pos 4UL 1719 #define USBFS_USBHOST_INTR_USBHOST_MASKED_URIRQED_Msk 0x10UL 1720 #define USBFS_USBHOST_INTR_USBHOST_MASKED_RWKIRQED_Pos 5UL 1721 #define USBFS_USBHOST_INTR_USBHOST_MASKED_RWKIRQED_Msk 0x20UL 1722 #define USBFS_USBHOST_INTR_USBHOST_MASKED_RESERVED_6_Pos 6UL 1723 #define USBFS_USBHOST_INTR_USBHOST_MASKED_RESERVED_6_Msk 0x40UL 1724 #define USBFS_USBHOST_INTR_USBHOST_MASKED_TCANED_Pos 7UL 1725 #define USBFS_USBHOST_INTR_USBHOST_MASKED_TCANED_Msk 0x80UL 1726 /* USBFS_USBHOST.INTR_HOST_EP */ 1727 #define USBFS_USBHOST_INTR_HOST_EP_EP1DRQ_Pos 2UL 1728 #define USBFS_USBHOST_INTR_HOST_EP_EP1DRQ_Msk 0x4UL 1729 #define USBFS_USBHOST_INTR_HOST_EP_EP1SPK_Pos 3UL 1730 #define USBFS_USBHOST_INTR_HOST_EP_EP1SPK_Msk 0x8UL 1731 #define USBFS_USBHOST_INTR_HOST_EP_EP2DRQ_Pos 4UL 1732 #define USBFS_USBHOST_INTR_HOST_EP_EP2DRQ_Msk 0x10UL 1733 #define USBFS_USBHOST_INTR_HOST_EP_EP2SPK_Pos 5UL 1734 #define USBFS_USBHOST_INTR_HOST_EP_EP2SPK_Msk 0x20UL 1735 /* USBFS_USBHOST.INTR_HOST_EP_SET */ 1736 #define USBFS_USBHOST_INTR_HOST_EP_SET_EP1DRQS_Pos 2UL 1737 #define USBFS_USBHOST_INTR_HOST_EP_SET_EP1DRQS_Msk 0x4UL 1738 #define USBFS_USBHOST_INTR_HOST_EP_SET_EP1SPKS_Pos 3UL 1739 #define USBFS_USBHOST_INTR_HOST_EP_SET_EP1SPKS_Msk 0x8UL 1740 #define USBFS_USBHOST_INTR_HOST_EP_SET_EP2DRQS_Pos 4UL 1741 #define USBFS_USBHOST_INTR_HOST_EP_SET_EP2DRQS_Msk 0x10UL 1742 #define USBFS_USBHOST_INTR_HOST_EP_SET_EP2SPKS_Pos 5UL 1743 #define USBFS_USBHOST_INTR_HOST_EP_SET_EP2SPKS_Msk 0x20UL 1744 /* USBFS_USBHOST.INTR_HOST_EP_MASK */ 1745 #define USBFS_USBHOST_INTR_HOST_EP_MASK_EP1DRQM_Pos 2UL 1746 #define USBFS_USBHOST_INTR_HOST_EP_MASK_EP1DRQM_Msk 0x4UL 1747 #define USBFS_USBHOST_INTR_HOST_EP_MASK_EP1SPKM_Pos 3UL 1748 #define USBFS_USBHOST_INTR_HOST_EP_MASK_EP1SPKM_Msk 0x8UL 1749 #define USBFS_USBHOST_INTR_HOST_EP_MASK_EP2DRQM_Pos 4UL 1750 #define USBFS_USBHOST_INTR_HOST_EP_MASK_EP2DRQM_Msk 0x10UL 1751 #define USBFS_USBHOST_INTR_HOST_EP_MASK_EP2SPKM_Pos 5UL 1752 #define USBFS_USBHOST_INTR_HOST_EP_MASK_EP2SPKM_Msk 0x20UL 1753 /* USBFS_USBHOST.INTR_HOST_EP_MASKED */ 1754 #define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP1DRQED_Pos 2UL 1755 #define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP1DRQED_Msk 0x4UL 1756 #define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP1SPKED_Pos 3UL 1757 #define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP1SPKED_Msk 0x8UL 1758 #define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP2DRQED_Pos 4UL 1759 #define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP2DRQED_Msk 0x10UL 1760 #define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP2SPKED_Pos 5UL 1761 #define USBFS_USBHOST_INTR_HOST_EP_MASKED_EP2SPKED_Msk 0x20UL 1762 /* USBFS_USBHOST.HOST_DMA_ENBL */ 1763 #define USBFS_USBHOST_HOST_DMA_ENBL_DM_EP1DRQE_Pos 2UL 1764 #define USBFS_USBHOST_HOST_DMA_ENBL_DM_EP1DRQE_Msk 0x4UL 1765 #define USBFS_USBHOST_HOST_DMA_ENBL_DM_EP2DRQE_Pos 3UL 1766 #define USBFS_USBHOST_HOST_DMA_ENBL_DM_EP2DRQE_Msk 0x8UL 1767 /* USBFS_USBHOST.HOST_EP1_BLK */ 1768 #define USBFS_USBHOST_HOST_EP1_BLK_BLK_NUM_Pos 16UL 1769 #define USBFS_USBHOST_HOST_EP1_BLK_BLK_NUM_Msk 0xFFFF0000UL 1770 /* USBFS_USBHOST.HOST_EP2_BLK */ 1771 #define USBFS_USBHOST_HOST_EP2_BLK_BLK_NUM_Pos 16UL 1772 #define USBFS_USBHOST_HOST_EP2_BLK_BLK_NUM_Msk 0xFFFF0000UL 1773 1774 1775 #endif /* _CYIP_USBFS_H_ */ 1776 1777 1778 /* [] END OF FILE */ 1779
