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Searched refs:TRIG_OUT_MUX_0_PDMA0_TR_IN5 (Results 1 – 5 of 5) sorted by relevance

/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dpsoc6_04_config.h847 TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ enumerator
Dpsoc6_03_config.h897 TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ enumerator
Dpsoc6_02_config.h1344 TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ enumerator
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dxmc7100_config.h1254 TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ enumerator
Dxmc7200_config.h1672 TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ enumerator