1 /***************************************************************************//** 2 * \file cyip_srss.h 3 * 4 * \brief 5 * SRSS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_SRSS_H_ 28 #define _CYIP_SRSS_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * SRSS 34 *******************************************************************************/ 35 36 #define CSV_HF_CSV_SECTION_SIZE 0x00000010UL 37 #define CSV_HF_SECTION_SIZE 0x00000100UL 38 #define CSV_REF_CSV_SECTION_SIZE 0x00000010UL 39 #define CSV_REF_SECTION_SIZE 0x00000010UL 40 #define CSV_LF_CSV_SECTION_SIZE 0x00000010UL 41 #define CSV_LF_SECTION_SIZE 0x00000010UL 42 #define CSV_ILO_CSV_SECTION_SIZE 0x00000010UL 43 #define CSV_ILO_SECTION_SIZE 0x00000010UL 44 #define CLK_PLL400M_SECTION_SIZE 0x00000010UL 45 #define CLK_DPLL_LP_SECTION_SIZE 0x00000020UL 46 #define RAM_TRIM_SECTION_SIZE 0x00000008UL 47 #define MCWDT_STRUCT_SECTION_SIZE 0x00000040UL 48 #define SRSS_SECTION_SIZE 0x00010000UL 49 50 /** 51 * \brief Active domain Clock Supervisor (CSV) registers (CSV_HF_CSV) 52 */ 53 typedef struct { 54 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 55 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 56 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 57 __IM uint32_t RESERVED; 58 } CSV_HF_CSV_Type; /*!< Size = 16 (0x10) */ 59 60 /** 61 * \brief Clock Supervisor (CSV) registers for Root clocks (CSV_HF) 62 */ 63 typedef struct { 64 CSV_HF_CSV_Type CSV[16]; /*!< 0x00000000 Active domain Clock Supervisor (CSV) registers */ 65 } CSV_HF_Type; /*!< Size = 256 (0x100) */ 66 67 /** 68 * \brief Active domain Clock Supervisor (CSV) registers for CSV Reference clock (CSV_REF_CSV) 69 */ 70 typedef struct { 71 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 72 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 73 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 74 __IM uint32_t RESERVED; 75 } CSV_REF_CSV_Type; /*!< Size = 16 (0x10) */ 76 77 /** 78 * \brief CSV registers for the CSV Reference clock (CSV_REF) 79 */ 80 typedef struct { 81 CSV_REF_CSV_Type CSV; /*!< 0x00000000 Active domain Clock Supervisor (CSV) registers for CSV 82 Reference clock */ 83 } CSV_REF_Type; /*!< Size = 16 (0x10) */ 84 85 /** 86 * \brief LF clock Clock Supervisor registers (CSV_LF_CSV) 87 */ 88 typedef struct { 89 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 90 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 91 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 92 __IM uint32_t RESERVED; 93 } CSV_LF_CSV_Type; /*!< Size = 16 (0x10) */ 94 95 /** 96 * \brief CSV registers for LF clock (CSV_LF) 97 */ 98 typedef struct { 99 CSV_LF_CSV_Type CSV; /*!< 0x00000000 LF clock Clock Supervisor registers */ 100 } CSV_LF_Type; /*!< Size = 16 (0x10) */ 101 102 /** 103 * \brief HVILO clock DeepSleep domain Clock Supervisor registers (CSV_ILO_CSV) 104 */ 105 typedef struct { 106 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 107 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 108 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 109 __IM uint32_t RESERVED; 110 } CSV_ILO_CSV_Type; /*!< Size = 16 (0x10) */ 111 112 /** 113 * \brief CSV registers for ILO clock (CSV_ILO) 114 */ 115 typedef struct { 116 CSV_ILO_CSV_Type CSV; /*!< 0x00000000 HVILO clock DeepSleep domain Clock Supervisor registers */ 117 } CSV_ILO_Type; /*!< Size = 16 (0x10) */ 118 119 /** 120 * \brief 400MHz PLL Configuration Register (CLK_PLL400M) 121 */ 122 typedef struct { 123 __IOM uint32_t CONFIG; /*!< 0x00000000 400MHz PLL Configuration Register */ 124 __IOM uint32_t CONFIG2; /*!< 0x00000004 400MHz PLL Configuration Register 2 */ 125 __IOM uint32_t CONFIG3; /*!< 0x00000008 400MHz PLL Configuration Register 3 */ 126 __IOM uint32_t STATUS; /*!< 0x0000000C 400MHz PLL Status Register */ 127 } CLK_PLL400M_Type; /*!< Size = 16 (0x10) */ 128 129 /** 130 * \brief DPLL LP Configuration Register (CLK_DPLL_LP) 131 */ 132 typedef struct { 133 __IOM uint32_t CONFIG; /*!< 0x00000000 DPLL_LP Configuration Register */ 134 __IOM uint32_t CONFIG2; /*!< 0x00000004 DPLL_LP Configuration Register 2 */ 135 __IOM uint32_t CONFIG3; /*!< 0x00000008 DPLL_LP Configuration Register 3 */ 136 __IOM uint32_t CONFIG4; /*!< 0x0000000C DPLL_LP Configuration Register 4 */ 137 __IOM uint32_t CONFIG5; /*!< 0x00000010 DPLL_LP Configuration Register 5 */ 138 __IOM uint32_t CONFIG6; /*!< 0x00000014 DPLL_LP Configuration Register 6 */ 139 __IOM uint32_t CONFIG7; /*!< 0x00000018 DPLL_LP Configuration Register 7 */ 140 __IOM uint32_t STATUS; /*!< 0x0000001C DPLL_LP Status Register */ 141 } CLK_DPLL_LP_Type; /*!< Size = 32 (0x20) */ 142 143 /** 144 * \brief SRAM Trim registers (RAM_TRIM) 145 */ 146 typedef struct { 147 __IOM uint32_t TRIM_RAM_CTL; /*!< 0x00000000 Trim Register for RAM Type 0 */ 148 __IOM uint32_t TRIM_ROM_CTL; /*!< 0x00000004 Trim Register for ROM */ 149 } RAM_TRIM_Type; /*!< Size = 8 (0x8) */ 150 151 /** 152 * \brief Multi-Counter Watchdog Timer (Type A) (MCWDT_STRUCT) 153 */ 154 typedef struct { 155 __IM uint32_t RESERVED; 156 __IOM uint32_t MCWDT_CNTLOW; /*!< 0x00000004 Multi-Counter Watchdog Sub-counters 0/1 */ 157 __IOM uint32_t MCWDT_CNTHIGH; /*!< 0x00000008 Multi-Counter Watchdog Sub-counter 2 */ 158 __IOM uint32_t MCWDT_MATCH; /*!< 0x0000000C Multi-Counter Watchdog Counter Match Register */ 159 __IOM uint32_t MCWDT_CONFIG; /*!< 0x00000010 Multi-Counter Watchdog Counter Configuration */ 160 __IOM uint32_t MCWDT_CTL; /*!< 0x00000014 Multi-Counter Watchdog Counter Control */ 161 __IOM uint32_t MCWDT_INTR; /*!< 0x00000018 Multi-Counter Watchdog Counter Interrupt Register */ 162 __IOM uint32_t MCWDT_INTR_SET; /*!< 0x0000001C Multi-Counter Watchdog Counter Interrupt Set Register */ 163 __IOM uint32_t MCWDT_INTR_MASK; /*!< 0x00000020 Multi-Counter Watchdog Counter Interrupt Mask Register */ 164 __IM uint32_t MCWDT_INTR_MASKED; /*!< 0x00000024 Multi-Counter Watchdog Counter Interrupt Masked Register */ 165 __IOM uint32_t MCWDT_LOCK; /*!< 0x00000028 Multi-Counter Watchdog Counter Lock Register */ 166 __IOM uint32_t MCWDT_LOWER_LIMIT; /*!< 0x0000002C Multi-Counter Watchdog Counter Lower Limit Register */ 167 __IM uint32_t RESERVED1[4]; 168 } MCWDT_STRUCT_Type; /*!< Size = 64 (0x40) */ 169 170 /** 171 * \brief SRSS Core Registers (SRSS) 172 */ 173 typedef struct { 174 __IM uint32_t RESERVED[16]; 175 __IM uint32_t PWR_LVD_STATUS; /*!< 0x00000040 High Voltage / Low Voltage Detector (HVLVD) Status Register */ 176 __IM uint32_t PWR_LVD_STATUS2; /*!< 0x00000044 High Voltage / Low Voltage Detector (HVLVD) Status Register #2 */ 177 __IM uint32_t RESERVED1[46]; 178 __IOM uint32_t CLK_DSI_SELECT[16]; /*!< 0x00000100 Clock DSI Select Register */ 179 __IOM uint32_t CLK_OUTPUT_FAST; /*!< 0x00000140 Fast Clock Output Select Register */ 180 __IOM uint32_t CLK_OUTPUT_SLOW; /*!< 0x00000144 Slow Clock Output Select Register */ 181 __IOM uint32_t CLK_CAL_CNT1; /*!< 0x00000148 Clock Calibration Counter 1 */ 182 __IM uint32_t CLK_CAL_CNT2; /*!< 0x0000014C Clock Calibration Counter 2 */ 183 __IM uint32_t RESERVED2[44]; 184 __IOM uint32_t SRSS_INTR; /*!< 0x00000200 SRSS Interrupt Register */ 185 __IOM uint32_t SRSS_INTR_SET; /*!< 0x00000204 SRSS Interrupt Set Register */ 186 __IOM uint32_t SRSS_INTR_MASK; /*!< 0x00000208 SRSS Interrupt Mask Register */ 187 __IM uint32_t SRSS_INTR_MASKED; /*!< 0x0000020C SRSS Interrupt Masked Register */ 188 __IM uint32_t RESERVED3[60]; 189 __IOM uint32_t SRSS_AINTR; /*!< 0x00000300 SRSS Additional Interrupt Register */ 190 __IOM uint32_t SRSS_AINTR_SET; /*!< 0x00000304 SRSS Additional Interrupt Set Register */ 191 __IOM uint32_t SRSS_AINTR_MASK; /*!< 0x00000308 SRSS Additional Interrupt Mask Register */ 192 __IM uint32_t SRSS_AINTR_MASKED; /*!< 0x0000030C SRSS Additional Interrupt Masked Register */ 193 __IM uint32_t RESERVED4[61]; 194 __IOM uint32_t BOOT_DLM_CTL; /*!< 0x00000404 Debug Control Register */ 195 __IOM uint32_t BOOT_DLM_CTL2; /*!< 0x00000408 Debug Control Register 2 */ 196 __IOM uint32_t BOOT_DLM_STATUS; /*!< 0x0000040C Debug Status Register */ 197 __IOM uint32_t RES_SOFT_CTL; /*!< 0x00000410 Soft Reset Trigger Register */ 198 __IM uint32_t RESERVED5; 199 __IOM uint32_t BOOT_STATUS; /*!< 0x00000418 Boot Execution Status Register */ 200 __IM uint32_t RESERVED6[5]; 201 __IOM uint32_t BOOT_ENTRY; /*!< 0x00000430 Warm Boot Entry Address */ 202 __IM uint32_t RESERVED7[243]; 203 __IOM uint32_t PWR_HIB_DATA[16]; /*!< 0x00000800 HIBERNATE Data Register */ 204 __IM uint32_t RESERVED8[24]; 205 __IOM uint32_t PWR_HIB_WAKE_CTL; /*!< 0x000008A0 Hibernate Wakeup Mask Register */ 206 __IOM uint32_t PWR_HIB_WAKE_CTL2; /*!< 0x000008A4 Hibernate Wakeup Polarity Register */ 207 __IM uint32_t RESERVED9; 208 __IOM uint32_t PWR_HIB_WAKE_CAUSE; /*!< 0x000008AC Hibernate Wakeup Cause Register */ 209 __IM uint32_t RESERVED10[468]; 210 __IM uint32_t PWR_CTL; /*!< 0x00001000 Power Mode Control */ 211 __IOM uint32_t PWR_CTL2; /*!< 0x00001004 Power Mode Control 2 */ 212 __IOM uint32_t PWR_HIBERNATE; /*!< 0x00001008 HIBERNATE Mode Register */ 213 __IM uint32_t RESERVED11; 214 __IOM uint32_t PWR_BUCK_CTL; /*!< 0x00001010 Buck Control Register */ 215 __IOM uint32_t PWR_BUCK_CTL2; /*!< 0x00001014 Buck Control Register 2 */ 216 __IOM uint32_t PWR_SSV_CTL; /*!< 0x00001018 Supply Supervision Control Register */ 217 __IM uint32_t PWR_SSV_STATUS; /*!< 0x0000101C Supply Supervision Status Register */ 218 __IOM uint32_t PWR_LVD_CTL; /*!< 0x00001020 High Voltage / Low Voltage Detector (HVLVD) Configuration 219 Register */ 220 __IOM uint32_t PWR_LVD_CTL2; /*!< 0x00001024 High Voltage / Low Voltage Detector (HVLVD) Configuration 221 Register #2 */ 222 __IOM uint32_t PWR_REGHC_CTL; /*!< 0x00001028 REGHC Control Register */ 223 __IM uint32_t PWR_REGHC_STATUS; /*!< 0x0000102C REGHC Status Register */ 224 __IOM uint32_t PWR_REGHC_CTL2; /*!< 0x00001030 REGHC Control Register 2 */ 225 __IM uint32_t RESERVED12[35]; 226 __IOM uint32_t PWR_PMIC_CTL; /*!< 0x000010C0 PMIC Control Register */ 227 __IM uint32_t PWR_PMIC_STATUS; /*!< 0x000010C4 PMIC Status Register */ 228 __IOM uint32_t PWR_PMIC_CTL2; /*!< 0x000010C8 PMIC Control Register 2 */ 229 __IM uint32_t RESERVED13; 230 __IOM uint32_t PWR_PMIC_CTL4; /*!< 0x000010D0 PMIC Control Register 4 */ 231 __IM uint32_t RESERVED14[75]; 232 __IOM uint32_t CLK_PATH_SELECT[16]; /*!< 0x00001200 Clock Path Select Register */ 233 __IOM uint32_t CLK_ROOT_SELECT[16]; /*!< 0x00001240 Clock Root Select Register */ 234 __IOM uint32_t CLK_DIRECT_SELECT[16]; /*!< 0x00001280 Clock Root Direct Select Register */ 235 __IM uint32_t RESERVED15[80]; 236 CSV_HF_Type CSV_HF; /*!< 0x00001400 Clock Supervisor (CSV) registers for Root clocks */ 237 __IOM uint32_t CLK_SELECT; /*!< 0x00001500 Clock selection register */ 238 __IM uint32_t RESERVED16; 239 __IOM uint32_t CLK_ILO0_CONFIG; /*!< 0x00001508 ILO0 Configuration */ 240 __IOM uint32_t CLK_ILO1_CONFIG; /*!< 0x0000150C ILO1 Configuration */ 241 __IM uint32_t RESERVED17[2]; 242 __IOM uint32_t CLK_IMO_CONFIG; /*!< 0x00001518 IMO Configuration */ 243 __IOM uint32_t CLK_ECO_CONFIG; /*!< 0x0000151C ECO Configuration Register */ 244 __IOM uint32_t CLK_ECO_PRESCALE; /*!< 0x00001520 ECO Prescaler Configuration Register */ 245 __IM uint32_t CLK_ECO_STATUS; /*!< 0x00001524 ECO Status Register */ 246 __IOM uint32_t CLK_PILO_CONFIG; /*!< 0x00001528 Precision ILO Configuration Register */ 247 __IM uint32_t RESERVED18; 248 __IOM uint32_t CLK_FLL_CONFIG; /*!< 0x00001530 FLL Configuration Register */ 249 __IOM uint32_t CLK_FLL_CONFIG2; /*!< 0x00001534 FLL Configuration Register 2 */ 250 __IOM uint32_t CLK_FLL_CONFIG3; /*!< 0x00001538 FLL Configuration Register 3 */ 251 __IOM uint32_t CLK_FLL_CONFIG4; /*!< 0x0000153C FLL Configuration Register 4 */ 252 __IOM uint32_t CLK_FLL_STATUS; /*!< 0x00001540 FLL Status Register */ 253 __IOM uint32_t CLK_ECO_CONFIG2; /*!< 0x00001544 ECO Configuration Register 2 */ 254 __IOM uint32_t CLK_ILO_CONFIG; /*!< 0x00001548 ILO Configuration */ 255 __IOM uint32_t CLK_TRIM_ILO_CTL; /*!< 0x0000154C ILO Trim Register */ 256 __IOM uint32_t CLK_TRIM_ILO0_CTL; /*!< 0x00001550 ILO0 Trim Register */ 257 __IOM uint32_t CLK_MF_SELECT; /*!< 0x00001554 Medium Frequency Clock Select Register */ 258 __IOM uint32_t CLK_MFO_CONFIG; /*!< 0x00001558 MFO Configuration Register */ 259 __IM uint32_t RESERVED19; 260 __IOM uint32_t CLK_IHO_CONFIG; /*!< 0x00001560 IHO Configuration Register */ 261 __IOM uint32_t CLK_ALTHF_CTL; /*!< 0x00001564 Alternate High Frequency Clock Control Register */ 262 __IM uint32_t RESERVED20[38]; 263 __IOM uint32_t CLK_PLL_CONFIG[15]; /*!< 0x00001600 PLL Configuration Register */ 264 __IM uint32_t RESERVED21; 265 __IOM uint32_t CLK_PLL_STATUS[15]; /*!< 0x00001640 PLL Status Register */ 266 __IM uint32_t RESERVED22[33]; 267 __IOM uint32_t CSV_REF_SEL; /*!< 0x00001700 Select CSV Reference clock for Active domain */ 268 __IM uint32_t RESERVED23[3]; 269 CSV_REF_Type CSV_REF; /*!< 0x00001710 CSV registers for the CSV Reference clock */ 270 CSV_LF_Type CSV_LF; /*!< 0x00001720 CSV registers for LF clock */ 271 CSV_ILO_Type CSV_ILO; /*!< 0x00001730 CSV registers for ILO clock */ 272 __IM uint32_t RESERVED24[48]; 273 __IOM uint32_t RES_CAUSE; /*!< 0x00001800 Reset Cause Observation Register */ 274 __IOM uint32_t RES_CAUSE2; /*!< 0x00001804 Reset Cause Observation Register 2 */ 275 __IOM uint32_t RES_CAUSE_EXTEND; /*!< 0x00001808 Extended Reset Cause Observation Register */ 276 __IM uint32_t RESERVED25[2]; 277 __OM uint32_t RES_PXRES_CTL; /*!< 0x00001814 Programmable XRES Control Register */ 278 __IM uint32_t RESERVED26[58]; 279 CLK_PLL400M_Type CLK_PLL400M[15]; /*!< 0x00001900 400MHz PLL Configuration Register */ 280 __IM uint32_t RESERVED27[4]; 281 CLK_DPLL_LP_Type CLK_DPLL_LP[15]; /*!< 0x00001A00 DPLL LP Configuration Register */ 282 __IM uint32_t RESERVED28[8]; 283 __IOM uint32_t PWR_CBUCK_CTL; /*!< 0x00001C00 Core Buck Control Register */ 284 __IOM uint32_t PWR_CBUCK_CTL2; /*!< 0x00001C04 Core Buck Control Register 2 */ 285 __IOM uint32_t PWR_CBUCK_CTL3; /*!< 0x00001C08 Core Buck Control Register 3 */ 286 __IM uint32_t PWR_CBUCK_STATUS; /*!< 0x00001C0C Core Buck Status Register */ 287 __IOM uint32_t PWR_SDR0_CTL; /*!< 0x00001C10 Step Down Regulator 0 Control Register */ 288 __IOM uint32_t PWR_SDR1_CTL; /*!< 0x00001C14 Step Down Regulator 1 Control Register */ 289 __IM uint32_t RESERVED29[6]; 290 __IOM uint32_t PWR_HVLDO0_CTL; /*!< 0x00001C30 HVLDO0 Control Register */ 291 __IM uint32_t RESERVED30[264]; 292 __IOM uint32_t TST_XRES_SECURE; /*!< 0x00002054 SECURE TEST and FIRMWARE TEST Key control register */ 293 __IM uint32_t RESERVED31[21]; 294 __IOM uint32_t PWR_TRIM_CBUCK_CTL; /*!< 0x000020AC CBUCK Trim Register */ 295 __IM uint32_t RESERVED32[987]; 296 __IOM uint32_t CLK_TRIM_ECO_CTL; /*!< 0x0000301C ECO Trim Register */ 297 __IM uint32_t RESERVED33[128]; 298 __IOM uint32_t CLK_TRIM_ILO1_CTL; /*!< 0x00003220 ILO1 Trim Register */ 299 __IM uint32_t RESERVED34[887]; 300 RAM_TRIM_Type RAM_TRIM; /*!< 0x00004000 SRAM Trim registers */ 301 __IM uint32_t RESERVED35[8190]; 302 __IOM uint32_t WDT_CTL; /*!< 0x0000C000 Watchdog Counter Control Register (Type A) */ 303 __IOM uint32_t WDT_CNT; /*!< 0x0000C004 Watchdog Counter Count Register (Type A) */ 304 __IOM uint32_t WDT_MATCH; /*!< 0x0000C008 Watchdog Counter Match Register (Type A) */ 305 __IOM uint32_t WDT_MATCH2; /*!< 0x0000C00C Watchdog Counter Match Register 2 (Type A) */ 306 __IM uint32_t RESERVED36[1020]; 307 MCWDT_STRUCT_Type MCWDT_STRUCT[4]; /*!< 0x0000D000 Multi-Counter Watchdog Timer (Type A) */ 308 } SRSS_Type; /*!< Size = 53504 (0xD100) */ 309 310 311 /* CSV_HF_CSV.REF_CTL */ 312 #define CSV_HF_CSV_REF_CTL_STARTUP_Pos 0UL 313 #define CSV_HF_CSV_REF_CTL_STARTUP_Msk 0xFFFFUL 314 #define CSV_HF_CSV_REF_CTL_CSV_ACTION_Pos 30UL 315 #define CSV_HF_CSV_REF_CTL_CSV_ACTION_Msk 0x40000000UL 316 #define CSV_HF_CSV_REF_CTL_CSV_EN_Pos 31UL 317 #define CSV_HF_CSV_REF_CTL_CSV_EN_Msk 0x80000000UL 318 /* CSV_HF_CSV.REF_LIMIT */ 319 #define CSV_HF_CSV_REF_LIMIT_LOWER_Pos 0UL 320 #define CSV_HF_CSV_REF_LIMIT_LOWER_Msk 0xFFFFUL 321 #define CSV_HF_CSV_REF_LIMIT_UPPER_Pos 16UL 322 #define CSV_HF_CSV_REF_LIMIT_UPPER_Msk 0xFFFF0000UL 323 /* CSV_HF_CSV.MON_CTL */ 324 #define CSV_HF_CSV_MON_CTL_PERIOD_Pos 0UL 325 #define CSV_HF_CSV_MON_CTL_PERIOD_Msk 0xFFFFUL 326 327 328 /* CSV_REF_CSV.REF_CTL */ 329 #define CSV_REF_CSV_REF_CTL_STARTUP_Pos 0UL 330 #define CSV_REF_CSV_REF_CTL_STARTUP_Msk 0xFFFFUL 331 #define CSV_REF_CSV_REF_CTL_CSV_ACTION_Pos 30UL 332 #define CSV_REF_CSV_REF_CTL_CSV_ACTION_Msk 0x40000000UL 333 #define CSV_REF_CSV_REF_CTL_CSV_EN_Pos 31UL 334 #define CSV_REF_CSV_REF_CTL_CSV_EN_Msk 0x80000000UL 335 /* CSV_REF_CSV.REF_LIMIT */ 336 #define CSV_REF_CSV_REF_LIMIT_LOWER_Pos 0UL 337 #define CSV_REF_CSV_REF_LIMIT_LOWER_Msk 0xFFFFUL 338 #define CSV_REF_CSV_REF_LIMIT_UPPER_Pos 16UL 339 #define CSV_REF_CSV_REF_LIMIT_UPPER_Msk 0xFFFF0000UL 340 /* CSV_REF_CSV.MON_CTL */ 341 #define CSV_REF_CSV_MON_CTL_PERIOD_Pos 0UL 342 #define CSV_REF_CSV_MON_CTL_PERIOD_Msk 0xFFFFUL 343 344 345 /* CSV_LF_CSV.REF_CTL */ 346 #define CSV_LF_CSV_REF_CTL_STARTUP_Pos 0UL 347 #define CSV_LF_CSV_REF_CTL_STARTUP_Msk 0xFFUL 348 #define CSV_LF_CSV_REF_CTL_CSV_EN_Pos 31UL 349 #define CSV_LF_CSV_REF_CTL_CSV_EN_Msk 0x80000000UL 350 /* CSV_LF_CSV.REF_LIMIT */ 351 #define CSV_LF_CSV_REF_LIMIT_LOWER_Pos 0UL 352 #define CSV_LF_CSV_REF_LIMIT_LOWER_Msk 0xFFUL 353 #define CSV_LF_CSV_REF_LIMIT_UPPER_Pos 16UL 354 #define CSV_LF_CSV_REF_LIMIT_UPPER_Msk 0xFF0000UL 355 /* CSV_LF_CSV.MON_CTL */ 356 #define CSV_LF_CSV_MON_CTL_PERIOD_Pos 0UL 357 #define CSV_LF_CSV_MON_CTL_PERIOD_Msk 0xFFUL 358 359 360 /* CSV_ILO_CSV.REF_CTL */ 361 #define CSV_ILO_CSV_REF_CTL_STARTUP_Pos 0UL 362 #define CSV_ILO_CSV_REF_CTL_STARTUP_Msk 0xFFUL 363 #define CSV_ILO_CSV_REF_CTL_CSV_EN_Pos 31UL 364 #define CSV_ILO_CSV_REF_CTL_CSV_EN_Msk 0x80000000UL 365 /* CSV_ILO_CSV.REF_LIMIT */ 366 #define CSV_ILO_CSV_REF_LIMIT_LOWER_Pos 0UL 367 #define CSV_ILO_CSV_REF_LIMIT_LOWER_Msk 0xFFUL 368 #define CSV_ILO_CSV_REF_LIMIT_UPPER_Pos 16UL 369 #define CSV_ILO_CSV_REF_LIMIT_UPPER_Msk 0xFF0000UL 370 /* CSV_ILO_CSV.MON_CTL */ 371 #define CSV_ILO_CSV_MON_CTL_PERIOD_Pos 0UL 372 #define CSV_ILO_CSV_MON_CTL_PERIOD_Msk 0xFFUL 373 374 375 /* CLK_PLL400M.CONFIG */ 376 #define CLK_PLL400M_CONFIG_FEEDBACK_DIV_Pos 0UL 377 #define CLK_PLL400M_CONFIG_FEEDBACK_DIV_Msk 0xFFUL 378 #define CLK_PLL400M_CONFIG_REFERENCE_DIV_Pos 8UL 379 #define CLK_PLL400M_CONFIG_REFERENCE_DIV_Msk 0x1F00UL 380 #define CLK_PLL400M_CONFIG_OUTPUT_DIV_Pos 16UL 381 #define CLK_PLL400M_CONFIG_OUTPUT_DIV_Msk 0x1F0000UL 382 #define CLK_PLL400M_CONFIG_LOCK_DELAY_Pos 25UL 383 #define CLK_PLL400M_CONFIG_LOCK_DELAY_Msk 0x6000000UL 384 #define CLK_PLL400M_CONFIG_BYPASS_SEL_Pos 28UL 385 #define CLK_PLL400M_CONFIG_BYPASS_SEL_Msk 0x30000000UL 386 #define CLK_PLL400M_CONFIG_ENABLE_Pos 31UL 387 #define CLK_PLL400M_CONFIG_ENABLE_Msk 0x80000000UL 388 /* CLK_PLL400M.CONFIG2 */ 389 #define CLK_PLL400M_CONFIG2_FRAC_DIV_Pos 0UL 390 #define CLK_PLL400M_CONFIG2_FRAC_DIV_Msk 0xFFFFFFUL 391 #define CLK_PLL400M_CONFIG2_FRAC_DITHER_EN_Pos 28UL 392 #define CLK_PLL400M_CONFIG2_FRAC_DITHER_EN_Msk 0x70000000UL 393 #define CLK_PLL400M_CONFIG2_FRAC_EN_Pos 31UL 394 #define CLK_PLL400M_CONFIG2_FRAC_EN_Msk 0x80000000UL 395 /* CLK_PLL400M.CONFIG3 */ 396 #define CLK_PLL400M_CONFIG3_SSCG_DEPTH_Pos 0UL 397 #define CLK_PLL400M_CONFIG3_SSCG_DEPTH_Msk 0x3FFUL 398 #define CLK_PLL400M_CONFIG3_SSCG_RATE_Pos 16UL 399 #define CLK_PLL400M_CONFIG3_SSCG_RATE_Msk 0x70000UL 400 #define CLK_PLL400M_CONFIG3_SSCG_DITHER_EN_Pos 24UL 401 #define CLK_PLL400M_CONFIG3_SSCG_DITHER_EN_Msk 0x1000000UL 402 #define CLK_PLL400M_CONFIG3_SSCG_MODE_Pos 28UL 403 #define CLK_PLL400M_CONFIG3_SSCG_MODE_Msk 0x10000000UL 404 #define CLK_PLL400M_CONFIG3_SSCG_EN_Pos 31UL 405 #define CLK_PLL400M_CONFIG3_SSCG_EN_Msk 0x80000000UL 406 /* CLK_PLL400M.STATUS */ 407 #define CLK_PLL400M_STATUS_LOCKED_Pos 0UL 408 #define CLK_PLL400M_STATUS_LOCKED_Msk 0x1UL 409 #define CLK_PLL400M_STATUS_UNLOCK_OCCURRED_Pos 1UL 410 #define CLK_PLL400M_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 411 412 413 /* CLK_DPLL_LP.CONFIG */ 414 #define CLK_DPLL_LP_CONFIG_FEEDBACK_DIV_Pos 0UL 415 #define CLK_DPLL_LP_CONFIG_FEEDBACK_DIV_Msk 0xFFUL 416 #define CLK_DPLL_LP_CONFIG_REFERENCE_DIV_Pos 8UL 417 #define CLK_DPLL_LP_CONFIG_REFERENCE_DIV_Msk 0x1F00UL 418 #define CLK_DPLL_LP_CONFIG_OUTPUT_DIV_Pos 16UL 419 #define CLK_DPLL_LP_CONFIG_OUTPUT_DIV_Msk 0x1F0000UL 420 #define CLK_DPLL_LP_CONFIG_PLL_DCO_MODE_MULT_Pos 27UL 421 #define CLK_DPLL_LP_CONFIG_PLL_DCO_MODE_MULT_Msk 0x8000000UL 422 #define CLK_DPLL_LP_CONFIG_BYPASS_SEL_Pos 28UL 423 #define CLK_DPLL_LP_CONFIG_BYPASS_SEL_Msk 0x30000000UL 424 #define CLK_DPLL_LP_CONFIG_ENABLE_Pos 31UL 425 #define CLK_DPLL_LP_CONFIG_ENABLE_Msk 0x80000000UL 426 /* CLK_DPLL_LP.CONFIG2 */ 427 #define CLK_DPLL_LP_CONFIG2_FRAC_DIV_Pos 0UL 428 #define CLK_DPLL_LP_CONFIG2_FRAC_DIV_Msk 0xFFFFFFUL 429 #define CLK_DPLL_LP_CONFIG2_FRAC_DITHER_EN_Pos 28UL 430 #define CLK_DPLL_LP_CONFIG2_FRAC_DITHER_EN_Msk 0x70000000UL 431 #define CLK_DPLL_LP_CONFIG2_FRAC_EN_Pos 31UL 432 #define CLK_DPLL_LP_CONFIG2_FRAC_EN_Msk 0x80000000UL 433 /* CLK_DPLL_LP.CONFIG3 */ 434 #define CLK_DPLL_LP_CONFIG3_SSCG_DEPTH_Pos 0UL 435 #define CLK_DPLL_LP_CONFIG3_SSCG_DEPTH_Msk 0x3FFUL 436 #define CLK_DPLL_LP_CONFIG3_SSCG_RATE_Pos 16UL 437 #define CLK_DPLL_LP_CONFIG3_SSCG_RATE_Msk 0x70000UL 438 #define CLK_DPLL_LP_CONFIG3_SSCG_DITHER_EN_Pos 24UL 439 #define CLK_DPLL_LP_CONFIG3_SSCG_DITHER_EN_Msk 0x1000000UL 440 #define CLK_DPLL_LP_CONFIG3_SSCG_MODE_Pos 28UL 441 #define CLK_DPLL_LP_CONFIG3_SSCG_MODE_Msk 0x10000000UL 442 #define CLK_DPLL_LP_CONFIG3_SSCG_EN_Pos 31UL 443 #define CLK_DPLL_LP_CONFIG3_SSCG_EN_Msk 0x80000000UL 444 /* CLK_DPLL_LP.CONFIG4 */ 445 #define CLK_DPLL_LP_CONFIG4_DCO_CODE_Pos 0UL 446 #define CLK_DPLL_LP_CONFIG4_DCO_CODE_Msk 0x7FFUL 447 #define CLK_DPLL_LP_CONFIG4_ACC_MODE_Pos 16UL 448 #define CLK_DPLL_LP_CONFIG4_ACC_MODE_Msk 0x30000UL 449 #define CLK_DPLL_LP_CONFIG4_TDC_MODE_Pos 18UL 450 #define CLK_DPLL_LP_CONFIG4_TDC_MODE_Msk 0xC0000UL 451 #define CLK_DPLL_LP_CONFIG4_PLL_TG_Pos 20UL 452 #define CLK_DPLL_LP_CONFIG4_PLL_TG_Msk 0x300000UL 453 #define CLK_DPLL_LP_CONFIG4_ACC_CNT_LOCK_Pos 24UL 454 #define CLK_DPLL_LP_CONFIG4_ACC_CNT_LOCK_Msk 0x1000000UL 455 /* CLK_DPLL_LP.CONFIG5 */ 456 #define CLK_DPLL_LP_CONFIG5_KI_INT_Pos 0UL 457 #define CLK_DPLL_LP_CONFIG5_KI_INT_Msk 0x7FUL 458 #define CLK_DPLL_LP_CONFIG5_KP_INT_Pos 8UL 459 #define CLK_DPLL_LP_CONFIG5_KP_INT_Msk 0x7F00UL 460 #define CLK_DPLL_LP_CONFIG5_KI_ACC_INT_Pos 16UL 461 #define CLK_DPLL_LP_CONFIG5_KI_ACC_INT_Msk 0x7F0000UL 462 #define CLK_DPLL_LP_CONFIG5_KP_ACC_INT_Pos 24UL 463 #define CLK_DPLL_LP_CONFIG5_KP_ACC_INT_Msk 0x7F000000UL 464 /* CLK_DPLL_LP.CONFIG6 */ 465 #define CLK_DPLL_LP_CONFIG6_KI_FRACT_Pos 0UL 466 #define CLK_DPLL_LP_CONFIG6_KI_FRACT_Msk 0x7FUL 467 #define CLK_DPLL_LP_CONFIG6_KP_FRACT_Pos 8UL 468 #define CLK_DPLL_LP_CONFIG6_KP_FRACT_Msk 0x7F00UL 469 #define CLK_DPLL_LP_CONFIG6_KI_ACC_FRACT_Pos 16UL 470 #define CLK_DPLL_LP_CONFIG6_KI_ACC_FRACT_Msk 0x7F0000UL 471 #define CLK_DPLL_LP_CONFIG6_KP_ACC_FRACT_Pos 24UL 472 #define CLK_DPLL_LP_CONFIG6_KP_ACC_FRACT_Msk 0x7F000000UL 473 /* CLK_DPLL_LP.CONFIG7 */ 474 #define CLK_DPLL_LP_CONFIG7_KI_SSCG_Pos 0UL 475 #define CLK_DPLL_LP_CONFIG7_KI_SSCG_Msk 0x7FUL 476 #define CLK_DPLL_LP_CONFIG7_KP_SSCG_Pos 8UL 477 #define CLK_DPLL_LP_CONFIG7_KP_SSCG_Msk 0x7F00UL 478 #define CLK_DPLL_LP_CONFIG7_KI_ACC_SSCG_Pos 16UL 479 #define CLK_DPLL_LP_CONFIG7_KI_ACC_SSCG_Msk 0x7F0000UL 480 #define CLK_DPLL_LP_CONFIG7_KP_ACC_SSCG_Pos 24UL 481 #define CLK_DPLL_LP_CONFIG7_KP_ACC_SSCG_Msk 0x7F000000UL 482 /* CLK_DPLL_LP.STATUS */ 483 #define CLK_DPLL_LP_STATUS_LOCKED_Pos 0UL 484 #define CLK_DPLL_LP_STATUS_LOCKED_Msk 0x1UL 485 #define CLK_DPLL_LP_STATUS_UNLOCK_OCCURRED_Pos 1UL 486 #define CLK_DPLL_LP_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 487 488 489 /* RAM_TRIM.TRIM_RAM_CTL */ 490 #define RAM_TRIM_TRIM_RAM_CTL_TRIM_Pos 0UL 491 #define RAM_TRIM_TRIM_RAM_CTL_TRIM_Msk 0xFFFFFFFFUL 492 /* RAM_TRIM.TRIM_ROM_CTL */ 493 #define RAM_TRIM_TRIM_ROM_CTL_TRIM_Pos 0UL 494 #define RAM_TRIM_TRIM_ROM_CTL_TRIM_Msk 0xFFFFFFFFUL 495 496 497 /* MCWDT_STRUCT.MCWDT_CNTLOW */ 498 #define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Pos 0UL 499 #define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk 0xFFFFUL 500 #define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Pos 16UL 501 #define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Msk 0xFFFF0000UL 502 /* MCWDT_STRUCT.MCWDT_CNTHIGH */ 503 #define MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2_Pos 0UL 504 #define MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2_Msk 0xFFFFFFFFUL 505 /* MCWDT_STRUCT.MCWDT_MATCH */ 506 #define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Pos 0UL 507 #define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk 0xFFFFUL 508 #define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1_Pos 16UL 509 #define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1_Msk 0xFFFF0000UL 510 /* MCWDT_STRUCT.MCWDT_CONFIG */ 511 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0_Pos 0UL 512 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0_Msk 0x3UL 513 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Pos 2UL 514 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk 0x4UL 515 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Pos 3UL 516 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Msk 0x8UL 517 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE0_Pos 4UL 518 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE0_Msk 0x30UL 519 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY0_1_Pos 6UL 520 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY0_1_Msk 0x40UL 521 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH0_1_Pos 7UL 522 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH0_1_Msk 0x80UL 523 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1_Pos 8UL 524 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1_Msk 0x300UL 525 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Pos 10UL 526 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Msk 0x400UL 527 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Pos 11UL 528 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Msk 0x800UL 529 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE1_Pos 12UL 530 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE1_Msk 0x3000UL 531 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY1_2_Pos 14UL 532 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY1_2_Msk 0x4000UL 533 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH1_2_Pos 15UL 534 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH1_2_Msk 0x8000UL 535 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2_Pos 16UL 536 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2_Msk 0x10000UL 537 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2_Pos 24UL 538 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2_Msk 0x1F000000UL 539 /* MCWDT_STRUCT.MCWDT_CTL */ 540 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Pos 0UL 541 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk 0x1UL 542 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0_Pos 1UL 543 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0_Msk 0x2UL 544 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Pos 3UL 545 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Msk 0x8UL 546 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Pos 8UL 547 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk 0x100UL 548 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1_Pos 9UL 549 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1_Msk 0x200UL 550 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Pos 11UL 551 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Msk 0x800UL 552 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Pos 16UL 553 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk 0x10000UL 554 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2_Pos 17UL 555 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2_Msk 0x20000UL 556 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Pos 19UL 557 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Msk 0x80000UL 558 /* MCWDT_STRUCT.MCWDT_INTR */ 559 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT0_Pos 0UL 560 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT0_Msk 0x1UL 561 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT1_Pos 1UL 562 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT1_Msk 0x2UL 563 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT2_Pos 2UL 564 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT2_Msk 0x4UL 565 /* MCWDT_STRUCT.MCWDT_INTR_SET */ 566 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT0_Pos 0UL 567 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT0_Msk 0x1UL 568 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT1_Pos 1UL 569 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT1_Msk 0x2UL 570 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT2_Pos 2UL 571 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT2_Msk 0x4UL 572 /* MCWDT_STRUCT.MCWDT_INTR_MASK */ 573 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT0_Pos 0UL 574 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT0_Msk 0x1UL 575 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT1_Pos 1UL 576 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT1_Msk 0x2UL 577 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT2_Pos 2UL 578 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT2_Msk 0x4UL 579 /* MCWDT_STRUCT.MCWDT_INTR_MASKED */ 580 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT0_Pos 0UL 581 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT0_Msk 0x1UL 582 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT1_Pos 1UL 583 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT1_Msk 0x2UL 584 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT2_Pos 2UL 585 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT2_Msk 0x4UL 586 /* MCWDT_STRUCT.MCWDT_LOCK */ 587 #define MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Pos 30UL 588 #define MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Msk 0xC0000000UL 589 /* MCWDT_STRUCT.MCWDT_LOWER_LIMIT */ 590 #define MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT0_Pos 0UL 591 #define MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT0_Msk 0xFFFFUL 592 #define MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT1_Pos 16UL 593 #define MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT1_Msk 0xFFFF0000UL 594 595 596 /* SRSS.PWR_LVD_STATUS */ 597 #define SRSS_PWR_LVD_STATUS_HVLVD1_OK_Pos 0UL 598 #define SRSS_PWR_LVD_STATUS_HVLVD1_OK_Msk 0x1UL 599 /* SRSS.PWR_LVD_STATUS2 */ 600 #define SRSS_PWR_LVD_STATUS2_HVLVD2_OUT_Pos 0UL 601 #define SRSS_PWR_LVD_STATUS2_HVLVD2_OUT_Msk 0x1UL 602 /* SRSS.CLK_DSI_SELECT */ 603 #define SRSS_CLK_DSI_SELECT_DSI_MUX_Pos 0UL 604 #define SRSS_CLK_DSI_SELECT_DSI_MUX_Msk 0x1FUL 605 /* SRSS.CLK_OUTPUT_FAST */ 606 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Pos 0UL 607 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk 0xFUL 608 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Pos 4UL 609 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk 0xF0UL 610 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos 8UL 611 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk 0xF00UL 612 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Pos 16UL 613 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk 0xF0000UL 614 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Pos 20UL 615 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk 0xF00000UL 616 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos 24UL 617 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk 0xF000000UL 618 /* SRSS.CLK_OUTPUT_SLOW */ 619 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos 0UL 620 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk 0xFUL 621 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos 4UL 622 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk 0xF0UL 623 /* SRSS.CLK_CAL_CNT1 */ 624 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Pos 0UL 625 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Msk 0xFFFFFFUL 626 #define SRSS_CLK_CAL_CNT1_CAL_RESET_Pos 29UL 627 #define SRSS_CLK_CAL_CNT1_CAL_RESET_Msk 0x20000000UL 628 #define SRSS_CLK_CAL_CNT1_CAL_CLK1_PRESENT_Pos 30UL 629 #define SRSS_CLK_CAL_CNT1_CAL_CLK1_PRESENT_Msk 0x40000000UL 630 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos 31UL 631 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk 0x80000000UL 632 /* SRSS.CLK_CAL_CNT2 */ 633 #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Pos 0UL 634 #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Msk 0xFFFFFFUL 635 /* SRSS.SRSS_INTR */ 636 #define SRSS_SRSS_INTR_WDT_MATCH_Pos 0UL 637 #define SRSS_SRSS_INTR_WDT_MATCH_Msk 0x1UL 638 #define SRSS_SRSS_INTR_CLK_CAL_Pos 5UL 639 #define SRSS_SRSS_INTR_CLK_CAL_Msk 0x20UL 640 #define SRSS_SRSS_INTR_AINTR_Pos 31UL 641 #define SRSS_SRSS_INTR_AINTR_Msk 0x80000000UL 642 /* SRSS.SRSS_INTR_SET */ 643 #define SRSS_SRSS_INTR_SET_WDT_MATCH_Pos 0UL 644 #define SRSS_SRSS_INTR_SET_WDT_MATCH_Msk 0x1UL 645 #define SRSS_SRSS_INTR_SET_CLK_CAL_Pos 5UL 646 #define SRSS_SRSS_INTR_SET_CLK_CAL_Msk 0x20UL 647 /* SRSS.SRSS_INTR_MASK */ 648 #define SRSS_SRSS_INTR_MASK_WDT_MATCH_Pos 0UL 649 #define SRSS_SRSS_INTR_MASK_WDT_MATCH_Msk 0x1UL 650 #define SRSS_SRSS_INTR_MASK_CLK_CAL_Pos 5UL 651 #define SRSS_SRSS_INTR_MASK_CLK_CAL_Msk 0x20UL 652 /* SRSS.SRSS_INTR_MASKED */ 653 #define SRSS_SRSS_INTR_MASKED_WDT_MATCH_Pos 0UL 654 #define SRSS_SRSS_INTR_MASKED_WDT_MATCH_Msk 0x1UL 655 #define SRSS_SRSS_INTR_MASKED_CLK_CAL_Pos 5UL 656 #define SRSS_SRSS_INTR_MASKED_CLK_CAL_Msk 0x20UL 657 #define SRSS_SRSS_INTR_MASKED_AINTR_Pos 31UL 658 #define SRSS_SRSS_INTR_MASKED_AINTR_Msk 0x80000000UL 659 /* SRSS.SRSS_AINTR */ 660 #define SRSS_SRSS_AINTR_HVLVD1_Pos 1UL 661 #define SRSS_SRSS_AINTR_HVLVD1_Msk 0x2UL 662 #define SRSS_SRSS_AINTR_HVLVD2_Pos 2UL 663 #define SRSS_SRSS_AINTR_HVLVD2_Msk 0x4UL 664 /* SRSS.SRSS_AINTR_SET */ 665 #define SRSS_SRSS_AINTR_SET_HVLVD1_Pos 1UL 666 #define SRSS_SRSS_AINTR_SET_HVLVD1_Msk 0x2UL 667 #define SRSS_SRSS_AINTR_SET_HVLVD2_Pos 2UL 668 #define SRSS_SRSS_AINTR_SET_HVLVD2_Msk 0x4UL 669 /* SRSS.SRSS_AINTR_MASK */ 670 #define SRSS_SRSS_AINTR_MASK_HVLVD1_Pos 1UL 671 #define SRSS_SRSS_AINTR_MASK_HVLVD1_Msk 0x2UL 672 #define SRSS_SRSS_AINTR_MASK_HVLVD2_Pos 2UL 673 #define SRSS_SRSS_AINTR_MASK_HVLVD2_Msk 0x4UL 674 /* SRSS.SRSS_AINTR_MASKED */ 675 #define SRSS_SRSS_AINTR_MASKED_HVLVD1_Pos 1UL 676 #define SRSS_SRSS_AINTR_MASKED_HVLVD1_Msk 0x2UL 677 #define SRSS_SRSS_AINTR_MASKED_HVLVD2_Pos 2UL 678 #define SRSS_SRSS_AINTR_MASKED_HVLVD2_Msk 0x4UL 679 /* SRSS.BOOT_DLM_CTL */ 680 #define SRSS_BOOT_DLM_CTL_REQUEST_Pos 0UL 681 #define SRSS_BOOT_DLM_CTL_REQUEST_Msk 0xFUL 682 #define SRSS_BOOT_DLM_CTL_INPUT_AVAIL_Pos 29UL 683 #define SRSS_BOOT_DLM_CTL_INPUT_AVAIL_Msk 0x20000000UL 684 #define SRSS_BOOT_DLM_CTL_RESET_Pos 30UL 685 #define SRSS_BOOT_DLM_CTL_RESET_Msk 0x40000000UL 686 #define SRSS_BOOT_DLM_CTL_WFA_Pos 31UL 687 #define SRSS_BOOT_DLM_CTL_WFA_Msk 0x80000000UL 688 /* SRSS.BOOT_DLM_CTL2 */ 689 #define SRSS_BOOT_DLM_CTL2_APP_CTL_Pos 0UL 690 #define SRSS_BOOT_DLM_CTL2_APP_CTL_Msk 0xFFFFFFFFUL 691 /* SRSS.BOOT_DLM_STATUS */ 692 #define SRSS_BOOT_DLM_STATUS_DEBUG_STATUS_Pos 0UL 693 #define SRSS_BOOT_DLM_STATUS_DEBUG_STATUS_Msk 0xFFFFFFFFUL 694 /* SRSS.RES_SOFT_CTL */ 695 #define SRSS_RES_SOFT_CTL_TRIGGER_SOFT_Pos 0UL 696 #define SRSS_RES_SOFT_CTL_TRIGGER_SOFT_Msk 0x1UL 697 /* SRSS.BOOT_STATUS */ 698 #define SRSS_BOOT_STATUS_DEBUG_STATUS_Pos 0UL 699 #define SRSS_BOOT_STATUS_DEBUG_STATUS_Msk 0xFFFFFFFFUL 700 /* SRSS.BOOT_ENTRY */ 701 #define SRSS_BOOT_ENTRY_WARM_BOOT_ENTRY_Pos 0UL 702 #define SRSS_BOOT_ENTRY_WARM_BOOT_ENTRY_Msk 0xFFFFFFFFUL 703 /* SRSS.PWR_HIB_DATA */ 704 #define SRSS_PWR_HIB_DATA_HIB_DATA_Pos 0UL 705 #define SRSS_PWR_HIB_DATA_HIB_DATA_Msk 0xFFFFFFFFUL 706 /* SRSS.PWR_HIB_WAKE_CTL */ 707 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_SRC_Pos 0UL 708 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_SRC_Msk 0xFFFFFFUL 709 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_CSV_BAK_Pos 29UL 710 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_CSV_BAK_Msk 0x20000000UL 711 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_RTC_Pos 30UL 712 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_RTC_Msk 0x40000000UL 713 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_WDT_Pos 31UL 714 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_WDT_Msk 0x80000000UL 715 /* SRSS.PWR_HIB_WAKE_CTL2 */ 716 #define SRSS_PWR_HIB_WAKE_CTL2_HIB_WAKE_SRC_Pos 0UL 717 #define SRSS_PWR_HIB_WAKE_CTL2_HIB_WAKE_SRC_Msk 0xFFFFFFUL 718 /* SRSS.PWR_HIB_WAKE_CAUSE */ 719 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_SRC_Pos 0UL 720 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_SRC_Msk 0xFFFFFFUL 721 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_CSV_BAK_Pos 29UL 722 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_CSV_BAK_Msk 0x20000000UL 723 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_RTC_Pos 30UL 724 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_RTC_Msk 0x40000000UL 725 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_WDT_Pos 31UL 726 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_WDT_Msk 0x80000000UL 727 /* SRSS.PWR_CTL */ 728 #define SRSS_PWR_CTL_POWER_MODE_Pos 0UL 729 #define SRSS_PWR_CTL_POWER_MODE_Msk 0x3UL 730 #define SRSS_PWR_CTL_DEBUG_SESSION_Pos 4UL 731 #define SRSS_PWR_CTL_DEBUG_SESSION_Msk 0x10UL 732 #define SRSS_PWR_CTL_LPM_READY_Pos 5UL 733 #define SRSS_PWR_CTL_LPM_READY_Msk 0x20UL 734 /* SRSS.PWR_CTL2 */ 735 #define SRSS_PWR_CTL2_LINREG_DIS_Pos 0UL 736 #define SRSS_PWR_CTL2_LINREG_DIS_Msk 0x1UL 737 #define SRSS_PWR_CTL2_LINREG_OK_Pos 1UL 738 #define SRSS_PWR_CTL2_LINREG_OK_Msk 0x2UL 739 #define SRSS_PWR_CTL2_LINREG_LPMODE_Pos 2UL 740 #define SRSS_PWR_CTL2_LINREG_LPMODE_Msk 0x4UL 741 #define SRSS_PWR_CTL2_DPSLP_REG_DIS_Pos 4UL 742 #define SRSS_PWR_CTL2_DPSLP_REG_DIS_Msk 0x10UL 743 #define SRSS_PWR_CTL2_RET_REG_DIS_Pos 8UL 744 #define SRSS_PWR_CTL2_RET_REG_DIS_Msk 0x100UL 745 #define SRSS_PWR_CTL2_NWELL_REG_DIS_Pos 12UL 746 #define SRSS_PWR_CTL2_NWELL_REG_DIS_Msk 0x1000UL 747 #define SRSS_PWR_CTL2_REFV_DIS_Pos 16UL 748 #define SRSS_PWR_CTL2_REFV_DIS_Msk 0x10000UL 749 #define SRSS_PWR_CTL2_REFV_OK_Pos 17UL 750 #define SRSS_PWR_CTL2_REFV_OK_Msk 0x20000UL 751 #define SRSS_PWR_CTL2_REFVBUF_DIS_Pos 20UL 752 #define SRSS_PWR_CTL2_REFVBUF_DIS_Msk 0x100000UL 753 #define SRSS_PWR_CTL2_REFVBUF_OK_Pos 21UL 754 #define SRSS_PWR_CTL2_REFVBUF_OK_Msk 0x200000UL 755 #define SRSS_PWR_CTL2_REFI_DIS_Pos 24UL 756 #define SRSS_PWR_CTL2_REFI_DIS_Msk 0x1000000UL 757 #define SRSS_PWR_CTL2_REFI_OK_Pos 25UL 758 #define SRSS_PWR_CTL2_REFI_OK_Msk 0x2000000UL 759 #define SRSS_PWR_CTL2_REFI_LPMODE_Pos 26UL 760 #define SRSS_PWR_CTL2_REFI_LPMODE_Msk 0x4000000UL 761 #define SRSS_PWR_CTL2_PORBOD_LPMODE_Pos 27UL 762 #define SRSS_PWR_CTL2_PORBOD_LPMODE_Msk 0x8000000UL 763 #define SRSS_PWR_CTL2_BGREF_LPMODE_Pos 28UL 764 #define SRSS_PWR_CTL2_BGREF_LPMODE_Msk 0x10000000UL 765 #define SRSS_PWR_CTL2_FREEZE_DPSLP_Pos 30UL 766 #define SRSS_PWR_CTL2_FREEZE_DPSLP_Msk 0x40000000UL 767 #define SRSS_PWR_CTL2_PLL_LS_BYPASS_Pos 31UL 768 #define SRSS_PWR_CTL2_PLL_LS_BYPASS_Msk 0x80000000UL 769 /* SRSS.PWR_HIBERNATE */ 770 #define SRSS_PWR_HIBERNATE_TOKEN_Pos 0UL 771 #define SRSS_PWR_HIBERNATE_TOKEN_Msk 0xFFUL 772 #define SRSS_PWR_HIBERNATE_UNLOCK_Pos 8UL 773 #define SRSS_PWR_HIBERNATE_UNLOCK_Msk 0xFF00UL 774 #define SRSS_PWR_HIBERNATE_FREEZE_Pos 17UL 775 #define SRSS_PWR_HIBERNATE_FREEZE_Msk 0x20000UL 776 #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Pos 18UL 777 #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk 0x40000UL 778 #define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Pos 19UL 779 #define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk 0x80000UL 780 #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos 20UL 781 #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk 0xF00000UL 782 #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos 24UL 783 #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk 0xF000000UL 784 #define SRSS_PWR_HIBERNATE_SENSE_MODE_Pos 29UL 785 #define SRSS_PWR_HIBERNATE_SENSE_MODE_Msk 0x20000000UL 786 #define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Pos 30UL 787 #define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Msk 0x40000000UL 788 #define SRSS_PWR_HIBERNATE_HIBERNATE_Pos 31UL 789 #define SRSS_PWR_HIBERNATE_HIBERNATE_Msk 0x80000000UL 790 /* SRSS.PWR_BUCK_CTL */ 791 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Pos 0UL 792 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Msk 0x7UL 793 #define SRSS_PWR_BUCK_CTL_BUCK_EN_Pos 30UL 794 #define SRSS_PWR_BUCK_CTL_BUCK_EN_Msk 0x40000000UL 795 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Pos 31UL 796 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Msk 0x80000000UL 797 /* SRSS.PWR_BUCK_CTL2 */ 798 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Pos 0UL 799 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Msk 0x7UL 800 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Pos 30UL 801 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Msk 0x40000000UL 802 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Pos 31UL 803 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Msk 0x80000000UL 804 /* SRSS.PWR_SSV_CTL */ 805 #define SRSS_PWR_SSV_CTL_BODVDDD_VSEL_Pos 0UL 806 #define SRSS_PWR_SSV_CTL_BODVDDD_VSEL_Msk 0x1UL 807 #define SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Pos 3UL 808 #define SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Msk 0x8UL 809 #define SRSS_PWR_SSV_CTL_BODVDDA_VSEL_Pos 4UL 810 #define SRSS_PWR_SSV_CTL_BODVDDA_VSEL_Msk 0x10UL 811 #define SRSS_PWR_SSV_CTL_BODVDDA_ACTION_Pos 6UL 812 #define SRSS_PWR_SSV_CTL_BODVDDA_ACTION_Msk 0xC0UL 813 #define SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Pos 8UL 814 #define SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Msk 0x100UL 815 #define SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Pos 11UL 816 #define SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Msk 0x800UL 817 #define SRSS_PWR_SSV_CTL_OVDVDDD_VSEL_Pos 16UL 818 #define SRSS_PWR_SSV_CTL_OVDVDDD_VSEL_Msk 0x10000UL 819 #define SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Pos 19UL 820 #define SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk 0x80000UL 821 #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Pos 20UL 822 #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Msk 0x100000UL 823 #define SRSS_PWR_SSV_CTL_OVDVDDA_ACTION_Pos 22UL 824 #define SRSS_PWR_SSV_CTL_OVDVDDA_ACTION_Msk 0xC00000UL 825 #define SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Pos 24UL 826 #define SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk 0x1000000UL 827 #define SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Pos 27UL 828 #define SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk 0x8000000UL 829 /* SRSS.PWR_SSV_STATUS */ 830 #define SRSS_PWR_SSV_STATUS_BODVDDD_OK_Pos 0UL 831 #define SRSS_PWR_SSV_STATUS_BODVDDD_OK_Msk 0x1UL 832 #define SRSS_PWR_SSV_STATUS_BODVDDA_OK_Pos 1UL 833 #define SRSS_PWR_SSV_STATUS_BODVDDA_OK_Msk 0x2UL 834 #define SRSS_PWR_SSV_STATUS_BODVCCD_OK_Pos 2UL 835 #define SRSS_PWR_SSV_STATUS_BODVCCD_OK_Msk 0x4UL 836 #define SRSS_PWR_SSV_STATUS_OVDVDDD_OK_Pos 8UL 837 #define SRSS_PWR_SSV_STATUS_OVDVDDD_OK_Msk 0x100UL 838 #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Pos 9UL 839 #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Msk 0x200UL 840 #define SRSS_PWR_SSV_STATUS_OVDVCCD_OK_Pos 10UL 841 #define SRSS_PWR_SSV_STATUS_OVDVCCD_OK_Msk 0x400UL 842 #define SRSS_PWR_SSV_STATUS_OCD_ACT_LINREG_OK_Pos 16UL 843 #define SRSS_PWR_SSV_STATUS_OCD_ACT_LINREG_OK_Msk 0x10000UL 844 #define SRSS_PWR_SSV_STATUS_OCD_DPSLP_REG_OK_Pos 17UL 845 #define SRSS_PWR_SSV_STATUS_OCD_DPSLP_REG_OK_Msk 0x20000UL 846 /* SRSS.PWR_LVD_CTL */ 847 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Pos 0UL 848 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Msk 0xFUL 849 #define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Pos 4UL 850 #define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Msk 0x70UL 851 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_Pos 7UL 852 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_Msk 0x80UL 853 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Pos 8UL 854 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Msk 0x1F00UL 855 #define SRSS_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Pos 14UL 856 #define SRSS_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Msk 0x4000UL 857 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Pos 15UL 858 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Msk 0x8000UL 859 #define SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Pos 16UL 860 #define SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Msk 0x30000UL 861 #define SRSS_PWR_LVD_CTL_HVLVD1_ACTION_Pos 18UL 862 #define SRSS_PWR_LVD_CTL_HVLVD1_ACTION_Msk 0x40000UL 863 /* SRSS.PWR_LVD_CTL2 */ 864 #define SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Pos 8UL 865 #define SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Msk 0x1F00UL 866 #define SRSS_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Pos 14UL 867 #define SRSS_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Msk 0x4000UL 868 #define SRSS_PWR_LVD_CTL2_HVLVD2_EN_HT_Pos 15UL 869 #define SRSS_PWR_LVD_CTL2_HVLVD2_EN_HT_Msk 0x8000UL 870 #define SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Pos 16UL 871 #define SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Msk 0x30000UL 872 #define SRSS_PWR_LVD_CTL2_HVLVD2_ACTION_Pos 18UL 873 #define SRSS_PWR_LVD_CTL2_HVLVD2_ACTION_Msk 0x40000UL 874 /* SRSS.PWR_REGHC_CTL */ 875 #define SRSS_PWR_REGHC_CTL_REGHC_MODE_Pos 0UL 876 #define SRSS_PWR_REGHC_CTL_REGHC_MODE_Msk 0x1UL 877 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Pos 2UL 878 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Msk 0xCUL 879 #define SRSS_PWR_REGHC_CTL_REGHC_VADJ_Pos 4UL 880 #define SRSS_PWR_REGHC_CTL_REGHC_VADJ_Msk 0x1F0UL 881 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Pos 10UL 882 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Msk 0x400UL 883 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_RADJ_Pos 11UL 884 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_RADJ_Msk 0x800UL 885 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_RADJ_Pos 12UL 886 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_RADJ_Msk 0x7000UL 887 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Pos 16UL 888 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Msk 0x10000UL 889 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Pos 17UL 890 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Msk 0x20000UL 891 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Pos 18UL 892 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Msk 0x40000UL 893 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Pos 19UL 894 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Msk 0x80000UL 895 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT_Pos 20UL 896 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT_Msk 0x3FF00000UL 897 #define SRSS_PWR_REGHC_CTL_REGHC_TRANS_USE_OCD_Pos 30UL 898 #define SRSS_PWR_REGHC_CTL_REGHC_TRANS_USE_OCD_Msk 0x40000000UL 899 #define SRSS_PWR_REGHC_CTL_REGHC_CONFIGURED_Pos 31UL 900 #define SRSS_PWR_REGHC_CTL_REGHC_CONFIGURED_Msk 0x80000000UL 901 /* SRSS.PWR_REGHC_STATUS */ 902 #define SRSS_PWR_REGHC_STATUS_REGHC_ENABLED_Pos 0UL 903 #define SRSS_PWR_REGHC_STATUS_REGHC_ENABLED_Msk 0x1UL 904 #define SRSS_PWR_REGHC_STATUS_REGHC_OCD_OK_Pos 1UL 905 #define SRSS_PWR_REGHC_STATUS_REGHC_OCD_OK_Msk 0x2UL 906 #define SRSS_PWR_REGHC_STATUS_REGHC_CKT_OK_Pos 2UL 907 #define SRSS_PWR_REGHC_STATUS_REGHC_CKT_OK_Msk 0x4UL 908 #define SRSS_PWR_REGHC_STATUS_REGHC_UV_OUT_Pos 8UL 909 #define SRSS_PWR_REGHC_STATUS_REGHC_UV_OUT_Msk 0x100UL 910 #define SRSS_PWR_REGHC_STATUS_REGHC_OV_OUT_Pos 9UL 911 #define SRSS_PWR_REGHC_STATUS_REGHC_OV_OUT_Msk 0x200UL 912 #define SRSS_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK_Pos 12UL 913 #define SRSS_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK_Msk 0x1000UL 914 #define SRSS_PWR_REGHC_STATUS_REGHC_SEQ_BUSY_Pos 31UL 915 #define SRSS_PWR_REGHC_STATUS_REGHC_SEQ_BUSY_Msk 0x80000000UL 916 /* SRSS.PWR_REGHC_CTL2 */ 917 #define SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Pos 0UL 918 #define SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Msk 0xFFUL 919 #define SRSS_PWR_REGHC_CTL2_REGHC_EN_Pos 31UL 920 #define SRSS_PWR_REGHC_CTL2_REGHC_EN_Msk 0x80000000UL 921 /* SRSS.PWR_PMIC_CTL */ 922 #define SRSS_PWR_PMIC_CTL_PMIC_VREF_Pos 2UL 923 #define SRSS_PWR_PMIC_CTL_PMIC_VREF_Msk 0xCUL 924 #define SRSS_PWR_PMIC_CTL_PMIC_VADJ_Pos 4UL 925 #define SRSS_PWR_PMIC_CTL_PMIC_VADJ_Msk 0x1F0UL 926 #define SRSS_PWR_PMIC_CTL_PMIC_USE_LINREG_Pos 10UL 927 #define SRSS_PWR_PMIC_CTL_PMIC_USE_LINREG_Msk 0x400UL 928 #define SRSS_PWR_PMIC_CTL_PMIC_VADJ_BUF_EN_Pos 15UL 929 #define SRSS_PWR_PMIC_CTL_PMIC_VADJ_BUF_EN_Msk 0x8000UL 930 #define SRSS_PWR_PMIC_CTL_PMIC_CTL_OUTEN_Pos 16UL 931 #define SRSS_PWR_PMIC_CTL_PMIC_CTL_OUTEN_Msk 0x10000UL 932 #define SRSS_PWR_PMIC_CTL_PMIC_CTL_POLARITY_Pos 17UL 933 #define SRSS_PWR_PMIC_CTL_PMIC_CTL_POLARITY_Msk 0x20000UL 934 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_INEN_Pos 18UL 935 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_INEN_Msk 0x40000UL 936 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_POLARITY_Pos 19UL 937 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_POLARITY_Msk 0x80000UL 938 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_WAIT_Pos 20UL 939 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_WAIT_Msk 0x3FF00000UL 940 #define SRSS_PWR_PMIC_CTL_PMIC_CONFIGURED_Pos 31UL 941 #define SRSS_PWR_PMIC_CTL_PMIC_CONFIGURED_Msk 0x80000000UL 942 /* SRSS.PWR_PMIC_STATUS */ 943 #define SRSS_PWR_PMIC_STATUS_PMIC_ENABLED_Pos 0UL 944 #define SRSS_PWR_PMIC_STATUS_PMIC_ENABLED_Msk 0x1UL 945 #define SRSS_PWR_PMIC_STATUS_PMIC_STATUS_OK_Pos 12UL 946 #define SRSS_PWR_PMIC_STATUS_PMIC_STATUS_OK_Msk 0x1000UL 947 #define SRSS_PWR_PMIC_STATUS_PMIC_SEQ_BUSY_Pos 31UL 948 #define SRSS_PWR_PMIC_STATUS_PMIC_SEQ_BUSY_Msk 0x80000000UL 949 /* SRSS.PWR_PMIC_CTL2 */ 950 #define SRSS_PWR_PMIC_CTL2_PMIC_STATUS_TIMEOUT_Pos 0UL 951 #define SRSS_PWR_PMIC_CTL2_PMIC_STATUS_TIMEOUT_Msk 0xFFUL 952 #define SRSS_PWR_PMIC_CTL2_PMIC_EN_Pos 31UL 953 #define SRSS_PWR_PMIC_CTL2_PMIC_EN_Msk 0x80000000UL 954 /* SRSS.PWR_PMIC_CTL4 */ 955 #define SRSS_PWR_PMIC_CTL4_PMIC_VADJ_DIS_Pos 30UL 956 #define SRSS_PWR_PMIC_CTL4_PMIC_VADJ_DIS_Msk 0x40000000UL 957 #define SRSS_PWR_PMIC_CTL4_PMIC_DPSLP_Pos 31UL 958 #define SRSS_PWR_PMIC_CTL4_PMIC_DPSLP_Msk 0x80000000UL 959 /* SRSS.CLK_PATH_SELECT */ 960 #define SRSS_CLK_PATH_SELECT_PATH_MUX_Pos 0UL 961 #define SRSS_CLK_PATH_SELECT_PATH_MUX_Msk 0x7UL 962 /* SRSS.CLK_ROOT_SELECT */ 963 #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Pos 0UL 964 #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Msk 0xFUL 965 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Pos 4UL 966 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk 0x30UL 967 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_INT_Pos 8UL 968 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_INT_Msk 0xF00UL 969 #define SRSS_CLK_ROOT_SELECT_ENABLE_Pos 31UL 970 #define SRSS_CLK_ROOT_SELECT_ENABLE_Msk 0x80000000UL 971 /* SRSS.CLK_DIRECT_SELECT */ 972 #define SRSS_CLK_DIRECT_SELECT_DIRECT_MUX_Pos 8UL 973 #define SRSS_CLK_DIRECT_SELECT_DIRECT_MUX_Msk 0x100UL 974 /* SRSS.CLK_SELECT */ 975 #define SRSS_CLK_SELECT_LFCLK_SEL_Pos 0UL 976 #define SRSS_CLK_SELECT_LFCLK_SEL_Msk 0x7UL 977 #define SRSS_CLK_SELECT_PUMP_SEL_Pos 8UL 978 #define SRSS_CLK_SELECT_PUMP_SEL_Msk 0xF00UL 979 #define SRSS_CLK_SELECT_PUMP_DIV_Pos 12UL 980 #define SRSS_CLK_SELECT_PUMP_DIV_Msk 0x7000UL 981 #define SRSS_CLK_SELECT_PUMP_ENABLE_Pos 15UL 982 #define SRSS_CLK_SELECT_PUMP_ENABLE_Msk 0x8000UL 983 /* SRSS.CLK_ILO0_CONFIG */ 984 #define SRSS_CLK_ILO0_CONFIG_ILO0_BACKUP_Pos 0UL 985 #define SRSS_CLK_ILO0_CONFIG_ILO0_BACKUP_Msk 0x1UL 986 #define SRSS_CLK_ILO0_CONFIG_ILO0_MON_ENABLE_Pos 30UL 987 #define SRSS_CLK_ILO0_CONFIG_ILO0_MON_ENABLE_Msk 0x40000000UL 988 #define SRSS_CLK_ILO0_CONFIG_ENABLE_Pos 31UL 989 #define SRSS_CLK_ILO0_CONFIG_ENABLE_Msk 0x80000000UL 990 /* SRSS.CLK_ILO1_CONFIG */ 991 #define SRSS_CLK_ILO1_CONFIG_ILO1_MON_ENABLE_Pos 30UL 992 #define SRSS_CLK_ILO1_CONFIG_ILO1_MON_ENABLE_Msk 0x40000000UL 993 #define SRSS_CLK_ILO1_CONFIG_ENABLE_Pos 31UL 994 #define SRSS_CLK_ILO1_CONFIG_ENABLE_Msk 0x80000000UL 995 /* SRSS.CLK_IMO_CONFIG */ 996 #define SRSS_CLK_IMO_CONFIG_DPSLP_ENABLE_Pos 30UL 997 #define SRSS_CLK_IMO_CONFIG_DPSLP_ENABLE_Msk 0x40000000UL 998 #define SRSS_CLK_IMO_CONFIG_ENABLE_Pos 31UL 999 #define SRSS_CLK_IMO_CONFIG_ENABLE_Msk 0x80000000UL 1000 /* SRSS.CLK_ECO_CONFIG */ 1001 #define SRSS_CLK_ECO_CONFIG_AGC_EN_Pos 1UL 1002 #define SRSS_CLK_ECO_CONFIG_AGC_EN_Msk 0x2UL 1003 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Pos 27UL 1004 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Msk 0x8000000UL 1005 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Pos 28UL 1006 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Msk 0x10000000UL 1007 #define SRSS_CLK_ECO_CONFIG_ECO_EN_Pos 31UL 1008 #define SRSS_CLK_ECO_CONFIG_ECO_EN_Msk 0x80000000UL 1009 /* SRSS.CLK_ECO_PRESCALE */ 1010 #define SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Pos 0UL 1011 #define SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk 0x1UL 1012 #define SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Pos 8UL 1013 #define SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Msk 0xFF00UL 1014 #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos 16UL 1015 #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk 0x3FF0000UL 1016 /* SRSS.CLK_ECO_STATUS */ 1017 #define SRSS_CLK_ECO_STATUS_ECO_OK_Pos 0UL 1018 #define SRSS_CLK_ECO_STATUS_ECO_OK_Msk 0x1UL 1019 #define SRSS_CLK_ECO_STATUS_ECO_READY_Pos 1UL 1020 #define SRSS_CLK_ECO_STATUS_ECO_READY_Msk 0x2UL 1021 /* SRSS.CLK_PILO_CONFIG */ 1022 #define SRSS_CLK_PILO_CONFIG_PILO_BACKUP_Pos 0UL 1023 #define SRSS_CLK_PILO_CONFIG_PILO_BACKUP_Msk 0x1UL 1024 #define SRSS_CLK_PILO_CONFIG_PILO_TCSC_EN_Pos 16UL 1025 #define SRSS_CLK_PILO_CONFIG_PILO_TCSC_EN_Msk 0x10000UL 1026 #define SRSS_CLK_PILO_CONFIG_PILO_EN_Pos 31UL 1027 #define SRSS_CLK_PILO_CONFIG_PILO_EN_Msk 0x80000000UL 1028 /* SRSS.CLK_FLL_CONFIG */ 1029 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos 0UL 1030 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk 0x3FFFFUL 1031 #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos 24UL 1032 #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk 0x1000000UL 1033 #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Pos 31UL 1034 #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk 0x80000000UL 1035 /* SRSS.CLK_FLL_CONFIG2 */ 1036 #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos 0UL 1037 #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk 0x1FFFUL 1038 #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Pos 16UL 1039 #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk 0xFF0000UL 1040 #define SRSS_CLK_FLL_CONFIG2_UPDATE_TOL_Pos 24UL 1041 #define SRSS_CLK_FLL_CONFIG2_UPDATE_TOL_Msk 0xFF000000UL 1042 /* SRSS.CLK_FLL_CONFIG3 */ 1043 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos 0UL 1044 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk 0xFUL 1045 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos 4UL 1046 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk 0xF0UL 1047 #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos 8UL 1048 #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk 0x1FFF00UL 1049 #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Pos 28UL 1050 #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Msk 0x30000000UL 1051 /* SRSS.CLK_FLL_CONFIG4 */ 1052 #define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Pos 0UL 1053 #define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Msk 0xFFUL 1054 #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Pos 8UL 1055 #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Msk 0x700UL 1056 #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos 16UL 1057 #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk 0x1FF0000UL 1058 #define SRSS_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Pos 30UL 1059 #define SRSS_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Msk 0x40000000UL 1060 #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Pos 31UL 1061 #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk 0x80000000UL 1062 /* SRSS.CLK_FLL_STATUS */ 1063 #define SRSS_CLK_FLL_STATUS_LOCKED_Pos 0UL 1064 #define SRSS_CLK_FLL_STATUS_LOCKED_Msk 0x1UL 1065 #define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Pos 1UL 1066 #define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 1067 #define SRSS_CLK_FLL_STATUS_CCO_READY_Pos 2UL 1068 #define SRSS_CLK_FLL_STATUS_CCO_READY_Msk 0x4UL 1069 /* SRSS.CLK_ECO_CONFIG2 */ 1070 #define SRSS_CLK_ECO_CONFIG2_WDTRIM_Pos 0UL 1071 #define SRSS_CLK_ECO_CONFIG2_WDTRIM_Msk 0x7UL 1072 #define SRSS_CLK_ECO_CONFIG2_ATRIM_Pos 4UL 1073 #define SRSS_CLK_ECO_CONFIG2_ATRIM_Msk 0xF0UL 1074 #define SRSS_CLK_ECO_CONFIG2_FTRIM_Pos 8UL 1075 #define SRSS_CLK_ECO_CONFIG2_FTRIM_Msk 0x300UL 1076 #define SRSS_CLK_ECO_CONFIG2_RTRIM_Pos 10UL 1077 #define SRSS_CLK_ECO_CONFIG2_RTRIM_Msk 0xC00UL 1078 #define SRSS_CLK_ECO_CONFIG2_GTRIM_Pos 12UL 1079 #define SRSS_CLK_ECO_CONFIG2_GTRIM_Msk 0x7000UL 1080 /* SRSS.CLK_ILO_CONFIG */ 1081 #define SRSS_CLK_ILO_CONFIG_ILO_BACKUP_Pos 0UL 1082 #define SRSS_CLK_ILO_CONFIG_ILO_BACKUP_Msk 0x1UL 1083 #define SRSS_CLK_ILO_CONFIG_ENABLE_Pos 31UL 1084 #define SRSS_CLK_ILO_CONFIG_ENABLE_Msk 0x80000000UL 1085 /* SRSS.CLK_TRIM_ILO_CTL */ 1086 #define SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM_Pos 0UL 1087 #define SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM_Msk 0x3FUL 1088 /* SRSS.CLK_TRIM_ILO0_CTL */ 1089 #define SRSS_CLK_TRIM_ILO0_CTL_ILO0_FTRIM_Pos 0UL 1090 #define SRSS_CLK_TRIM_ILO0_CTL_ILO0_FTRIM_Msk 0x3FUL 1091 #define SRSS_CLK_TRIM_ILO0_CTL_ILO0_MONTRIM_Pos 8UL 1092 #define SRSS_CLK_TRIM_ILO0_CTL_ILO0_MONTRIM_Msk 0xF00UL 1093 /* SRSS.CLK_MF_SELECT */ 1094 #define SRSS_CLK_MF_SELECT_MFCLK_SEL_Pos 0UL 1095 #define SRSS_CLK_MF_SELECT_MFCLK_SEL_Msk 0x7UL 1096 #define SRSS_CLK_MF_SELECT_MFCLK_DIV_Pos 8UL 1097 #define SRSS_CLK_MF_SELECT_MFCLK_DIV_Msk 0xFF00UL 1098 #define SRSS_CLK_MF_SELECT_ENABLE_Pos 31UL 1099 #define SRSS_CLK_MF_SELECT_ENABLE_Msk 0x80000000UL 1100 /* SRSS.CLK_MFO_CONFIG */ 1101 #define SRSS_CLK_MFO_CONFIG_DPSLP_ENABLE_Pos 30UL 1102 #define SRSS_CLK_MFO_CONFIG_DPSLP_ENABLE_Msk 0x40000000UL 1103 #define SRSS_CLK_MFO_CONFIG_ENABLE_Pos 31UL 1104 #define SRSS_CLK_MFO_CONFIG_ENABLE_Msk 0x80000000UL 1105 /* SRSS.CLK_IHO_CONFIG */ 1106 #define SRSS_CLK_IHO_CONFIG_ENABLE_Pos 31UL 1107 #define SRSS_CLK_IHO_CONFIG_ENABLE_Msk 0x80000000UL 1108 /* SRSS.CLK_ALTHF_CTL */ 1109 #define SRSS_CLK_ALTHF_CTL_ALTHF_ENABLED_Pos 0UL 1110 #define SRSS_CLK_ALTHF_CTL_ALTHF_ENABLED_Msk 0x1UL 1111 #define SRSS_CLK_ALTHF_CTL_ALTHF_ENABLE_Pos 31UL 1112 #define SRSS_CLK_ALTHF_CTL_ALTHF_ENABLE_Msk 0x80000000UL 1113 /* SRSS.CLK_PLL_CONFIG */ 1114 #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos 0UL 1115 #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk 0x7FUL 1116 #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Pos 8UL 1117 #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Msk 0x1F00UL 1118 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos 16UL 1119 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Msk 0x1F0000UL 1120 #define SRSS_CLK_PLL_CONFIG_LOCK_DELAY_Pos 25UL 1121 #define SRSS_CLK_PLL_CONFIG_LOCK_DELAY_Msk 0x6000000UL 1122 #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Pos 27UL 1123 #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Msk 0x8000000UL 1124 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos 28UL 1125 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk 0x30000000UL 1126 #define SRSS_CLK_PLL_CONFIG_ENABLE_Pos 31UL 1127 #define SRSS_CLK_PLL_CONFIG_ENABLE_Msk 0x80000000UL 1128 /* SRSS.CLK_PLL_STATUS */ 1129 #define SRSS_CLK_PLL_STATUS_LOCKED_Pos 0UL 1130 #define SRSS_CLK_PLL_STATUS_LOCKED_Msk 0x1UL 1131 #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos 1UL 1132 #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 1133 /* SRSS.CSV_REF_SEL */ 1134 #define SRSS_CSV_REF_SEL_REF_MUX_Pos 0UL 1135 #define SRSS_CSV_REF_SEL_REF_MUX_Msk 0x7UL 1136 /* SRSS.RES_CAUSE */ 1137 #define SRSS_RES_CAUSE_RESET_WDT_Pos 0UL 1138 #define SRSS_RES_CAUSE_RESET_WDT_Msk 0x1UL 1139 #define SRSS_RES_CAUSE_RESET_ACT_FAULT_Pos 1UL 1140 #define SRSS_RES_CAUSE_RESET_ACT_FAULT_Msk 0x2UL 1141 #define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Pos 2UL 1142 #define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Msk 0x4UL 1143 #define SRSS_RES_CAUSE_RESET_TC_DBGRESET_Pos 3UL 1144 #define SRSS_RES_CAUSE_RESET_TC_DBGRESET_Msk 0x8UL 1145 #define SRSS_RES_CAUSE_RESET_SOFT_Pos 4UL 1146 #define SRSS_RES_CAUSE_RESET_SOFT_Msk 0x10UL 1147 #define SRSS_RES_CAUSE_RESET_MCWDT0_Pos 5UL 1148 #define SRSS_RES_CAUSE_RESET_MCWDT0_Msk 0x20UL 1149 #define SRSS_RES_CAUSE_RESET_MCWDT1_Pos 6UL 1150 #define SRSS_RES_CAUSE_RESET_MCWDT1_Msk 0x40UL 1151 #define SRSS_RES_CAUSE_RESET_MCWDT2_Pos 7UL 1152 #define SRSS_RES_CAUSE_RESET_MCWDT2_Msk 0x80UL 1153 #define SRSS_RES_CAUSE_RESET_MCWDT3_Pos 8UL 1154 #define SRSS_RES_CAUSE_RESET_MCWDT3_Msk 0x100UL 1155 /* SRSS.RES_CAUSE2 */ 1156 #define SRSS_RES_CAUSE2_RESET_CSV_HF_Pos 0UL 1157 #define SRSS_RES_CAUSE2_RESET_CSV_HF_Msk 0xFFFFUL 1158 #define SRSS_RES_CAUSE2_RESET_CSV_REF_Pos 16UL 1159 #define SRSS_RES_CAUSE2_RESET_CSV_REF_Msk 0x10000UL 1160 /* SRSS.RES_CAUSE_EXTEND */ 1161 #define SRSS_RES_CAUSE_EXTEND_RESET_XRES_Pos 16UL 1162 #define SRSS_RES_CAUSE_EXTEND_RESET_XRES_Msk 0x10000UL 1163 #define SRSS_RES_CAUSE_EXTEND_RESET_BODVDDD_Pos 17UL 1164 #define SRSS_RES_CAUSE_EXTEND_RESET_BODVDDD_Msk 0x20000UL 1165 #define SRSS_RES_CAUSE_EXTEND_RESET_BODVDDA_Pos 18UL 1166 #define SRSS_RES_CAUSE_EXTEND_RESET_BODVDDA_Msk 0x40000UL 1167 #define SRSS_RES_CAUSE_EXTEND_RESET_BODVCCD_Pos 19UL 1168 #define SRSS_RES_CAUSE_EXTEND_RESET_BODVCCD_Msk 0x80000UL 1169 #define SRSS_RES_CAUSE_EXTEND_RESET_OVDVDDD_Pos 20UL 1170 #define SRSS_RES_CAUSE_EXTEND_RESET_OVDVDDD_Msk 0x100000UL 1171 #define SRSS_RES_CAUSE_EXTEND_RESET_OVDVDDA_Pos 21UL 1172 #define SRSS_RES_CAUSE_EXTEND_RESET_OVDVDDA_Msk 0x200000UL 1173 #define SRSS_RES_CAUSE_EXTEND_RESET_OVDVCCD_Pos 22UL 1174 #define SRSS_RES_CAUSE_EXTEND_RESET_OVDVCCD_Msk 0x400000UL 1175 #define SRSS_RES_CAUSE_EXTEND_RESET_OCD_ACT_LINREG_Pos 23UL 1176 #define SRSS_RES_CAUSE_EXTEND_RESET_OCD_ACT_LINREG_Msk 0x800000UL 1177 #define SRSS_RES_CAUSE_EXTEND_RESET_OCD_DPSLP_LINREG_Pos 24UL 1178 #define SRSS_RES_CAUSE_EXTEND_RESET_OCD_DPSLP_LINREG_Msk 0x1000000UL 1179 #define SRSS_RES_CAUSE_EXTEND_RESET_OCD_REGHC_Pos 25UL 1180 #define SRSS_RES_CAUSE_EXTEND_RESET_OCD_REGHC_Msk 0x2000000UL 1181 #define SRSS_RES_CAUSE_EXTEND_RESET_PMIC_Pos 26UL 1182 #define SRSS_RES_CAUSE_EXTEND_RESET_PMIC_Msk 0x4000000UL 1183 #define SRSS_RES_CAUSE_EXTEND_RESET_PXRES_Pos 28UL 1184 #define SRSS_RES_CAUSE_EXTEND_RESET_PXRES_Msk 0x10000000UL 1185 #define SRSS_RES_CAUSE_EXTEND_RESET_STRUCT_XRES_Pos 29UL 1186 #define SRSS_RES_CAUSE_EXTEND_RESET_STRUCT_XRES_Msk 0x20000000UL 1187 #define SRSS_RES_CAUSE_EXTEND_RESET_PORVDDD_Pos 30UL 1188 #define SRSS_RES_CAUSE_EXTEND_RESET_PORVDDD_Msk 0x40000000UL 1189 /* SRSS.RES_PXRES_CTL */ 1190 #define SRSS_RES_PXRES_CTL_PXRES_TRIGGER_Pos 0UL 1191 #define SRSS_RES_PXRES_CTL_PXRES_TRIGGER_Msk 0x1UL 1192 /* SRSS.PWR_CBUCK_CTL */ 1193 #define SRSS_PWR_CBUCK_CTL_CBUCK_VSEL_Pos 0UL 1194 #define SRSS_PWR_CBUCK_CTL_CBUCK_VSEL_Msk 0x1FUL 1195 #define SRSS_PWR_CBUCK_CTL_CBUCK_MODE_Pos 8UL 1196 #define SRSS_PWR_CBUCK_CTL_CBUCK_MODE_Msk 0x1F00UL 1197 /* SRSS.PWR_CBUCK_CTL2 */ 1198 #define SRSS_PWR_CBUCK_CTL2_CBUCK_OVERRIDE_Pos 28UL 1199 #define SRSS_PWR_CBUCK_CTL2_CBUCK_OVERRIDE_Msk 0x10000000UL 1200 #define SRSS_PWR_CBUCK_CTL2_CBUCK_PAUSE_Pos 29UL 1201 #define SRSS_PWR_CBUCK_CTL2_CBUCK_PAUSE_Msk 0x20000000UL 1202 #define SRSS_PWR_CBUCK_CTL2_CBUCK_COPY_SETTINGS_Pos 30UL 1203 #define SRSS_PWR_CBUCK_CTL2_CBUCK_COPY_SETTINGS_Msk 0x40000000UL 1204 #define SRSS_PWR_CBUCK_CTL2_CBUCK_USE_SETTINGS_Pos 31UL 1205 #define SRSS_PWR_CBUCK_CTL2_CBUCK_USE_SETTINGS_Msk 0x80000000UL 1206 /* SRSS.PWR_CBUCK_CTL3 */ 1207 #define SRSS_PWR_CBUCK_CTL3_CBUCK_INRUSH_SEL_Pos 31UL 1208 #define SRSS_PWR_CBUCK_CTL3_CBUCK_INRUSH_SEL_Msk 0x80000000UL 1209 /* SRSS.PWR_CBUCK_STATUS */ 1210 #define SRSS_PWR_CBUCK_STATUS_PMU_DONE_Pos 31UL 1211 #define SRSS_PWR_CBUCK_STATUS_PMU_DONE_Msk 0x80000000UL 1212 /* SRSS.PWR_SDR0_CTL */ 1213 #define SRSS_PWR_SDR0_CTL_SDR0_CBUCK_VSEL_Pos 0UL 1214 #define SRSS_PWR_SDR0_CTL_SDR0_CBUCK_VSEL_Msk 0x1FUL 1215 #define SRSS_PWR_SDR0_CTL_SDR0_CBUCK_MODE_Pos 5UL 1216 #define SRSS_PWR_SDR0_CTL_SDR0_CBUCK_MODE_Msk 0x3E0UL 1217 #define SRSS_PWR_SDR0_CTL_SDR0_CBUCK_DPSLP_VSEL_Pos 10UL 1218 #define SRSS_PWR_SDR0_CTL_SDR0_CBUCK_DPSLP_VSEL_Msk 0x7C00UL 1219 #define SRSS_PWR_SDR0_CTL_SDR0_CBUCK_DPSLP_MODE_Pos 15UL 1220 #define SRSS_PWR_SDR0_CTL_SDR0_CBUCK_DPSLP_MODE_Msk 0xF8000UL 1221 #define SRSS_PWR_SDR0_CTL_SDR0_VSEL_Pos 20UL 1222 #define SRSS_PWR_SDR0_CTL_SDR0_VSEL_Msk 0xF00000UL 1223 #define SRSS_PWR_SDR0_CTL_SDR0_DPSLP_VSEL_Pos 26UL 1224 #define SRSS_PWR_SDR0_CTL_SDR0_DPSLP_VSEL_Msk 0x3C000000UL 1225 #define SRSS_PWR_SDR0_CTL_SDR0_ALLOW_BYPASS_Pos 31UL 1226 #define SRSS_PWR_SDR0_CTL_SDR0_ALLOW_BYPASS_Msk 0x80000000UL 1227 /* SRSS.PWR_SDR1_CTL */ 1228 #define SRSS_PWR_SDR1_CTL_SDR1_CBUCK_VSEL_Pos 0UL 1229 #define SRSS_PWR_SDR1_CTL_SDR1_CBUCK_VSEL_Msk 0x1FUL 1230 #define SRSS_PWR_SDR1_CTL_SDR1_CBUCK_MODE_Pos 8UL 1231 #define SRSS_PWR_SDR1_CTL_SDR1_CBUCK_MODE_Msk 0x1F00UL 1232 #define SRSS_PWR_SDR1_CTL_SDR1_VSEL_Pos 16UL 1233 #define SRSS_PWR_SDR1_CTL_SDR1_VSEL_Msk 0xF0000UL 1234 #define SRSS_PWR_SDR1_CTL_SDR1_HW_SEL_Pos 30UL 1235 #define SRSS_PWR_SDR1_CTL_SDR1_HW_SEL_Msk 0x40000000UL 1236 #define SRSS_PWR_SDR1_CTL_SDR1_ENABLE_Pos 31UL 1237 #define SRSS_PWR_SDR1_CTL_SDR1_ENABLE_Msk 0x80000000UL 1238 /* SRSS.PWR_HVLDO0_CTL */ 1239 #define SRSS_PWR_HVLDO0_CTL_HVLDO0_VSEL_Pos 0UL 1240 #define SRSS_PWR_HVLDO0_CTL_HVLDO0_VSEL_Msk 0xFUL 1241 #define SRSS_PWR_HVLDO0_CTL_HVLDO0_HW_SEL_Pos 30UL 1242 #define SRSS_PWR_HVLDO0_CTL_HVLDO0_HW_SEL_Msk 0x40000000UL 1243 #define SRSS_PWR_HVLDO0_CTL_HVLDO0_ENABLE_Pos 31UL 1244 #define SRSS_PWR_HVLDO0_CTL_HVLDO0_ENABLE_Msk 0x80000000UL 1245 /* SRSS.TST_XRES_SECURE */ 1246 #define SRSS_TST_XRES_SECURE_DATA8_Pos 0UL 1247 #define SRSS_TST_XRES_SECURE_DATA8_Msk 0xFFUL 1248 #define SRSS_TST_XRES_SECURE_FW_WR_Pos 8UL 1249 #define SRSS_TST_XRES_SECURE_FW_WR_Msk 0xF00UL 1250 #define SRSS_TST_XRES_SECURE_SECURE_WR_Pos 16UL 1251 #define SRSS_TST_XRES_SECURE_SECURE_WR_Msk 0xF0000UL 1252 #define SRSS_TST_XRES_SECURE_FW_KEY_OK_Pos 29UL 1253 #define SRSS_TST_XRES_SECURE_FW_KEY_OK_Msk 0x20000000UL 1254 #define SRSS_TST_XRES_SECURE_SECURE_KEY_OK_Pos 30UL 1255 #define SRSS_TST_XRES_SECURE_SECURE_KEY_OK_Msk 0x40000000UL 1256 #define SRSS_TST_XRES_SECURE_SECURE_DISABLE_Pos 31UL 1257 #define SRSS_TST_XRES_SECURE_SECURE_DISABLE_Msk 0x80000000UL 1258 /* SRSS.PWR_TRIM_CBUCK_CTL */ 1259 #define SRSS_PWR_TRIM_CBUCK_CTL_CBUCK_DPSLP_VSEL_Pos 0UL 1260 #define SRSS_PWR_TRIM_CBUCK_CTL_CBUCK_DPSLP_VSEL_Msk 0x1FUL 1261 #define SRSS_PWR_TRIM_CBUCK_CTL_CBUCK_DPSLP_MODE_Pos 8UL 1262 #define SRSS_PWR_TRIM_CBUCK_CTL_CBUCK_DPSLP_MODE_Msk 0x1F00UL 1263 /* SRSS.CLK_TRIM_ECO_CTL */ 1264 #define SRSS_CLK_TRIM_ECO_CTL_ITRIM_Pos 16UL 1265 #define SRSS_CLK_TRIM_ECO_CTL_ITRIM_Msk 0x3F0000UL 1266 /* SRSS.CLK_TRIM_ILO1_CTL */ 1267 #define SRSS_CLK_TRIM_ILO1_CTL_ILO1_FTRIM_Pos 0UL 1268 #define SRSS_CLK_TRIM_ILO1_CTL_ILO1_FTRIM_Msk 0x3FUL 1269 #define SRSS_CLK_TRIM_ILO1_CTL_ILO1_MONTRIM_Pos 8UL 1270 #define SRSS_CLK_TRIM_ILO1_CTL_ILO1_MONTRIM_Msk 0xF00UL 1271 /* SRSS.WDT_CTL */ 1272 #define SRSS_WDT_CTL_WDT_EN_Pos 0UL 1273 #define SRSS_WDT_CTL_WDT_EN_Msk 0x1UL 1274 #define SRSS_WDT_CTL_WDT_CLK_SEL_Pos 4UL 1275 #define SRSS_WDT_CTL_WDT_CLK_SEL_Msk 0x30UL 1276 #define SRSS_WDT_CTL_WDT_LOCK_Pos 30UL 1277 #define SRSS_WDT_CTL_WDT_LOCK_Msk 0xC0000000UL 1278 /* SRSS.WDT_CNT */ 1279 #define SRSS_WDT_CNT_COUNTER_Pos 0UL 1280 #define SRSS_WDT_CNT_COUNTER_Msk 0xFFFFFFFFUL 1281 /* SRSS.WDT_MATCH */ 1282 #define SRSS_WDT_MATCH_MATCH_Pos 0UL 1283 #define SRSS_WDT_MATCH_MATCH_Msk 0xFFFFFFFFUL 1284 /* SRSS.WDT_MATCH2 */ 1285 #define SRSS_WDT_MATCH2_IGNORE_BITS_ABOVE_Pos 0UL 1286 #define SRSS_WDT_MATCH2_IGNORE_BITS_ABOVE_Msk 0x1FUL 1287 1288 1289 #endif /* _CYIP_SRSS_H_ */ 1290 1291 1292 /* [] END OF FILE */ 1293
