Searched refs:SRSS_PWR_CTL (Results 1 – 7 of 7) sorted by relevance
925 if (0U != _FLD2VAL(SRSS_PWR_CTL_LPM_READY, SRSS_PWR_CTL)) in Cy_SysPm_SystemSetMinRegulatorCurrent()930 SRSS_PWR_CTL |= PWR_CIRCUITS_SET_LPMODE_LDO_MASK; in Cy_SysPm_SystemSetMinRegulatorCurrent()942 SRSS_PWR_CTL |= PWR_CIRCUITS_SET_LPMODE_BUCK_MASK; in Cy_SysPm_SystemSetMinRegulatorCurrent()951 SRSS_PWR_CTL |= SRSS_PWR_CTL_ACT_REF_DIS_Msk; in Cy_SysPm_SystemSetMinRegulatorCurrent()977 SRSS_PWR_CTL &= (uint32_t) ~CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_LDO_MASK; in Cy_SysPm_SystemSetNormalRegulatorCurrent()981 SRSS_PWR_CTL &= (uint32_t) ~CY_SYSPM_PWR_CIRCUITS_LPMODE_ACTIVE_BUCK_MASK; in Cy_SysPm_SystemSetNormalRegulatorCurrent()987 while ((0U == _FLD2VAL(SRSS_PWR_CTL_ACT_REF_OK, SRSS_PWR_CTL)) && (0U != timeOut)) in Cy_SysPm_SystemSetNormalRegulatorCurrent()995 SRSS_PWR_CTL &= (uint32_t) ~SRSS_PWR_CTL_BGREF_LPMODE_Msk; in Cy_SysPm_SystemSetNormalRegulatorCurrent()1180 SRSS_PWR_CTL |= (_VAL2FLD(SRSS_PWR_CTL_DPSLP_REG_DIS, 1U) | in Cy_SysPm_BuckEnable()1196 SRSS_PWR_CTL |= _VAL2FLD(SRSS_PWR_CTL_LINREG_DIS, 1U); in Cy_SysPm_BuckEnable()[all …]
969 return (_FLD2BOOL(SRSS_PWR_CTL_LPM_READY, SRSS_PWR_CTL)? true : false); in Cy_SysPm_IsLpmReady()1616 return ((SRSS_PWR_CTL & regMask) == regMask); in Cy_SysPm_SystemIsMinRegulatorCurrentSet()
785 return ((SRSS_PWR_CTL & regMask) == regMask); in Cy_SysPm_SystemIsMinRegulatorCurrentSet()1727 return (_FLD2BOOL(SRSS_PWR_CTL_LPM_READY, SRSS_PWR_CTL)? true : false); in Cy_SysPm_IsLpmReady()
1492 return (_FLD2BOOL(SRSS_PWR_CTL_LPM_READY, SRSS_PWR_CTL)? true : false); in Cy_SysPm_IsLpmReady()
231 #define SRSS_PWR_CTL (((SRSS_V1_Type *) SRSS)->PWR_CTL) macro
167 #define SRSS_PWR_CTL (((SRSS_Type *) SRSS)->PWR_CTL) macro
866 #define SRSS_PWR_CTL (((SRSS_Type *) SRSS)->PWR_CTL) macro
