Searched refs:SRSS_PWR_BUCK_CTL (Results 1 – 3 of 3) sorted by relevance
| /hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/ |
| D | cy_syspm.c | 1185 SRSS_PWR_BUCK_CTL = in Cy_SysPm_BuckEnable()
1186 … _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, (uint32_t) voltage); in Cy_SysPm_BuckEnable()
1188 SRSS_PWR_BUCK_CTL |= _VAL2FLD(SRSS_PWR_BUCK_CTL_BUCK_EN, 1U); in Cy_SysPm_BuckEnable()
1190 SRSS_PWR_BUCK_CTL |= _VAL2FLD(SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN, 1U); in Cy_SysPm_BuckEnable()
1261 SRSS_PWR_BUCK_CTL = in Cy_SysPm_BuckSetVoltage1()
1262 … _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, BUCK_OUT1_VOLTAGE_0_95V); in Cy_SysPm_BuckSetVoltage1()
1281 SRSS_PWR_BUCK_CTL = in Cy_SysPm_BuckSetVoltage1()
1282 … _CLR_SET_FLD32U((SRSS_PWR_BUCK_CTL), SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL, (uint32_t) voltage); in Cy_SysPm_BuckSetVoltage1()
1322 retVal = (_FLD2BOOL(SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN, SRSS_PWR_BUCK_CTL)); in Cy_SysPm_BuckIsOutputEnabled()
1351 SRSS_PWR_BUCK_CTL |= _VAL2FLD(SRSS_PWR_BUCK_CTL_BUCK_EN, 1U); in Cy_SysPm_BuckEnableVoltage2()
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| /hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ |
| D | cy_device.h | 234 #define SRSS_PWR_BUCK_CTL (((SRSS_V1_Type *) SRSS)->PWR_BUCK_CTL) macro
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| /hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ |
| D | cy_device.h | 170 #define SRSS_PWR_BUCK_CTL (((SRSS_Type *) SRSS)->PWR_BUCK_CTL) macro
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